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authorAndre Sihera <asihera@nvidia.com>2011-04-07 20:37:11 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-04-14 21:22:15 -0700
commitd6ad1d95125bf21ed6c99cc8a633f0a23779d18a (patch)
treee700a8b2823e95b9a839a86eea4f28ae46c168a1
parent0342de866ae3db18d6c68f4040b9210f54bc3386 (diff)
rtc: tps6586x RTC clock fix
Specified OSC_SRC_SEL flag to force clock signal to be taken from an externally generated source rather than be calculated internally. This should raise the accuracy to within +/-2 seconds/24 hours. Bug 811075 Bug 810537 Change-Id: I7b7c4e4d752fdc03b81239f362a1d6f7aa4d3b92 Reviewed-on: http://git-master/r/27222 Reviewed-by: Andre Sihera <asihera@nvidia.com> Tested-by: Andre Sihera <asihera@nvidia.com> Reviewed-by: David Schalig <dschalig@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com>
-rw-r--r--drivers/rtc/rtc-tps6586x.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c
index b70614fb7d5e..641f1461646d 100644
--- a/drivers/rtc/rtc-tps6586x.c
+++ b/drivers/rtc/rtc-tps6586x.c
@@ -291,8 +291,9 @@ static int __devinit tps6586x_rtc_probe(struct platform_device *pdev)
/* 1 kHz tick mode, enable tick counting */
err = tps6586x_update(tps_dev, RTC_CTRL,
- RTC_ENABLE | ((pdata->cl_sel<<CL_SEL_POS)&CL_SEL_MASK),
- RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
+ RTC_ENABLE | OSC_SRC_SEL | ((pdata->cl_sel << CL_SEL_POS) &
+ CL_SEL_MASK),
+ RTC_ENABLE | OSC_SRC_SEL | PRE_BYPASS | CL_SEL_MASK);
if (err < 0) {
dev_err(&pdev->dev, "unable to start counter\n");
goto fail;