[ARM/tegra] RM: added LP2 configuration options.

Added configuration options to set default LP2 policy.

Change-Id: I81820f575858dda62d31b304b6adf09f7d0f3689
Reviewed-on: http://git-master/r/4164
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>

4 files changed, 54 insertions, 6 deletions

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 8a7ec5bfea0a..cfc54a2261b1 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -154,6 +154,41 @@ config TEGRA_USB_VBUS_DETECT_BY_PMU
 	help
 		Enables USB VBUS detection by PMU
 
+choice
+	prompt "Tegra CPU power off [LP2 state] policy"
+	depends on TEGRA_NVRM
+	default TEGRA_LP2POLICY_IGNORE_LC
+	help
+	  Selects additional DVFS qualification policy for the CPU idle
+	  governor decision to put CPU into LP2 state
+
+config TEGRA_LP2POLICY_DISABLED
+	bool "LP2 is not allowed"
+	help
+	  Disregards CPU idle governor LP2 requests, never enters LP2 state
+
+config TEGRA_LP2POLICY_ENTER_IN_LC
+	bool "LP2 is allowed in DVFS low corner"
+	help
+	  Carries on CPU idle governor LP2 request and disables DVFS wake
+	  interrupt only if all DVFS clock loads are under low frequency
+	  thresholds, and none of DVFS clients is busy
+
+config TEGRA_LP2POLICY_PERSIST_IN_LC
+	bool "LP2 is persistent in DVFS low corner"
+	help
+	  Always carries on CPU idle governor LP2 request, but disables DVFS
+	  wake interrupt only if all DVFS clock loads are under low frequency
+	  thresholds, or DVFS clients busy request floors are reached
+
+config TEGRA_LP2POLICY_IGNORE_LC
+	bool "LP2 is always allowed and persistent"
+	help
+	  Always carries on CPU idle governor LP2 request, and disables DVFS
+	  wake interrupt regardless of DVFS clock activities
+
+endchoice
+
 if TEGRA_ODM_KIT
 source "arch/arm/mach-tegra/odm_kit/Kconfig"
 endif
diff --git a/arch/arm/mach-tegra/include/nvrm_power_private.h b/arch/arm/mach-tegra/include/nvrm_power_private.h
index bd0fe6e0ef88..a2663df8df6c 100644
--- a/arch/arm/mach-tegra/include/nvrm_power_private.h
+++ b/arch/arm/mach-tegra/include/nvrm_power_private.h
@@ -128,7 +128,26 @@ typedef enum
     NvRmLp2Policy_Force32 = 0x7FFFFFFF
 } NvRmLp2Policy;
 
+#ifdef CONFIG_TEGRA_LP2POLICY_DISABLED
+#define NVRM_DEFAULT_LP2POLICY (NvRmLp2Policy_Disabled)
+#endif
+
+#ifdef CONFIG_TEGRA_LP2POLICY_ENTER_IN_LC
+#define NVRM_DEFAULT_LP2POLICY (NvRmLp2Policy_EnterInLowCorner)
+#endif
+
+#ifdef CONFIG_TEGRA_LP2POLICY_PERSIST_IN_LC
+#define NVRM_DEFAULT_LP2POLICY (NvRmLp2Policy_MaskInLowCorner)
+#endif
+
+#ifdef CONFIG_TEGRA_LP2POLICY_IGNORE_LC
 #define NVRM_DEFAULT_LP2POLICY (NvRmLp2Policy_IgnoreLowCorner)
+#endif
+
+#ifndef NVRM_DEFAULT_LP2POLICY
+#define NVRM_DEFAULT_LP2POLICY (NvRmLp2Policy_IgnoreLowCorner)
+#endif
+
 extern NvRmLp2Policy g_Lp2Policy;
 
 /**
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
index af6c0309a8d1..985f8df19643 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -74,12 +74,10 @@ void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs)
     {
         case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
             pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamLpDddr2;
-            g_Lp2Policy = NVRM_AP20_LPDDR2_LP2POLICY;
             break;
 
         case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
             pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamDddr2;
-            g_Lp2Policy = NVRM_AP20_DDR2_LP2POLICY;
             break;
 
         default:
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
index 3d8c85be21c5..8b5c9d4ded39 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -233,10 +233,6 @@ extern "C"
 
 #define NVRM_DFS_PARAM_EMC_AP20 NVRM_DFS_PARAM_EMC_AP20_LPDDR2
 
-// Defines LP2 entry policy each supported SDRAM type
-#define NVRM_AP20_DDR2_LP2POLICY (NvRmLp2Policy_IgnoreLowCorner)
-#define NVRM_AP20_LPDDR2_LP2POLICY (NvRmLp2Policy_MaskInLowCorner)
-
 /**
  * Defines CPU frequency threshold for slave CPU1 power management:
  * - CPU1 is turned Off when cpu clock is below ON_MIN for