arm: tegra: common: remove initial refcnt on pllm

Use pmc registers to shutdown/start pll_m
Set the pllm enable bit in
APBDEV_PMC_PLLP_WB0_OVERRIDE_0 register before entering
LP0

BUG 852523

Change-Id: I8aec1af5ef6ab1cd5c9838232497a54bbc9fa682
Reviewed-on: http://git-master/r/41266
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

5 files changed, 27 insertions, 7 deletions

diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c
index 6c56f309a323..ee739bd4eedd 100644
--- a/arch/arm/mach-tegra/board-cardhu.c
+++ b/arch/arm/mach-tegra/board-cardhu.c
@@ -196,7 +196,7 @@ static inline void tegra_setup_bluesleep(void) { }
 
 static __initdata struct tegra_clk_init_table cardhu_clk_init_table[] = {
 	/* name		parent		rate		enabled */
-	{ "pll_m",	NULL,		0,		true},
+	{ "pll_m",	NULL,		0,		false},
 	{ "hda",	"pll_p",	108000000,	false},
 	{ "hda2codec_2x","pll_p",	48000000,	false},
 	{ "pwm",	"clk_32k",	32768,		false},
diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c
index 3a6546839b92..1203322cebd9 100644
--- a/arch/arm/mach-tegra/board-enterprise.c
+++ b/arch/arm/mach-tegra/board-enterprise.c
@@ -190,7 +190,7 @@ err_free_dev:
 
 static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = {
 	/* name		parent		rate		enabled */
-	{ "pll_m",	NULL,		0,		true},
+	{ "pll_m",	NULL,		0,		false},
 	{ "hda",	"pll_p",	108000000,	false},
 	{ "hda2codec_2x","pll_p",	48000000,	false},
 	{ "pwm",	"clk_32k",	32768,		false},
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 164ee1da3a4d..ef229fe94584 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -121,7 +121,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ "pll_p_out1",	"pll_p",	9600000,	true },
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	102000000,	true },
-	{ "pll_m_out1",	"pll_m",	275000000,	true },
+	{ "pll_m_out1",	"pll_m",	275000000,	false},
 	{ "pll_p_out4",	"pll_p",	102000000,	true },
 	{ "sclk",	"pll_p_out4",	102000000,	true },
 	{ "hclk",	"sclk",		102000000,	true },
@@ -132,7 +132,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ "pll_p_out1",	"pll_p",	28800000,	true },
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
 	{ "pll_p_out3",	"pll_p",	72000000,	true },
-	{ "pll_m_out1",	"pll_m",	275000000,	true },
+	{ "pll_m_out1",	"pll_m",	275000000,	false},
 	{ "pll_c",	NULL,		ULONG_MAX,	false },
 	{ "pll_c_out1",	"pll_c",	208000000,	false },
 	{ "pll_p_out4",	"pll_p",	108000000,	true },
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index cf91bdb8ee05..00469a555fb9 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -224,6 +224,9 @@
 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT	16
 #define PMC_BLINK_TIMER_DATA_OFF_MASK	0xffff
 
+#define PMC_PLLP_WB0_OVERRIDE_0		0xf8
+#define PMC_PLLP_WB0_OVERRIDE_0_PLLM_ENABLE		(1 << 12)
+
 #define UTMIP_PLL_CFG2					0x488
 #define UTMIP_PLL_CFG2_STABLE_COUNT(x)			(((x) & 0xfff) << 6)
 #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x)		(((x) & 0x3f) << 18)
@@ -1351,6 +1354,12 @@ static int tegra3_pll_clk_enable(struct clk *c)
 		clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE);
 	}
 
+	if (c->flags & PLLM) {
+		val = pmc_readl(PMC_PLLP_WB0_OVERRIDE_0);
+		val |= PMC_PLLP_WB0_OVERRIDE_0_PLLM_ENABLE;
+		pmc_writel(val, PMC_PLLP_WB0_OVERRIDE_0);
+	}
+
 	tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK);
 
 	return 0;
@@ -1370,6 +1379,11 @@ static void tegra3_pll_clk_disable(struct clk *c)
 		val &= ~PLLD_MISC_CLKENABLE;
 		clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE);
 	}
+	if (c->flags & PLLM) {
+		val = pmc_readl(PMC_PLLP_WB0_OVERRIDE_0);
+		val &= ~PMC_PLLP_WB0_OVERRIDE_0_PLLM_ENABLE;
+		pmc_writel(val, PMC_PLLP_WB0_OVERRIDE_0);
+	}
 }
 
 static int tegra3_pll_clk_set_rate(struct clk *c, unsigned long rate)
@@ -2308,7 +2322,7 @@ static int tegra3_emc_clk_set_rate(struct clk *c, unsigned long rate)
 		return ret;
 
 	if (p != c->parent) {
-		if(c->refcnt && c->parent)
+		if (c->refcnt && c->parent)
 			clk_disable(c->parent);
 		clk_reparent(c, p);
 	}
diff --git a/arch/arm/mach-tegra/tegra3_save.S b/arch/arm/mach-tegra/tegra3_save.S
index 8dd462fa90af..26c35f03c8df 100644
--- a/arch/arm/mach-tegra/tegra3_save.S
+++ b/arch/arm/mach-tegra/tegra3_save.S
@@ -583,12 +583,18 @@ powerdown_l2_done:
 
 	/* disable PLLM via PMC in LP0 and LP1 states */
 	tst	sp, #TEGRA_POWER_EFFECT_LP0
-	bne	powerdown_pll_pcx
+	bne	enable_pllm_lp0
 	ldr	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
 	bic	r0, r0, #(1<<12)
 	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
-powerdown_pll_pcx:
+	b	powerdown_pll_pcx
 
+enable_pllm_lp0:
+	ldr	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+	orr	r0, r0, #((1<<12) | (1 << 11))
+	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
+
+powerdown_pll_pcx:
 	/* disable PLLP, PLLA, PLLC, and PLLX in LP0 and LP1 states */
 	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
 	bic	r0, r0, #(1<<30)