diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-05-04 20:11:04 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-05-05 18:38:48 -0700 |
| commit | 8447d4e116e3103cc2623f5bffefa0823a2014ba (patch) | |
| tree | d02256ae216646571c779620cb8d16118bb767a7 | |
| parent | 0218442f458a15357202af01cf3f7b65430c0617 (diff) | |
tegra ODM: Added CPU rail sequencer delay.
Added CPU rail power up sequencer delay on Whistler to make sure that
core rail is powered On 1st on LP0 exit.
Change-Id: I1156186048b80584f6409f3dfbbdb76fa8b80345
Reviewed-on: http://git-master/r/1304
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c | 13 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h | 8 |
2 files changed, 17 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c index 7da23407345c..285044034f97 100644 --- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c +++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b.c @@ -1255,13 +1255,22 @@ Max8907bPwrEnAttach( switch (Supply) { case Max8907bPmuSupply_LX_V1: // CPU - CntData = Attach ? MAX8907B_SEQCNT_PWREN_LX_V1 : - MAX8907B_SEQCNT_DEFAULT_LX_V1; + // No sequencer delay for CPU rail when it is attached + CntData = Attach ? 0x00 : MAX8907B_SEQCNT_DEFAULT_LX_V1; SeqSel = Attach ? MAX8907B_SEQSEL_PWREN_LXX : MAX8907B_SEQSEL_DEFAULT_LX_V1; break; case Max8907bPmuSupply_LX_V2: // Core + // Change CPU sequencer delay when core is attached to assure + // order of Core/CPU rails control; clear CPU delay when core + // is detached + CntAddr = Max8907bSupplyInfoTable[ + Max8907bPmuSupply_LX_V1].SequencerCountRegAddr; + CntData = Attach ? MAX8907B_SEQCNT_PWREN_LX_V1 : 0x00; + if (!Max8907bI2cWrite8(hDevice, CntAddr, CntData)) + return NV_FALSE; + CntData = Attach ? MAX8907B_SEQCNT_PWREN_LX_V2 : MAX8907B_SEQCNT_DEFAULT_LX_V2; SeqSel = Attach ? MAX8907B_SEQSEL_PWREN_LXX : diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h index 91b55a082d1b..1b362aac43f4 100644 --- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h +++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/max8907b_supply_info_table.h @@ -90,8 +90,12 @@ extern "C" #define MAX8907B_SEQCNT_DEFAULT_LX_V1 0x1C #define MAX8907B_SEQCNT_DEFAULT_LX_V2 0x1C -// Defines sequencer count PWREN control values -#define MAX8907B_SEQCNT_PWREN_LX_V1 0x00 /* no delay */ +// Defines sequencer count PWREN control values (these settings applied +// togeteher, when both CPU/V1 and CORE/V2 rails are attached to PWREN; +// in case when only CPU/V1 rail is attached no delay is specified) +// B[7:4] - power up delay in 20us taps +// B[3:0] - power down delay in 20us taps +#define MAX8907B_SEQCNT_PWREN_LX_V1 0xC0 /* 240us up delay */ #define MAX8907B_SEQCNT_PWREN_LX_V2 0x00 /* no delay */ // Defines PMU output timing parameters. Scaling up time is dynamically |