diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-05-25 21:02:13 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-05-26 13:50:41 -0700 |
| commit | 4abce88680dc0edc9ab43166e8340b4b562cea2d (patch) | |
| tree | 6cd5f604016ef9ef66e98a715104d8d866da53f2 | |
| parent | 65b26306f8ebbd4660baa3720f3734575e4effc3 (diff) | |
tegra power: Utilized "Wait-for-WFE" for LP2 entry.
Replaced final LP2 entry procedure: "Power gate CPU, then sit in WFI
loop" with the new one: "Wait-for-WFE, then power gate CPU". The latter
guarantees clean (no DRAM access) CPU power down. Fix for bug 682246.
Change-Id: I1cf5e0e2b4cea0c20d942c3f642e23ba743fc35a
Reviewed-on: http://git-master/r/1619
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/power-lp.S | 20 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/power-t2.c | 1 |
2 files changed, 15 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/power-lp.S b/arch/arm/mach-tegra/power-lp.S index 80453eecbc2d..9758d3fd4045 100644 --- a/arch/arm/mach-tegra/power-lp.S +++ b/arch/arm/mach-tegra/power-lp.S @@ -305,9 +305,13 @@ ENTRY(enter_lp2) bic r2, r2, #(1<<14) //Unset the SIDE_EFFECT bit str r2, [r5, #APBDEV_PMC_CNTRL_0] - //Powergate the cpu by setting the ENABLE bit + // Get ready to powergate the cpu by setting the ENABLE bit and + // configuring Wait-for-WFE mechanism ldr r2, [r6, #FLOW_CTLR_CPU_CSR_0] orr r2, r2, #(1<<0) + orr r2, r2, #(1<<4) // Set CPU0 WFE bit mask + bic r2, r2, #(1<<5) // Clear CPU1 WFE bit mask + orr r2, r2, #(1<<14) // Clear Event Flag (WC) str r2, [r6, #FLOW_CTLR_CPU_CSR_0] //Put the CPU on the desired clock source for wakeup, @@ -329,17 +333,17 @@ cclk_delay: ldr r2, [r7] str r2, [r5, #APBDEV_PMC_SCRATCH38_0] - //Finally, halt the CPU + // Enable wake events and halt the CPU (no real halt if Wait-for-WFE) mov r2, #0 orr r2, r2, #(4<<29) //STOP_UNTIL_IRQ orr r2, r2, #(1<<10) //IRQ_0 event orr r2, r2, #(1<<8) //FIQ_0 event str r2, [r6, #FLOW_CTLR_HALT_CPU_EVENTS_0] -DoWFI: +DoWFloop: dsb - wfi - b DoWFI + wfe // CPU halted and power gated here + b DoWFloop ENDPROC(enter_lp2) ENTRY(exit_lp2) @@ -402,9 +406,13 @@ reset_poll: str r0, [r10, r1] //Unlock CPU0 str r0, [r10, r2] //Unlock CPU1 - //Make sure we no longer powergate the CPU island when halting. + //Make sure we no longer powergate the CPU island when halting, + // and disable Wait-for-WFE mechanism ldr r1, [r6, #FLOW_CTLR_CPU_CSR_0] bic r1, r1, #(1<<0) + bic r1, r1, #(1<<4) // Clear CPU0 WFE bit mask + bic r1, r1, #(1<<5) // Clear CPU1 WFE bit mask + orr r1, r1, #(1<<14) // Clear Event Flag (WC) str r1, [r6, #FLOW_CTLR_CPU_CSR_0] //Restore the input parameters passed to enter_lp2 diff --git a/arch/arm/mach-tegra/power-t2.c b/arch/arm/mach-tegra/power-t2.c index d4f2f73a50d0..2a15fc48e84a 100644 --- a/arch/arm/mach-tegra/power-t2.c +++ b/arch/arm/mach-tegra/power-t2.c @@ -269,6 +269,7 @@ void cpu_ap20_do_lp2(void) //Restore burst policy NV_REGW(s_hRmGlobal, NvRmPrivModuleID_ClockAndReset, 0, CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0, g_currentCcbp); + NvOsWaitUS(2); //Restore the CoreSight clock source. NV_REGW(s_hRmGlobal, NvRmPrivModuleID_ClockAndReset, 0, |