diff options
| author | Dong Aisheng <b29396@freescale.com> | 2014-08-06 13:04:09 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2014-08-06 16:56:33 +0800 |
| commit | ef3bce5feb2ed36c9f4483287454d35ae330dbe3 (patch) | |
| tree | 12cf32bd809423852793347cea322e56876ac51f | |
| parent | 789d6703b1372ec59ddf65a7bc87bf28f9186acd (diff) | |
ENGR00324668 mmc: core: add delay for SD3.0 UHS mode switch
We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition table
The root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.
So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
| -rw-r--r-- | drivers/mmc/core/sd.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 353b844c2722..398eee195cd3 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -514,6 +514,13 @@ static int sd_set_bus_speed_mode(struct mmc_card *card, u8 *status) else { mmc_set_timing(card->host, timing); mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr); + + /* + * FIXME: Sandisk SD3.0 cards DDR50 mode requires such + * delay to get stable, without this delay we may encounter + * CRC errors after switch to DDR50 mode + */ + mmc_delay(100); } return 0; |