diff options
| author | Manoj Chourasia <mchourasia@nvidia.com> | 2011-09-19 16:25:57 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-09-21 20:17:42 -0700 |
| commit | 7c3e671d05fcabdac4e73adf8f3f297924d44498 (patch) | |
| tree | 4fce74fdf625398ba078e968e090f9f8f0e60b05 | |
| parent | 10f747a674951ef977f4cc66767ade1b6caa6565 (diff) | |
tegra: p852: Add initial support of p852 platform
This patch adds initial support for p852 platform
bug 872849
Signed-off-by: Manoj Chourasia<mchourasia@nvidia.com>
Change-Id: Ifab059cfebb0c30cd85eac66618e283d1b45ec04
Reviewed-on: http://git-master/r/46397
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
25 files changed, 4399 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/p852/Kconfig b/arch/arm/mach-tegra/p852/Kconfig new file mode 100644 index 000000000000..ca44f9543be2 --- /dev/null +++ b/arch/arm/mach-tegra/p852/Kconfig @@ -0,0 +1,110 @@ +config MACH_P852 + bool "P852 board" + depends on ARCH_TEGRA_2x_SOC + help + Support for NVIDIA P852 platform + +config P852_SKU1 + bool "P852 SKU1 board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU1 platform + +config P852_SKU1_B00 + bool "P852 SKU1 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU1 B00 platform + +config P852_SKU1_C0x + bool "P852 SKU1 rev C boards" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU1 C0x platform + +config P852_SKU3 + bool "P852 SKU3 board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU3 platform + +config P852_SKU5_B00 + bool "P852 SKU5 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU5 B00 platform + +config P852_SKU5_C01 + bool "P852 SKU5 rev C board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU5 C01 platform + +config P852_SKU8_B00 + bool "P852 SKU8 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU8 B00 platform + +config P852_SKU8_C01 + bool "P852 SKU8 rev C board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU8 C01 platform + +config P852_SKU9_B00 + bool "P852 SKU9 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU9 B00 platform + +config P852_SKU9_C01 + bool "P852 SKU9 rev C board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU9 C01 platform + +config P852_SKU13 + bool "P852 SKU13 board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU13 platform + +config P852_SKU13_B00 + bool "P852 SKU13 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU23 B00 platform + +config P852_SKU23 + bool "P852 SKU23 board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU23 platform + +config P852_SKU23_B00 + bool "P852 SKU23 rev B board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU23 B00 platform + +config P852_SKU23_C01 + bool "P852 SKU23 rev C board" + depends on MACH_P852 + default MACH_P852 + help + Support for NVIDIA P852 SKU23 C01 platform diff --git a/arch/arm/mach-tegra/p852/Makefile b/arch/arm/mach-tegra/p852/Makefile new file mode 100644 index 000000000000..2f04ba08f71f --- /dev/null +++ b/arch/arm/mach-tegra/p852/Makefile @@ -0,0 +1,39 @@ +# +# arch/arm/mach-tegra/p852/Makefile +# +# Copyright (c) 2010-2011, NVIDIA Corporation. +# +# This software is licensed under the terms of the GNU General Public +# License version 2, as published by the Free Software Foundation, and +# may be copied, distributed, and modified under those terms. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# + +obj-${CONFIG_MACH_P852} += board-p852.o +obj-${CONFIG_MACH_P852} += board-p852-sdhci.o +obj-${CONFIG_MACH_P852} += board-p852-i2c.o +obj-${CONFIG_MACH_P852} += board-p852-power.o +obj-${CONFIG_MACH_P852} += board-p852-pinmux.o +obj-${CONFIG_MACH_P852} += board-p852-gpio.o +obj-${CONFIG_MACH_P852} += board-p852-panel.o + +obj-${CONFIG_P852_SKU1} += board-p852-sku1.o +obj-${CONFIG_P852_SKU1_B00} += board-p852-sku1-b00.o +obj-${CONFIG_P852_SKU1_C0x} += board-p852-sku1-c0x.o +obj-${CONFIG_P852_SKU3} += board-p852-sku3.o +obj-${CONFIG_P852_SKU5_B00} += board-p852-sku5-b00.o +obj-${CONFIG_P852_SKU5_C01} += board-p852-sku5-c01.o +obj-${CONFIG_P852_SKU8_B00} += board-p852-sku8-b00.o +obj-${CONFIG_P852_SKU8_C01} += board-p852-sku8-c01.o +obj-${CONFIG_P852_SKU9_B00} += board-p852-sku9-b00.o +obj-${CONFIG_P852_SKU9_C01} += board-p852-sku9-c01.o +obj-${CONFIG_P852_SKU13} += board-p852-sku13.o +obj-${CONFIG_P852_SKU13_B00} += board-p852-sku13-b00.o +obj-${CONFIG_P852_SKU23} += board-p852-sku23.o +obj-${CONFIG_P852_SKU23_B00} += board-p852-sku23-b00.o +obj-${CONFIG_P852_SKU23_C01} += board-p852-sku23-c01.o diff --git a/arch/arm/mach-tegra/p852/board-p852-gpio.c b/arch/arm/mach-tegra/p852/board-p852-gpio.c new file mode 100644 index 000000000000..71f568087c5d --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-gpio.c @@ -0,0 +1,158 @@ +/* + * arch/arm/mach-tegra/board-p852-gpio.c + * + * Copyright (C) 2010-2011 NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/irq.h> + +#include "board-p852.h" + +static struct gpio p852_sku23_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_LOW, "usbpwr0_ena"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_LOW, "usbpwr1_ena"}, + {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"}, + {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"}, + {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"}, + {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"}, + {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"}, + {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"}, + {TEGRA_GPIO_PW4, GPIOF_IN, "w4"}, + {TEGRA_GPIO_PW5, GPIOF_IN, "w5"}, + {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"}, + {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"}, + {TEGRA_GPIO_PD5, GPIOF_IN, "d5"}, + {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"}, +}; + +static struct gpio p852_sku23_b00_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "usbpwr0_ena"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "usbpwr1_ena"}, + {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"}, + {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"}, + {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"}, + {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"}, + {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"}, + {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"}, + {TEGRA_GPIO_PW4, GPIOF_IN, "w4"}, + {TEGRA_GPIO_PW5, GPIOF_IN, "w5"}, + {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"}, + {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"}, + {TEGRA_GPIO_PD5, GPIOF_IN, "d5"}, + {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"}, +}; + +static struct gpio p852_sku5_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "usbpwr0_ena"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "usbpwr1_ena"}, + {TEGRA_GPIO_PA0, GPIOF_OUT_INIT_LOW, "a0"}, + {TEGRA_GPIO_PV2, GPIOF_OUT_INIT_HIGH, "v2"}, + {TEGRA_GPIO_PT4, GPIOF_OUT_INIT_LOW, "t4"}, + {TEGRA_GPIO_PD6, GPIOF_OUT_INIT_HIGH, "d6"}, + {TEGRA_GPIO_PI3, GPIOF_OUT_INIT_LOW, "i3"}, + {TEGRA_GPIO_PV3, GPIOF_OUT_INIT_HIGH, "v3"}, + {TEGRA_GPIO_PW4, GPIOF_IN, "w4"}, + {TEGRA_GPIO_PW5, GPIOF_IN, "w5"}, + {TEGRA_GPIO_PT1, GPIOF_OUT_INIT_LOW, "t1"}, + {TEGRA_GPIO_PW3, GPIOF_OUT_INIT_HIGH, "w3"}, + {TEGRA_GPIO_PD5, GPIOF_IN, "d5"}, + {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"}, + {TEGRA_GPIO_PS3, GPIOF_IN, "s3"}, +}; + +static struct gpio p852_sku8_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "w1"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "b2"}, +}; + +static struct gpio p852_sku13_b00_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_HIGH, "w1"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_HIGH, "b2"}, + {TEGRA_GPIO_PW2, GPIOF_IN, "w2"}, + {TEGRA_GPIO_PW3, GPIOF_IN, "w3"}, + {TEGRA_GPIO_PD5, GPIOF_OUT_INIT_LOW, "d5"}, + {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"}, + {TEGRA_GPIO_PN7, GPIOF_OUT_INIT_LOW, "n7"}, + {TEGRA_GPIO_PA6, GPIOF_OUT_INIT_HIGH, "a6"}, + {TEGRA_GPIO_PA7, GPIOF_OUT_INIT_HIGH, "a7"}, +}; + +static struct gpio p852_gpios[] = { + {TEGRA_GPIO_PW1, GPIOF_OUT_INIT_LOW, "w1"}, + {TEGRA_GPIO_PB2, GPIOF_OUT_INIT_LOW, "b2"}, + {TEGRA_GPIO_PW2, GPIOF_IN, "w2"}, + {TEGRA_GPIO_PW3, GPIOF_IN, "w3"}, + {TEGRA_GPIO_PD5, GPIOF_OUT_INIT_LOW, "d5"}, + {TEGRA_GPIO_PBB1, GPIOF_OUT_INIT_LOW, "bb1"}, + {TEGRA_GPIO_PN7, GPIOF_OUT_INIT_LOW, "n7"}, + {TEGRA_GPIO_PA6, GPIOF_OUT_INIT_HIGH, "a6"}, + {TEGRA_GPIO_PA7, GPIOF_OUT_INIT_HIGH, "a7"}, +}; + +void __init p852_gpio_init(void) +{ + int pin_count = 0; + int i; + struct gpio *gpios_info = NULL; + + switch (system_rev) { + case P852_SKU23: + { + gpios_info = p852_sku23_gpios; + pin_count = ARRAY_SIZE(p852_sku23_gpios); + } + break; + case P852_SKU23_B00: + case P852_SKU23_C01: + { + gpios_info = p852_sku23_b00_gpios; + pin_count = ARRAY_SIZE(p852_sku23_b00_gpios); + } + break; + case P852_SKU5_B00: + case P852_SKU5_C01: + { + gpios_info = p852_sku5_gpios; + pin_count = ARRAY_SIZE(p852_sku5_gpios); + } + break; + case P852_SKU8_B00: + case P852_SKU8_C01: + case P852_SKU9_B00: + case P852_SKU9_C01: + { + gpios_info = p852_sku8_gpios; + pin_count = ARRAY_SIZE(p852_sku8_gpios); + } + break; + case P852_SKU13_B00: + { + gpios_info = p852_sku13_b00_gpios; + pin_count = ARRAY_SIZE(p852_sku13_b00_gpios); + } + break; + default: + { + gpios_info = p852_gpios; + pin_count = ARRAY_SIZE(p852_gpios); + } + } + + gpio_request_array(gpios_info, pin_count); + for (i = 0; i < pin_count; i++) { + tegra_gpio_enable(gpios_info[i].gpio); + gpio_export(gpios_info[i].gpio, true); + } +} diff --git a/arch/arm/mach-tegra/p852/board-p852-i2c.c b/arch/arm/mach-tegra/p852/board-p852-i2c.c new file mode 100644 index 000000000000..041ec252b6c1 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-i2c.c @@ -0,0 +1,180 @@ +/* + * arch/arm/mach-tegra/board-p852-i2c.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/resource.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <linux/i2c.h> +#include <mach/pinmux.h> +#include <asm/mach-types.h> + +#include "board-p852.h" + +static struct resource i2c_resource1[] = { + [0] = { + .start = INT_I2C, + .end = INT_I2C, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C_BASE, + .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource2[] = { + [0] = { + .start = INT_I2C2, + .end = INT_I2C2, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C2_BASE, + .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource3[] = { + [0] = { + .start = INT_I2C3, + .end = INT_I2C3, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_I2C3_BASE, + .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource i2c_resource4[] = { + [0] = { + .start = INT_DVC, + .end = INT_DVC, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_DVC_BASE, + .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static const struct tegra_pingroup_config i2c2_ddc = { + .pingroup = TEGRA_PINGROUP_DDC, + .func = TEGRA_MUX_I2C2, +}; + +static const struct tegra_pingroup_config i2c_i2cp = { + .pingroup = TEGRA_PINGROUP_I2CP, + .func = TEGRA_MUX_I2C, +}; + +static struct tegra_i2c_platform_data p852_i2c1_platform_data = { + .adapter_nr = 0, + .bus_count = 1, + .bus_clk_rate = {400000}, +}; + +static struct tegra_i2c_platform_data p852_i2c2_platform_data = { + .adapter_nr = 1, + .bus_count = 1, + .bus_clk_rate = {100000}, + .bus_mux = {&i2c2_ddc}, + .bus_mux_len = {1}, +}; + +static struct tegra_i2c_platform_data p852_i2c3_platform_data = { + .adapter_nr = 2, + .bus_count = 1, + .bus_clk_rate = {400000}, +}; + +static struct tegra_i2c_platform_data p852_dvc_platform_data = { + .adapter_nr = 3, + .bus_count = 1, + .bus_clk_rate = {100000}, + .bus_mux = {&i2c_i2cp}, + .bus_mux_len = {1}, + .is_dvc = true, +}; + +struct platform_device tegra_i2c_device[] = { + { + .name = "tegra-i2c", + .id = 0, + .resource = i2c_resource1, + .num_resources = ARRAY_SIZE(i2c_resource1), + .dev = { + .platform_data = &p852_i2c1_platform_data, + }, + }, + { + .name = "tegra-i2c", + .id = 1, + .resource = i2c_resource2, + .num_resources = ARRAY_SIZE(i2c_resource2), + .dev = { + .platform_data = &p852_i2c2_platform_data, + }, + }, + { + .name = "tegra-i2c", + .id = 2, + .resource = i2c_resource3, + .num_resources = ARRAY_SIZE(i2c_resource3), + .dev = { + .platform_data = &p852_i2c3_platform_data, + }, + }, + { + .name = "tegra-i2c", + .id = 3, + .resource = i2c_resource4, + .num_resources = ARRAY_SIZE(i2c_resource4), + .dev = { + .platform_data = &p852_dvc_platform_data, + }, + } +}; + +void __init p852_i2c_set_default_clock(int adapter, unsigned long clock) +{ + if (adapter >= 0 && adapter < ARRAY_SIZE(tegra_i2c_device)) + ((struct tegra_i2c_platform_data *)tegra_i2c_device[adapter]. + dev.platform_data)->bus_clk_rate[0] = clock; +} + +void __init p852_i2c_init(void) +{ + int i; + unsigned int i2c_config = 0; + if (p852_sku_peripherals & P852_SKU_I2C_ENABLE) { + for (i = 0; i < P852_MAX_I2C; i++) { + i2c_config = + (p852_i2c_peripherals >> (P852_I2C_SHIFT * i)); + if (i2c_config & P852_I2C_ENABLE) + platform_device_register(&tegra_i2c_device[i]); + } + } +} diff --git a/arch/arm/mach-tegra/p852/board-p852-panel.c b/arch/arm/mach-tegra/p852/board-p852-panel.c new file mode 100644 index 000000000000..bfd35fa5da53 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-panel.c @@ -0,0 +1,191 @@ +/* + * arch/arm/mach-tegra/board-p852-panel.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/resource.h> +#include <linux/nvhost.h> +#include <linux/platform_device.h> +#include <asm/mach-types.h> +#include <mach/nvmap.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/dc.h> +#include <mach/fb.h> + +#include "board-p852.h" + +#define CARVEOUT_IRAM {\ + .name = "iram",\ + .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM,\ + .base = TEGRA_IRAM_BASE,\ + .size = TEGRA_IRAM_SIZE,\ + .buddy_size = 0, /* no buddy allocation for IRAM */\ +} + +static int p852_panel_enable(void) +{ + pr_info("%s\n", __func__); + return 0; +} + +static int p852_panel_disable(void) +{ + pr_info("%s\n", __func__); + return 0; +} + +static struct resource p852_disp_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_GENERAL, + .end = INT_DISPLAY_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY_BASE, + .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .start = 0, + .end = 0, + .flags = IORESOURCE_MEM, + }, +}; + +static struct tegra_dc_mode p852_panel_modes[] = { +/* Timings for the LG LB070WV4 panel */ + { + .pclk = 33230769, + + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + + .h_sync_width = 128, + .v_sync_width = 2, + + .h_back_porch = 88, + .v_back_porch = 30, + + .h_front_porch = 40, + .v_front_porch = 13, + + .h_active = 800, + .v_active = 480, + }, +}; + +static struct tegra_fb_data p852_fb_data = { + .win = 0, + .xres = 800, + .yres = 480, + .bits_per_pixel = 16, +}; + +static struct tegra_dc_out p852_disp_out = { + .type = TEGRA_DC_OUT_RGB, + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + + .modes = p852_panel_modes, + .n_modes = ARRAY_SIZE(p852_panel_modes), + + .enable = p852_panel_enable, + .disable = p852_panel_disable, +}; + +static struct tegra_dc_platform_data p852_disp_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &p852_disp_out, + .fb = &p852_fb_data, +}; + +static struct nvhost_device p852_disp_device = { + .name = "tegradc", + .id = 0, + .resource = p852_disp_resources, + .num_resources = ARRAY_SIZE(p852_disp_resources), + .dev = { + .platform_data = &p852_disp_pdata, + }, +}; + +static struct nvmap_platform_carveout p852_carveouts[] = { + [0] = CARVEOUT_IRAM, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, + .size = 0, + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data p852_nvmap_data = { + .carveouts = p852_carveouts, + .nr_carveouts = ARRAY_SIZE(p852_carveouts), +}; + +static struct platform_device p852_nvmap_device = { + .name = "tegra-nvmap", + .id = -1, + .dev = { + .platform_data = &p852_nvmap_data, + }, +}; + +static struct platform_device *p852_gfx_devices[] __initdata = { + &tegra_grhost_device, + &tegra_pwfm2_device, +}; + +int __init p852_panel_init(void) +{ + int err; + struct resource *res; + + pr_info("%s\n", __func__); + + p852_carveouts[1].base = tegra_carveout_start; + p852_carveouts[1].size = tegra_carveout_size; + + err = platform_device_register(&p852_nvmap_device); + if (err) + return err; + + err = platform_add_devices(p852_gfx_devices, + ARRAY_SIZE(p852_gfx_devices)); + + res = nvhost_get_resource_byname(&p852_disp_device, + IORESOURCE_MEM, "fbmem"); + + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + if (!err) + err = nvhost_device_register(&p852_disp_device); + + return err; +} diff --git a/arch/arm/mach-tegra/p852/board-p852-pinmux.c b/arch/arm/mach-tegra/p852/board-p852-pinmux.c new file mode 100644 index 000000000000..0ded989f7a13 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-pinmux.c @@ -0,0 +1,439 @@ +/* + * arch/arm/mach-tegra/board-p852-pinmux.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <mach/pinmux.h> +#include <asm/mach-types.h> + +#include "board-p852.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +#define P852_PAD_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_DISABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_18, \ + .pull_up = TEGRA_PULL_22, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +#define P852_PAD_DRIVE_HSM(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_ENABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +#define DAP_PAD_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_3, \ + .pull_up = TEGRA_PULL_3, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +static __initdata struct tegra_drive_pingroup_config p852_drive_pinmux[] = { + DEFAULT_DRIVE(DBG), + DEFAULT_DRIVE(DDC), + DEFAULT_DRIVE(VI1), + DEFAULT_DRIVE(VI2), + DEFAULT_DRIVE(SDIO1), + P852_PAD_DRIVE(SPI), + DAP_PAD_DRIVE(DAP1), + DAP_PAD_DRIVE(DAP2), + DEFAULT_DRIVE(CDEV1), + DEFAULT_DRIVE(CDEV2), +}; + +static __initdata struct tegra_drive_pingroup_config + p852_drive_pinmux_sku8_sku9[] = { + DAP_PAD_DRIVE(DAP3), +}; + + +static __initdata struct tegra_pingroup_config p852_common_pinmux[] = { + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_SPI3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTE, TEGRA_MUX_SPI1, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + /* IRDA is same as UART2 option for the pingroup */ + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_SDIO2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_SPDIF, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_SPI2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAC, TEGRA_MUX_OWR, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_KBC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_OWC, TEGRA_MUX_RSVD2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPV, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PTA, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_nand_pinmux[] = { + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_UARTB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATA, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE}, +}; + +static __initdata struct tegra_pingroup_config p852_sdio3_pinmux[] = { + {TEGRA_PINGROUP_SDD, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_SDIO3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_uarta_pinmux[] = { + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, +}; + +static __initdata struct tegra_pingroup_config p852_ulpi_pinmux[] = { + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_uarta_1_pinmux[] = { + {TEGRA_PINGROUP_UAA, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, +}; + +static __initdata struct tegra_pingroup_config p852_uartd_pinmux[] = { + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_spi4_pinmux[] = { + {TEGRA_PINGROUP_GMC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_PCIE, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPDIF, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_spi4_1_pinmux[] = { + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_nor_pinmux[] = { + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UCB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_display_a_pinmux[] = { + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE}, +}; + +static __initdata struct tegra_pingroup_config p852_display_b_pinmux[] = { + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDC, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_drive_pingroup_config + p852_drive_pinmux_sku23[] = { + P852_PAD_DRIVE_HSM(SDMMC3), +}; + +static __initdata struct tegra_drive_pingroup_config + p852_drive_pinmux_sku13[] = { + P852_PAD_DRIVE_HSM(SDMMC3), +}; + +static __initdata struct tegra_pingroup_config p852_pupd_sku23[] = { + {TEGRA_PINGROUP_GPV, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMC, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +}; + + +static __initdata struct tegra_pingroup_config p852_pupd_sku13[] = { + {TEGRA_PINGROUP_GPV, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +}; + +static __initdata struct tegra_pingroup_config p852_pupd_sku5[] = { + {TEGRA_PINGROUP_GMC, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DTB, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +}; + +static void tegra_pinmux_config_pupd_table( + const struct tegra_pingroup_config *config, + int len) +{ + int i; + for (i = 0; i < len; i++) { + /* config.func, the pin_mux setting is not used here */ + tegra_pinmux_config_pullupdown_table(&config[i], 1, + config[i].pupd); + } +} + +void __init p852_pinmux_init(void) +{ + unsigned int sdio3_config = (p852_sdhci_peripherals >> + P852_SDHCI3_SHIFT) & P852_SDHCI_MASK; + unsigned int uartd_config = (p852_uart_peripherals >> P852_UARTD_SHIFT) + & P852_UART_MASK; + unsigned int uarta_config = (p852_uart_peripherals >> P852_UARTA_SHIFT) + & P852_UART_MASK; + unsigned int spi4_config = (p852_spi_peripherals >> P852_SPI4_SHIFT) + & P852_SPI_MASK; + unsigned int displayb_config = (p852_display_peripherals >> + P852_DISPB_SHIFT) & P852_DISP_MASK; + + tegra_pinmux_config_table(p852_common_pinmux, + ARRAY_SIZE(p852_common_pinmux)); + + if ((uarta_config & P852_UART_ENABLE) + && (uarta_config & P852_UART_ALT_PIN_CFG)) { + tegra_pinmux_config_table(p852_uarta_1_pinmux, + ARRAY_SIZE(p852_uarta_1_pinmux)); + } else { + tegra_pinmux_config_table(p852_ulpi_pinmux, + ARRAY_SIZE(p852_ulpi_pinmux)); + } + + if (sdio3_config & P852_SDHCI_ENABLE) { + tegra_pinmux_config_table(p852_sdio3_pinmux, + ARRAY_SIZE(p852_sdio3_pinmux)); + } else { + tegra_pinmux_config_table(p852_uarta_pinmux, + ARRAY_SIZE(p852_uarta_pinmux)); + } + + if ((uartd_config & P852_UART_ENABLE) && + (spi4_config & P852_SPI_ENABLE)) { + tegra_pinmux_config_table(p852_uartd_pinmux, + ARRAY_SIZE(p852_uartd_pinmux)); + tegra_pinmux_config_table(p852_spi4_1_pinmux, + ARRAY_SIZE(p852_spi4_1_pinmux)); + } else { + tegra_pinmux_config_table(p852_spi4_pinmux, + ARRAY_SIZE(p852_spi4_pinmux)); + } + + if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) { + tegra_pinmux_config_table(p852_nor_pinmux, + ARRAY_SIZE(p852_nor_pinmux)); + } else { + tegra_pinmux_config_table(p852_nand_pinmux, + ARRAY_SIZE(p852_nand_pinmux)); + } + + if (p852_sku_peripherals & P852_SKU_DISPLAY_ENABLE) { + if (displayb_config) { + tegra_pinmux_config_table(p852_display_b_pinmux, + ARRAY_SIZE(p852_display_b_pinmux)); + } else { + tegra_pinmux_config_table(p852_display_a_pinmux, + ARRAY_SIZE(p852_display_a_pinmux)); + } + } + + tegra_drive_pinmux_config_table(p852_drive_pinmux, + ARRAY_SIZE(p852_drive_pinmux)); + + if (system_rev == P852_SKU23 || + system_rev == P852_SKU23_B00 || + system_rev == P852_SKU23_C01) { + tegra_drive_pinmux_config_table(p852_drive_pinmux_sku23, + ARRAY_SIZE(p852_drive_pinmux_sku23)); + + tegra_pinmux_config_pupd_table(p852_pupd_sku23, + ARRAY_SIZE(p852_pupd_sku23)); + } else if (system_rev == P852_SKU13 || + system_rev == P852_SKU13_B00) { + tegra_drive_pinmux_config_table(p852_drive_pinmux_sku13, + ARRAY_SIZE(p852_drive_pinmux_sku13)); + + tegra_pinmux_config_pupd_table(p852_pupd_sku13, + ARRAY_SIZE(p852_pupd_sku13)); + } else if (system_rev == P852_SKU5_B00 || system_rev == P852_SKU5_C01) { + tegra_pinmux_config_pupd_table(p852_pupd_sku5, + ARRAY_SIZE(p852_pupd_sku5)); + } else if (system_rev == P852_SKU8_B00 || system_rev == P852_SKU9_B00 || + system_rev == P852_SKU8_C01 || system_rev == P852_SKU9_C01) { + tegra_drive_pinmux_config_table(p852_drive_pinmux_sku8_sku9, + ARRAY_SIZE(p852_drive_pinmux_sku8_sku9)); + } + +} + + diff --git a/arch/arm/mach-tegra/p852/board-p852-power.c b/arch/arm/mach-tegra/p852/board-p852-power.c new file mode 100644 index 000000000000..6a71ce0e0093 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-power.c @@ -0,0 +1,233 @@ +/* + * arch/arm/mach-tegra/p852/board-p852-power.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/i2c.h> +#include <linux/pda_power.h> +#include <linux/platform_device.h> +#include <linux/resource.h> +#include <linux/regulator/machine.h> +#include <linux/mfd/tps6586x.h> +#include <linux/gpio.h> +#include <mach/suspend.h> +#include <linux/io.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> + +#include "board-p852.h" + +#define PMC_CTRL 0x0 +#define PMC_CTRL_INTR_LOW (1 << 17) + +static struct regulator_consumer_supply tps658621_sm0_supply[] = { + REGULATOR_SUPPLY("vdd_core", NULL), +}; +static struct regulator_consumer_supply tps658621_sm1_supply[] = { + REGULATOR_SUPPLY("vdd_cpu", NULL), +}; +static struct regulator_consumer_supply tps658621_sm2_supply[] = { + REGULATOR_SUPPLY("vdd_sm2", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo0_supply[] = { + REGULATOR_SUPPLY("vddio_pex_clk", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo1_supply[] = { + REGULATOR_SUPPLY("avdd_pll", NULL), + REGULATOR_SUPPLY("avdd_plla_pc", NULL), + REGULATOR_SUPPLY("avdd_pllm", NULL), + REGULATOR_SUPPLY("avdd_pllu", NULL), + REGULATOR_SUPPLY("avdd_pllx6", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo2_supply[] = { + REGULATOR_SUPPLY("vdd_rtc", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo3_supply[] = { + REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("avdd_usb_pll", NULL), + REGULATOR_SUPPLY("avdd_lvds", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo4_supply[] = { + REGULATOR_SUPPLY("avdd_osc", NULL), + REGULATOR_SUPPLY("vddio_sys", "panjit_touch"), +}; +static struct regulator_consumer_supply tps658621_ldo5_supply[] = { + REGULATOR_SUPPLY("vddio_lcd", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo6_supply[] = { + REGULATOR_SUPPLY("avdd_vdac", NULL), +}; +static struct regulator_consumer_supply tps658621_ldo7_supply[] = { + REGULATOR_SUPPLY("vddio_vi", NULL), + REGULATOR_SUPPLY("vdd_fuse", NULL), + REGULATOR_SUPPLY("vspi", "spi_tegra.0"), +}; +static struct regulator_consumer_supply tps658621_ldo8_supply[] = { + REGULATOR_SUPPLY("vddio_bb", NULL), + REGULATOR_SUPPLY("vmmc", "sdhci-tegra.0"), + REGULATOR_SUPPLY("vmmc", "sdhci-tegra.2"), +}; +static struct regulator_consumer_supply tps658621_ldo9_supply[] = { + REGULATOR_SUPPLY("vdd_ddr_rx", NULL), + REGULATOR_SUPPLY("vmmc", "sdhci-tegra.3"), +}; + +#define REGULATOR_INIT(_id, _minmv, _maxmv) \ + { \ + .constraints = { \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(tps658621_##_id##_supply),\ + .consumer_supplies = tps658621_##_id##_supply, \ + } + +static struct regulator_init_data sm0_data = REGULATOR_INIT(sm0, 725, 1500); +static struct regulator_init_data sm1_data = REGULATOR_INIT(sm1, 725, 1500); +static struct regulator_init_data sm2_data = REGULATOR_INIT(sm2, 3000, 4550); +static struct regulator_init_data ldo0_data = REGULATOR_INIT(ldo0, 1250, 3300); +static struct regulator_init_data ldo1_data = REGULATOR_INIT(ldo1, 725, 1500); +static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1225); +static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300); +static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 2475); +static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 3300); +static struct regulator_init_data ldo6_data = REGULATOR_INIT(ldo6, 1250, 3300); +static struct regulator_init_data ldo7_data = REGULATOR_INIT(ldo7, 1250, 3300); +static struct regulator_init_data ldo8_data = REGULATOR_INIT(ldo8, 1250, 3300); +static struct regulator_init_data ldo9_data = REGULATOR_INIT(ldo9, 1250, 3300); + + +static struct tps6586x_rtc_platform_data rtc_data = { + .irq = TEGRA_NR_IRQS + TPS6586X_INT_RTC_ALM1, + .cl_sel = 0, +}; + + +#define TPS_REG(_id, _data) \ + { \ + .id = TPS6586X_ID_##_id, \ + .name = "tps6586x-regulator", \ + .platform_data = _data, \ + } + +static struct tps6586x_subdev_info tps_devs[] = { + TPS_REG(SM_0, &sm0_data), + TPS_REG(SM_1, &sm1_data), + TPS_REG(SM_2, &sm2_data), + TPS_REG(LDO_0, &ldo0_data), + TPS_REG(LDO_1, &ldo1_data), + TPS_REG(LDO_2, &ldo2_data), + TPS_REG(LDO_3, &ldo3_data), + TPS_REG(LDO_4, &ldo4_data), + TPS_REG(LDO_5, &ldo5_data), + TPS_REG(LDO_6, &ldo6_data), + TPS_REG(LDO_7, &ldo7_data), + TPS_REG(LDO_8, &ldo8_data), + TPS_REG(LDO_9, &ldo9_data), + { + .id = 0, + .name = "tps6586x-rtc", + .platform_data = &rtc_data, + }, +}; + +static struct tps6586x_platform_data tps_platform = { + .irq_base = TEGRA_NR_IRQS, + .num_subdevs = ARRAY_SIZE(tps_devs), + .subdevs = tps_devs, + .gpio_base = TEGRA_NR_GPIOS, +}; + +static struct i2c_board_info __initdata p852_regulators[] = { + { + I2C_BOARD_INFO("tps6586x", 0x34), + .irq = INT_EXTERNAL_PMU, + .platform_data = &tps_platform, + }, +}; + +static struct tegra_suspend_platform_data p852_suspend_data = { + .cpu_timer = 2000, + .cpu_off_timer = 0, + .suspend_mode = TEGRA_SUSPEND_LP1, + .core_timer = 0x7e7e, + .core_off_timer = 0, + .separate_req = true, + .corereq_high = false, + .sysclkreq_high = true, + .wake_enb = TEGRA_WAKE_GPIO_PV2, + .wake_high = 0, + .wake_low = TEGRA_WAKE_GPIO_PV2, + .wake_any = 0, +}; + +static void p852_power_off(void) +{ + int ret; + + ret = tps6586x_power_off(); + if (ret) + pr_err("p852: failed to power off\n"); + + while (1) + ; +} + +void __init p852_power_off_init(void) +{ + pm_power_off = p852_power_off; +} + +static void __init tps6586x_rtc_preinit(void) +{ + int i; + struct tps6586x_rtc_platform_data *rtc_pdata; + + if (system_rev == P852_SKU23_B00 || + system_rev == P852_SKU23_C01 || + system_rev == P852_SKU13_B00 || + system_rev == P852_SKU5_B00 || + system_rev == P852_SKU5_C01) { + for (i = 0; i < tps_platform.num_subdevs; ++i) + if (!strcmp(tps_platform.subdevs[i].name, + "tps6586x-rtc")) + rtc_pdata = + (struct tps6586x_rtc_platform_data *) + (tps_platform.subdevs[i].platform_data); + rtc_pdata->cl_sel = TPS6586X_RTC_CL_SEL_1_5PF; + } +} + +int __init p852_regulator_init(void) +{ + void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + u32 pmc_ctrl; + + /* configure the power management controller to trigger PMU + * interrupts when low */ + pmc_ctrl = readl(pmc + PMC_CTRL); + writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); + i2c_register_board_info(3, p852_regulators, 1); + tegra_init_suspend(&p852_suspend_data); + + tps6586x_rtc_preinit(); + + return 0; +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sdhci.c b/arch/arm/mach-tegra/p852/board-p852-sdhci.c new file mode 100644 index 000000000000..28c9e10b9fe9 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sdhci.c @@ -0,0 +1,207 @@ +/* + * arch/arm/mach-tegra/board-p852-sdhci.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/resource.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <mach/irqs.h> +#include <mach/iomap.h> +#include <mach/sdhci.h> +#include <mach/pinmux.h> +#include <asm/mach-types.h> + +#include "board-p852.h" + +static struct resource sdhci_resource1[] = { + [0] = { + .start = INT_SDMMC1, + .end = INT_SDMMC1, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC1_BASE, + .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource2[] = { + [0] = { + .start = INT_SDMMC2, + .end = INT_SDMMC2, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC2_BASE, + .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource3[] = { + [0] = { + .start = INT_SDMMC3, + .end = INT_SDMMC3, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC3_BASE, + .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource sdhci_resource4[] = { + [0] = { + .start = INT_SDMMC4, + .end = INT_SDMMC4, + .flags = IORESOURCE_IRQ, + }, + [1] = { + .start = TEGRA_SDMMC4_BASE, + .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct tegra_sdhci_platform_data p852_sdhci_platform_data[] = { + { + .clk_id = NULL, + .force_hs = 0, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + }, + { + .clk_id = NULL, + .force_hs = 0, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + }, + { + .clk_id = NULL, + .force_hs = 0, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + }, + { + .clk_id = NULL, + .force_hs = 0, + .cd_gpio = -1, + .wp_gpio = -1, + .power_gpio = -1, + }, +}; + +static struct platform_device tegra_sdhci_device[] = { + { + .name = "sdhci-tegra", + .id = 0, + .resource = sdhci_resource1, + .num_resources = ARRAY_SIZE(sdhci_resource1), + .dev = { + .platform_data = &p852_sdhci_platform_data[0], + }, + }, + { + .name = "sdhci-tegra", + .id = 1, + .resource = sdhci_resource2, + .num_resources = ARRAY_SIZE(sdhci_resource2), + .dev = { + .platform_data = &p852_sdhci_platform_data[1], + }, + }, + { + .name = "sdhci-tegra", + .id = 2, + .resource = sdhci_resource3, + .num_resources = ARRAY_SIZE(sdhci_resource3), + .dev = { + .platform_data = &p852_sdhci_platform_data[2], + }, + }, + { + .name = "sdhci-tegra", + .id = 3, + .resource = sdhci_resource4, + .num_resources = ARRAY_SIZE(sdhci_resource4), + .dev = { + .platform_data = &p852_sdhci_platform_data[3], + }, + }, + +}; + +void __init p852_sdhci_init(void) +{ + + int i, count = 10; + int cd = 0, wp = 0, pw = 0; + static char gpio_name[12][10]; + unsigned int sdhci_config = 0; + + if (p852_sku_peripherals & P852_SKU_SDHCI_ENABLE) + for (i = 0; i < P852_MAX_SDHCI; i++) { + sdhci_config = + (p852_sdhci_peripherals >> (P852_SDHCI_SHIFT * i)); + cd = i * 3; + wp = cd + 1; + pw = wp + 1; + if (sdhci_config & P852_SDHCI_ENABLE) { + if (sdhci_config & P852_SDHCI_CD_EN) { + snprintf(gpio_name[cd], count, + "sdhci%d_cd", i); + gpio_request(p852_sdhci_platform_data + [i].cd_gpio, + gpio_name[cd]); + tegra_gpio_enable + (p852_sdhci_platform_data[i]. + cd_gpio); + } + + if (sdhci_config & P852_SDHCI_WP_EN) { + snprintf(gpio_name[wp], count, + "sdhci%d_wp", i); + gpio_request(p852_sdhci_platform_data + [i].wp_gpio, + gpio_name[wp]); + tegra_gpio_enable + (p852_sdhci_platform_data[i]. + wp_gpio); + } + + if (sdhci_config & P852_SDHCI_PW_EN) { + snprintf(gpio_name[pw], count, + "sdhci%d_pw", i); + gpio_request(p852_sdhci_platform_data + [i].power_gpio, + gpio_name[pw]); + tegra_gpio_enable + (p852_sdhci_platform_data[i]. + power_gpio); + } + + platform_device_register(&tegra_sdhci_device + [i]); + } + } +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c new file mode 100644 index 000000000000..1cd89c5dfd76 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-tegra/board-p852-sku1-b00.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku1_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku1_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku1_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku1_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS | P852_UART_ALT_PIN_CFG) + << P852_UARTA_SHIFT); +} + +static inline void p852_sku1_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPB_SHIFT); +} + +static inline void p852_sku1_b00_ulpi_init(void) +{ + p852_sku_peripherals |= P852_SKU_ULPI_DISABLE; +} + +static inline void p852_sku1_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku1_b00_init(void) +{ + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku1_b00_spi_init(); + p852_sku1_b00_i2s_init(); + p852_sku1_b00_uart_init(); + p852_sku1_b00_sdhci_init(); + p852_sku1_b00_i2c_init(); + p852_sku1_b00_display_init(); + p852_sku1_b00_ulpi_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c new file mode 100644 index 000000000000..4a783fb9b635 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c @@ -0,0 +1,98 @@ +/* + * arch/arm/mach-tegra/board-p852-sku1-c0x.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku1_c0x_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku1_c0x_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku1_c0x_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku1_c0x_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS | P852_UART_ALT_PIN_CFG) + << P852_UARTA_SHIFT); +} + +static inline void p852_sku1_c0x_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPB_SHIFT); +} + +static inline void p852_sku1_c0x_ulpi_init(void) +{ + p852_sku_peripherals |= P852_SKU_ULPI_DISABLE; +} + +static inline void p852_sku1_c0x_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku1_c0x_init(void) +{ + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku1_c0x_spi_init(); + p852_sku1_c0x_i2s_init(); + p852_sku1_c0x_uart_init(); + p852_sku1_c0x_sdhci_init(); + p852_sku1_c0x_i2c_init(); + p852_sku1_c0x_display_init(); + p852_sku1_c0x_ulpi_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1.c b/arch/arm/mach-tegra/p852/board-p852-sku1.c new file mode 100644 index 000000000000..387ba054bd84 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku1.c @@ -0,0 +1,89 @@ +/* + * arch/arm/mach-tegra/board-p852-sku1.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku1_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku1_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku1_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI4_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku1_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT); +} + +static inline void p852_sku1_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPB_SHIFT); +} + +static inline void p852_sku1_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku1_init(void) +{ + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku1_spi_init(); + p852_sku1_i2s_init(); + p852_sku1_uart_init(); + p852_sku1_sdhci_init(); + p852_sku1_i2c_init(); + p852_sku1_display_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c new file mode 100644 index 000000000000..2e1447019f0e --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c @@ -0,0 +1,119 @@ +/* + * arch/arm/mach-tegra/board-p852-sku13-b00.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku13_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku13_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) | + (P852_I2S_ENABLE << P852_I2S2_SHIFT); +} + +static inline void p852_sku13_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; +} + +static inline void p852_sku13_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE) << P852_UARTC_SHIFT); +} + +static inline void p852_sku13_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku13_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); + p852_i2c_set_default_clock(0, 40000); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PT5, + .active_state = 1, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PV7, + .active_state = 1, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku13_b00_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL); + /* cpld_gpio_dir2 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku13_b00_init(void) +{ + tegra_i2s_audio_pdata[0].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[0].mode = I2S_BIT_FORMAT_RJM; + tegra_i2s_audio_pdata[1].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[1].mode = I2S_BIT_FORMAT_RJM; + + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + + p852_sku13_b00_spi_init(); + p852_sku13_b00_i2s_init(); + p852_sku13_b00_uart_init(); + p852_sku13_b00_sdhci_init(); + p852_sku13_b00_i2c_init(); + p852_sku13_b00_display_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku13_b00_spi_i2s_init(); +#endif +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13.c b/arch/arm/mach-tegra/p852/board-p852-sku13.c new file mode 100644 index 000000000000..43dc9dbfcffa --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku13.c @@ -0,0 +1,117 @@ +/* + * arch/arm/mach-tegra/board-p852-sku13.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku13_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); + +} + +static inline void p852_sku13_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) | + (P852_I2S_ENABLE << P852_I2S2_SHIFT); +} + +static inline void p852_sku13_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; +} + +static inline void p852_sku13_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE) << P852_UARTC_SHIFT); +} + +static inline void p852_sku13_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku13_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); + p852_i2c_set_default_clock(0, 40000); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PS3, + .active_state = 0, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PS4, + .active_state = 0, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku13_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 and cpld_gpio_dir2*/ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku13_init(void) +{ + tegra_i2s_audio_pdata[0].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[0].mode = I2S_BIT_FORMAT_RJM; + tegra_i2s_audio_pdata[1].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[1].mode = I2S_BIT_FORMAT_RJM; + + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku13_spi_init(); + p852_sku13_i2s_init(); + p852_sku13_uart_init(); + p852_sku13_sdhci_init(); + p852_sku13_i2c_init(); + p852_sku13_display_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku13_spi_i2s_init(); +#endif +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c new file mode 100644 index 000000000000..ed5f4073c806 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-tegra/board-p852-sku23-b00.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku23_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku23_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) | + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT); +} + +static inline void p852_sku23_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; +} + +static inline void p852_sku23_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT); +} + +static inline void p852_sku23_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku23_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PT5, + .active_state = 1, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PV7, + .active_state = 1, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku23_b00_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL); + /* cpld_gpio_dir2 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku23_b00_init(void) +{ + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku23_b00_spi_init(); + p852_sku23_b00_i2s_init(); + p852_sku23_b00_uart_init(); + p852_sku23_b00_sdhci_init(); + p852_sku23_b00_i2c_init(); + p852_sku23_b00_display_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku23_b00_spi_i2s_init(); +#endif +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c new file mode 100644 index 000000000000..35b69cb06115 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c @@ -0,0 +1,87 @@ +/* + * arch/arm/mach-tegra/board-p852-sku23-c01.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku23_c01_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku23_c01_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) | + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT); +} + +static inline void p852_sku23_c01_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; +} + +static inline void p852_sku23_c01_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT); +} + +static inline void p852_sku23_c01_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku23_c01_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku23_c01_init(void) +{ + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku23_c01_spi_init(); + p852_sku23_c01_i2s_init(); + p852_sku23_c01_uart_init(); + p852_sku23_c01_sdhci_init(); + p852_sku23_c01_i2c_init(); + p852_sku23_c01_display_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23.c b/arch/arm/mach-tegra/p852/board-p852-sku23.c new file mode 100644 index 000000000000..00dcb386ba76 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku23.c @@ -0,0 +1,113 @@ +/* + * arch/arm/mach-tegra/board-p852-sku23.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void __init p852_sku23_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku23_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN) << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; +} + +static inline void p852_sku23_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) | + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT); +} + +static inline void p852_sku23_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT); +} + +static inline void p852_sku23_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku23_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PS3, + .active_state = 0, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PS4, + .active_state = 0, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku23_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 and cpld_gpio_dir2*/ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku23_init(void) +{ + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku23_spi_init(); + p852_sku23_i2s_init(); + p852_sku23_uart_init(); + p852_sku23_sdhci_init(); + p852_sku23_i2c_init(); + p852_sku23_display_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku23_spi_i2s_init(); +#endif +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku3.c b/arch/arm/mach-tegra/p852/board-p852-sku3.c new file mode 100644 index 000000000000..feffa2aacf7c --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku3.c @@ -0,0 +1,108 @@ +/* + * arch/arm/mach-tegra/board-p852-sku3.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku3_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku3_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= (P852_I2S_ENABLE << P852_I2S1_SHIFT) | + (P852_I2S_ENABLE << P852_I2S2_SHIFT); +} + +static inline void p852_sku3_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + (P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT); + + p852_sdhci_platform_data[1].is_8bit_supported = true; +} + +static inline void p852_sku3_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTC_SHIFT); +} + +static inline void p852_sku3_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); + p852_i2c_set_default_clock(0, 40000); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PS3, + .active_state = 0, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PS4, + .active_state = 0, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku3_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 and cpld_gpio_dir2*/ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_KBCB, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku3_init(void) +{ + tegra_i2s_audio_pdata[0].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[0].mode = I2S_BIT_FORMAT_RJM; + tegra_i2s_audio_pdata[1].dap_clk = "clk_dev1"; + tegra_i2s_audio_pdata[1].mode = I2S_BIT_FORMAT_RJM; + + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku3_spi_init(); + p852_sku3_i2s_init(); + p852_sku3_uart_init(); + p852_sku3_sdhci_init(); + p852_sku3_i2c_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku3_spi_i2s_init(); +#endif +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c new file mode 100644 index 000000000000..9368dcc3c7da --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c @@ -0,0 +1,115 @@ +/* + * arch/arm/mach-tegra/board-p852-sku5_b00.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku5_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku5_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) | + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT); +} + +static inline void p852_sku5_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE << P852_SDHCI1_SHIFT) | + (P852_SDHCI_ENABLE << P852_SDHCI2_SHIFT)); + + p852_sdhci_platform_data[1].is_8bit_supported = true; +} + +static inline void p852_sku5_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT); +} + +static inline void p852_sku5_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku5_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +#ifdef CONFIG_TEGRA_SPI_I2S +static struct tegra_spi_i2s_platform_data spi_i2s_data = { + .gpio_i2s = { + .gpio_no = TEGRA_GPIO_PT5, + .active_state = 1, + }, + .gpio_spi = { + .gpio_no = TEGRA_GPIO_PV7, + .active_state = 1, + }, + .spi_i2s_timeout_ms = 25, +}; + +static inline void p852_sku5_b00_spi_i2s_init(void) +{ + tegra_spi_i2s_device.platform_data = &spi_i2s_data; + /* cpld_gpio_dir1 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_PTA, TEGRA_TRI_NORMAL); + /* cpld_gpio_dir2 */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LVP0, TEGRA_TRI_NORMAL); + p852_spi_i2s_init(); +} +#endif + +void __init p852_sku5_b00_init(void) +{ + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku5_b00_spi_init(); + p852_sku5_b00_i2s_init(); + p852_sku5_b00_uart_init(); + p852_sku5_b00_sdhci_init(); + p852_sku5_b00_i2c_init(); + p852_sku5_b00_display_init(); + + p852_common_init(); + +#ifdef CONFIG_TEGRA_SPI_I2S + p852_sku5_b00_spi_i2s_init(); +#endif +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c new file mode 100644 index 000000000000..f9c8e72911b6 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c @@ -0,0 +1,93 @@ +/* + * arch/arm/mach-tegra/board-p852-sku5-c01.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku5_c01_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI2_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI3_SHIFT) | + ((P852_SPI_SLAVE | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku5_c01_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S1_SHIFT) | + ((P852_I2S_TDM | P852_I2S_ENABLE) << P852_I2S2_SHIFT); +} + +static inline void p852_sku5_c01_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; +} + +static inline void p852_sku5_c01_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE) << P852_UARTA_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT) | + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTC_SHIFT); +} + +static inline void p852_sku5_c01_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; + p852_display_peripherals |= + (P852_DISP_ENABLE << P852_DISPA_SHIFT); +} + +static inline void p852_sku5_c01_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C3_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +static inline void p852_sku5_c01_ulpi_init(void) +{ + p852_sku_peripherals |= P852_SKU_ULPI_DISABLE; +} + +void __init p852_sku5_c01_init(void) +{ + p852_sku_peripherals |= P852_SKU_NAND_ENABLE; + + p852_sku5_c01_spi_init(); + p852_sku5_c01_i2s_init(); + p852_sku5_c01_uart_init(); + p852_sku5_c01_sdhci_init(); + p852_sku5_c01_i2c_init(); + p852_sku5_c01_display_init(); + p852_sku5_c01_ulpi_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c new file mode 100644 index 000000000000..2cbae665e55a --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c @@ -0,0 +1,91 @@ +/* + * arch/arm/mach-tegra/board-p852-sku8-b00.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku8_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku8_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku8_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku8_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT); +} + +static inline void p852_sku8_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; +} + +static inline void p852_sku8_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + + +void __init p852_sku8_b00_init(void) +{ + tegra_tdm_audio_pdata[0].dap_port_num = 1; + tegra_tdm_audio_pdata[1].dap_port_num = 3; + + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku8_b00_spi_init(); + p852_sku8_b00_i2s_init(); + p852_sku8_b00_uart_init(); + p852_sku8_b00_sdhci_init(); + p852_sku8_b00_display_init(); + p852_sku8_b00_i2c_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c new file mode 100644 index 000000000000..04553c23d747 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c @@ -0,0 +1,90 @@ +/* + * arch/arm/mach-tegra/board-p852-sku8-c00.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku8_c00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku8_c00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku8_c00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku8_c00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT); +} + +static inline void p852_sku8_c00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; +} + +static inline void p852_sku8_c00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + + +void __init p852_sku8_c00_init(void) +{ + tegra_tdm_audio_pdata[0].dap_port_num = 1; + tegra_tdm_audio_pdata[1].dap_port_num = 3; + + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku8_c00_spi_init(); + p852_sku8_c00_i2s_init(); + p852_sku8_c00_uart_init(); + p852_sku8_c00_sdhci_init(); + p852_sku8_c00_display_init(); + p852_sku8_c00_i2c_init(); + + p852_common_init(); +} diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c new file mode 100644 index 000000000000..02729f6e130f --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c @@ -0,0 +1,96 @@ +/* + * arch/arm/mach-tegra/board-p852-sku9-b00.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku9_b00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku9_b00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku9_b00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku9_b00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT); +} + +static inline void p852_sku9_b00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; +} + +static inline void p852_sku9_b00_ulpi_init(void) +{ + p852_sku_peripherals |= P852_SKU_ULPI_DISABLE; +} + +static inline void p852_sku9_b00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku9_b00_init(void) +{ + tegra_i2s_audio_pdata[0].dap_port_num = 1; + tegra_i2s_audio_pdata[1].dap_port_num = 3; + + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku9_b00_spi_init(); + p852_sku9_b00_i2s_init(); + p852_sku9_b00_uart_init(); + p852_sku9_b00_sdhci_init(); + p852_sku9_b00_display_init(); + p852_sku9_b00_ulpi_init(); + p852_sku9_b00_i2c_init(); + + p852_common_init(); +} + diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c new file mode 100644 index 000000000000..8712473b335d --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c @@ -0,0 +1,95 @@ +/* + * arch/arm/mach-tegra/board-p852-sku9-c00.c + * + * Copyright (C) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" + +static inline void p852_sku9_c00_spi_init(void) +{ + p852_sku_peripherals |= P852_SKU_SPI_ENABLE; + p852_spi_peripherals |= + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI1_SHIFT) | + ((P852_SPI_MASTER | P852_SPI_ENABLE) << P852_SPI4_SHIFT); +} + +static inline void p852_sku9_c00_i2s_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2S_ENABLE; + p852_i2s_peripherals |= ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S1_SHIFT) | ((P852_I2S_ENABLE | P852_I2S_TDM) + << P852_I2S2_SHIFT); +} + +static inline void p852_sku9_c00_sdhci_init(void) +{ + p852_sku_peripherals |= P852_SKU_SDHCI_ENABLE; + p852_sdhci_peripherals |= + ((P852_SDHCI_ENABLE) + << P852_SDHCI4_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI1_SHIFT) | + ((P852_SDHCI_ENABLE | P852_SDHCI_CD_EN | P852_SDHCI_WP_EN) + << P852_SDHCI3_SHIFT); + + p852_sdhci_platform_data[0].cd_gpio = TEGRA_GPIO_PV0; + p852_sdhci_platform_data[0].wp_gpio = TEGRA_GPIO_PV1; + p852_sdhci_platform_data[2].cd_gpio = TEGRA_GPIO_PD7; + p852_sdhci_platform_data[2].wp_gpio = TEGRA_GPIO_PT4; +} + +static inline void p852_sku9_c00_uart_init(void) +{ + p852_sku_peripherals |= P852_SKU_UART_ENABLE; + p852_uart_peripherals |= + ((P852_UART_ENABLE | P852_UART_DB) << P852_UARTD_SHIFT) | + ((P852_UART_ENABLE | P852_UART_HS) << P852_UARTB_SHIFT); +} + +static inline void p852_sku9_c00_display_init(void) +{ + p852_sku_peripherals |= P852_SKU_DISPLAY_ENABLE; +} + +static inline void p852_sku9_c00_ulpi_init(void) +{ + p852_sku_peripherals |= P852_SKU_ULPI_DISABLE; +} + +static inline void p852_sku9_c00_i2c_init(void) +{ + p852_sku_peripherals |= P852_SKU_I2C_ENABLE; + p852_i2c_peripherals |= + ((P852_I2C_ENABLE) << P852_I2C1_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C2_SHIFT) | + ((P852_I2C_ENABLE) << P852_I2C4_SHIFT); +} + +void __init p852_sku9_c00_init(void) +{ + tegra_i2s_audio_pdata[0].dap_port_num = 1; + tegra_i2s_audio_pdata[1].dap_port_num = 3; + + p852_sku_peripherals |= P852_SKU_NOR_ENABLE; + + p852_sku9_c00_spi_init(); + p852_sku9_c00_i2s_init(); + p852_sku9_c00_uart_init(); + p852_sku9_c00_sdhci_init(); + p852_sku9_c00_display_init(); + p852_sku9_c00_ulpi_init(); + p852_sku9_c00_i2c_init(); + + p852_common_init(); +} diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c new file mode 100644 index 000000000000..4bc8b9d6d0e0 --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852.c @@ -0,0 +1,1015 @@ +/* + * arch/arm/mach-tegra/board-p852.c + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "board-p852.h" +#include <mach/spdif.h> +#include <mach/tegra_das.h> + +unsigned int p852_sku_peripherals; +unsigned int p852_spi_peripherals; +unsigned int p852_i2s_peripherals; +unsigned int p852_uart_peripherals; +unsigned int p852_i2c_peripherals; +unsigned int p852_sdhci_peripherals; +unsigned int p852_display_peripherals; + +/* If enable_usb3 can have two options ehci3=eth or usb*/ +static char enable_usb3[4]; + +int __init parse_enable_usb3(char *arg) +{ + if (!arg) + return 0; + + strncpy(enable_usb3, arg, sizeof(enable_usb3)); + return 0; +} + +early_param("ehci3", parse_enable_usb3); + +static __initdata struct tegra_clk_init_table p852_clk_init_table[] = { + /* name parent rate enabled */ + {"uarta", "pll_p", 216000000, true}, + {"uartb", "pll_p", 216000000, true}, + {"uartc", "pll_p", 216000000, true}, + {"uartd", "pll_p", 216000000, true}, + {"pll_m", "clk_m", 600000000, true}, + {"pll_m_out1", "pll_m", 240000000, true}, + {"pll_p_out4", "pll_p", 240000000, true}, + {"host1x", "pll_p", 166000000, true}, + {"disp1", "pll_p", 216000000, true}, + {"vi", "pll_m", 100000000, true}, + {"csus", "pll_m", 100000000, true}, + {"emc", "pll_m", 600000000, true}, + {"pll_c", "clk_m", 600000000, true}, + {"pll_c_out1", "pll_c", 240000000, true}, + {"pwm", "clk_32k", 32768, false}, + {"clk_32k", NULL, 32768, true}, + {"pll_a", NULL, 56448000, true}, + {"pll_a_out0", "pll_a", 11289600, true}, + {"audio", "pll_a_out0", 11289600, true}, + {"audio_2x", "audio", 22579200, false}, + {"vde", "pll_c", 240000000, false}, + {"vi_sensor", "pll_m", 111000000, true}, + {"epp", "pll_m", 111000000, true}, + {"mpe", "pll_m", 111000000, true}, + {"i2s1", "pll_a_out0", 11289600, true}, + {"i2s2", "pll_a_out0", 11289600, true}, + {"ndflash", "pll_p", 86500000, true}, + {"sbc1", "pll_p", 12000000, false}, + {"spdif_in", "pll_m", 22579000, true}, + {"spdif_out", "pll_a_out0", 5644800, true}, + {"sbc2", "pll_p", 12000000, false}, + {"sbc3", "pll_p", 12000000, false}, + {"sbc4", "pll_p", 12000000, false}, + {"nor", "pll_p", 86500000, true}, + {NULL, NULL, 0, 0}, +}; + +struct tegra_audio_platform_data tegra_i2s_audio_pdata[] = { + /* For I2S1 */ + [0] = { + .i2s_master = false, + .dma_on = true, /* use dma by default */ + .dev_clk_rate = 2822400, + .dap_clk = "", + .audio_sync_clk = "audio_2x", + .mode = AUDIO_FRAME_FORMAT_I2S, + .fifo_fmt = I2S_FIFO_PACKED, + .bit_size = I2S_BIT_SIZE_16, + .i2s_bus_width = 32, + }, + /* For I2S2 */ + [1] = { + .i2s_master = true, + .dma_on = true, /* use dma by default */ + .dev_clk_rate = 2822400, + .dap_clk = "", + .audio_sync_clk = "audio_2x", + .mode = AUDIO_FRAME_FORMAT_I2S, + .fifo_fmt = I2S_FIFO_PACKED, + .bit_size = I2S_BIT_SIZE_16, + .i2s_bus_width = 32, + }, +}; + +struct tegra_audio_platform_data tegra_tdm_audio_pdata[] = { + /* For TDM1 */ + [0] = { + .tdm_enable = true, + .total_slots = 4, + .tdm_bitsize = 32, + .rx_bit_offset = 0, + .tx_bit_offset = 0, + .fsync_width = 32, + .rx_slot_enables = 0xff, + .tx_slot_enables = 0xff, + .mode = AUDIO_FRAME_FORMAT_TDM, + .i2s_bus_width = 32, + }, + /* For TDM2 */ + [1] = { + .dma_on = true, /* use dma by default */ + .tdm_enable = true, + .total_slots = 8, + .tdm_bitsize = 32, + .rx_bit_offset = 0, + .tx_bit_offset = 0, + .fsync_width = 32, + .rx_slot_enables = 0xff, + .tx_slot_enables = 0xff, + .mode = AUDIO_FRAME_FORMAT_TDM, + .i2s_bus_width = 32, + }, +}; + +#ifdef CONFIG_EMBEDDED_TEGRA_ALSA_SPDIF +static struct tegra_audio_platform_data tegra_spdif_audio_pdata = { + .tdm_enable = true, + .total_slots = 4, + .dma_on = 0, + .fifo_fmt = 0, + .mode = SPDIF_BIT_MODE_MODE16BIT, +}; +#endif + +static struct tegra_nand_chip_parms nand_chip_parms[] = { + /* Micron 29F4G08ABADA */ + [0] = { + .vendor_id = 0x2C, + .device_id = 0xDC, + .capacity = 512, + .read_id_fourth_byte = 0x95, + .timing = { + .trp = 1, + .trh = 1, + .twp = 12, + .twh = 12, + .tcs = 24, + .twhr = 58, + .tcr_tar_trr = 12, + .twb = 116, + .trp_resp = 24, + .tadl = 24, + }, + }, + /* Micron 29F4G16ABADA */ + [1] = { + .vendor_id = 0x2C, + .device_id = 0xCC, + .capacity = 512, + .read_id_fourth_byte = 0xD5, + .timing = { + .trp = 10, + .trh = 7, + .twp = 10, + .twh = 7, + .tcs = 15, + .twhr = 60, + .tcr_tar_trr = 20, + .twb = 100, + .trp_resp = 20, + .tadl = 70, + }, + }, + /* Hynix HY27UF084G2B */ + [2] = { + .vendor_id = 0xAD, + .device_id = 0xDC, + .read_id_fourth_byte = 0x95, + .capacity = 512, + .timing = { + .trp = 12, + .trh = 1, + .twp = 12, + .twh = 0, + .tcs = 24, + .twhr = 58, + .tcr_tar_trr = 0, + .twb = 116, + .trp_resp = 24, + .tadl = 24, + }, + }, +}; + +struct tegra_nand_platform p852_nand_data = { + .max_chips = 8, + .chip_parms = nand_chip_parms, + .nr_chip_parms = ARRAY_SIZE(nand_chip_parms), + .wp_gpio = TEGRA_GPIO_PC7, +}; + +static struct resource resources_nand[] = { + [0] = { + .start = INT_NANDFLASH, + .end = INT_NANDFLASH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device p852_nand_device = { + .name = "tegra_nand", + .id = -1, + .num_resources = ARRAY_SIZE(resources_nand), + .resource = resources_nand, + .dev = { + .platform_data = &p852_nand_data, + }, +}; + +unsigned int p852_uart_irqs[] = { + INT_UARTA, + INT_UARTB, + INT_UARTC, + INT_UARTD, +}; + +unsigned int p852_uart_bases[] = { + TEGRA_UARTA_BASE, + TEGRA_UARTB_BASE, + TEGRA_UARTC_BASE, + TEGRA_UARTD_BASE, +}; + +static struct platform_device *p852_spi_devices[] __initdata = { + &tegra_spi_device1, + &tegra_spi_device2, + &tegra_spi_device3, + &tegra_spi_device4, +}; + +static struct plat_serial8250_port debug_uart_platform_data[] = { + { + .flags = UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 216000000, + }, + { + .flags = 0, + } +}; + +#define DEF_8250_PLATFORM_DATA(_base, _irq) { \ + .flags = UPF_BOOT_AUTOCONF, \ + .iotype = UPIO_MEM, \ + .membase = IO_ADDRESS(_base), \ + .mapbase = _base, \ + .irq = _irq, \ + .regshift = 2, \ + .uartclk = 216000000, \ +} + +static struct plat_serial8250_port tegra_8250_uarta_platform_data[] = { + DEF_8250_PLATFORM_DATA(TEGRA_UARTA_BASE, INT_UARTA), + { + .flags = 0, + } +}; + +static struct plat_serial8250_port tegra_8250_uartb_platform_data[] = { + DEF_8250_PLATFORM_DATA(TEGRA_UARTB_BASE, INT_UARTB), + { + .flags = 0, + } +}; + +static struct plat_serial8250_port tegra_8250_uartc_platform_data[] = { + DEF_8250_PLATFORM_DATA(TEGRA_UARTC_BASE, INT_UARTC), + { + .flags = 0, + } +}; + +static struct plat_serial8250_port tegra_8250_uartd_platform_data[] = { + DEF_8250_PLATFORM_DATA(TEGRA_UARTD_BASE, INT_UARTD), + { + .flags = 0, + } +}; + +static struct plat_serial8250_port tegra_8250_uarte_platform_data[] = { + DEF_8250_PLATFORM_DATA(TEGRA_UARTE_BASE, INT_UARTE), + { + .flags = 0, + } +}; + +struct platform_device tegra_8250_uarta_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = tegra_8250_uarta_platform_data, + }, +}; + +struct platform_device tegra_8250_uartb_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = tegra_8250_uartb_platform_data, + }, +}; + +struct platform_device tegra_8250_uartc_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = tegra_8250_uartc_platform_data, + }, +}; + +struct platform_device tegra_8250_uartd_device = { + .name = "serial8250", + .id = PLAT8250_DEV_FOURPORT, + .dev = { + .platform_data = tegra_8250_uartd_platform_data, + }, +}; + +struct platform_device tegra_8250_uarte_device = { + .name = "serial8250", + .id = PLAT8250_DEV_ACCENT, + .dev = { + .platform_data = tegra_8250_uarte_platform_data, + }, +}; + +static struct platform_device debug_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = debug_uart_platform_data, + }, +}; + +static struct tegra_utmip_config utmi_phy_config[] = { + [0] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 15, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, + [1] = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 8, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + }, +}; + +static struct tegra_ulpi_config ulpi_usb2_config = { + .reset_gpio = TEGRA_GPIO_PI5, +}; + +static struct tegra_ehci_platform_data tegra_ehci_pdata[] = { + [0] = { + .phy_config = &utmi_phy_config[0], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 0, + }, + [1] = { + .phy_config = &ulpi_usb2_config, + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 0, + .phy_type = TEGRA_USB_PHY_TYPE_LINK_ULPI, + }, + [2] = { + .phy_config = &utmi_phy_config[1], + .operating_mode = TEGRA_USB_HOST, + .power_down_on_bus_suspend = 0, + }, +}; + +static void p852_usb_gpio_config(void) +{ + unsigned int usbeth_mux_gpio = 0, usb_ena_val; + unsigned int has_onboard_ethernet = 0; + unsigned int p852_eth_reset = TEGRA_GPIO_PD3; + + switch (system_rev) { + case P852_SKU13_B00: + case P852_SKU23_B00: + case P852_SKU23_C01: + case P852_SKU8_B00: + case P852_SKU8_C01: + case P852_SKU9_B00: + case P852_SKU9_C01: + { + usbeth_mux_gpio = TEGRA_GPIO_PS3; + has_onboard_ethernet = 1; + usb_ena_val = 1; + } + break; + case P852_SKU5_B00: + case P852_SKU5_C01: + { + usb_ena_val = 1; + has_onboard_ethernet = 0; + } + break; + case P852_SKU1: + { + has_onboard_ethernet = 0; + usb_ena_val = 0; + strncpy(enable_usb3, "usb", sizeof(enable_usb3)); + } + break; + case P852_SKU1_B00: + case P852_SKU1_C0X: + { + has_onboard_ethernet = 0; + usb_ena_val = 1; + strncpy(enable_usb3, "usb", sizeof(enable_usb3)); + } + break; + default: + { + usbeth_mux_gpio = TEGRA_GPIO_PD4; + has_onboard_ethernet = 1; + usb_ena_val = 0; + } + } + + if (has_onboard_ethernet) { + gpio_request_one(usbeth_mux_gpio, GPIOF_OUT_INIT_LOW, + "eth_ena"); + tegra_gpio_enable(usbeth_mux_gpio); + + /* eth reset */ + gpio_request_one(p852_eth_reset, GPIOF_OUT_INIT_LOW, + "eth_reset"); + tegra_gpio_enable(p852_eth_reset); + udelay(1); + gpio_direction_output(p852_eth_reset, 1); + + if (!strcmp(enable_usb3, "eth")) + gpio_direction_output(usbeth_mux_gpio, 1); + + /* exporting usbeth_mux_gpio */ + gpio_export(usbeth_mux_gpio, true); + } + + if (!strcmp(enable_usb3, "usb")) { + gpio_direction_output(TEGRA_GPIO_PB2, usb_ena_val); + gpio_direction_output(TEGRA_GPIO_PW1, usb_ena_val); + } +} + +static struct platform_device *p852_uart_devices[] __initdata = { + &tegra_uarta_device, + &tegra_uartb_device, + &tegra_uartc_device, + &tegra_uartd_device, +}; + +static struct platform_device *p852_8250_uart_devices[] __initdata = { + &tegra_8250_uarta_device, + &tegra_8250_uartb_device, + &tegra_8250_uartc_device, + &tegra_8250_uartd_device, + &tegra_8250_uarte_device, +}; + +static struct platform_device tegra_itu656 = { + .name = "tegra_itu656", + .id = -1, +}; + +static struct platform_device *p852_devices[] __initdata = { + &pmu_device, + &tegra_gart_device, + &tegra_avp_device, + &tegra_itu656, +}; + +#ifdef CONFIG_MTD_NOR_TEGRA +static struct tegra_nor_chip_parms nor_chip_parms[] = { + [0] = { + .timing_default = { + .pg_rdy = 120, + .pg_seq = 35, + .mux = 5, + .hold = 25, + .adv = 50, + .ce = 35, + .we = 50, + .oe = 50, + .wait = 70, + }, + .timing_read = { + .pg_rdy = 120, + .pg_seq = 25, + .mux = 5, + .hold = 25, + .adv = 50, + .ce = 35, + .we = 5, + .oe = 120, + .wait = 5, + }, + }, +}; + +static struct flash_platform_data p852_flash = { + .map_name = "cfi_probe", + .width = 2, +}; + +static struct tegra_nor_platform p852_nor_data = { + .flash = &p852_flash, + .chip_parms = nor_chip_parms, + .nr_chip_parms = ARRAY_SIZE(nor_chip_parms), +}; + +static struct resource resources_nor[] = { + [0] = { + .start = INT_SNOR, + .end = INT_SNOR, + .flags = IORESOURCE_IRQ, + }, + [1] = { + /* Map the size of flash */ + .start = 0xd0000000, + .end = 0xd0000000 + SZ_64M - 1, + .flags = IORESOURCE_MEM, + } +}; + +struct platform_device p852_nor_device = { + .name = "tegra_nor", + .id = -1, + .num_resources = ARRAY_SIZE(resources_nor), + .resource = resources_nor, + .dev = { + .platform_data = &p852_nor_data, + .coherent_dma_mask = 0xffffffff, + }, +}; +#endif + +#ifdef CONFIG_TEGRA_SPI_I2S +struct spi_board_info tegra_spi_i2s_device __initdata = { + .modalias = "spi_i2s_pcm", + .bus_num = 2, + .chip_select = 2, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, +}; + +void __init p852_spi_i2s_init(void) +{ + struct tegra_spi_i2s_platform_data *pdata; + + pdata = (struct tegra_spi_i2s_platform_data *) + tegra_spi_i2s_device.platform_data; + if (pdata->gpio_i2s.active_state) { + gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_LOW, + "i2s_cpld_dir1"); + } else { + gpio_request_one(pdata->gpio_i2s.gpio_no, GPIOF_OUT_INIT_HIGH, + "i2s_cpld_dir1"); + } + tegra_gpio_enable(pdata->gpio_i2s.gpio_no); + if (pdata->gpio_spi.active_state) { + gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_LOW, + "spi_cpld_dir2"); + } else { + gpio_request_one(pdata->gpio_spi.gpio_no, GPIOF_OUT_INIT_HIGH, + "spi_cpld_dir2"); + } + + tegra_gpio_enable(pdata->gpio_spi.gpio_no); + spi_register_board_info(&tegra_spi_i2s_device, 1); +} +#endif + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .modalias = "spidev", + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 1, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, + { + .modalias = "spidev", + .bus_num = 3, + .chip_select = 1, + .mode = SPI_MODE_0, + .max_speed_hz = 18000000, + .platform_data = NULL, + .irq = 0, + }, +}; + +static void __init p852_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else +#define p852_register_spidev() do {} while (0) +#endif + +static void __init p852_usb_init(void) +{ + + p852_usb_gpio_config(); + /* + if (system_rev == P852_SKU8) + { + platform_device_register(&tegra_udc_device); + } + else + */ + { + tegra_ehci1_device.dev.platform_data = &tegra_ehci_pdata[0]; + platform_device_register(&tegra_ehci1_device); + } + + if (!(p852_sku_peripherals & P852_SKU_ULPI_DISABLE)) { + tegra_ehci2_device.dev.platform_data = &tegra_ehci_pdata[1]; + platform_device_register(&tegra_ehci2_device); + } + + tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata[2]; + platform_device_register(&tegra_ehci3_device); +} + +static void __init spi3_pingroup_clear_tristate(void) +{ + /* spi3 mosi, miso, cs, clk */ + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDI, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSDA, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LCSN, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_LSCK, TEGRA_TRI_NORMAL); +} + +static void __init p852_spi_init(void) +{ + if (p852_sku_peripherals & P852_SKU_SPI_ENABLE) { + int i = 0; + unsigned int spi_config = 0; + unsigned int spi3_config = + (p852_spi_peripherals >> P852_SPI3_SHIFT) & P852_SPI_MASK; + + for (i = 0; i < P852_MAX_SPI; i++) { + spi_config = + (p852_spi_peripherals >> (P852_SPI_SHIFT * i)) & + P852_SPI_MASK; + if (spi_config & P852_SPI_ENABLE) { + if (spi_config & P852_SPI_SLAVE) + p852_spi_devices[i]->name = + "tegra_spi_slave"; + platform_device_register(p852_spi_devices[i]); + } + } + /* Default spi3 pingroups are in tristate */ + if (spi3_config & P852_SPI_ENABLE) + spi3_pingroup_clear_tristate(); + } +} + +static void __init p852_uart_init(void) +{ + if (p852_sku_peripherals & P852_SKU_UART_ENABLE) { + int i = 0; + unsigned int uart_config = 0, uart8250Id = 0; + int debug_console = -1; + + /* register the debug console as the first serial console */ + for (i = 0; i < P852_MAX_UART; i++) { + uart_config = + (p852_uart_peripherals >> (P852_UART_SHIFT * i)); + if (uart_config & P852_UART_DB) { + debug_console = i; + debug_uart_platform_data[0].membase = + IO_ADDRESS(p852_uart_bases[i]); + debug_uart_platform_data[0].mapbase = + p852_uart_bases[i]; + debug_uart_platform_data[0].irq = + p852_uart_irqs[i]; + uart8250Id++; + platform_device_register(&debug_uart); + break; + } + } + + /* register remaining UARTS */ + for (i = 0; i < P852_MAX_UART; i++) { + uart_config = + (p852_uart_peripherals >> (P852_UART_SHIFT * i)) & + P852_UART_MASK; + if ((uart_config & P852_UART_ENABLE) + && i != debug_console) { + if (uart_config & P852_UART_HS) { + platform_device_register + (p852_uart_devices[i]); + } else { + p852_8250_uart_devices[i]->id = + uart8250Id++; + platform_device_register + (p852_8250_uart_devices[i]); + } + } + } + } +} + +struct tegra_das_platform_data tegra_das_pdata = { + .dap_clk = "clk_dev1", + .tegra_dap_port_info_table = { + /* I2S1 <--> DAC1 <--> DAP1 <--> Hifi Codec */ + [0] = { + .dac_port = tegra_das_port_i2s1, + .dap_port = tegra_das_port_dap1, + .codec_type = tegra_audio_codec_type_hifi, + .device_property = { + .num_channels = 8, + .bits_per_sample = 16, + .rate = 44100, + .dac_dap_data_comm_format = + dac_dap_data_format_rjm, + }, + }, + [1] = { + .dac_port = tegra_das_port_i2s2, + .dap_port = tegra_das_port_dap2, + .codec_type = tegra_audio_codec_type_hifi, + .device_property = { + .num_channels = 16, + .bits_per_sample = 16, + .rate = 44100, + .dac_dap_data_comm_format = + dac_dap_data_format_rjm, + }, + }, + [2] = { + .dac_port = tegra_das_port_none, + .dap_port = tegra_das_port_none, + .codec_type = tegra_audio_codec_type_none, + .device_property = { + .num_channels = 0, + .bits_per_sample = 0, + .rate = 0, + .dac_dap_data_comm_format = 0, + }, + }, + [3] = { + .dac_port = tegra_das_port_none, + .dap_port = tegra_das_port_none, + .codec_type = tegra_audio_codec_type_none, + .device_property = { + .num_channels = 0, + .bits_per_sample = 0, + .rate = 0, + .dac_dap_data_comm_format = + dac_dap_data_format_dsp, + }, + }, + [4] = { + .dac_port = tegra_das_port_none, + .dap_port = tegra_das_port_none, + .codec_type = tegra_audio_codec_type_none, + .device_property = { + .num_channels = 0, + .bits_per_sample = 0, + .rate = 0, + .dac_dap_data_comm_format = 0, + }, + }, + }, + .tegra_das_con_table = { + [0] = { + .con_id = tegra_das_port_con_id_hifi, + .num_entries = 4, + .con_line = { + [0] = {tegra_das_port_i2s1, + tegra_das_port_dap1, false}, + [1] = {tegra_das_port_dap1, + tegra_das_port_i2s1, true}, + [2] = {tegra_das_port_i2s2, + tegra_das_port_dap2, false}, + [3] = {tegra_das_port_dap2, + tegra_das_port_i2s2, true}, + }, + }, + } +}; + +static struct platform_device generic_codec_driver = { + .name = "generic-dit", +}; + +static void __init p852_audio_init(void) +{ + struct audio_dev_property *pdev_property; + + /* Using the Generic Codec Driver in Kernel */ + platform_device_register(&generic_codec_driver); + + if (p852_sku_peripherals & P852_SKU_I2S_ENABLE) { + unsigned int i2s_config1 = + (p852_i2s_peripherals >> P852_I2S1_SHIFT) & P852_I2S_MASK; + unsigned int i2s_config2 = + (p852_i2s_peripherals >> P852_I2S2_SHIFT) & P852_I2S_MASK; + if (i2s_config1 & P852_I2S_ENABLE) { + tegra_i2s_device1.dev.platform_data = + &tegra_i2s_audio_pdata[0]; + + if (i2s_config1 & P852_I2S_TDM) { + tegra_i2s_device1.dev.platform_data = + &tegra_tdm_audio_pdata[0]; + pdev_property = + &(tegra_das_pdata.tegra_dap_port_info_table[0].device_property); + pdev_property->dac_dap_data_comm_format = + dac_dap_data_format_tdm; + pdev_property = + &(tegra_das_pdata.tegra_dap_port_info_table[1].device_property); + pdev_property->dac_dap_data_comm_format = + dac_dap_data_format_tdm; + } + platform_device_register(&tegra_i2s_device1); + } + if (i2s_config2 & P852_I2S_ENABLE) { + tegra_i2s_device2.dev.platform_data = + &tegra_i2s_audio_pdata[1]; + + if (i2s_config2 & P852_I2S_TDM) { + tegra_i2s_device2.dev.platform_data = + &tegra_tdm_audio_pdata[1]; + } + platform_device_register(&tegra_i2s_device2); + } + } + tegra_das_device.dev.platform_data = &tegra_das_pdata; + platform_device_register(&tegra_das_device); +#ifdef CONFIG_EMBEDDED_TEGRA_ALSA_SPDIF + tegra_spdif_input_device.name = "spdif"; + tegra_spdif_input_device.dev.platform_data = &tegra_spdif_audio_pdata; + platform_device_register(&tegra_spdif_input_device); +#endif +} + +static void __init p852_flash_init(void) +{ + if (p852_sku_peripherals & P852_SKU_NAND_ENABLE) + platform_device_register(&p852_nand_device); +#ifdef CONFIG_MTD_NOR_TEGRA + if (p852_sku_peripherals & P852_SKU_NOR_ENABLE) + platform_device_register(&p852_nor_device); +#endif +} + +void __init p852_common_init(void) +{ + tegra_common_init(); + + tegra_clk_init_from_table(p852_clk_init_table); + + p852_pinmux_init(); + + p852_i2c_init(); + + p852_regulator_init(); + + p852_uart_init(); + + p852_flash_init(); + + p852_audio_init(); + + platform_add_devices(p852_devices, ARRAY_SIZE(p852_devices)); + + p852_panel_init(); + + p852_spi_init(); + + p852_register_spidev(); + + p852_usb_init(); + + p852_sdhci_init(); + + p852_gpio_init(); + + p852_power_off_init(); +} + +void __init tegra_p852_init(void) +{ + switch (system_rev) { + case P852_SKU3: + p852_sku3_init(); + break; + case P852_SKU13: + p852_sku13_init(); + break; + case P852_SKU13_B00: + case P852_SKU13_C01: + p852_sku13_b00_init(); + break; + case P852_SKU23: + p852_sku23_init(); + break; + case P852_SKU23_B00: + p852_sku23_b00_init(); + break; + case P852_SKU23_C01: + p852_sku23_c01_init(); + break; + case P852_SKU1: + p852_sku1_init(); + break; + case P852_SKU11: + case P852_SKU1_B00: + p852_sku1_b00_init(); + break; + case P852_SKU1_C0X: + p852_sku1_c0x_init(); + break; + case P852_SKU5_B00: + p852_sku5_b00_init(); + break; + case P852_SKU5_C01: + p852_sku5_c01_init(); + break; + case P852_SKU8_B00: + p852_sku8_b00_init(); + break; + case P852_SKU8_C01: + p852_sku8_c00_init(); + break; + case P852_SKU9_B00: + p852_sku9_b00_init(); + break; + case P852_SKU9_C01: + p852_sku9_c00_init(); + break; + default: + printk(KERN_ERR "Unknow Board Revision\n"); + break; + } +} + +static void __init tegra_p852_reserve(void) +{ + switch (system_rev) { + case P852_SKU3: + case P852_SKU5_B00: + case P852_SKU5_C01: + case P852_SKU9_B00: + case P852_SKU9_C01: + tegra_reserve(SZ_64M + SZ_16M, SZ_8M, 0); + break; + default: + tegra_reserve(SZ_128M, SZ_8M, 0); + break; + } +} + +MACHINE_START(P852, "Tegra P852") + .boot_params = 0x00000100, + .phys_io = IO_APB_PHYS, + .io_pg_offst = ((IO_APB_VIRT) >> 18) & 0xfffc, + .init_irq = tegra_init_irq, + .init_machine = tegra_p852_init, + .map_io = tegra_map_common_io, + .reserve = tegra_p852_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/p852/board-p852.h b/arch/arm/mach-tegra/p852/board-p852.h new file mode 100644 index 000000000000..6e304e37f0aa --- /dev/null +++ b/arch/arm/mach-tegra/p852/board-p852.h @@ -0,0 +1,303 @@ +/* + * arch/arm/mach-tegra/board-p852.h + * + * Copyright (c) 2010-2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_P852M_H +#define _MACH_TEGRA_BOARD_P852M_H + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/partitions.h> +#include <linux/dma-mapping.h> +#include <linux/io.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/spi/spi.h> +#include <linux/i2c-tegra.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/gpio.h> + +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/flash.h> + +#include <mach/sdhci.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/nand.h> +#include <mach/usb_phy.h> +#include <mach/clk.h> +#include <mach/i2s.h> +#include <mach/audio.h> +#include <mach/tegra_das.h> + +#include "../clock.h" +#include "../board.h" +#include "../devices.h" +#include "../gpio-names.h" +#include "../power.h" +#include "../wakeups-t2.h" + + +#define P852_SKU3 0x030000UL +#define P852_SKU13 0x130000UL +#define P852_SKU13_B00 0x130200UL +#define P852_SKU13_C01 0x130401UL +#define P852_SKU23 0x230000UL +#define P852_SKU23_B00 0x230200UL +#define P852_SKU23_C01 0x230401UL +#define P852_SKU1 0x010000UL +#define P852_SKU1_B00 0x010200UL +#define P852_SKU1_C0X 0x010400UL +#define P852_SKU11 0x110000UL +#define P852_SKU5_B00 0x040200UL +#define P852_SKU5_C01 0x050401UL +#define P852_SKU8_B00 0x080200UL +#define P852_SKU8_C01 0x080401UL +#define P852_SKU9_B00 0x090200UL +#define P852_SKU9_C01 0x090401UL + +int p852_regulator_init(void); +int p852_panel_init(void); +void p852_sdhci_init(void); +void p852_i2c_init(void); +void p852_i2c_set_default_clock(int adapter, unsigned long clock); +void p852_pinmux_init(void); +void p852_gpio_init(void); +void p852_power_off_init(void); + +void p852_sku1_init(void); +void p852_sku1_b00_init(void); +void p852_sku1_c0x_init(void); +void p852_sku3_init(void); +void p852_sku5_b00_init(void); +void p852_sku5_c01_init(void); +void p852_sku8_b00_init(void); +void p852_sku8_c00_init(void); +void p852_sku9_b00_init(void); +void p852_sku9_c00_init(void); +void p852_sku13_init(void); +void p852_sku13_b00_init(void); +void p852_sku23_init(void); +void p852_sku23_b00_init(void); +void p852_sku23_c01_init(void); + +#ifndef CONFIG_P852_SKU1 +void p852_sku1_init(void); +#endif +#ifndef CONFIG_P852_SKU1_B00 +void p852_sku1_b00_init(void); +#endif +#ifndef CONFIG_P852_SKU1_C0x +void p852_sku1_c0x_init(void); +#endif +#ifndef CONFIG_P852_SKU3 +void p852_sku3_init(void); +#endif +#ifndef CONFIG_P852_SKU5_B00 +void p852_sku5_b00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU5_C01 +void p852_sku5_c01_init(void){}; +#endif +#ifndef CONFIG_P852_SKU8_B00 +void p852_sku8_b00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU8_C01 +void p852_sku8_c00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU9_B00 +void p852_sku9_b00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU9_C01 +void p852_sku9_c00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU13 +void p852_sku13_init(void){}; +#endif +#ifndef CONFIG_P852_SKU13_B00 +void p852_sku13_b00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU23 +void p852_sku23_init(void){}; +#endif +#ifndef CONFIG_P852_SKU23_B00 +void p852_sku23_b00_init(void){}; +#endif +#ifndef CONFIG_P852_SKU23_C01 +void p852_sku23_c01_init(void){}; +#endif + +extern unsigned int system_rev; +extern unsigned int p852_sku_peripherals; +extern unsigned int p852_spi_peripherals; +extern unsigned int p852_i2s_peripherals; +extern unsigned int p852_uart_peripherals; +extern unsigned int p852_sdhci_peripherals; +extern unsigned int p852_display_peripherals; +extern unsigned int p852_i2c_peripherals; +extern struct tegra_sdhci_platform_data p852_sdhci_platform_data[]; +extern struct platform_device tegra_8250_uarta_device; +extern struct platform_device tegra_8250_uartb_device; +extern struct platform_device tegra_8250_uartc_device; +extern struct platform_device tegra_8250_uartd_device; +extern struct platform_device tegra_8250_uarte_device; +extern struct tegra_audio_platform_data tegra_i2s_audio_pdata[]; +extern struct tegra_audio_platform_data tegra_tdm_audio_pdata[]; + +#ifdef CONFIG_TEGRA_SPI_I2S +extern void p852_spi_i2s_init(void); +extern struct spi_board_info tegra_spi_i2s_device; +#endif + +void tegra_p852_fixup(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi); + +void p852_common_init(void); + +#define P852_SDIO3_PINMUX_ENABLE 0x01 + +#define P852_SKU_SPI_SHIFT 0x00 +#define P852_SKU_SPI_ENABLE (1 << P852_SKU_SPI_SHIFT) +#define P852_SKU_SPI_MASK (1 << P852_SKU_SPI_SHIFT) + +#define P852_SKU_I2S_SHIFT 0x01 +#define P852_SKU_I2S_ENABLE (1 << P852_SKU_I2S_SHIFT) +#define P852_SKU_I2S_MASK (1 << P852_SKU_I2S_SHIFT) + +#define P852_SKU_SDHCI_SHIFT 0x02 +#define P852_SKU_SDHCI_ENABLE (1 << P852_SKU_SDHCI_SHIFT) +#define P852_SKU_SDHCI_MASK (1 << P852_SKU_SDHCI_SHIFT) + +#define P852_SKU_UART_SHIFT 0x03 +#define P852_SKU_UART_ENABLE (1 << P852_SKU_UART_SHIFT) +#define P852_SKU_UART_MASK (1 << P852_SKU_UART_SHIFT) + +#define P852_SKU_NAND_SHIFT 0x04 +#define P852_SKU_NAND_ENABLE (1 << P852_SKU_NAND_SHIFT) +#define P852_SKU_NAND_MASK (1 << P852_SKU_NAND_SHIFT) + +#define P852_SKU_NOR_SHIFT 0x05 +#define P852_SKU_NOR_ENABLE (1 << P852_SKU_NOR_SHIFT) +#define P852_SKU_NOR_MASK (1 << P852_SKU_NOR_SHIFT) + +#define P852_SKU_DISPLAY_SHIFT 0x06 +#define P852_SKU_DISPLAY_ENABLE (1 << P852_SKU_DISPLAY_SHIFT) +#define P852_SKU_DISPLAY_MASK (1 << P852_SKU_DISPLAY_SHIFT) + +#define P852_SKU_ULPI_SHIFT 0x07 +#define P852_SKU_ULPI_DISABLE (1 << P852_SKU_ULPI_SHIFT) + +#define P852_SKU_I2C_SHIFT 0x08 +#define P852_SKU_I2C_ENABLE (1 << P852_SKU_I2C_SHIFT) +#define P852_SKU_I2C_MASK (1 << P852_SKU_I2C_SHIFT) + +#define P852_MAX_DISP 0x2 +#define P852_DISP_SHIFT 0x16 +#define P852_DISPA_SHIFT 0x0 +#define P852_DISPB_SHIFT 0x16 + +#define P852_DISP_MASK 0x1 +#define P852_DISP_ENABLE 0x1 +#define P852_DISPA_MASK (P852_DISP_MASK << P852_DISPA_SHIFT) +#define P852_DISPB_MASK (P852_DISP_MASK << P852_DISPB_SHIFT) + +#define P852_MAX_SPI 0x04 +#define P852_SPI_SHIFT 0x03 +#define P852_SPI1_SHIFT 0x00 +#define P852_SPI2_SHIFT 0x03 +#define P852_SPI3_SHIFT 0x06 +#define P852_SPI4_SHIFT 0x09 + +#define P852_SPI_MASK 0x07 +#define P852_SPI1_MASK (P852_SPI_MASK << P852_SPI1_SHIFT) +#define P852_SPI2_MASK (P852_SPI_MASK << P852_SPI2_SHIFT) +#define P852_SPI3_MASK (P852_SPI_MASK << P852_SPI3_SHIFT) +#define P852_SPI4_MASK (P852_SPI_MASK << P852_SPI4_SHIFT) + +#define P852_SPI_ENABLE 0x01 +#define P852_SPI_MASTER 0x02 +#define P852_SPI_SLAVE 0x04 + +#define P852_I2S_SHIFT 0x05 +#define P852_I2S1_SHIFT 0x00 +#define P852_I2S2_SHIFT 0x05 + +#define P852_I2S_MASK 0x1F +#define P852_I2S1_MASK (P852_I2S_MASK << P852_I2S1_SHIFT) +#define P852_I2S2_MASK (P852_I2S_MASK << P852_I2S2_SHIFT) + +#define P852_I2S_ENABLE 0x10 +#define P852_I2S_TDM 0x08 +#define P852_MAX_SDHCI 0x04 +#define P852_SDHCI_SHIFT 0x04 +#define P852_SDHCI1_SHIFT 0x00 +#define P852_SDHCI2_SHIFT 0x04 +#define P852_SDHCI3_SHIFT 0x08 +#define P852_SDHCI4_SHIFT 0x0C + +#define P852_SDHCI_MASK 0x0F +#define P852_SDHCI1_MASK (P852_SDHCI_MASK << P852_SDHCI1_SHIFT) +#define P852_SDHCI2_MASK (P852_SDHCI_MASK << P852_SDHCI2_SHIFT) +#define P852_SDHCI3_MASK (P852_SDHCI_MASK << P852_SDHCI3_SHIFT) +#define P852_SDHCI4_MASK (P852_SDHCI_MASK << P852_SDHCI4_SHIFT) + +#define P852_SDHCI_ENABLE 0x01 +#define P852_SDHCI_CD_EN 0x02 +#define P852_SDHCI_WP_EN 0x04 +#define P852_SDHCI_PW_EN 0x08 + +#define P852_UART_SHIFT 0x04 +#define P852_UARTA_SHIFT 0x00 +#define P852_UARTB_SHIFT 0x04 +#define P852_UARTC_SHIFT 0x08 +#define P852_UARTD_SHIFT 0x0C + +#define P852_UART_MASK 0x0F +#define P852_UARTA_MASK (P852_UART_MASK << P852_UARTA_SHIFT) +#define P852_UARTB_MASK (P852_UART_MASK << P852_UARTB_SHIFT) +#define P852_UARTC_MASK (P852_UART_MASK << P852_UARTC_SHIFT) +#define P852_UARTD_MASK (P852_UART_MASK << P852_UARTD_SHIFT) + +#define P852_MAX_UART 0x4 +#define P852_UART_ALT_PIN_CFG 0x8 +#define P852_UART_ENABLE 0x4 +#define P852_UART_DB 0x1 +#define P852_UART_HS 0x2 + +#define P852_MAX_I2C 0x4 +#define P852_I2C_SHIFT 0x01 +#define P852_I2C1_SHIFT 0x00 +#define P852_I2C2_SHIFT 0x01 +#define P852_I2C3_SHIFT 0x02 +#define P852_I2C4_SHIFT 0x03 + + +#define P852_I2C_MASK 0x01 +#define P852_I2C1_MASK (P852_I2C_MASK << P852_I2C1_SHIFT) +#define P852_I2C2_MASK (P852_I2C_MASK << P852_I2C2_SHIFT) +#define P852_I2C3_MASK (P852_I2C_MASK << P852_I2C3_SHIFT) +#define P852_I2C4_MASK (P852_I2C_MASK << P852_I2C4_SHIFT) + +#define P852_I2C_ENABLE 0x01 + +#endif |