diff options
author | Bai Ping <ping.bai@nxp.com> | 2017-08-25 13:07:27 +0800 |
---|---|---|
committer | Stefan Agner <stefan.agner@toradex.com> | 2018-08-16 14:52:21 +0200 |
commit | 496776ddb74fb2b2a203f917950e42b7421ea474 (patch) | |
tree | f061a31abe42fe5c97a1f49ccc0a8fd8748da53b | |
parent | 35434ac3918c5ba303cb9cb2396a3f75dd1e247c (diff) |
MLK-16266-01 ARM: imx: improve the soc revision calculation flow
On our i.MX6 SOC, the DIGPROG register is used for represent the
SOC ID and silicon revision. The revision has two part: MAJOR and
MINOR. each is represented in 8 bits in the register.
bits [15:8]: reflect the MAJOR part of the revision;
bits [7:0]: reflect the MINOR part of the revision;
In our linux kernel, the soc revision is represented in 8 bits. MAJOR
part and MINOR each occupy 4 bits.
previous method does NOT take care about the MAJOR part in DIGPROG register.
So reformat the revision read from the HW to compatible the revision format
used in kernel.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit cf6fa1477149d4bddd096c71b46fa6c4cf9cf750)
Acked-by: Stefan Agner <stefan.agner@toradex.com>
-rw-r--r-- | arch/arm/mach-imx/anatop.c | 52 |
1 files changed, 19 insertions, 33 deletions
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index 77b2326a3a61..2470e1a4fead 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -209,6 +210,7 @@ void __init imx_init_revision_from_anatop(void) unsigned int revision; u32 digprog; u16 offset = ANADIG_DIGPROG; + u16 major_part, minor_part; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); anatop_base = of_iomap(np, 0); @@ -220,41 +222,25 @@ void __init imx_init_revision_from_anatop(void) digprog = readl_relaxed(anatop_base + offset); iounmap(anatop_base); - switch (digprog & 0xff) { - case 0: - if (digprog >> 8 & 0x01) - revision = IMX_CHIP_REVISION_2_0; - else - revision = IMX_CHIP_REVISION_1_0; - break; - case 1: - revision = IMX_CHIP_REVISION_1_1; - break; - case 2: - revision = IMX_CHIP_REVISION_1_2; - break; - case 3: - revision = IMX_CHIP_REVISION_1_3; - break; - case 4: - revision = IMX_CHIP_REVISION_1_4; - break; - case 5: - /* - * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked - * as 'D' in Part Number last character. - */ - revision = IMX_CHIP_REVISION_1_5; - break; - default: + /* + * On i.MX7D digprog value match linux version format, so + * it needn't map again and we can use register value directly. + */ + if (of_device_is_compatible(np, "fsl,imx7d-anatop")) { + revision = digprog & 0xff; + } else { /* - * Fail back to return raw register value instead of 0xff. - * It will be easy know version information in SOC if it - * can't recongized by known version. And some chip like - * i.MX7D soc digprog value match linux version format, - * needn't map again and direct use register value. + * MAJOR: [15:8], the major silicon revison; + * MINOR: [7: 0], the minor silicon revison; + * + * please refer to the i.MX RM for the detailed + * silicon revison bit define. + * format the major part and minor part to match the + * linux kernel soc version format. */ - revision = digprog & 0xff; + major_part = (digprog >> 8) & 0xf; + minor_part = digprog & 0xf; + revision = ((major_part + 1) << 4) | minor_part; } mxc_set_cpu_type(digprog >> 16 & 0xff); |