diff options
| author | Haibo Chen <haibo.chen@nxp.com> | 2016-09-06 13:19:37 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2016-09-14 17:26:25 +0800 |
| commit | 873b54c48e53faf7f9e33d51e899c7b06316cf87 (patch) | |
| tree | 0b5eefdf2e8367f18719e45dc009904d5b32a606 | |
| parent | e83837e669221ce9872211f4dbddc36e83a848b6 (diff) | |
MLK-13188-2 dts: imx6ull: change the usdhc root clock to 396MHz
Due to the errata ERR010450 limit, this patch change the imx6ull
usdhc root clock to 132MHz in soc related dts file, remove all
the root clock setting in board dts file, after this patch,
SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit a59b2c333031a71604488ea448d13dd38361db94)
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts | 3 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx6ull.dtsi | 10 |
3 files changed, 8 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts index 69323b663a50..934e6f6b8502 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-ddr3-arm2-emmc.dts @@ -12,9 +12,6 @@ pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD0>; - assigned-clock-rates = <0>, <176000000>; cd-gpios = <>; wp-gpios = <>; vmmc-supply = <>; diff --git a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts index bf8db204017a..4ea3d91e2cb6 100644 --- a/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts +++ b/arch/arm/boot/dts/imx6ull-14x14-evk-emmc.dts @@ -13,10 +13,6 @@ pinctrl-0 = <&pinctrl_usdhc2_8bit>; pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; - assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; - assigned-clock-rates = <0>, <396000000>; - max-frequency = <132000000>; bus-width = <8>; non-removable; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index f350da34805f..d8b6706800ea 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -888,26 +888,32 @@ }; usdhc1: usdhc@02190000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02190000 0x4000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_USDHC1>, <&clks IMX6UL_CLK_USDHC1>, <&clks IMX6UL_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; bus-width = <4>; fsl,tuning-step= <2>; status = "disabled"; }; usdhc2: usdhc@02194000 { - compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; reg = <0x02194000 0x4000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6UL_CLK_USDHC2>, <&clks IMX6UL_CLK_USDHC2>, <&clks IMX6UL_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; bus-width = <4>; fsl,tuning-step= <2>; status = "disabled"; |