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authorAri Hirvonen <ahirvonen@nvidia.com>2011-03-12 17:47:04 +0200
committerVarun Colbert <vcolbert@nvidia.com>2011-03-16 19:45:34 -0800
commita904334b06a7b3bf255edadedd8b04055b2a0457 (patch)
treee59929406659721ed28b3592d3bfd2f84dc08697
parent87a9efe751716ca741caac72b9061fdfdcec540a (diff)
arm: tegra: ventana: fix dc out bit depthtegra-11.2.2
Set to 18bit which is what Ventana's panel expects. Enabled ordered dithering for smoother gradients. Bug 797698 Change-Id: Icfc7a9a9d27fc79c8b46cd1cf736d2447638e0ef Signed-off-by: Ari Hirvonen <ahirvonen@nvidia.com> Reviewed-on: http://git-master/r/22717 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-ventana-panel.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-ventana-panel.c b/arch/arm/mach-tegra/board-ventana-panel.c
index f90fd6e18ea2..5859e51e70a5 100644
--- a/arch/arm/mach-tegra/board-ventana-panel.c
+++ b/arch/arm/mach-tegra/board-ventana-panel.c
@@ -224,6 +224,8 @@ static struct tegra_dc_out ventana_disp1_out = {
.align = TEGRA_DC_ALIGN_MSB,
.order = TEGRA_DC_ORDER_RED_BLUE,
+ .depth = 18,
+ .dither = TEGRA_DC_ORDERED_DITHER,
.modes = ventana_panel_modes,
.n_modes = ARRAY_SIZE(ventana_panel_modes),