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authorShreshtha SAHU <ssahu@nvidia.com>2014-09-03 17:45:17 +0530
committerWinnie Hsu <whsu@nvidia.com>2014-10-13 18:50:01 -0700
commitc7460e0d6afd754ebf5555477129579bc83c47b9 (patch)
tree4a1c5741ee017013f697813c85a5d975f0401f96
parent36a8e8ba4538d17acaac60ffca6835cf21f33709 (diff)
arm: tegra30: pcie: do not disable clk after deasserting resetstegra-l4t-r16-16.5daily-2014.11.07.0_l4t/l4t-r16
Do not disable and re-enable clocks after deasserting PCIE, AFI and PCIEX resets. Deasserting the resets should be followed by programming the PCIE. Bug 1521306 Change-Id: Idc43bc9b21cac3818852ed059fe512f4cd75b748 Signed-off-by: Shreshtha SAHU <ssahu@nvidia.com> Reviewed-on: http://git-master/r/495616 GVS: Gerrit_Virtual_Submit Reviewed-by: Eric Brower <ebrower@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/powergate.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index 4c0d8bec276e..e8f96a4cac0e 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -709,7 +709,10 @@ int tegra_unpowergate_partition(int id)
mc_flush_done(id);
/* Disable all clks enabled earlier. Drivers should enable clks */
- partition_clk_disable(id);
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ if (id != TEGRA_POWERGATE_PCIE)
+#endif
+ partition_clk_disable(id);
return 0;
@@ -743,9 +746,14 @@ int tegra_unpowergate_partition_with_clk_on(int id)
goto err_unpowergating;
/* Enable clks for the partition */
- ret = partition_clk_enable(id);
- if (ret)
- goto err_unpowergate_clk;
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+ if (id != TEGRA_POWERGATE_PCIE)
+#endif
+ {
+ ret = partition_clk_enable(id);
+ if (ret)
+ goto err_unpowergate_clk;
+ }
return ret;