diff options
authorEvalds Iodzevics <>2020-04-22 11:17:59 +0300
committerGreg Kroah-Hartman <>2020-04-24 07:59:16 +0200
commit552e8e39e155bf8532a8c602ebf070dd8d4c4c41 (patch)
parent737677595c76821726dc277e15d982d56b98fc26 (diff)
x86/microcode/intel: replace sync_core() with native_cpuid_reg(eax)
On Intel it is required to do CPUID(1) before reading the microcode revision MSR. Current code in 4.4 an 4.9 relies on sync_core() to call CPUID, unfortunately on 32 bit machines code inside sync_core() always jumps past CPUID instruction as it depends on data structure boot_cpu_data witch are not populated correctly so early in boot sequence. It depends on: commit 5dedade6dfa2 ("x86/CPU: Add native CPUID variants returning a single datum") This patch is for 4.4 but also should apply to 4.9 Signed-off-by: Evalds Iodzevics <> Cc: Signed-off-by: Greg Kroah-Hartman <>
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h
index a61ec81b27db..c8e472e2c896 100644
--- a/arch/x86/include/asm/microcode_intel.h
+++ b/arch/x86/include/asm/microcode_intel.h
@@ -59,7 +59,7 @@ static inline u32 intel_get_microcode_revision(void)
native_wrmsrl(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */
- sync_core();
+ native_cpuid_eax(1);
/* get the current revision from MSR 0x8B */
native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);