diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2021-03-22 15:19:20 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2022-08-24 12:10:37 +0000 |
| commit | 97853b1213051b6394e65bb414d04acc98e09679 (patch) | |
| tree | 140c52853fa8c25c385f3620af91746b0e38ed01 | |
| parent | f4b1f8a9877eaf8dd6d0456767dd33a995a367ab (diff) | |
ASoC: fsl_sai: enable mclk out early on i.mx 8m plus
Some audio codecs need the MCLK during setup of the codec.
For some SAI versions, e.g. on i.MX 8M Plus, the physical MCLK pin
output is gated with the TCSR BCE bit. The BCE bit gets implicitely
set when the transmitter gets enabled, however that is done only
when starting playback.
Enable the BCE bit already in fsl_sai_hw_params() which is an
early state when initalizing sai and codec.
Notably the WM8904 codec used on a Toradex Dahlia carrier board is
affected and shows a huge timeout of about 8 seconds and it fails
to calibrate DC offsets due to the lack of MCLK.
Fixes a timeout on audio start:
root@verdin-imx8mp:~# aplay Gong.wav
[ 1356.402716] wm8904 3-001a: DC servo timed out
[ 1362.410401] wm8904 3-001a: DC servo timed out
Playing WAVE 'Gong.wav' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo
Upstream-status: Pending [mainline does not support SAI yet]
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | sound/soc/fsl/fsl_sai.c | 6 | ||||
| -rw-r--r-- | sound/soc/fsl/fsl_sai.h | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 5cf671139324..05860be95ec3 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -710,6 +710,11 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream, regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << min(channels, slots)) - 1)); + if (sai->soc_data->mclk_gated_by_bce) + /* Enable phyiscal MCLK pin signal early */ + regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs), + FSL_SAI_CSR_BCE, FSL_SAI_CSR_BCE); + return 0; } @@ -1620,6 +1625,7 @@ static const struct fsl_sai_soc_data fsl_sai_imx8mp_data = { .fifos = 8, .flags = 0, .max_register = FSL_SAI_MDIV, + .mclk_gated_by_bce = 1, }; static const struct fsl_sai_soc_data fsl_sai_imx8ulp_data = { diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index f6c27b8165bf..919c8a0e6eac 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -91,6 +91,7 @@ /* SAI Transmit/Receive Control Register */ #define FSL_SAI_CSR_TERE BIT(31) #define FSL_SAI_CSR_SE BIT(30) +#define FSL_SAI_CSR_BCE BIT(28) #define FSL_SAI_CSR_FR BIT(25) #define FSL_SAI_CSR_SR BIT(24) #define FSL_SAI_CSR_xF_SHIFT 16 @@ -233,6 +234,8 @@ struct fsl_sai_soc_data { unsigned int dataline; unsigned int flags; unsigned int max_register; + /* Set to 1 if the SAI gates MCLK to the output pin with BCE */ + bool mclk_gated_by_bce; }; /** |