diff options
| author | Andrejs Cainikovs <andrejs.cainikovs@toradex.com> | 2022-05-11 09:44:30 +0200 |
|---|---|---|
| committer | Andrejs Cainikovs <andrejs.cainikovs@toradex.com> | 2022-05-11 11:54:43 +0200 |
| commit | 226073276f6be24718d364b0cfd12019c07cab14 (patch) | |
| tree | 35d5ac65e488e3216cf76dc19541d533920c978c | |
| parent | 0f0011824921d175b0e124c5393e2f8cefa611a8 (diff) | |
arm64: dts: imx8mm-verdin: update CAN clock to 40MHz
Update SPI CAN controller clock to match current hardware design.
Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 27764662b129..d03e33a4142f 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -32,10 +32,10 @@ }; /* fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { + clk40m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <20000000>; + clock-frequency = <40000000>; }; gpio-keys { @@ -169,7 +169,7 @@ can1: can@0 { compatible = "microchip,mcp2517fd"; - clocks = <&clk20m>; + clocks = <&clk40m>; gpio-controller; interrupt-parent = <&gpio1>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; @@ -183,7 +183,7 @@ can2: can@1 { compatible = "microchip,mcp2517fd"; - clocks = <&clk20m>; + clocks = <&clk40m>; gpio-controller; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; |