board Apalis iMX6: add most pinmuxing with platform data

Register eMMC as the first mmc driver, so it gets always mmcblk0
Fixed mmc speed dependent pin setting to use the correct
  controller to pins assignment
Use the speed dependent pin setting also for initial pinmuxing
Added all pinmuxing
Added touch driver platform data from Apalis T30
Initalize USB Host, so the ports get VBUS powered
HDMI I2C not yet working, so switch pinmuxing to use I2C2
Register eMMC as the first mmc driver, so it gets always mmcblk0
Fixed mmc speed dependent pin setting to use the correct
  controller to pins assignment
Use the speed dependent pin setting also for initial pinmuxing
Added all pinmuxing
Added touch driver platform data from Apalis T30
Initalize USB Host, so the ports get VBUS powered
HDMI I2C not yet working, so switch pinmuxing to use I2C2

2 files changed, 391 insertions, 149 deletions

diff --git a/arch/arm/mach-mx6/board-apalis_imx6.c b/arch/arm/mach-mx6/board-apalis_imx6.c
index a4e76c4392d6..6fd73fe22025 100644
--- a/arch/arm/mach-mx6/board-apalis_imx6.c
+++ b/arch/arm/mach-mx6/board-apalis_imx6.c
@@ -32,6 +32,10 @@
 #include <linux/spi/flash.h>
 #include <linux/i2c.h>
 #include <linux/ata.h>
+#ifdef TODO
+#include <linux/input/fusion_F0710A.h>
+#endif
+#include <linux/mfd/stmpe.h>
 #include <linux/mtd/map.h>
 #include <linux/mtd/partitions.h>
 #include <linux/regulator/consumer.h>
@@ -79,12 +83,13 @@
 #define GP_SD1_WP	(-1)
 #define GP_SD2_CD	IMX_GPIO_NR(6, 14) /* Apalis SD1 */
 #define GP_SD2_WP	(-1)
-#define GP_ECSPI1_CS1	IMX_GPIO_NR(3, 19)
+#define GP_ECSPI1_CS1	IMX_GPIO_NR(5, 25)	/* TODO muxing uses not GPIO!*/
 #define GP_USB_OTG_PWR	IMX_GPIO_NR(3, 22)
-#define GP_CAP_TCH_INT1	IMX_GPIO_NR(1, 9)
+#define GP_CAP_TCH_INT1	IMX_GPIO_NR(1, 9)	/* TODO PCIe RESET */
 #define GP_USB_PEN	IMX_GPIO_NR(1, 0)	/* USBH_EN */
 #define GP_USB_HUB_VBUS	IMX_GPIO_NR(3, 28)	/* USB_VBUS_DET */
-#define GP_ENET_PHY_INT	IMX_GPIO_NR(1, 28)
+#define GP_ENET_PHY_INT	IMX_GPIO_NR(1, 30)
+#define STMPE811_IRQ	IMX_GPIO_NR(4, 10)
 
 #define CAN1_ERR_TEST_PADCFG	(PAD_CTL_PKE | PAD_CTL_PUE | \
 		PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
@@ -151,13 +156,14 @@ static int plt_sd_pad_change(unsigned int index, int clock)
 {
 	/* LOW speed is the default state of SD pads */
 	static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
-	int i = (index - 1) * SD_SPEED_CNT;
+	int i = index * SD_SPEED_CNT;
+
+	printk("plt_sd_pad_change index %d, clock %d\n", index, clock);
 
-	if ((index < 1) || (index > 3)) {
+	if (index > 3) {
 		printk(KERN_ERR "no such SD host controller index %d\n", index);
 		return -EINVAL;
 	}
-
 	if (clock > 100000000) {
 		if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
 			return 0;
@@ -403,14 +409,146 @@ static struct platform_device audio_device = {
 	.name = "imx-sgtl5000",
 };
 
-static struct imxi2c_platform_data i2c_data = {
-	.bitrate = 100000,
+//**************************************************************************************************
+/*
+ * Fusion touch screen GPIOs (using Toradex display/touch adapater)
+ * Apalis GPIO 5, MXM-11, Ixora X27-17, pen down interrupt
+ * Apalis GPIO 6, MXM-13, Ixora X27-18, reset
+ * gpio_request muxes the GPIO function automatically, we only have to make
+ * sure input/output muxing is done and the GPIO is freed here.
+ */
+#ifdef TODO
+static int pinmux_fusion_pins(void);
+
+static struct fusion_f0710a_init_data apalis_fusion_pdata = {
+	.pinmux_fusion_pins = &pinmux_fusion_pins,
+	.gpio_int = APALIS_GPIO5, 	/* MXM-11, Pen down interrupt */
+	.gpio_reset = APALIS_GPIO6,	/* MXM-13, Reset interrupt */
 };
 
+static int pinmux_fusion_pins(void)
+{
+	gpio_free(apalis_fusion_pdata.gpio_int);
+	gpio_free(apalis_fusion_pdata.gpio_reset);
+	apalis_fusion_pdata.pinmux_fusion_pins = NULL;
+	return 0;
+}
+#endif
+/* I2C */
+
+/* Make sure that the pinmuxing enable the 'open drain' feature for pins used
+   for I2C */
+
+/* I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier board) */
 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 	{
+		/* M41T0M6 real time clock on Iris carrier board */
+		I2C_BOARD_INFO("rtc-ds1307", 0x68),
+			.type = "m41t00",
+	},
+#ifdef TODO
+	{
+		/* TouchRevolution Fusion 7 and 10 multi-touch controller */
+		I2C_BOARD_INFO("fusion_F0710A", 0x10),
+		.platform_data = &apalis_fusion_pdata,
+	},
+#endif
+};
+
+/* DDC: I2C_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
+
+/* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on carrier
+   board) */
+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+};
+
+/* PWR_I2C: power I2C to audio codec, PMIC and touch screen controller */
+
+/* STMPE811 touch screen controller */
+static struct stmpe_ts_platform_data stmpe811_ts_data = {
+	.adc_freq		= 1, /* 3.25 MHz ADC clock speed */
+	.ave_ctrl		= 3, /* 8 sample average control */
+	.fraction_z		= 7, /* 7 length fractional part in z */
+	.i_drive		= 1, /* 50 mA typical 80 mA max touchscreen
+					drivers current limit value */
+	.mod_12b		= 1, /* 12-bit ADC */
+	.ref_sel		= 0, /* internal ADC reference */
+	.sample_time		= 4, /* ADC converstion time: 80 clocks */
+	.settling		= 3, /* 1 ms panel driver settling time */
+	.touch_det_delay	= 5, /* 5 ms touch detect interrupt delay */
+};
+#ifdef TODO
+/* STMPE811 ADC controller */
+static struct stmpe_adc_platform_data stmpe811_adc_data = {
+	.sample_time		= 4, /* ADC converstion time: 80 clocks */
+	.mod_12b		= 1, /* 12-bit ADC */
+	.ref_sel		= 0, /* internal ADC reference */
+	.adc_freq		= 1, /* 3.25 MHz ADC clock speed */
+};
+#endif
+static struct stmpe_platform_data stmpe811_data = {
+	.blocks		= STMPE_BLOCK_TOUCHSCREEN | STMPE_BLOCK_ADC,
+	.id		= 1,
+	.irq_base	= STMPE811_IRQ,
+	.irq_trigger	= IRQF_TRIGGER_FALLING,
+	.ts		= &stmpe811_ts_data,
+#ifdef TODO
+	.adc		= &stmpe811_adc_data,
+#endif
+};
+
+static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
+	{
+		/* SGTL5000 audio codec */
 		I2C_BOARD_INFO("sgtl5000", 0x0a),
 	},
+	{
+		/* STMPE811 touch screen controller */
+		I2C_BOARD_INFO("stmpe", 0x41),
+			.flags = I2C_CLIENT_WAKE,
+			.platform_data = &stmpe811_data,
+			.type = "stmpe811",
+	},
+#if 0
+	{
+		/* PMIC */
+		I2C_BOARD_INFO("pf0100", 0x08),
+	},
+#endif
+	{
+		I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
+	},
+};
+
+#if 0
+static void __init apalis_t30_i2c_init(void)
+{
+	tegra_i2c_device1.dev.platform_data = &apalis_t30_i2c1_platform_data;
+	tegra_i2c_device3.dev.platform_data = &apalis_t30_i2c3_platform_data;
+	tegra_i2c_device4.dev.platform_data = &apalis_t30_i2c4_platform_data;
+	tegra_i2c_device5.dev.platform_data = &apalis_t30_i2c5_platform_data;
+
+	platform_device_register(&tegra_i2c_device1);
+	platform_device_register(&tegra_i2c_device3);
+	platform_device_register(&tegra_i2c_device4);
+	platform_device_register(&tegra_i2c_device5);
+
+	i2c_register_board_info(0, apalis_t30_i2c_bus1_board_info,
+				ARRAY_SIZE(apalis_t30_i2c_bus1_board_info));
+
+	/* enable touch interrupt GPIO */
+	gpio_request(TOUCH_PEN_INT, "TOUCH_PEN_INT");
+	gpio_direction_input(TOUCH_PEN_INT);
+
+	apalis_t30_i2c_bus5_board_info[1].irq = gpio_to_irq(TOUCH_PEN_INT);
+	i2c_register_board_info(4, apalis_t30_i2c_bus5_board_info,
+				ARRAY_SIZE(apalis_t30_i2c_bus5_board_info));
+}
+#endif
+//***********************************************************************************************************************
+
+static struct imxi2c_platform_data i2c_data = {
+	.bitrate = 100000,
 };
 
 static void camera_reset(int power_gp, int poweroff_level, int reset_gp, int reset_gp2)
@@ -566,17 +704,20 @@ static struct fsl_mxc_tvin_platform_data adv7180_data = {
 	.csi = 1,
 };
 
+#if 0
 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 	{
 		I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
 	},
 };
-
+#endif
+#if 0
 static struct fsl_mxc_lcd_platform_data adv7391_data = {
 	.ipu_id = 0,
 	.disp_id = 0,
 	.default_ifmt = IPU_PIX_FMT_BT656,
 };
+#endif
 
 static void usbotg_vbus(bool on)
 {
@@ -586,7 +727,7 @@ static void usbotg_vbus(bool on)
 		gpio_set_value(GP_USB_OTG_PWR, 0);
 }
 
-static void __init init_usb(void)
+static void __init init_usb_otg(void)
 {
 	int ret = 0;
 
@@ -606,6 +747,16 @@ static void __init init_usb(void)
 	mx6_set_otghost_vbus_func(usbotg_vbus);
 }
 
+static void __init init_usb_host(void)
+{
+	/* VBUS to hub on module */
+	gpio_request(GP_USB_HUB_VBUS, "USB_HUB_EN");
+	gpio_direction_output(GP_USB_HUB_VBUS, 1);
+	/* USBH Power Enable */
+	gpio_request(GP_USB_PEN, "USBH_PEN");
+	gpio_direction_output(GP_USB_PEN, 1);
+}
+
 /* HW Initialization, if return 0, initialization is successful. */
 static int init_sata(struct device *dev, void __iomem *addr)
 {
@@ -716,29 +867,29 @@ static struct imx_asrc_platform_data imx_asrc_data = {
 	.clk_map_ver = 2,
 };
 
-static struct ipuv3_fb_platform_data fb_data[] = {
-	{ /*fb0*/
-	.disp_dev = "ldb",
-	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
-	.mode_str = "LDB-XGA",
+static struct ipuv3_fb_platform_data fb_data[] = { {
+	/*fb0*/
+	.disp_dev = "hdmi",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB24,
+	.mode_str = "EDT-WVGA",
 	.default_bpp = 16,
 	.int_clk = false,
-	}, {
+	},{
 	.disp_dev = "lcd",
-	.interface_pix_fmt = IPU_PIX_FMT_RGB565,
-	.mode_str = "CLAA-WVGA",
+	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
+	.mode_str = "EDT-WVGA",
 	.default_bpp = 16,
 	.int_clk = false,
 	}, {
 	.disp_dev = "ldb",
 	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
-	.mode_str = "LDB-SVGA",
+	.mode_str = "LDB-XGA",
 	.default_bpp = 16,
 	.int_clk = false,
 	}, {
 	.disp_dev = "ldb",
 	.interface_pix_fmt = IPU_PIX_FMT_RGB666,
-	.mode_str = "LDB-VGA",
+	.mode_str = "800x480M@60",
 	.default_bpp = 16,
 	.int_clk = false,
 	},
@@ -775,11 +926,13 @@ static void hdmi_init(int ipu_id, int disp_id)
 
 static void hdmi_enable_ddc_pin(void)
 {
+	printk("hdmi: pinmux for EDID");
 	IOMUX_SETUP(hdmi_ddc_pads);
 }
 
 static void hdmi_disable_ddc_pin(void)
 {
+	printk("hdmi: pinmux for PWR_I2C\n");
 	IOMUX_SETUP(i2c2_pads);
 }
 
@@ -791,7 +944,7 @@ static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 
 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
 	.ipu_id = 0,
-	.disp_id = 1,
+	.disp_id = 0,
 };
 
 static void lcd_enable_pins(void)
@@ -803,7 +956,7 @@ static void lcd_enable_pins(void)
 static void lcd_disable_pins(void)
 {
 	pr_info("%s\n", __func__);
-//	IOMUX_SETUP(lcd_pads_disable);
+	IOMUX_SETUP(lcd_pads_disable);
 }
 
 static void vga_dac_enable_pins(void)
@@ -819,7 +972,7 @@ static void vga_dac_disable_pins(void)
 }
 
 static struct fsl_mxc_lcd_platform_data lcdif_data = {
-	.ipu_id = 1,
+	.ipu_id = 0,
 	.disp_id = 1,
 	.default_ifmt = IPU_PIX_FMT_RGB24,
 	.enable_pins = lcd_enable_pins,
@@ -828,7 +981,7 @@ static struct fsl_mxc_lcd_platform_data lcdif_data = {
 
 static struct fsl_mxc_lcd_platform_data vgadacif_data = {
 	.ipu_id = 1,
-	.disp_id = 0,
+	.disp_id = 1,
 	.default_ifmt = IPU_PIX_FMT_RGB565,
 	.enable_pins = vga_dac_enable_pins,
 	.disable_pins = vga_dac_disable_pins,
@@ -842,13 +995,13 @@ static struct fsl_mxc_ldb_platform_data ldb_data = {
 	.sec_ipu_id = 1,
 	.sec_disp_id = 1,
 };
-
+#if 0
 static struct fsl_mxc_lcd_platform_data bt656_data = {
 	.ipu_id = 0,
 	.disp_id = 0,
 	.default_ifmt = IPU_PIX_FMT_BT656,
 };
-
+#endif
 static struct imx_ipuv3_platform_data ipu_data[] = {
 	{
 	.rev = 4,
@@ -1199,6 +1352,10 @@ static const struct imx_pcie_platform_data pcie_data  __initconst = {
 /*!
  * Board specific initialization.
  */
+#define imx6q_add_lcdif1(pdata)	\
+	platform_device_register_resndata(NULL, "mxc_lcdif",\
+			1, NULL, 0, pdata, sizeof(*pdata));
+
 static void __init board_init(void)
 {
 	int i, j;
@@ -1206,15 +1363,18 @@ static void __init board_init(void)
 	struct clk *clko2;
 	struct clk *new_parent;
 	int rate;
-	int isn6 ;
 #ifdef ONE_WIRE
 	int one_wire_gp;
 #endif
 	IOMUX_SETUP(common_pads);
-	lcd_disable_pins();
-	//vga_dac_enable_pins();
+	IOMUX_SETUP(hdmi_ddc_pads);
+	/* setup MMC/SD pads with settings for slow clock */
+	plt_sd_pad_change(0, 400000);
+	plt_sd_pad_change(1, 400000);
+	plt_sd_pad_change(2, 400000);
 
-	isn6 = is_nitrogen6w();
+	lcd_disable_pins();
+	vga_dac_enable_pins();
 
 #ifdef CONFIG_FEC_1588
 	/* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
@@ -1260,9 +1420,10 @@ static void __init board_init(void)
 
 	imx6q_add_vdoa();
 	imx6q_add_lcdif(&lcdif_data);
+//	imx6q_add_lcdif1(&vgadacif_data);
 	imx6q_add_ldb(&ldb_data);
 	imx6q_add_v4l2_output(0);
-	imx6q_add_bt656(&bt656_data);
+//	imx6q_add_bt656(&bt656_data);
 
 	for (i = 0; i < ARRAY_SIZE(capture_data); i++) {
 		if (!cpu_is_mx6q())
@@ -1279,12 +1440,8 @@ static void __init board_init(void)
 	imx6q_add_imx_i2c(0, &i2c_data);
 	imx6q_add_imx_i2c(1, &i2c_data);
 	imx6q_add_imx_i2c(2, &i2c_data);
-	/*
-	 * SABRE Lite does not have an ISL1208 RTC
-	 */
 	i2c_register_board_info(0, mxc_i2c0_board_info,
-			isn6    ? ARRAY_SIZE(mxc_i2c0_board_info)
-				: ARRAY_SIZE(mxc_i2c0_board_info)-1);
+			ARRAY_SIZE(mxc_i2c0_board_info));
 	i2c_register_board_info(1, mxc_i2c1_board_info,
 			ARRAY_SIZE(mxc_i2c1_board_info));
 	i2c_register_board_info(2, mxc_i2c2_board_info,
@@ -1302,11 +1459,12 @@ static void __init board_init(void)
 	imx6q_add_anatop_thermal_imx(1, &anatop_thermal_data);
 	imx6_init_fec(fec_data);
 	imx6q_add_pm_imx(0, &pm_data);
+	/* register onboard eMMC first */
+	imx6q_add_sdhci_usdhc_imx(2, &sd3_data);
 	imx6q_add_sdhci_usdhc_imx(0, &sd1_data);
 	imx6q_add_sdhci_usdhc_imx(1, &sd2_data);
-	imx6q_add_sdhci_usdhc_imx(2, &sd3_data);
 	imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata);
-	init_usb();
+	init_usb_otg();
 	if (cpu_is_mx6q())
 		imx6q_add_ahci(0, &sata_data);
 	imx6q_add_vpu();
@@ -1317,8 +1475,7 @@ static void __init board_init(void)
 	imx6q_add_asrc(&imx_asrc_data);
 
 	/* USB host */
-	gpio_set_value(GP_USB_HUB_VBUS, 1);
-	gpio_set_value(GP_USB_PEN, 1);
+	init_usb_host();
 
 	imx6q_add_mxc_pwm(0);
 	imx6q_add_mxc_pwm(1);
diff --git a/arch/arm/mach-mx6/pads-apalis_imx6.h b/arch/arm/mach-mx6/pads-apalis_imx6.h
index 9eea5fa93ec2..3e28478c13d1 100644
--- a/arch/arm/mach-mx6/pads-apalis_imx6.h
+++ b/arch/arm/mach-mx6/pads-apalis_imx6.h
@@ -14,69 +14,34 @@
 #define MX6NAME(a) mx6q_##a
 #endif
 
-#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
-		PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
-		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define MX6Q_USDHC_PAD_CTRL_50MHZ	MX6Q_USDHC_PAD_CTRL
-#define MX6Q_PAD_SD3_CLK__USDHC3_CLK	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
-#define MX6Q_PAD_SD3_CMD__USDHC3_CMD	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
-#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
-#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
-#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
-#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
-#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
-#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
-#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
-#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
-#define MX6Q_PAD_SD4_CLK__USDHC4_CLK	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
-#define MX6Q_PAD_SD4_CMD__USDHC4_CMD	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
-#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
-#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
-#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
-#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
-
-#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ
-#define MX6DL_USDHC_PAD_CTRL_50MHZ	MX6DL_USDHC_PAD_CTRL
-#define MX6DL_PAD_SD3_CLK__USDHC3_CLK	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
-#define MX6DL_PAD_SD3_CMD__USDHC3_CMD	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
-#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
-#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
-#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
-#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
-#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
-#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
-#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
-#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
-#define MX6DL_PAD_SD4_CLK__USDHC4_CLK	MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
-#define MX6DL_PAD_SD4_CMD__USDHC4_CMD	MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
-#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
-#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
-#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
-#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
-
-#define NP(id, pin, pad_ctl) \
-	NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))
-
-#define SD_PINS(id, pad_ctl) \
-	NP(id, CLK, pad_ctl),	\
-	NP(id, CMD, pad_ctl),	\
-	NP(id, DAT0, pad_ctl),	\
-	NP(id, DAT1, pad_ctl),	\
-	NP(id, DAT2, pad_ctl),	\
-	NP(id, DAT3, pad_ctl)
-
-static iomux_v3_cfg_t MX6NAME(nitrogen6x_pads)[] = {
-#ifdef TODO
-	NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_PADCFG),	/* wl1271 wl_irq */
-#endif
-
 
 static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	/* CCM  */
-	MX6PAD(GPIO_5__CCM_CLKO),		/* local AC97 sys_mclk */
+	MX6PAD(GPIO_5__CCM_CLKO),		/* I2S sys_mclk */
 	MX6PAD(NANDF_CS2__CCM_CLKO2),		/* MXM193 CAM1_MCLK */
 
+	/* Apalis GPIO */
+	MX6PAD(NANDF_D4__GPIO_2_4),	/* 1 */
+	MX6PAD(NANDF_D5__GPIO_2_5),	/* 2 */
+	MX6PAD(NANDF_D6__GPIO_2_6),	/* 3 */
+	MX6PAD(NANDF_D7__GPIO_2_7),	/* 4 */
+	MX6PAD(NANDF_RB0__GPIO_6_10),	/* 5 */
+	MX6PAD(NANDF_WP_B__GPIO_6_9),	/* 6 */
+	MX6PAD(GPIO_2__GPIO_1_2),	/* 7 */
+	MX6PAD(GPIO_6__GPIO_1_6),	/* 8 */
+
+	/* Apalis SPI1, ECSPI1 */
+	MX6PAD(CSI0_DAT6__ECSPI1_MISO),
+	MX6PAD(CSI0_DAT5__ECSPI1_MOSI),
+	MX6PAD(CSI0_DAT4__ECSPI1_SCLK),
+	MX6PAD(CSI0_DAT7__ECSPI1_SS0),
+
+	/* Apalis SPI2, ECSPI2 */
+	MX6PAD(EIM_CS1__ECSPI2_MOSI),
+	MX6PAD(EIM_CS0__ECSPI2_SCLK),
+	MX6PAD(EIM_OE__ECSPI2_MISO),
+	MX6PAD(EIM_RW__ECSPI2_SS0),
+
 	/* ENET */
 	MX6PAD(ENET_MDIO__ENET_MDIO),
 	MX6PAD(ENET_MDC__ENET_MDC),
@@ -136,8 +101,8 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	MX6PAD(EIM_DA12__IPU1_CSI1_VSYNC),	/* GPIO3[12] */
 	MX6PAD(EIM_A16__IPU1_CSI1_PIXCLK),	/* GPIO2[22] */
 #else
-	MX6PAD(EIM_EB2__IPU2_CSI1_D_19),	/* GPIO2[30] */
 #ifdef TODO
+	MX6PAD(EIM_EB2__IPU2_CSI1_D_19),	/* GPIO2[30] */
 	MX6PAD(EIM_A23__IPU2_CSI1_D_18),	/* GPIO6[6] */
 	MX6PAD(EIM_A22__IPU2_CSI1_D_17),	/* GPIO2[16] */
 	MX6PAD(EIM_A21__IPU2_CSI1_D_16),	/* GPIO2[17] */
@@ -163,33 +128,50 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	MX6PAD(EIM_A16__IPU2_CSI1_PIXCLK),	/* GPIO2[22] */
 #endif
 #endif
-	MX6PAD(EIM_DA13__GPIO_3_13),		/* Power */
-	MX6PAD(EIM_DA14__GPIO_3_14),		/* Reset */
-	MX6PAD(EIM_WAIT__GPIO_5_0),		/* Irq */
+	MX6PAD(EIM_DA13__GPIO_3_13),		/* BKL1_ON */
+	MX6PAD(EIM_DA14__GPIO_3_14),		/* BKL1_PWM */
+	MX6PAD(EIM_A25__GPIO_5_2),		/* BKL1_PWM_EN */
+	MX6PAD(EIM_BCLK__GPIO_6_31),		/* VGA_PSAVE# */
+
+	MX6PAD(KEY_ROW2__HDMI_TX_CEC_LINE),	/* HDMI CEC */
+
+	MX6PAD(EIM_WAIT__GPIO_5_0),		/* TS_6 */
 #ifdef TODO
 	MX6PAD(EIM_A24__GPIO_5_4),		/* Field */
 #endif
-	MX6PAD(EIM_RW__GPIO_2_26),		/* GPIO2[26] - unused */
-	MX6PAD(EIM_LBA__GPIO_2_27),		/* GPIO2[27] - unused */
+	MX6PAD(EIM_LBA__GPIO_2_27),		/* DAP1_RESET */
 #ifdef TODO
 	MX6PAD(EIM_EB3__GPIO_2_31),		/* GPIO2[31] - unused */
 #endif
-	MX6PAD(EIM_DA15__GPIO_3_15),		/* GPIO3[15] - unused */
+	MX6PAD(EIM_DA15__GPIO_3_15),		/* SATA1_ACT# */
 
 	/* NANDF_CS1/2/3 are unused for sabrelite */
-	NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_TEST_PADCFG),	/* wl1271 wl_irq */
-	NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), N6_EN_PADCFG),	/* wl1271 bt_en */
+	MX6PAD(NANDF_CS1__GPIO_6_14),		/* SD1_CD# */
+	MX6PAD(NANDF_CS3__GPIO_6_16),		/* TS_DIFF6- */
 
-	/* GPIO7 */
-	MX6PAD(GPIO_17__GPIO_7_12),	/* USB Hub Reset */
-	MX6PAD(GPIO_18__GPIO_7_13),	/* J14 - Volume Up */
+	MX6PAD(GPIO_16__SPDIF_IN1),		/* SPDIF1_IN */
+	MX6PAD(GPIO_17__SPDIF_OUT1),		/* SPDIF1_OUT */
+	MX6PAD(GPIO_18__GPIO_7_13),		/* PWR_INT */
 
+	MX6PAD(DI0_PIN4__GPIO_4_20),		/* MMC1_CD# */
 
-	/* DISPLAY */
-	NEW_PAD_CTRL(MX6PAD(DI0_PIN4__GPIO_4_20),
-		     WEAK_PULLUP),			/* I2C Touch IRQ */
-	MX6PAD(GPIO_7__GPIO_1_7),		/* J7 - Display Connector GP */
-	MX6PAD(GPIO_9__GPIO_1_9),		/* J7 - Display Connector GP */
+	/* Apalis CAN1 */
+	MX6PAD(GPIO_7__CAN1_TXCAN),
+	MX6PAD(GPIO_8__CAN1_RXCAN),
+	/* Apalis CAN2 */
+	MX6PAD(KEY_ROW4__CAN2_RXCAN),
+	MX6PAD(KEY_COL4__CAN2_TXCAN),
+#ifdef TODO
+	MX6PAD(GPIO_2__GPIO_1_2),		/* STNDBY */
+	MX6PAD(GPIO_7__GPIO_1_7),		/* NERR */
+	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_TEST_PADCFG),
+	MX6PAD(GPIO_4__GPIO_1_4),		/* Enable */
+#endif
+
+	MX6PAD(GPIO_9__PWM1_PWMO),		/* PWM1 */
+	MX6PAD(GPIO_1__PWM2_PWMO),		/* PWM2 */
+	MX6PAD(SD4_DAT1__PWM3_PWMO),		/* PWM3 */
+	MX6PAD(SD4_DAT2__PWM4_PWMO),		/* PWM4 */
 #ifdef TODO
 	MX6PAD(NANDF_D0__GPIO_2_0),		/* J6 - LVDS Display contrast */
 #endif
@@ -208,7 +190,7 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	MX6PAD(SD1_CMD__PWM4_PWMO),		/* GPIO1[18] */
 #endif
 	/* RTC ISL1208 irq*/
-	MX6PAD(NANDF_CLE__GPIO_6_7),
+	MX6PAD(NANDF_CLE__GPIO_6_7),		/* TS_DIFF5- */
 
 	/* Apalis UART1 */
 	MX6PAD(CSI0_DAT10__UART1_TXD),
@@ -234,33 +216,62 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	MX6PAD(KEY_COL1__UART5_TXD),
 	MX6PAD(KEY_ROW1__UART5_RXD),
 
-	/* Apalis, AUDMUX, local AC97 */
-	MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD),
+	/* Apalis, AUDMUX, local I2S */
 	MX6PAD(DISP0_DAT20__AUDMUX_AUD4_TXC),
 	MX6PAD(DISP0_DAT21__AUDMUX_AUD4_TXD),
 	MX6PAD(DISP0_DAT22__AUDMUX_AUD4_TXFS),
-	/* Apalis MMC1 */
-	SD_PINS(1, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
-	NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	/* Apalis SD1 */
-	SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
-	/* Apalis eMMC */
-	SD_PINS(3, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ),
-	NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(USDHC_PAD_CTRL_22KPU_40OHM_50MHZ)),
-	MX6PAD(SD3_RST__USDHC3_RST),
+	MX6PAD(DISP0_DAT23__AUDMUX_AUD4_RXD),
 
 	/* USBOTG ID pin */
 	MX6PAD(ENET_RX_ER__ANATOP_USBOTG_ID),
+	/* USBOTG USB_VBUS_DET to internal HUB pin */
+	MX6PAD(EIM_D28__GPIO_3_28),
+	/* USB OTG OC pin */
+	MX6PAD(EIM_D21__USBOH3_USBOTG_OC),
+	/* USBOTG Power Enable */
+	MX6PAD(EIM_D22__GPIO_3_22),
 
+	/* USBH Power Enable */
+	MX6PAD(GPIO_0__GPIO_1_0), /*GPIO_0__USBOH3_USBH1_PWR*/
 	/* USB OC pin */
-	MX6PAD(EIM_D21__USBOH3_USBOTG_OC),
 	MX6PAD(GPIO_3__USBOH3_USBH1_OC),
+
+	/* Apalis I2C1, i.MX I2C1*/
+	MX6PAD(CSI0_DAT9__I2C1_SCL),
+	MX6PAD(CSI0_DAT8__I2C1_SDA),
+
+	/* Apalis I2C3 (CAM), i.MX I2C3 */
+	MX6PAD(EIM_D17__I2C3_SCL),
+	MX6PAD(EIM_D18__I2C3_SDA),
+
+	/* Touch Int */
+	MX6PAD(KEY_COL2__GPIO_4_10),
+	0
+};
+
+/* Apalis I2C2 (DDC) */
+#define DDC_USE_I2C2
+static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = {
+#ifdef DDC_USE_I2C2
+	MX6PAD(KEY_COL3__GPIO_4_12),	/* I2C2 SCL */
+	MX6PAD(KEY_ROW3__GPIO_4_13),	/* I2C2 SDA */
+	MX6PAD(EIM_EB2__I2C2_SCL), 	/* HDMI DDC SCL */
+	MX6PAD(EIM_D16__I2C2_SDA), 	/* HDMI DDC SDA */
+#else
+	MX6PAD(EIM_EB2__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
+	MX6PAD(EIM_D16__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
+#endif
+	0
+};
+
+/* Apalis power I2C, i.MX I2C2*/
+static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = {
+#ifdef DDC_USE_I2C2
+	MX6PAD(EIM_EB2__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
+	MX6PAD(EIM_D16__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
+#endif
+	MX6PAD(KEY_COL3__I2C2_SCL),	/* I2C2 SCL */
+	MX6PAD(KEY_ROW3__I2C2_SDA),	/* I2C2 SDA */
 	0
 };
 
@@ -335,6 +346,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = {
 	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
 	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),		/* HSync */
 	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),		/* VSync */
+	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),		/* DE */
 	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
 	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
 	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
@@ -356,6 +368,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_enable)[] = {
 	MX6PAD(DI0_DISP_CLK__IPU2_DI0_DISP_CLK),
 	MX6PAD(DI0_PIN2__IPU2_DI0_PIN2),		/* HSync */
 	MX6PAD(DI0_PIN3__IPU2_DI0_PIN3),		/* VSync */
+	MX6PAD(DI0_PIN15__IPU2_DI0_PIN15),		/* DE */
 	MX6PAD(DISP0_DAT0__IPU2_DISP0_DAT_0),
 	MX6PAD(DISP0_DAT1__IPU2_DISP0_DAT_1),
 	MX6PAD(DISP0_DAT2__IPU2_DISP0_DAT_2),
@@ -380,6 +393,7 @@ static iomux_v3_cfg_t MX6NAME(vga_dac_disable)[] = {
 	MX6PAD(DI0_DISP_CLK__GPIO_4_16),
 	MX6PAD(DI0_PIN2__GPIO_4_18),			/* HSync */
 	MX6PAD(DI0_PIN3__GPIO_4_19),			/* VSync */
+	MX6PAD(DI0_PIN15__GPIO_4_17),		/* DE */
 	MX6PAD(DISP0_DAT0__GPIO_4_21),
 	MX6PAD(DISP0_DAT1__GPIO_4_22),
 	MX6PAD(DISP0_DAT2__GPIO_4_23),
@@ -436,29 +450,97 @@ static iomux_v3_cfg_t MX6NAME(csi0_sensor_pads)[] = {
 };
 #endif
 
-static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = {
-	MX6PAD(KEY_COL3__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */
-	MX6PAD(KEY_ROW3__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */
-	0
-};
-/* TODO fix that i2c mess */
-static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = {
-#ifdef TODO
-	MX6PAD(KEY_COL3__I2C2_SCL),	/* I2C2 SCL */
-	MX6PAD(KEY_ROW3__I2C2_SDA),	/* I2C2 SDA */
-#endif
-	0
-};
-
 #ifdef TODO
 static iomux_v3_cfg_t MX6NAME(mc33902_flexcan_pads)[] = {
 	NEW_PAD_CTRL(MX6PAD(GPIO_7__GPIO_1_7), CAN1_ERR_PADCFG),
 	0
 };
 #endif
+
+/* MMC / SD Cards */
+#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
+		PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define MX6Q_USDHC_PAD_CTRL_50MHZ	MX6Q_USDHC_PAD_CTRL
+#define MX6Q_PAD_SD3_CLK__USDHC3_CLK	MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6Q_PAD_SD3_CMD__USDHC3_CMD	MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6Q_PAD_SD3_DAT4__USDHC3_DAT4	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6Q_PAD_SD3_DAT5__USDHC3_DAT5	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6Q_PAD_SD3_DAT6__USDHC3_DAT6	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6Q_PAD_SD3_DAT7__USDHC3_DAT7	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6Q_PAD_SD4_CLK__USDHC4_CLK	MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6Q_PAD_SD4_CMD__USDHC4_CMD	MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ	MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ
+#define MX6DL_USDHC_PAD_CTRL_50MHZ	MX6DL_USDHC_PAD_CTRL
+#define MX6DL_PAD_SD3_CLK__USDHC3_CLK	MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ
+#define MX6DL_PAD_SD3_CMD__USDHC3_CMD	MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ
+#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6DL_PAD_SD3_DAT4__USDHC3_DAT4	MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ
+#define MX6DL_PAD_SD3_DAT5__USDHC3_DAT5	MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ
+#define MX6DL_PAD_SD3_DAT6__USDHC3_DAT6	MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ
+#define MX6DL_PAD_SD3_DAT7__USDHC3_DAT7	MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ
+#define MX6DL_PAD_SD4_CLK__USDHC4_CLK	MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ
+#define MX6DL_PAD_SD4_CMD__USDHC4_CMD	MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ
+#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0	MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ
+#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1	MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ
+#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2	MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ
+#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3	MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ
+
+#define NP(id, pin, pad_ctl) \
+	NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl))
+
+#define SD_PINS(id, pad_ctl) \
+	NP(id, CLK, pad_ctl),	\
+	NP(id, CMD, pad_ctl),	\
+	NP(id, DAT0, pad_ctl),	\
+	NP(id, DAT1, pad_ctl),	\
+	NP(id, DAT2, pad_ctl),	\
+	NP(id, DAT3, pad_ctl)
+
+/* Apalis MMC1 */
+#define SD_PINS1(pad_ctl) \
+	SD_PINS(1, pad_ctl), \
+	NEW_PAD_CTRL(MX6PAD(NANDF_D0__USDHC1_DAT4), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(NANDF_D1__USDHC1_DAT5), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(NANDF_D2__USDHC1_DAT6), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(NANDF_D3__USDHC1_DAT7), MX6(pad_ctl))
+
+/* Apalis SD1 */
+#define SD_PINS2(pad_ctl) \
+	SD_PINS(2, pad_ctl)
+
+/* Apalis eMMC */
+#define SD_PINS3(pad_ctl) \
+	SD_PINS(3, pad_ctl), \
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT4__USDHC3_DAT4), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT5__USDHC3_DAT5), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT6__USDHC3_DAT6), MX6(pad_ctl)), \
+	NEW_PAD_CTRL(MX6PAD(SD3_DAT7__USDHC3_DAT7), MX6(pad_ctl)), \
+	MX6PAD(SD3_RST__USDHC3_RST)
+
+/* not in default pinmuxing, pins partly used for UART2 & PWM */
+#define SD_PINS4(pad_ctl) \
+	SD_PINS(4, pad_ctl)
+
 #define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl)	\
-		MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 }
+		MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS##id(pad_ctl), 0 }
 
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 100, USDHC_PAD_CTRL_100MHZ);
+static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(1, 200, USDHC_PAD_CTRL_200MHZ);
 static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ);
 static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ);
 static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ);
@@ -475,6 +557,9 @@ static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(4, 200, USDHC_PAD_CTRL_200MHZ);
 #define SD_SPEED_CNT 3
 static iomux_v3_cfg_t * MX6NAME(sd_pads)[] =
 {
+	MX6NAME(sd1_50mhz),
+	MX6NAME(sd1_100mhz),
+	MX6NAME(sd1_200mhz),
 	MX6NAME(sd2_50mhz),
 	MX6NAME(sd2_100mhz),
 	MX6NAME(sd2_200mhz),