diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-23 17:10:22 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2019-04-24 13:56:38 +0200 |
| commit | 3157324388241f3864496156c9a69b0988913290 (patch) | |
| tree | ea2188915e7d31c28ef823bdd938add5c0068c95 | |
| parent | 7c093605960442f6bc90684686bebc132dd99b3c (diff) | |
ARM: dts: imx8: apalis-imx8qm: enable adc0/1
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 78d8470b71a0..bea711d0b7fd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -203,6 +203,32 @@ <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_sata1_act>; apalis-imx8qm { + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + SC_P_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + /* Apalis AN1_ADC1 */ + SC_P_ADC_IN1_DMA_ADC0_IN1 0xc0000060 + /* Apalis AN1_ADC2 */ + SC_P_ADC_IN2_DMA_ADC0_IN2 0xc0000060 + /* Apalis AN1_TSWIP_ADC3 */ + SC_P_ADC_IN3_DMA_ADC0_IN3 0xc0000060 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + /* Apalis AN1_TSPX */ + SC_P_ADC_IN4_DMA_ADC1_IN0 0xc0000060 + /* Apalis AN1_TSMX */ + SC_P_ADC_IN5_DMA_ADC1_IN1 0xc0000060 + /* Apalis AN1_TSPY */ + SC_P_ADC_IN6_DMA_ADC1_IN2 0xc0000060 + /* Apalis AN1_TSMY */ + SC_P_ADC_IN7_DMA_ADC1_IN3 0xc0000060 + >; + }; + pinctrl_sgtl5000: sgtl5000grp { fsl,pins = < /* On-module SGTL5000 SYS_MCLK */ @@ -696,6 +722,20 @@ }; }; +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc1>; + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + &asrc0 { fsl,asrc-rate = <48000>; status = "okay"; |