diff options
author | Stefan Agner <stefan.agner@toradex.com> | 2018-01-17 15:57:51 +0100 |
---|---|---|
committer | Stefan Agner <stefan.agner@toradex.com> | 2018-01-17 15:57:51 +0100 |
commit | 4fc7d05a989cada7eef8c526c35edd83232241e3 (patch) | |
tree | ebc7196e959191e6edca6e597d6edc0b83b13c32 | |
parent | 6a09ad5345af7b1b45c9c5f7f2c31c2504932e4a (diff) |
apalis-imx8qm: take PLX PCIe switch out of reset via GPIO7
The Apalis iMX8 does not make use of the PCIE_CTRL0_PERST_B signal.
However, the Apalis Evaluation Board uses GPIO7 as a PCIe reset
signal for the PLX PCIe switch. With this the Apalis PCIe port
comes up as Gen2 successfully on the Apalis Evaluation board.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index c3a158a4c30e..f9f2afd55afb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -327,6 +327,7 @@ SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 + SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 >; }; @@ -646,7 +647,7 @@ <&pcie_sata_refclk_gate>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; - reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; |