diff options
| author | Shengjiu Wang <shengjiu.wang@nxp.com> | 2017-11-17 16:38:41 +0800 |
|---|---|---|
| committer | Shengjiu Wang <shengjiu.wang@nxp.com> | 2017-11-17 17:21:19 +0800 |
| commit | 80ac7ab6dd4d46efaf0d551b1713a8b4cc8b715c (patch) | |
| tree | 1575f6654750e6a7ba6ed4be5d87be319f3ae47b | |
| parent | 8e919f858ac5f32667c9f73cddefd1ed726f0ae2 (diff) | |
MLK-16839-2: ARM64: dts: add clock source for asrc
add IMX8QM_ACM_AUD_CLK0_SEL and IMX8QM_ACM_AUD_CLK1_SEL for
asrc clock source. There is no clock gate for them, only
clock mux.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
(cherry picked from commit f6d3c3ad9f534e1725d1c96b0086beeec44f04c6)
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi index 7ccd24db3974..1cf89295b7b3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi @@ -2803,8 +2803,8 @@ <&clk IMX8QM_AUD_ASRC_0_MEM>, <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, - <&clk IMX8QM_CLK_DUMMY>, - <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>, <&clk IMX8QM_CLK_DUMMY>, <&clk IMX8QM_CLK_DUMMY>, <&clk IMX8QM_CLK_DUMMY>, @@ -2843,8 +2843,8 @@ <&clk IMX8QM_AUD_ASRC_1_MEM>, <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>, <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>, - <&clk IMX8QM_CLK_DUMMY>, - <&clk IMX8QM_CLK_DUMMY>, + <&clk IMX8QM_ACM_AUD_CLK0_SEL>, + <&clk IMX8QM_ACM_AUD_CLK1_SEL>, <&clk IMX8QM_CLK_DUMMY>, <&clk IMX8QM_CLK_DUMMY>, <&clk IMX8QM_CLK_DUMMY>, diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi index 98b70529bfae..4410e69c46ee 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi @@ -1956,8 +1956,8 @@ <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, - <&clk IMX8QXP_CLK_DUMMY>, - <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_CLK_DUMMY>, @@ -1996,8 +1996,8 @@ <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, - <&clk IMX8QXP_CLK_DUMMY>, - <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_ACM_AUD_CLK0_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK1_CLK>, <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_CLK_DUMMY>, |