diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-04-05 15:36:42 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2018-04-05 15:36:42 +0200 |
| commit | 7aa7248a3fc30f64061a18ad97d7b931b46fa79d (patch) | |
| tree | 037241a51d82847eb7a0723fcd39574624889984 | |
| parent | 0258be2764f78860c59303154fa1793b420499a0 (diff) | |
apalis-imx8qm: fix UART2 RTS/CTS signal
Add RTS/CTS signal to UART2. Also remove the wrong pins muxed
for UART3 (lpuart0). UART3 does not have RTS/CTS pins in the
Apalis standard.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 4eca070157ad..0772ec6c41b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -180,8 +180,6 @@ fsl,pins = < SC_P_UART0_RX_DMA_UART0_RX 0x06000020 SC_P_UART0_TX_DMA_UART0_TX 0x06000020 - SC_P_UART0_RTS_B_DMA_UART0_RTS_B 0x06000020 - SC_P_UART0_CTS_B_DMA_UART0_CTS_B 0x06000020 >; }; @@ -205,6 +203,8 @@ fsl,pins = < SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 + SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 + SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 >; }; |