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authorAfzal Mohammed <afzal@ti.com>2012-10-01 02:47:28 +0530
committerAfzal Mohammed <afzal@ti.com>2012-10-15 14:42:08 +0530
commit3852ccd66a9bcb2aa6f46bce5442b6d8d08e5b5d (patch)
tree194b7067ba84e37560631fb85f7e0f3a0f3080d6
parent47f88af4ed80ac9ca593543e21ebf86a31d7e8ba (diff)
ARM: OMAP2+: nand: bch capability check
Capability of bch schemes could be discovered using soc revision checks. If soc revision indicates that selected ecc scheme is not supported bail out. Signed-off-by: Afzal Mohammed <afzal@ti.com>
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index abdb78a95a94..e89a36c8143b 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -90,6 +90,27 @@ static int omap2_nand_gpmc_retime(
return 0;
}
+static bool __init gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
+{
+ /* support only OMAP3 class */
+ if (!cpu_is_omap34xx()) {
+ pr_err("BCH ecc is not supported on this CPU\n");
+ return 0;
+ }
+
+ /*
+ * For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1.
+ * Other chips may be added if confirmed to work.
+ */
+ if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
+ (!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0))) {
+ pr_err("BCH 4-bit mode is not supported on this CPU\n");
+ return 0;
+ }
+
+ return 1;
+}
+
int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
struct gpmc_timings *gpmc_t)
{
@@ -128,6 +149,9 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
+ if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
+ return -EINVAL;
+
err = platform_device_register(&gpmc_nand_device);
if (err < 0) {
dev_err(dev, "Unable to register NAND device\n");