diff options
| author | Xinyu Chen <b03824@freescale.com> | 2012-05-25 17:06:07 +0800 |
|---|---|---|
| committer | Xinyu Chen <b03824@freescale.com> | 2012-05-25 17:06:07 +0800 |
| commit | fd60e6b4548d6e31beff9a959148653481b2e695 (patch) | |
| tree | e64a630c6aafd3723dfd7f293ab970f0aaf17418 | |
| parent | 411d6f671b216f7127284349d9c30a6cca88a15d (diff) | |
| parent | 79f31695fcba11cb303e039eddaea82197416368 (diff) | |
Merge remote branch 'fsl-linux-sdk/imx_3.0.15' into imx_3.0.15_android
Conflicts:
arch/arm/configs/imx6_defconfig
arch/arm/kernel/smp.c
arch/arm/mach-mx6/board-mx6q_arm2.c
arch/arm/mach-mx6/board-mx6q_sabreauto.c
arch/arm/mach-mx6/board-mx6q_sabrelite.c
arch/arm/mach-mx6/board-mx6q_sabresd.c
arch/arm/mach-mx6/bus_freq.c
arch/arm/mach-mx6/clock.c
arch/arm/mach-mx6/cpu.c
arch/arm/mach-mx6/devices-imx6q.h
arch/arm/mach-mx6/mx6_ddr_freq.S
arch/arm/mach-mx6/mx6_mmdc.c
arch/arm/mach-mx6/mx6_suspend.S
arch/arm/mach-mx6/mx6_wfi.S
arch/arm/mach-mx6/plat_hotplug.c
arch/arm/mach-mx6/pm.c
arch/arm/mach-mx6/system.c
arch/arm/plat-mxc/cpufreq.c
arch/arm/plat-mxc/system.c
drivers/media/video/mxc/capture/Kconfig
drivers/media/video/mxc/capture/mxc_v4l2_capture.c
drivers/media/video/mxc/capture/ov5640_mipi.c
drivers/media/video/mxc/output/mxc_vout.c
drivers/mmc/host/sdhci.c
drivers/mtd/nand/gpmi-nand/gpmi-lib.c
drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c
drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c
drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h
drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h
drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c
drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c
drivers/mxc/ipu3/vdoa.c
drivers/power/max8903_charger.c
drivers/video/mxc/mxc_ipuv3_fb.c
sound/soc/codecs/mxc_spdif.c
sound/soc/imx/Makefile
sound/soc/imx/imx-wm8962.c
163 files changed, 73363 insertions, 1499 deletions
diff --git a/Documentation/arm/imx/udc.txt b/Documentation/arm/imx/udc.txt index e532f310d24d..27bee3b6b420 100644 --- a/Documentation/arm/imx/udc.txt +++ b/Documentation/arm/imx/udc.txt @@ -33,3 +33,27 @@ to different PCs. Since there is no feedback at current usb audio framework, it may have pop noise/no sound after play some minutes. +How to test auto remote wakeup with the g_zero gadget +1. Prepare a USB host which featured with remote wakeup alternatively, You can +use another i.mx board (like mx50 rdp, or mx6q) for test device board. +2. Boot up both boards, and connect two boards with USB cable. +3. At device side, do below commands: +modprobe g_zero autoresume=3000 interval=1 endms=5000 +we can use the above three parameters to control device send resume signal time. +Autoresume is the minimum number of milliseconds before sending resume signal, +and the time before sending resume signal will automatically increase according +to interval value,the endms is the max number of milliseconds before sending +resume signal.When autoresume is 0 or not be set,the test device auto remote +wakeup function will be disabled. +4. At host side, first do below command: +echo enabled > /sys/devices/platform/fsl-ehci.1/power/wakeup +echo enabled > /sys/bus/usb/devices/1-1/power/wakeup +And you need build a test script to repeat standby the system like below: +while [ 1 ] ;do echo mem > /sys/power/state;sleep 5 ;done +Then run the test script. +5. Then USB device will enter the suspended state ,and autoresume +milliseconds later,the device will send resume signal to wake up host. +6. The expected behavior is: the host device be waked up, and there is not +re-enumeration happens. +7. The host will enter suspended state again,and test case will repeat step +5 and step 6. diff --git a/arch/arm/configs/imx6_defconfig b/arch/arm/configs/imx6_defconfig index bf23d5ef3d4c..5b9078268f68 100644 --- a/arch/arm/configs/imx6_defconfig +++ b/arch/arm/configs/imx6_defconfig @@ -965,6 +965,7 @@ CONFIG_SMSC911X=y # CONFIG_KS8851 is not set # CONFIG_KS8851_MLL is not set CONFIG_FEC=y +CONFIG_FEC_NAPI=y # CONFIG_FEC_1588 is not set # CONFIG_FTMAC100 is not set # CONFIG_NETDEV_1000 is not set @@ -1067,11 +1068,12 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_EETI is not set CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_ELAN=y # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_MAX11801 is not set +CONFIG_TOUCHSCREEN_MAX11801=y # CONFIG_TOUCHSCREEN_MCS5000 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set @@ -1291,7 +1293,8 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_ISP1704 is not set -CONFIG_CHARGER_MAX8903=y +# CONFIG_CHARGER_MAX8903 is not set +CONFIG_SABRESD_MAX8903=y # CONFIG_CHARGER_GPIO is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set @@ -2088,7 +2091,8 @@ CONFIG_LEDS_CLASS=y # # CONFIG_LEDS_LM3530 is not set # CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP5521 is not set # CONFIG_LEDS_LP5523 is not set @@ -2098,7 +2102,7 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_REGULATOR is not set # CONFIG_LEDS_BD2802 is not set # CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_TRIGGERS is not set +CONFIG_LEDS_TRIGGERS=y # # LED Triggers @@ -2108,12 +2112,6 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set CONFIG_LEDS_TRIGGER_GPIO=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_LEDS_TRIGGER_SLEEP=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y # # iptables trigger is under Netfilter config (LED target) diff --git a/arch/arm/configs/imx6_updater_defconfig b/arch/arm/configs/imx6_updater_defconfig index c40094c2bde2..56406344b130 100644 --- a/arch/arm/configs/imx6_updater_defconfig +++ b/arch/arm/configs/imx6_updater_defconfig @@ -26,7 +26,7 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_FIQ=y CONFIG_VECTORS_BASE=0xffff0000 -# CONFIG_ARM_PATCH_PHYS_VIRT is not set +CONFIG_ARM_PATCH_PHYS_VIRT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_HAVE_IRQ_WORK=y CONFIG_IRQ_WORK=y @@ -264,6 +264,7 @@ CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM=y CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y @@ -292,6 +293,8 @@ CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y +CONFIG_IMX_HAVE_PLATFORM_IMX_VDOA=y +CONFIG_IMX_HAVE_PLATFORM_IMX_PCIE=y # # Freescale MXC Implementations @@ -306,7 +309,9 @@ CONFIG_ARCH_MX6=y CONFIG_ARCH_MX6Q=y CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y CONFIG_MACH_MX6Q_ARM2=y +CONFIG_MACH_MX6SL_ARM2=y CONFIG_MACH_MX6Q_SABRELITE=y CONFIG_MACH_MX6Q_SABRESD=y CONFIG_MACH_MX6Q_SABREAUTO=y @@ -315,10 +320,13 @@ CONFIG_MACH_MX6Q_SABREAUTO=y # MX6 Options: # # CONFIG_IMX_PCIE is not set +# CONFIG_MX6_INTER_LDO_BYPASS is not set CONFIG_ISP1504_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set CONFIG_MXC_PWM=y # CONFIG_MXC_DEBUG_BOARD is not set +# CONFIG_MXC_REBOOT_MFGMODE is not set +# CONFIG_MXC_REBOOT_ANDROID_CMD is not set CONFIG_ARCH_MXC_IOMUX_V3=y CONFIG_ARCH_MXC_AUDMUX_V2=y CONFIG_IRAM_ALLOC=y @@ -451,7 +459,7 @@ CONFIG_CMDLINE_FROM_BOOTLOADER=y # CONFIG_XIP_KERNEL is not set # CONFIG_KEXEC is not set # CONFIG_CRASH_DUMP is not set -# CONFIG_AUTO_ZRELADDR is not set +CONFIG_AUTO_ZRELADDR=y # # CPU Power Management @@ -904,6 +912,7 @@ CONFIG_SMSC911X=y # CONFIG_KS8851 is not set # CONFIG_KS8851_MLL is not set CONFIG_FEC=y +# CONFIG_FEC_NAPI is not set # CONFIG_FEC_1588 is not set # CONFIG_FTMAC100 is not set # CONFIG_NETDEV_1000 is not set @@ -981,6 +990,7 @@ CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set # CONFIG_TOUCHSCREEN_EETI is not set CONFIG_TOUCHSCREEN_EGALAX=y +# CONFIG_TOUCHSCREEN_ELAN is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set @@ -1414,10 +1424,10 @@ CONFIG_VIDEO_MXC_IPU_CAMERA=y # CONFIG_MXC_CAMERA_OV2640 is not set CONFIG_MXC_CAMERA_OV3640=m CONFIG_MXC_CAMERA_OV5640=m -# CONFIG_MXC_CAMERA_OV5640_MIPI is not set # CONFIG_MXC_CAMERA_OV8820_MIPI is not set CONFIG_MXC_CAMERA_OV5642=m # CONFIG_MXC_TVIN_ADV7180 is not set +# CONFIG_MXC_CAMERA_OV5640_MIPI is not set CONFIG_MXC_CAMERA_SENSOR_CLK=m CONFIG_MXC_IPU_PRP_VF_SDC=m CONFIG_MXC_IPU_PRP_ENC=m @@ -1555,7 +1565,9 @@ CONFIG_SND_SOC_AC97_BUS=y CONFIG_SND_IMX_SOC=y CONFIG_SND_MXC_SOC_MX2=y # CONFIG_SND_SOC_IMX_SGTL5000 is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set CONFIG_SND_SOC_IMX_CS42888=y +# CONFIG_SND_SOC_IMX_SI4763 is not set # CONFIG_SND_SOC_IMX_SPDIF is not set # CONFIG_SND_SOC_IMX_HDMI is not set CONFIG_SND_SOC_I2C_AND_SPI=y @@ -1886,7 +1898,6 @@ CONFIG_DMADEVICES=y # DMA Devices # # CONFIG_DW_DMAC is not set -# CONFIG_MXC_PXP is not set # CONFIG_MXC_PXP_V2 is not set # CONFIG_TIMB_DMA is not set CONFIG_IMX_SDMA=y @@ -2367,6 +2378,7 @@ CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_USER_API_HASH is not set # CONFIG_CRYPTO_USER_API_SKCIPHER is not set CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FSL_CAAM is not set # CONFIG_BINARY_PRINTF is not set # diff --git a/arch/arm/configs/imx6s_defconfig b/arch/arm/configs/imx6s_defconfig new file mode 100644 index 000000000000..3db0aeee4e22 --- /dev/null +++ b/arch/arm/configs/imx6s_defconfig @@ -0,0 +1,2639 @@ +# +# Automatically generated make config: don't edit +# Linux/arm 3.0.15 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_SCHED_CLOCK=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_FIQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +# CONFIG_SPARSE_IRQ is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +# CONFIG_TINY_RCU is not set +# CONFIG_TINY_PREEMPT_RCU is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_MXC=y +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_NUC93X is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS4 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_IMX_HAVE_PLATFORM_DMA=y +CONFIG_IMX_HAVE_PLATFORM_MXC_MLB=y +CONFIG_IMX_HAVE_PLATFORM_FEC=y +CONFIG_IMX_HAVE_PLATFORM_FLEXCAN=y +CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC=y +CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC=y +CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_I2C=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SSI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_ESAI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_UART=y +CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI=y +CONFIG_IMX_HAVE_PLATFORM_MXC_PWM=y +CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX=y +CONFIG_IMX_HAVE_PLATFORM_SPI_IMX=y +CONFIG_IMX_HAVE_PLATFORM_IMX_IPUV3=y +CONFIG_IMX_HAVE_PLATFORM_IMX_VPU=y +CONFIG_IMX_HAVE_PLATFORM_IMX_DVFS=y +CONFIG_IMX_HAVE_PLATFORM_AHCI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_OCOTP=y +CONFIG_IMX_HAVE_PLATFORM_IMX_VIIM=y +CONFIG_IMX_HAVE_PLATFORM_PERFMON=y +CONFIG_IMX_HAVE_PLATFORM_LDB=y +CONFIG_IMX_HAVE_PLATFORM_IMX_PXP=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF=y +CONFIG_IMX_HAVE_PLATFORM_VIV_GPU=y +CONFIG_IMX_HAVE_PLATFORM_MXC_HDMI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL=y +CONFIG_IMX_HAVE_PLATFORM_FSL_OTG=y +CONFIG_IMX_HAVE_PLATFORM_FSL_USB_WAKEUP=y +CONFIG_IMX_HAVE_PLATFORM_IMX_PM=y +CONFIG_IMX_HAVE_PLATFORM_IMX_ASRC=y +CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_DSI=y +CONFIG_IMX_HAVE_PLATFORM_IMX_MIPI_CSI2=y + +# +# Freescale MXC Implementations +# +# CONFIG_ARCH_MX1 is not set +# CONFIG_ARCH_MX2 is not set +# CONFIG_ARCH_MX25 is not set +# CONFIG_ARCH_MX3 is not set +# CONFIG_ARCH_MX503 is not set +# CONFIG_ARCH_MX51 is not set +CONFIG_ARCH_MX6=y +CONFIG_ARCH_MX6Q=y +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_MACH_MX6Q_ARM2=y +CONFIG_MACH_MX6SL_ARM2=y +CONFIG_MACH_MX6Q_SABRESD=y + +# +# MX6 Options: +# +# CONFIG_IMX_PCIE is not set +CONFIG_ISP1504_MXC=y +# CONFIG_MXC_IRQ_PRIOR is not set +CONFIG_MXC_PWM=y +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_ARCH_MXC_IOMUX_V3=y +CONFIG_ARCH_MXC_AUDMUX_V2=y +CONFIG_IRAM_ALLOC=y +CONFIG_CLK_DEBUG=y +CONFIG_DMA_ZONE_SIZE=184 + +# +# System MMU +# + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_CPU_HAS_PMU=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_PL310_ERRATA_727915 is not set +CONFIG_ARM_ERRATA_743622=y +# CONFIG_ARM_ERRATA_753970 is not set +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_GIC=y + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set +# CONFIG_PL310_ERRATA_769419 is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_SMP is not set +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw rootfstype=jffs2 ip=off" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_IMX=y +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_SUSPEND=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_SUSPEND_DEVICE_TIME_DEBUG=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_CAN_PM_TRACE=y +CONFIG_APM_EMULATION=y +CONFIG_PM_RUNTIME_CLK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_SLCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_MCP251X is not set +CONFIG_HAVE_CAN_FLEXCAN=y +CONFIG_CAN_FLEXCAN=y +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_C_CAN is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_ESD_USB2 is not set +# CONFIG_CAN_SOFTING is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +CONFIG_BT_HCIUART_ATH3K=y +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +CONFIG_BT_HCIVHCI=y +# CONFIG_BT_MRVL is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND_ECC=y +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_GPMI_NAND is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085 is not set +CONFIG_MXS_PERFMON=m +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +# CONFIG_SATA_PMP is not set + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_SATA_MV is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ARASAN_CF is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_PLATFORM is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_MII=y +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +CONFIG_MICREL_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_FEC=y +# CONFIG_FEC_1588 is not set +# CONFIG_FTMAC100 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +CONFIG_WLAN=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +CONFIG_ATH6KL=m +# CONFIG_ATH6KL_DEBUG is not set +CONFIG_HOSTAP=y +# CONFIG_HOSTAP_FIRMWARE is not set +# CONFIG_IWM is not set +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_WAN is not set + +# +# CAIF transport drivers +# +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_APMPOWER is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_IMX is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_MXC is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +CONFIG_TOUCHSCREEN_EGALAX=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_P1003 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set +CONFIG_INPUT_ISL29023=y + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_FSL_OTP=y +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_MXS_VIIM=y +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_IMX=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX_VER_2_3=y +CONFIG_SPI_IMX=y +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_BASIC_MMIO is not set +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_WM8994 is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_APM_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ20Z75 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +CONFIG_CHARGER_MAX8903=y +# CONFIG_CHARGER_GPIO is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +CONFIG_SENSORS_MAX17135=y +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_MAG3110=y +# CONFIG_MXC_MMA8450 is not set +CONFIG_MXC_MMA8451=y +CONFIG_THERMAL=y +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_IMX2_WDT=y + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set +CONFIG_MFD_SUPPORT=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +CONFIG_MFD_WM8994=y +# CONFIG_MFD_PCF50633 is not set +# CONFIG_PMIC_DIALOG is not set +# CONFIG_MFD_MC_PMIC is not set +# CONFIG_MFD_MC34708 is not set +CONFIG_MFD_PFUZE=y +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65910 is not set +CONFIG_MFD_MAX17135=y +CONFIG_MFD_MXC_HDMI=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_WM8994 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_MC34708 is not set +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ANATOP=y +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_MAX17135=y +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_VIVI is not set +CONFIG_VIDEO_MXC_CAMERA=m + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +# CONFIG_VIDEO_MXC_CSI_CAMERA is not set +# CONFIG_MXC_CAMERA_MICRON111 is not set +# CONFIG_MXC_CAMERA_OV2640 is not set +CONFIG_MXC_CAMERA_OV3640=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_CAMERA_OV8820_MIPI=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_CAMERA_SENSOR_CLK=m +CONFIG_MXC_IPU_PRP_VF_SDC=m +CONFIG_MXC_IPU_PRP_ENC=m +CONFIG_MXC_IPU_CSI_ENC=m +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set +# CONFIG_VIDEO_MXC_OPL is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_TIMBERDALE is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_PVRUSB2 is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_VIDEO_USBVISION is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_PWC is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_FB_MXC=y +CONFIG_FB_MXC_EDID=y +CONFIG_FB_MXC_SYNC_PANEL=y +# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +# CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL is not set +# CONFIG_FB_MXC_SII902X is not set +# CONFIG_FB_MXC_CH7026 is not set +# CONFIG_FB_MXC_TVOUT_CH7024 is not set +# CONFIG_FB_MXC_ASYNC_PANEL is not set +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set +# CONFIG_FB_MXC_ELCDIF_FB is not set +# CONFIG_FB_MXC_SIPIX_PANEL is not set +# CONFIG_FB_MXC_SIPIX_AUTO_UPDATE_MODE is not set +CONFIG_FB_MXC_HDMI=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +# CONFIG_SND_SOC_CACHE_LZO is not set +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_MXC_SOC_MX2=y +CONFIG_SND_MXC_SOC_SPDIF_DAI=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_WM_HUBS=y +CONFIG_SND_SOC_MXC_HDMI=y +CONFIG_SND_SOC_MXC_SPDIF=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_CS42888=y +CONFIG_SND_SOC_WM8994=y +CONFIG_SND_SOC_WM8962=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=m +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=m +CONFIG_HID_BELKIN=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +# CONFIG_HID_PRODIKEYS is not set +CONFIG_HID_CYPRESS=m +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +CONFIG_HID_EZKEY=m +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +CONFIG_HID_GYRATION=m +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +CONFIG_HID_LOGITECH=m +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWII_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +CONFIG_HID_PANTHERLORD=m +# CONFIG_PANTHERLORD_FF is not set +CONFIG_HID_PETALYNX=m +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_ROCCAT_ARVO is not set +# CONFIG_HID_ROCCAT_KONE is not set +# CONFIG_HID_ROCCAT_KONEPLUS is not set +# CONFIG_HID_ROCCAT_KOVAPLUS is not set +# CONFIG_HID_ROCCAT_PYRA is not set +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m +CONFIG_HID_SUNPLUS=m +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_EHCI_ARC_HSIC is not set +# CONFIG_USB_STATIC_IRAM is not set +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_SELECTED=y +CONFIG_USB_GADGET_ARC=y +CONFIG_USB_ARC=y +# CONFIG_USB_GADGET_FSL_USB2 is not set +# CONFIG_USB_GADGET_FUSB300 is not set +# CONFIG_USB_GADGET_R8A66597 is not set +# CONFIG_USB_GADGET_PXA_U2O is not set +# CONFIG_USB_GADGET_M66592 is not set +# CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MXC_OTG=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TRIGGERS is not set + +# +# LED Triggers +# + +# +# LED Triggers +# +# CONFIG_NFC_DEVICES is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_MXC is not set +# CONFIG_RTC_DRV_MXC_V2 is not set +CONFIG_RTC_DRV_SNVS=y +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_IMX_SDMA=y +# CONFIG_MXS_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_MMIO=y + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y +CONFIG_MXC_IPU_V3=y +CONFIG_MXC_IPU_V3H=y + +# +# MXC SSI support +# +# CONFIG_MXC_SSI is not set + +# +# MXC Digital Audio Multiplexer support +# +# CONFIG_MXC_DAM is not set + +# +# MXC PMIC support +# +# CONFIG_MXC_PMIC_MC13783 is not set +# CONFIG_MXC_PMIC_MC13892 is not set +# CONFIG_MXC_PMIC_MC34704 is not set +# CONFIG_MXC_PMIC_MC9SDZ60 is not set +# CONFIG_MXC_PMIC_MC9S08DZ60 is not set + +# +# MXC Security Drivers +# +# CONFIG_MXC_SECURITY_SCC is not set +# CONFIG_MXC_SECURITY_RNG is not set + +# +# MXC MPEG4 Encoder Kernel module support +# +# CONFIG_MXC_HMP4E is not set + +# +# MXC HARDWARE EVENT +# +# CONFIG_MXC_HWEVENT is not set + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set + +# +# MXC Asynchronous Sample Rate Converter support +# +CONFIG_MXC_ASRC=y + +# +# MXC Bluetooth support +# + +# +# Broadcom GPS ioctrl support +# + +# +# MXC Media Local Bus Driver +# +CONFIG_MXC_MLB=y +CONFIG_MXC_MLB150=m + +# +# i.MX ADC support +# +# CONFIG_IMX_ADC is not set + +# +# MXC Vivante GPU support +# +CONFIG_MXC_GPU_VIV=m + +# +# ANATOP_THERMAL +# +CONFIG_ANATOP_THERMAL=y + +# +# MXC MIPI Support +# +CONFIG_MXC_MIPI_CSI2=y + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=m +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_SPARSE_RCU_POINTER is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_LKDTM is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_OC_ETM is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +CONFIG_CRYPTO_TEST=m +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +# CONFIG_AVERAGE is not set diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig index 1db924a0975e..c6851d064eaa 100644 --- a/arch/arm/mach-mx6/Kconfig +++ b/arch/arm/mach-mx6/Kconfig @@ -23,6 +23,9 @@ config FORCE_MAX_ZONEORDER config SOC_IMX6Q bool +config SOC_IMX6SL + bool + config MACH_MX6Q_ARM2 bool "Support i.MX 6Quad Armadillo2 platform" select ARCH_MX6Q @@ -59,12 +62,46 @@ config MACH_MX6Q_ARM2 select IMX_HAVE_PLATFORM_PERFMON select IMX_HAVE_PLATFORM_MXC_MLB select IMX_HAVE_PLATFORM_IMX_EPDC + select IMX_HAVE_PLATFORM_IMX_ELCDIF select IMX_HAVE_PLATFORM_IMX_PXP select IMX_HAVE_PLATFORM_IMX_PCIE help Include support for i.MX 6Quad Armadillo2 platform. This includes specific configurations for the board and its peripherals. +config MACH_MX6SL_ARM2 + bool "Support i.MX 6SoloLite Armadillo2 platform" + select ARCH_MX6Q + select SOC_IMX6SL + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_DMA + select IMX_HAVE_PLATFORM_FEC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_VIV_GPU + select IMX_HAVE_PLATFORM_IMX_DVFS + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_FSL_OTG + select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP + select IMX_HAVE_PLATFORM_AHCI + select IMX_HAVE_PLATFORM_IMX_OCOTP + select IMX_HAVE_PLATFORM_IMX_VIIM + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_SNVS_RTC + select IMX_HAVE_PLATFORM_IMX_PM + select IMX_HAVE_PLATFORM_IMX_SPDIF + select IMX_HAVE_PLATFORM_PERFMON + select IMX_HAVE_PLATFORM_IMX_EPDC + select IMX_HAVE_PLATFORM_IMX_SPDC + select IMX_HAVE_PLATFORM_IMX_PXP + help + Include support for i.MX 6Sololite Armadillo2 platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX6Q_SABRELITE bool "Support i.MX 6Quad SABRE Lite platform" select ARCH_MX6Q @@ -172,4 +209,13 @@ config IMX_PCIE bool "PCI Express support" select PCI +config MX6_INTER_LDO_BYPASS + bool "Internal LDO in MX6Q/DL bypass" + depends on REGULATOR_PFUZE100 && CPU_FREQ_IMX && ARCH_MX6 + default n + help + This is choosed for bypass internal LDO in MX6. If choose it, internal + LDO will replaced by external pmic regulator(e.g. pfuze100), VDDCORE + can be adjust automatically adjust by cpu frequency. + endif diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile index e76f438c9194..03ae8ddfc75d 100644 --- a/arch/arm/mach-mx6/Makefile +++ b/arch/arm/mach-mx6/Makefile @@ -7,8 +7,9 @@ obj-y := cpu.o mm.o system.o devices.o dummy_gpio.o irq.o bus_freq.o usb_dr.o pm.o cpu_op-mx6.o mx6_wfi.o mx6_fec.o mx6_anatop_regulator.o cpu_regulator-mx6.o \ mx6_mmdc.o mx6_ddr_freq.o -obj-$(CONFIG_ARCH_MX6) += clock.o mx6q_suspend.o +obj-$(CONFIG_ARCH_MX6) += clock.o mx6_suspend.o clock_mx6sl.o obj-$(CONFIG_MACH_MX6Q_ARM2) += board-mx6q_arm2.o +obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o obj-$(CONFIG_MACH_MX6Q_SABRESD) += board-mx6q_sabresd.o mx6q_sabresd_pmic_pfuze100.o obj-$(CONFIG_MACH_MX6Q_SABREAUTO) += board-mx6q_sabreauto.o mx6q_sabreauto_pmic_pfuze100.o diff --git a/arch/arm/mach-mx6/board-mx6dl_sabresd.h b/arch/arm/mach-mx6/board-mx6dl_sabresd.h index b397163da06b..35701a4979d4 100644 --- a/arch/arm/mach-mx6/board-mx6dl_sabresd.h +++ b/arch/arm/mach-mx6/board-mx6dl_sabresd.h @@ -384,4 +384,10 @@ static iomux_v3_cfg_t mx6dl_sabresd_epdc_disable_pads[] = { */ }; +static iomux_v3_cfg_t mx6dl_arm2_elan_pads[] = { + MX6DL_PAD_EIM_A20__GPIO_2_18, + MX6DL_PAD_EIM_DA8__GPIO_3_8, + MX6DL_PAD_EIM_D28__GPIO_3_28, +}; + #endif diff --git a/arch/arm/mach-mx6/board-mx6q_arm2.c b/arch/arm/mach-mx6/board-mx6q_arm2.c index ba8f92fedfdd..c53840bbaf76 100644 --- a/arch/arm/mach-mx6/board-mx6q_arm2.c +++ b/arch/arm/mach-mx6/board-mx6q_arm2.c @@ -171,7 +171,6 @@ extern char *gp_reg_id; extern int epdc_enabled; extern void mx6_cpu_regulator_init(void); static int max17135_regulator_init(struct max17135 *max17135); -extern volatile int num_cpu_idle_lock; enum sd_pad_mode { SD_PAD_MODE_LOW_SPEED, @@ -588,6 +587,7 @@ static struct fsl_mxc_camera_platform_data camera_data = { .analog_regulator = "DA9052_LDO7", .core_regulator = "DA9052_LDO9", .mclk = 24000000, + .mclk_source = 0, .csi = 0, .io_init = mx6_csi0_io_init, }; @@ -649,15 +649,15 @@ static void mx6_mipi_sensor_io_init(void) mxc_iomux_v3_setup_multiple_pads(mipi_sensor_pads, mipi_sensor_pads_cnt); - if (cpu_is_mx6q()) - mxc_iomux_set_gpr_register(1, 19, 1, 0); + /*for mx6dl, mipi virtual channel 1 connect to csi 1*/ if (cpu_is_mx6dl()) - mxc_iomux_set_gpr_register(13, 0, 3, 0); + mxc_iomux_set_gpr_register(13, 3, 3, 1); } static struct fsl_mxc_camera_platform_data ov5640_mipi_data = { .mclk = 24000000, - .csi = 0, + .csi = 1, + .mclk_source = 0, .io_init = mx6_mipi_sensor_io_init, }; @@ -1538,6 +1538,21 @@ static struct mipi_csi2_platform_data mipi_csi2_pdata = { .pixel_clk = "emi_clk", }; +static struct fsl_mxc_capture_platform_data capture_data[] = { + { + .csi = 0, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 0, + }, { + .csi = 1, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 1, + }, +}; + + static void arm2_suspend_enter(void) { /* suspend preparation */ @@ -2013,7 +2028,6 @@ static void __init mx6_arm2_init(void) spdif_pads_cnt = ARRAY_SIZE(mx6dl_arm2_spdif_pads); flexcan_pads_cnt = ARRAY_SIZE(mx6dl_arm2_can_pads); i2c3_pads_cnt = ARRAY_SIZE(mx6dl_arm2_i2c3_pads); - num_cpu_idle_lock = 0xffff0000; } BUG_ON(!common_pads); @@ -2091,10 +2105,13 @@ static void __init mx6_arm2_init(void) imx6q_add_lcdif(&lcdif_data); imx6q_add_ldb(&ldb_data); imx6q_add_v4l2_output(0); - imx6q_add_v4l2_capture(0); + imx6q_add_v4l2_capture(0, &capture_data[0]); + imx6q_add_v4l2_capture(1, &capture_data[1]); imx6q_add_imx_snvs_rtc(); + imx6q_add_imx_caam(); + imx6q_add_imx_i2c(0, &mx6_arm2_i2c0_data); imx6q_add_imx_i2c(1, &mx6_arm2_i2c1_data); i2c_register_board_info(0, mxc_i2c0_board_info, @@ -2218,6 +2235,7 @@ static struct sys_timer mxc_timer = { static void __init mx6_arm2_reserve(void) { +#ifdef CONFIG_MXC_GPU_VIV phys_addr_t phys; if (imx6_gpu_pdata.reserved_mem_size) { @@ -2227,6 +2245,7 @@ static void __init mx6_arm2_reserve(void) memblock_remove(phys, imx6_gpu_pdata.reserved_mem_size); imx6_gpu_pdata.reserved_mem_base = phys; } +#endif if (imx_ion_data.heaps[0].size) { phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K); diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.c b/arch/arm/mach-mx6/board-mx6q_sabreauto.c index ba4ad5b05f63..5d59855a2204 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabreauto.c +++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.c @@ -139,7 +139,14 @@ static int mipi_sensor; static int can0_enable; static int uart3_en; static int tuner_en; -extern volatile int num_cpu_idle_lock; +static int spinor_en; + +static int __init spinor_enable(char *p) +{ + spinor_en = 1; + return 0; +} +early_param("spi-nor", spinor_enable); static int __init uart3_enable(char *p) { @@ -476,7 +483,7 @@ static int max7310_1_setup(struct i2c_client *client, /* 7 GPS_RST_B */ int max7310_gpio_value[] = { - 0, 1, 1, 1, 0, 0, 0, 0, + 0, 1, 1, 1, 0, 0, 1, 0, }; int n; @@ -1273,6 +1280,21 @@ static struct mxc_spdif_platform_data mxc_spdif_data = { .spdif_clk = NULL, /* spdif bus clk */ }; +static struct fsl_mxc_capture_platform_data capture_data[] = { + { + .csi = 0, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 0, + }, { + .csi = 1, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 1, + }, +}; + + /*! * Board specific initialization. */ @@ -1332,13 +1354,14 @@ static void __init mx6_board_init(void) i2c3_pads = mx6dl_i2c3_pads_rev_b; i2c3_pads_cnt = ARRAY_SIZE(mx6dl_i2c3_pads_rev_b); } - num_cpu_idle_lock = 0xffff0000; } BUG_ON(!common_pads); mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt); - BUG_ON(!i2c3_pads); - mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); + if (!spinor_en) { + BUG_ON(!i2c3_pads); + mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt); + } if (can0_enable) { BUG_ON(!can0_pads); @@ -1361,7 +1384,10 @@ static void __init mx6_board_init(void) if (!board_is_mx6_reva()) { /* enable i2c3_sda route path */ gpio_request(SABREAUTO_I2C3_STEER, "i2c3-steer"); - gpio_direction_output(SABREAUTO_I2C3_STEER, 1); + if (spinor_en) + gpio_direction_output(SABREAUTO_I2C3_STEER, 0); + else + gpio_direction_output(SABREAUTO_I2C3_STEER, 1); /* Set GPIO_16 input for IEEE-1588 ts_clk and * RMII reference clk * For MX6 GPR1 bit21 meaning: @@ -1405,7 +1431,8 @@ static void __init mx6_board_init(void) imx6q_add_lcdif(&lcdif_data); imx6q_add_ldb(&ldb_data); imx6q_add_v4l2_output(0); - imx6q_add_v4l2_capture(0); + imx6q_add_v4l2_capture(0, &capture_data[0]); + imx6q_add_v4l2_capture(1, &capture_data[1]); imx6q_add_android_device_buttons(); imx6q_add_imx_snvs_rtc(); @@ -1536,6 +1563,7 @@ static struct sys_timer mxc_timer = { static void __init mx6q_reserve(void) { +#ifdef CONFIG_MXC_GPU_VIV phys_addr_t phys; if (imx6q_gpu_pdata.reserved_mem_size) { @@ -1545,6 +1573,7 @@ static void __init mx6q_reserve(void) memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size); imx6q_gpu_pdata.reserved_mem_base = phys; } +#endif if (imx_ion_data.heaps[0].size) { phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K); diff --git a/arch/arm/mach-mx6/board-mx6q_sabrelite.c b/arch/arm/mach-mx6/board-mx6q_sabrelite.c index ce10d6d6a8fb..d692f968a383 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabrelite.c +++ b/arch/arm/mach-mx6/board-mx6q_sabrelite.c @@ -596,6 +596,7 @@ static void mx6q_csi0_io_init(void) static struct fsl_mxc_camera_platform_data camera_data = { .mclk = 24000000, + .mclk_source = 0, .csi = 0, .io_init = mx6q_csi0_io_init, }; @@ -843,6 +844,21 @@ static struct ion_platform_data imx_ion_data = { }, }; +static struct fsl_mxc_capture_platform_data capture_data[] = { + { + .csi = 0, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 0, + }, { + .csi = 1, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 1, + }, +}; + + static void sabrelite_suspend_enter(void) { /* suspend preparation */ @@ -1119,7 +1135,8 @@ static void __init mx6_sabrelite_board_init(void) imx6q_add_lcdif(&lcdif_data); imx6q_add_ldb(&ldb_data); imx6q_add_v4l2_output(0); - imx6q_add_v4l2_capture(0); + imx6q_add_v4l2_capture(0, &capture_data[0]); + imx6q_add_v4l2_capture(1, &capture_data[1]); imx6q_add_mipi_csi2(&mipi_csi2_pdata); imx6q_add_imx_snvs_rtc(); @@ -1221,6 +1238,7 @@ static struct sys_timer mx6_sabrelite_timer = { static void __init mx6q_sabrelite_reserve(void) { +#ifdef CONFIG_MXC_GPU_VIV phys_addr_t phys; int i; @@ -1231,6 +1249,7 @@ static void __init mx6q_sabrelite_reserve(void) memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size); imx6q_gpu_pdata.reserved_mem_base = phys; } +#endif if (imx_ion_data.heaps[0].size) { phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K); diff --git a/arch/arm/mach-mx6/board-mx6q_sabresd.c b/arch/arm/mach-mx6/board-mx6q_sabresd.c index 7548d8981514..bc0ee4058f04 100644 --- a/arch/arm/mach-mx6/board-mx6q_sabresd.c +++ b/arch/arm/mach-mx6/board-mx6q_sabresd.c @@ -47,7 +47,7 @@ #include <linux/gpio.h> #include <linux/ion.h> #include <linux/etherdevice.h> -#include <linux/power/max8903_charger.h> +#include <linux/power/sabresd_battery.h> #include <linux/regulator/anatop-regulator.h> #include <linux/regulator/consumer.h> #include <linux/regulator/machine.h> @@ -194,15 +194,20 @@ #define SABRESD_EPDC_VCOM IMX_GPIO_NR(3, 17) #define SABRESD_CHARGE_NOW IMX_GPIO_NR(1, 2) #define SABRESD_CHARGE_DONE IMX_GPIO_NR(1, 1) +#define SABRESD_ELAN_CE IMX_GPIO_NR(2, 18) +#define SABRESD_ELAN_RST IMX_GPIO_NR(3, 8) +#define SABRESD_ELAN_INT IMX_GPIO_NR(3, 28) static struct clk *sata_clk; +static struct clk *clko; static int mma8451_position = 1; static int mag3110_position = 2; -static int disable_ldb; +static int max11801_mode = 1; +static int enable_lcd_ldb; + extern char *gp_reg_id; extern int epdc_enabled; -extern volatile int num_cpu_idle_lock; static int max17135_regulator_init(struct max17135 *max17135); @@ -386,26 +391,20 @@ static struct platform_device mx6_sabresd_audio_wm8962_device = { .name = "imx-wm8962", }; -static struct wm8962_pdata wm8962_config_data = { - .gpio_init = { - [2] = WM8962_GPIO_FN_DMICCLK, - [4] = 0x8000 | WM8962_GPIO_FN_DMICDAT, - }, -}; +static struct mxc_audio_platform_data wm8962_data; -static struct mxc_audio_platform_data wm8962_data = { - .ssi_num = 1, - .src_port = 2, - .ext_port = 3, - .hp_gpio = SABRESD_HEADPHONE_DET, - .hp_active_low = 1, - .mic_gpio = SABRESD_MICROPHONE_DET, - .mic_active_low = 1, -}; +static int wm8962_clk_enable(int enable) +{ + if (enable) + clk_enable(clko); + else + clk_disable(clko); + + return 0; +} static int mxc_wm8962_init(void) { - struct clk *clko; int rate; clko = clk_get(NULL, "clko_clk"); @@ -415,13 +414,32 @@ static int mxc_wm8962_init(void) } /* both audio codec and comera use CLKO clk*/ rate = clk_round_rate(clko, 22000000); + clk_set_rate(clko, rate); wm8962_data.sysclk = rate; - clk_set_rate(clko, rate); return 0; } +static struct wm8962_pdata wm8962_config_data = { + .gpio_init = { + [2] = WM8962_GPIO_FN_DMICCLK, + [4] = 0x8000 | WM8962_GPIO_FN_DMICDAT, + }, +}; + +static struct mxc_audio_platform_data wm8962_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_gpio = SABRESD_HEADPHONE_DET, + .hp_active_low = 1, + .mic_gpio = SABRESD_MICROPHONE_DET, + .mic_active_low = 1, + .init = mxc_wm8962_init, + .clock_enable = wm8962_clk_enable, +}; + static struct regulator_consumer_supply sabresd_vwm8962_consumers[] = { REGULATOR_SUPPLY("SPKVDD1", "0-001a"), REGULATOR_SUPPLY("SPKVDD2", "0-001a"), @@ -507,6 +525,7 @@ static void mx6q_csi0_io_init(void) static struct fsl_mxc_camera_platform_data camera_data = { .mclk = 22000000, + .mclk_source = 0, .csi = 0, .io_init = mx6q_csi0_io_init, .pwdn = mx6q_csi0_cam_powerdown, @@ -539,16 +558,15 @@ static void mx6q_mipi_sensor_io_init(void) msleep(1); gpio_set_value(SABRESD_MIPICSI_PWN, 0); - if (cpu_is_mx6q()) - mxc_iomux_set_gpr_register(1, 19, 1, 0); - if (cpu_is_mx6dl()) { - mxc_iomux_set_gpr_register(13, 0, 3, 0); - } + /*for mx6dl, mipi virtual channel 1 connect to csi 1*/ + if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 3, 3, 1); } static struct fsl_mxc_camera_platform_data mipi_csi2_data = { .mclk = 24000000, - .csi = 0, + .mclk_source = 0, + .csi = 1, .io_init = mx6q_mipi_sensor_io_init, .pwdn = mx6q_mipi_powerdown, }; @@ -767,6 +785,11 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { I2C_BOARD_INFO("egalax_ts", 0x4), .irq = gpio_to_irq(SABRESD_CAP_TCH_INT0), }, + { + I2C_BOARD_INFO("max11801", 0x48), + .platform_data = (void *)&max11801_mode, + .irq = gpio_to_irq(SABRESD_TS_INT), + }, }; static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { @@ -787,6 +810,9 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { I2C_BOARD_INFO("isl29023", 0x44), .irq = gpio_to_irq(SABRESD_ALS_INT), .platform_data = &ls_data, + }, { + I2C_BOARD_INFO("elan-touch", 0x10), + .irq = gpio_to_irq(SABRESD_ELAN_INT), }, { I2C_BOARD_INFO("mxc_ldb_i2c", 0x50), @@ -1301,6 +1327,21 @@ static struct ion_platform_data imx_ion_data = { }, }; +static struct fsl_mxc_capture_platform_data capture_data[] = { + { + .csi = 0, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 0, + }, { + .csi = 1, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 1, + }, +}; + + static void sabresd_suspend_enter(void) { /* suspend preparation */ @@ -1366,32 +1407,30 @@ static int __init imx6q_init_audio(void) return 0; } -static void pcie_3v3_power(bool on) +#ifndef CONFIG_IMX_PCIE +static void pcie_3v3_power(void) { - /* Enable/disable PCIE_3V3 */ + /* disable PCIE_3V3 first */ gpio_request(SABRESD_PCIE_PWR_EN, "pcie_3v3_en"); - gpio_direction_output(SABRESD_PCIE_PWR_EN, 1); - - if (on) - gpio_set_value(SABRESD_PCIE_PWR_EN, 1); - else - gpio_set_value(SABRESD_PCIE_PWR_EN, 0); - + gpio_direction_output(SABRESD_PCIE_PWR_EN, 0); + mdelay(10); + /* enable PCIE_3V3 again */ + gpio_set_value(SABRESD_PCIE_PWR_EN, 1); + gpio_free(SABRESD_PCIE_PWR_EN); } -static void pcie_3v3_reset() +static void pcie_3v3_reset(void) { /* reset miniPCIe */ gpio_request(SABRESD_PCIE_RST_B_REVB, "pcie_reset_rebB"); - gpio_direction_output(SABRESD_PCIE_RST_B_REVB, 1); - - gpio_set_value(SABRESD_PCIE_RST_B_REVB, 0); + gpio_direction_output(SABRESD_PCIE_RST_B_REVB, 0); /* The PCI Express Mini CEM specification states that PREST# is deasserted minimum 1ms after 3.3vVaux has been applied and stable*/ - msleep(1); + mdelay(1); gpio_set_value(SABRESD_PCIE_RST_B_REVB, 1); + gpio_free(SABRESD_PCIE_RST_B_REVB); } - +#endif static void gps_power_on(bool on) { @@ -1407,6 +1446,7 @@ static void gps_power_on(bool on) gpio_free(SABRESD_GPS_EN); } + #if defined(CONFIG_LEDS_TRIGGER) || defined(CONFIG_LEDS_GPIO) #define GPIO_LED(gpio_led, name_led, act_low, state_suspend, trigger) \ @@ -1497,7 +1537,11 @@ static struct platform_pwm_backlight_data mx6_sabresd_pwm_backlight_data = { }; static struct mxc_dvfs_platform_data sabresd_dvfscore_data = { + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + .reg_id = "VDDCORE", + #else .reg_id = "cpu_vddgp", + #endif .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, @@ -1547,7 +1591,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, static struct mipi_csi2_platform_data mipi_csi2_pdata = { .ipu_id = 0, - .csi_id = 0, + .csi_id = 1, .v_channel = 0, .lanes = 2, .dphy_clk = "mipi_pllref_clk", @@ -1572,14 +1616,13 @@ static const struct imx_pcie_platform_data mx6_sabresd_pcie_data __initconst = { .pcie_dis = SABRESD_PCIE_DIS_B, }; -static int __init early_disable_ldb(char *p) +static int __init early_enable_lcd_ldb(char *p) { - /*mipi dsi need pll3_pfd_540M as 540MHz, ldb will change to 454Mhz*/ - disable_ldb = 1; + enable_lcd_ldb = 1; return 0; } +early_param("enable_lcd_ldb", early_enable_lcd_ldb); -early_param("disable_ldb", early_disable_ldb); /*! * Board specific initialization. */ @@ -1597,7 +1640,6 @@ static void __init mx6_sabresd_board_init(void) else if (cpu_is_mx6dl()) { mxc_iomux_v3_setup_multiple_pads(mx6dl_sabresd_pads, ARRAY_SIZE(mx6dl_sabresd_pads)); - num_cpu_idle_lock = 0xffff0000; } #ifdef CONFIG_FEC_1588 @@ -1609,15 +1651,6 @@ static void __init mx6_sabresd_board_init(void) mxc_iomux_set_gpr_register(1, 21, 1, 1); #endif -#ifdef CONFIG_FEC_1588 - /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock - * For MX6 GPR1 bit21 meaning: - * Bit21: 0 - GPIO_16 pad output - * 1 - GPIO_16 pad input - */ - mxc_iomux_set_gpr_register(1, 21, 1, 1); -#endif - gp_reg_id = sabresd_dvfscore_data.reg_id; mx6q_sabresd_init_uart(); @@ -1646,10 +1679,10 @@ static void __init mx6_sabresd_board_init(void) imx6q_add_vdoa(); imx6q_add_mipi_dsi(&mipi_dsi_pdata); imx6q_add_lcdif(&lcdif_data); - if (!disable_ldb) - imx6q_add_ldb(&ldb_data); + imx6q_add_ldb(&ldb_data); imx6q_add_v4l2_output(0); - imx6q_add_v4l2_capture(0); + imx6q_add_v4l2_capture(0, &capture_data[0]); + imx6q_add_v4l2_capture(1, &capture_data[1]); imx6q_add_mipi_csi2(&mipi_csi2_pdata); imx6q_add_imx_snvs_rtc(); @@ -1679,7 +1712,6 @@ static void __init mx6_sabresd_board_init(void) gpio_direction_input(SABRESD_PFUZE_INT); mx6q_sabresd_init_pfuze100(SABRESD_PFUZE_INT); } - /* SPI */ imx6q_add_ecspi(0, &mx6q_sabresd_spi_data); spi_device_init(); @@ -1719,7 +1751,9 @@ static void __init mx6_sabresd_board_init(void) imx6q_add_dma(); imx6q_add_dvfs_core(&sabresd_dvfscore_data); + #ifndef CONFIG_MX6_INTER_LDO_BYPASS mx6_cpu_regulator_init(); + #endif imx6q_add_ion(0, &imx_ion_data, sizeof(imx_ion_data) + sizeof(struct ion_platform_heap)); @@ -1774,20 +1808,39 @@ static void __init mx6_sabresd_board_init(void) gpio_direction_output(SABRESD_AUX_5V_EN, 1); gpio_set_value(SABRESD_AUX_5V_EN, 1); - pcie_3v3_power(false); - msleep(10); - pcie_3v3_power(true); - msleep(10); +#ifndef CONFIG_IMX_PCIE + /* enable pcie 3v3 power without pcie driver */ + pcie_3v3_power(); + mdelay(10); pcie_3v3_reset(); +#endif gps_power_on(true); - /* Register charger chips */ platform_device_register(&sabresd_max8903_charger_1); pm_power_off = mx6_snvs_poweroff; imx6q_add_busfreq(); imx6q_add_pcie(&mx6_sabresd_pcie_data); + if (cpu_is_mx6dl()) { + mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_elan_pads, + ARRAY_SIZE(mx6dl_arm2_elan_pads)); + + /* ELAN Touchscreen */ + gpio_request(SABRESD_ELAN_INT, "elan-interrupt"); + gpio_direction_input(SABRESD_ELAN_INT); + + gpio_request(SABRESD_ELAN_CE, "elan-cs"); + gpio_direction_output(SABRESD_ELAN_CE, 1); + gpio_direction_output(SABRESD_ELAN_CE, 0); + + gpio_request(SABRESD_ELAN_RST, "elan-rst"); + gpio_direction_output(SABRESD_ELAN_RST, 1); + gpio_direction_output(SABRESD_ELAN_RST, 0); + mdelay(1); + gpio_direction_output(SABRESD_ELAN_RST, 1); + gpio_direction_output(SABRESD_ELAN_CE, 1); + } } extern void __iomem *twd_base; @@ -1810,6 +1863,7 @@ static struct sys_timer mx6_sabresd_timer = { static void __init mx6q_sabresd_reserve(void) { +#ifdef CONFIG_MXC_GPU_VIV phys_addr_t phys; int i; @@ -1820,6 +1874,7 @@ static void __init mx6q_sabresd_reserve(void) memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size); imx6q_gpu_pdata.reserved_mem_base = phys; } +#endif if (imx_ion_data.heaps[0].size) { phys = memblock_alloc(imx_ion_data.heaps[0].size, SZ_4K); diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c new file mode 100755 index 000000000000..b57de6a21ee4 --- /dev/null +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c @@ -0,0 +1,1068 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/nodemask.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/smsc911x.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/i2c.h> +#include <linux/i2c/pca953x.h> +#include <linux/ata.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/pmic_external.h> +#include <linux/pmic_status.h> +#include <linux/mxcfb.h> +#include <linux/pwm_backlight.h> +#include <linux/fec.h> +#include <linux/memblock.h> +#include <linux/gpio.h> +#include <linux/etherdevice.h> +#include <linux/regulator/anatop-regulator.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> +#include <linux/mfd/max17135.h> +#include <sound/wm8962.h> +#include <sound/pcm.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include <mach/memory.h> +#include <mach/iomux-mx6sl.h> +#include <mach/imx-uart.h> +#include <mach/viv_gpu.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "usb.h" +#include "devices-imx6q.h" +#include "crm_regs.h" +#include "cpu_op-mx6.h" +#include "board-mx6sl_arm2.h" + +#define MX6_ARM2_USBOTG1_PWR IMX_GPIO_NR(4, 0) /* KEY_COL4 */ +#define MX6_ARM2_USBOTG2_PWR IMX_GPIO_NR(4, 2) /* KEY_COL5 */ +#define MX6_ARM2_LCD_PWR_EN IMX_GPIO_NR(4, 3) /* KEY_ROW5 */ +#define MX6_ARM2_SD1_WP IMX_GPIO_NR(4, 6) /* KEY_COL7 */ +#define MX6_ARM2_SD1_CD IMX_GPIO_NR(4, 7) /* KEY_ROW7 */ +#define MX6_ARM2_ECSPI1_CS0 IMX_GPIO_NR(4, 11) /* ECSPI1_SS0 */ +#define MX6_ARM2_HEADPHONE_DET IMX_GPIO_NR(4, 19) /* FEC_RX_ER */ +#define MX6_ARM2_SD2_WP IMX_GPIO_NR(4, 29) /* SD2_DAT6 */ +#define MX6_ARM2_SD2_CD IMX_GPIO_NR(5, 0) /* SD2_DAT7 */ +#define MX6_ARM2_SD3_CD IMX_GPIO_NR(3, 22) /* REF_CLK_32K */ +#define MX6_ARM2_FEC_PWR_EN IMX_GPIO_NR(4, 21) /* FEC_TX_CLK */ + +/* EPDC GPIO pins */ +#define MX6SL_ARM2_EPDC_SDDO_0 IMX_GPIO_NR(1, 7) +#define MX6SL_ARM2_EPDC_SDDO_1 IMX_GPIO_NR(1, 8) +#define MX6SL_ARM2_EPDC_SDDO_2 IMX_GPIO_NR(1, 9) +#define MX6SL_ARM2_EPDC_SDDO_3 IMX_GPIO_NR(1, 10) +#define MX6SL_ARM2_EPDC_SDDO_4 IMX_GPIO_NR(1, 11) +#define MX6SL_ARM2_EPDC_SDDO_5 IMX_GPIO_NR(1, 12) +#define MX6SL_ARM2_EPDC_SDDO_6 IMX_GPIO_NR(1, 13) +#define MX6SL_ARM2_EPDC_SDDO_7 IMX_GPIO_NR(1, 14) +#define MX6SL_ARM2_EPDC_SDDO_8 IMX_GPIO_NR(1, 15) +#define MX6SL_ARM2_EPDC_SDDO_9 IMX_GPIO_NR(1, 16) +#define MX6SL_ARM2_EPDC_SDDO_10 IMX_GPIO_NR(1, 17) +#define MX6SL_ARM2_EPDC_SDDO_11 IMX_GPIO_NR(1, 18) +#define MX6SL_ARM2_EPDC_SDDO_12 IMX_GPIO_NR(1, 19) +#define MX6SL_ARM2_EPDC_SDDO_13 IMX_GPIO_NR(1, 20) +#define MX6SL_ARM2_EPDC_SDDO_14 IMX_GPIO_NR(1, 21) +#define MX6SL_ARM2_EPDC_SDDO_15 IMX_GPIO_NR(1, 22) +#define MX6SL_ARM2_EPDC_GDCLK IMX_GPIO_NR(1, 31) +#define MX6SL_ARM2_EPDC_GDSP IMX_GPIO_NR(2, 2) +#define MX6SL_ARM2_EPDC_GDOE IMX_GPIO_NR(2, 0) +#define MX6SL_ARM2_EPDC_GDRL IMX_GPIO_NR(2, 1) +#define MX6SL_ARM2_EPDC_SDCLK IMX_GPIO_NR(1, 23) +#define MX6SL_ARM2_EPDC_SDOE IMX_GPIO_NR(1, 25) +#define MX6SL_ARM2_EPDC_SDLE IMX_GPIO_NR(1, 24) +#define MX6SL_ARM2_EPDC_SDSHR IMX_GPIO_NR(1, 26) +#define MX6SL_ARM2_EPDC_PWRCOM IMX_GPIO_NR(2, 11) +#define MX6SL_ARM2_EPDC_PWRSTAT IMX_GPIO_NR(2, 13) +#define MX6SL_ARM2_EPDC_PWRCTRL0 IMX_GPIO_NR(2, 7) +#define MX6SL_ARM2_EPDC_PWRCTRL1 IMX_GPIO_NR(2, 8) +#define MX6SL_ARM2_EPDC_PWRCTRL2 IMX_GPIO_NR(2, 9) +#define MX6SL_ARM2_EPDC_PWRCTRL3 IMX_GPIO_NR(2, 10) +#define MX6SL_ARM2_EPDC_BDR0 IMX_GPIO_NR(2, 5) +#define MX6SL_ARM2_EPDC_BDR1 IMX_GPIO_NR(2, 6) +#define MX6SL_ARM2_EPDC_SDCE0 IMX_GPIO_NR(1, 27) +#define MX6SL_ARM2_EPDC_SDCE1 IMX_GPIO_NR(1, 28) +#define MX6SL_ARM2_EPDC_SDCE2 IMX_GPIO_NR(1, 29) +#define MX6SL_ARM2_EPDC_SDCE3 IMX_GPIO_NR(1, 30) +#define MX6SL_ARM2_EPDC_PMIC_WAKE IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */ +#define MX6SL_ARM2_EPDC_PMIC_INT IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */ +#define MX6SL_ARM2_EPDC_VCOM IMX_GPIO_NR(2, 3) + +static int max17135_regulator_init(struct max17135 *max17135); +struct clk *extern_audio_root; + +extern int __init mx6sl_arm2_init_pfuze100(u32 int_gpio); +static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = { + .cd_gpio = MX6_ARM2_SD1_CD, + .wp_gpio = MX6_ARM2_SD1_WP, + .support_8bit = 1, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + +static const struct esdhc_platform_data mx6_arm2_sd2_data __initconst = { + .cd_gpio = MX6_ARM2_SD2_CD, + .wp_gpio = MX6_ARM2_SD2_WP, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + +static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = { + .cd_gpio = MX6_ARM2_SD3_CD, + .keep_power_at_suspend = 1, + .delay_line = 0, +}; + +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_consumer_supply display_consumers[] = { + { + /* MAX17135 */ + .supply = "DISPLAY", + }, +}; + +static struct regulator_consumer_supply vcom_consumers[] = { + { + /* MAX17135 */ + .supply = "VCOM", + }, +}; + +static struct regulator_consumer_supply v3p3_consumers[] = { + { + /* MAX17135 */ + .supply = "V3P3", + }, +}; + +static struct regulator_init_data max17135_init_data[] = { + { + .constraints = { + .name = "DISPLAY", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(display_consumers), + .consumer_supplies = display_consumers, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcom_consumers), + .consumer_supplies = vcom_consumers, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, { + .constraints = { + .name = "V3P3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(v3p3_consumers), + .consumer_supplies = v3p3_consumers, + }, +}; + +static struct platform_device max17135_sensor_device = { + .name = "max17135_sensor", + .id = 0, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = MX6SL_ARM2_EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = MX6SL_ARM2_EPDC_VCOM, + .gpio_pmic_wakeup = MX6SL_ARM2_EPDC_PMIC_WAKE, + .gpio_pmic_v3p3 = MX6SL_ARM2_EPDC_PWRCTRL0, + .gpio_pmic_intr = MX6SL_ARM2_EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .init = max17135_regulator_init, +}; + +static int __init max17135_regulator_init(struct max17135 *max17135) +{ + struct max17135_platform_data *pdata = &max17135_pdata; + int i, ret; + + max17135->gvee_pwrup = pdata->gvee_pwrup; + max17135->vneg_pwrup = pdata->vneg_pwrup; + max17135->vpos_pwrup = pdata->vpos_pwrup; + max17135->gvdd_pwrup = pdata->gvdd_pwrup; + max17135->gvdd_pwrdn = pdata->gvdd_pwrdn; + max17135->vpos_pwrdn = pdata->vpos_pwrdn; + max17135->vneg_pwrdn = pdata->vneg_pwrdn; + max17135->gvee_pwrdn = pdata->gvee_pwrdn; + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake"); + gpio_direction_output(max17135->gpio_pmic_wakeup, 0); + + gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom"); + gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0); + + gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3"); + gpio_direction_output(max17135->gpio_pmic_v3p3, 0); + + gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int"); + gpio_direction_input(max17135->gpio_pmic_intr); + + gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat"); + gpio_direction_input(max17135->gpio_pmic_pwrgood); + + max17135->vcom_setup = false; + max17135->init_done = false; + + for (i = 0; i < MAX17135_NUM_REGULATORS; i++) { + ret = max17135_register_regulator(max17135, i, + &pdata->regulator_init[i]); + if (ret != 0) { + printk(KERN_ERR"max17135 regulator init failed: %d\n", + ret); + return ret; + } + } + + /* + * TODO: We cannot enable full constraints for now, since + * it results in the PFUZE regulators being disabled + * at the end of boot, which disables critical regulators. + */ + /*regulator_has_full_constraints();*/ + + return 0; +} + +static int mx6_arm2_spi_cs[] = { + MX6_ARM2_ECSPI1_CS0, +}; + +static const struct spi_imx_master mx6_arm2_spi_data __initconst = { + .chipselect = mx6_arm2_spi_cs, + .num_chipselect = ARRAY_SIZE(mx6_arm2_spi_cs), +}; + +static struct imx_ssi_platform_data mx6_sabresd_ssi_pdata = { + .flags = IMX_SSI_DMA | IMX_SSI_SYN, +}; + +static struct mxc_audio_platform_data wm8962_data; + +static struct platform_device mx6_sabresd_audio_wm8962_device = { + .name = "imx-wm8962", +}; + +static struct wm8962_pdata wm8962_config_data = { + +}; + +static int wm8962_clk_enable(int enable) +{ + if (enable) + clk_enable(extern_audio_root); + else + clk_disable(extern_audio_root); + + return 0; +} + +static int mxc_wm8962_init(void) +{ + struct clk *pll4; + int rate; + + extern_audio_root = clk_get(NULL, "extern_audio_clk"); + if (IS_ERR(extern_audio_root)) { + pr_err("can't get extern_audio_root clock.\n"); + return PTR_ERR(extern_audio_root); + } + + pll4 = clk_get(NULL, "pll4"); + if (IS_ERR(pll4)) { + pr_err("can't get pll4 clock.\n"); + return PTR_ERR(pll4); + } + + clk_set_parent(extern_audio_root, pll4); + + rate = clk_round_rate(extern_audio_root, 26000000); + clk_set_rate(extern_audio_root, rate); + + wm8962_data.sysclk = rate; + + return 0; +} + +static struct mxc_audio_platform_data wm8962_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .hp_gpio = MX6_ARM2_HEADPHONE_DET, + .hp_active_low = 1, + .mic_gpio = -1, + .mic_active_low = 1, + .init = mxc_wm8962_init, + .clock_enable = wm8962_clk_enable, +}; + +static struct regulator_consumer_supply sabresd_vwm8962_consumers[] = { + REGULATOR_SUPPLY("SPKVDD1", "1-001a"), + REGULATOR_SUPPLY("SPKVDD2", "1-001a"), +}; + +static struct regulator_init_data sabresd_vwm8962_init = { + .constraints = { + .name = "SPKVDD", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sabresd_vwm8962_consumers), + .consumer_supplies = sabresd_vwm8962_consumers, +}; + +static struct fixed_voltage_config sabresd_vwm8962_reg_config = { + .supply_name = "SPKVDD", + .microvolts = 4325000, + .gpio = -1, + .enabled_at_boot = 1, + .init_data = &sabresd_vwm8962_init, +}; + +static struct platform_device sabresd_vwm8962_reg_devices = { + .name = "reg-fixed-voltage", + .id = 4, + .dev = { + .platform_data = &sabresd_vwm8962_reg_config, + }, +}; + +static int __init imx6q_init_audio(void) +{ + platform_device_register(&sabresd_vwm8962_reg_devices); + mxc_register_device(&mx6_sabresd_audio_wm8962_device, + &wm8962_data); + imx6q_add_imx_ssi(1, &mx6_sabresd_ssi_pdata); + + return 0; +} + +static struct imxi2c_platform_data mx6_arm2_i2c0_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data mx6_arm2_i2c1_data = { + .bitrate = 100000, +}; + +static struct imxi2c_platform_data mx6_arm2_i2c2_data = { + .bitrate = 400000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + I2C_BOARD_INFO("max17135", 0x48), + .platform_data = &max17135_pdata, + }, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + I2C_BOARD_INFO("wm8962", 0x1a), + .platform_data = &wm8962_config_data, + }, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + }, +}; + +static struct mxc_dvfs_platform_data mx6sl_arm2_dvfscore_data = { + .reg_id = "cpu_vddgp", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 80, +}; + +void __init early_console_setup(unsigned long base, struct clk *clk); + +static inline void mx6_arm2_init_uart(void) +{ + imx6q_add_imx_uart(0, NULL); /* DEBUG UART1 */ + + imx6q_add_sdhci_usdhc_imx(0, &mx6_arm2_sd1_data); + imx6q_add_sdhci_usdhc_imx(1, &mx6_arm2_sd2_data); + imx6q_add_sdhci_usdhc_imx(2, &mx6_arm2_sd3_data); +} + +static struct fec_platform_data fec_data __initdata = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + +static int epdc_get_pins(void) +{ + int ret = 0; + + /* Claim GPIOs for EPDC pins - used during power up/down */ + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_0, "epdc_d0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_1, "epdc_d1"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_2, "epdc_d2"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_3, "epdc_d3"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_4, "epdc_d4"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_5, "epdc_d5"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_6, "epdc_d6"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_7, "epdc_d7"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDCLK, "epdc_gdclk"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDSP, "epdc_gdsp"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDOE, "epdc_gdoe"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDRL, "epdc_gdrl"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCLK, "epdc_sdclk"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDOE, "epdc_sdoe"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDLE, "epdc_sdle"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDSHR, "epdc_sdshr"); + ret |= gpio_request(MX6SL_ARM2_EPDC_BDR0, "epdc_bdr0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE0, "epdc_sdce0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE1, "epdc_sdce1"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE2, "epdc_sdce2"); + + return ret; +} + +static void epdc_put_pins(void) +{ + gpio_free(MX6SL_ARM2_EPDC_SDDO_0); + gpio_free(MX6SL_ARM2_EPDC_SDDO_1); + gpio_free(MX6SL_ARM2_EPDC_SDDO_2); + gpio_free(MX6SL_ARM2_EPDC_SDDO_3); + gpio_free(MX6SL_ARM2_EPDC_SDDO_4); + gpio_free(MX6SL_ARM2_EPDC_SDDO_5); + gpio_free(MX6SL_ARM2_EPDC_SDDO_6); + gpio_free(MX6SL_ARM2_EPDC_SDDO_7); + gpio_free(MX6SL_ARM2_EPDC_GDCLK); + gpio_free(MX6SL_ARM2_EPDC_GDSP); + gpio_free(MX6SL_ARM2_EPDC_GDOE); + gpio_free(MX6SL_ARM2_EPDC_GDRL); + gpio_free(MX6SL_ARM2_EPDC_SDCLK); + gpio_free(MX6SL_ARM2_EPDC_SDOE); + gpio_free(MX6SL_ARM2_EPDC_SDLE); + gpio_free(MX6SL_ARM2_EPDC_SDSHR); + gpio_free(MX6SL_ARM2_EPDC_BDR0); + gpio_free(MX6SL_ARM2_EPDC_SDCE0); + gpio_free(MX6SL_ARM2_EPDC_SDCE1); + gpio_free(MX6SL_ARM2_EPDC_SDCE2); +} + +static void epdc_enable_pins(void) +{ + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_enable_pads, \ + ARRAY_SIZE(mx6sl_arm2_epdc_enable_pads)); + + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_2); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_3); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_4); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_5); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_6); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_7); + gpio_direction_input(MX6SL_ARM2_EPDC_GDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_GDSP); + gpio_direction_input(MX6SL_ARM2_EPDC_GDOE); + gpio_direction_input(MX6SL_ARM2_EPDC_GDRL); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_SDOE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDLE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDSHR); + gpio_direction_input(MX6SL_ARM2_EPDC_BDR0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_disable_pads, \ + ARRAY_SIZE(mx6sl_arm2_epdc_disable_pads)); + + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_2, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_3, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_4, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_5, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_6, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_7, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDSP, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDOE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDRL, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDOE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDLE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDSHR, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_BDR0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_v110_mode = { + .name = "E60_V110", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 18604700, + .left_margin = 8, + .right_margin = 178, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e60_v220_mode = { + .name = "E60_V220", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 30000000, + .left_margin = 8, + .right_margin = 164, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + .refresh = 85, + .xres = 800, + .yres = 600, +}; +static struct fb_videomode e060scm_mode = { + .name = "E060SCM", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 26666667, + .left_margin = 8, + .right_margin = 100, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e97_v110_mode = { + .name = "E97_V110", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 12, + .right_margin = 128, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_epdc_fb_mode panel_modes[] = { + { + &e60_v110_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e60_v220_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 465, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 9, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e060scm_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 419, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 5, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e97_v110_mode, + 8, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 632, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 3, /* num_ce */ + } +}; + +static struct imx_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + +static int spdc_get_pins(void) +{ + int ret = 0; + + /* Claim GPIOs for SPDC pins - used during power up/down */ + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_0, "SPDC_D0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_1, "SPDC_D1"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_2, "SPDC_D2"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_3, "SPDC_D3"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_4, "SPDC_D4"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_5, "SPDC_D5"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_6, "SPDC_D6"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_7, "SPDC_D7"); + + ret |= gpio_request(MX6SL_ARM2_EPDC_GDOE, "SIPIX_YOE"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_9, "SIPIX_PWR_RDY"); + + ret |= gpio_request(MX6SL_ARM2_EPDC_GDSP, "SIPIX_YDIO"); + + ret |= gpio_request(MX6SL_ARM2_EPDC_GDCLK, "SIPIX_YCLK"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDSHR, "SIPIX_XDIO"); + + ret |= gpio_request(MX6SL_ARM2_EPDC_SDLE, "SIPIX_LD"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE1, "SIPIX_SOE"); + + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCLK, "SIPIX_XCLK"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_10, "SIPIX_SHD_N"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE0, "SIPIX2_CE"); + + return ret; +} + +static void spdc_put_pins(void) +{ + gpio_free(MX6SL_ARM2_EPDC_SDDO_0); + gpio_free(MX6SL_ARM2_EPDC_SDDO_1); + gpio_free(MX6SL_ARM2_EPDC_SDDO_2); + gpio_free(MX6SL_ARM2_EPDC_SDDO_3); + gpio_free(MX6SL_ARM2_EPDC_SDDO_4); + gpio_free(MX6SL_ARM2_EPDC_SDDO_5); + gpio_free(MX6SL_ARM2_EPDC_SDDO_6); + gpio_free(MX6SL_ARM2_EPDC_SDDO_7); + + gpio_free(MX6SL_ARM2_EPDC_GDOE); + gpio_free(MX6SL_ARM2_EPDC_SDDO_9); + gpio_free(MX6SL_ARM2_EPDC_GDSP); + gpio_free(MX6SL_ARM2_EPDC_GDCLK); + gpio_free(MX6SL_ARM2_EPDC_SDSHR); + gpio_free(MX6SL_ARM2_EPDC_SDLE); + gpio_free(MX6SL_ARM2_EPDC_SDCE1); + gpio_free(MX6SL_ARM2_EPDC_SDCLK); + gpio_free(MX6SL_ARM2_EPDC_SDDO_10); + gpio_free(MX6SL_ARM2_EPDC_SDCE0); +} + +static void spdc_enable_pins(void) +{ + /* Configure MUX settings to enable SPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_spdc_enable_pads, \ + ARRAY_SIZE(mx6sl_arm2_spdc_enable_pads)); + + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_2); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_3); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_4); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_5); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_6); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_7); + gpio_direction_input(MX6SL_ARM2_EPDC_GDOE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_9); + gpio_direction_input(MX6SL_ARM2_EPDC_GDSP); + gpio_direction_input(MX6SL_ARM2_EPDC_GDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_SDSHR); + gpio_direction_input(MX6SL_ARM2_EPDC_SDLE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_10); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE0); +} + +static void spdc_disable_pins(void) +{ + /* Configure MUX settings for SPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_spdc_disable_pads, \ + ARRAY_SIZE(mx6sl_arm2_spdc_disable_pads)); + + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_2, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_3, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_4, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_5, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_6, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_7, 0); + + gpio_direction_output(MX6SL_ARM2_EPDC_GDOE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_9, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDSP, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDSHR, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDLE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_10, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE0, 0); +} + +static struct imx_spdc_panel_init_set spdc_init_set = { + .yoe_pol = false, + .dual_gate = false, + .resolution = 0, + .ud = false, + .rl = false, + .data_filter_n = true, + .power_ready = true, + .rgbw_mode_enable = false, + .hburst_len_en = true, +}; + +static struct fb_videomode erk_1_4_a01 = { + .name = "ERK_1_4_A01", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 40000000, + .vmode = FB_VMODE_NONINTERLACED, +}; + +static struct imx_spdc_fb_mode spdc_panel_modes[] = { + { + &erk_1_4_a01, + &spdc_init_set, + .wave_timing = "pvi" + }, +}; + +static struct imx_spdc_fb_platform_data spdc_data = { + .spdc_mode = spdc_panel_modes, + .num_modes = ARRAY_SIZE(spdc_panel_modes), + .get_pins = spdc_get_pins, + .put_pins = spdc_put_pins, + .enable_pins = spdc_enable_pins, + .disable_pins = spdc_disable_pins, +}; + +#if defined(CONFIG_FB_MXC_SIPIX_PANEL) +static void setup_spdc(void) +{ + /* GPR0[8]: 0:EPDC, 1:SPDC */ + mxc_iomux_set_gpr_register(0, 8, 1, 1); +} +#endif + +static void imx6_arm2_usbotg_vbus(bool on) +{ + if (on) + gpio_set_value(MX6_ARM2_USBOTG1_PWR, 1); + else + gpio_set_value(MX6_ARM2_USBOTG1_PWR, 0); +} + +static void __init mx6_arm2_init_usb(void) +{ + int ret = 0; + + imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR); + + /* disable external charger detect, + * or it will affect signal quality at dp. + */ + + ret = gpio_request(MX6_ARM2_USBOTG1_PWR, "usbotg-pwr"); + if (ret) { + pr_err("failed to get GPIO MX6_ARM2_USBOTG1_PWR:%d\n", ret); + return; + } + gpio_direction_output(MX6_ARM2_USBOTG1_PWR, 0); + + ret = gpio_request(MX6_ARM2_USBOTG2_PWR, "usbh1-pwr"); + if (ret) { + pr_err("failed to get GPIO MX6_ARM2_USBOTG2_PWR:%d\n", ret); + return; + } + gpio_direction_output(MX6_ARM2_USBOTG2_PWR, 1); + + mx6_set_otghost_vbus_func(imx6_arm2_usbotg_vbus); + mx6_usb_dr_init(); + mx6_usb_h1_init(); +#ifdef CONFIG_USB_EHCI_ARC_HSIC + mx6_usb_h2_init(); +#endif +} + +static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 32MHz */ + "SEIKO-WVGA", 60, 800, 480, 29850, 99, 164, 33, 10, 10, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = V4L2_PIX_FMT_RGB24, + .mode_str = "SEIKO-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), + }, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_seiko", +}; +/*! + * Board specific initialization. + */ +static void __init mx6_arm2_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_pads, ARRAY_SIZE(mx6sl_arm2_pads)); + + gp_reg_id = "cpu_vddgp"; + mx6_cpu_regulator_init(); + + imx6q_add_imx_snvs_rtc(); + + imx6q_add_imx_i2c(0, &mx6_arm2_i2c0_data); + imx6q_add_imx_i2c(1, &mx6_arm2_i2c1_data); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + imx6q_add_imx_i2c(2, &mx6_arm2_i2c2_data); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + mx6sl_arm2_init_pfuze100(0); + + mx6_arm2_init_uart(); + /* get enet tx reference clk from FEC_REF_CLK pad. + * GPR1[14] = 0, GPR1[18:17] = 00 + */ + mxc_iomux_set_gpr_register(1, 14, 1, 0); + mxc_iomux_set_gpr_register(1, 17, 2, 0); + + /* power on FEC phy and reset phy */ + gpio_request(MX6_ARM2_FEC_PWR_EN, "fec-pwr"); + gpio_direction_output(MX6_ARM2_FEC_PWR_EN, 1); + /* wait RC ms for hw reset */ + udelay(500); + + imx6_init_fec(fec_data); + + mx6_arm2_init_usb(); + + imx6q_add_mxc_pwm(0); + imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data); + imx6dl_add_imx_elcdif(&fb_data[0]); + + gpio_request(MX6_ARM2_LCD_PWR_EN, "elcdif-power-on"); + gpio_direction_output(MX6_ARM2_LCD_PWR_EN, 1); + mxc_register_device(&lcd_wvga_device, NULL); + + imx6dl_add_imx_pxp(); + imx6dl_add_imx_pxp_client(); + mxc_register_device(&max17135_sensor_device, NULL); + imx6dl_add_imx_epdc(&epdc_data); +#if defined(CONFIG_FB_MXC_SIPIX_PANEL) + setup_spdc(); +#endif + imx6sl_add_imx_spdc(&spdc_data); + imx6q_add_dvfs_core(&mx6sl_arm2_dvfscore_data); + + imx6q_init_audio(); + + imx6q_add_viim(); + imx6q_add_imx2_wdt(0, NULL); +} + +extern void __iomem *twd_base; +static void __init mx6_timer_init(void) +{ + struct clk *uart_clk; +#ifdef CONFIG_LOCAL_TIMERS + twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256); + BUG_ON(!twd_base); +#endif + mx6sl_clocks_init(32768, 24000000, 0, 0); + + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(UART1_BASE_ADDR, uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx6_timer_init, +}; + +static void __init mx6_arm2_reserve(void) +{ + +} + +MACHINE_START(MX6SL_ARM2, "Freescale i.MX 6SoloLite Armadillo2 Board") + .boot_params = MX6SL_PHYS_OFFSET + 0x100, + .map_io = mx6_map_io, + .init_irq = mx6_init_irq, + .init_machine = mx6_arm2_init, + .timer = &mxc_timer, + .reserve = mx6_arm2_reserve, +MACHINE_END diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h new file mode 100755 index 000000000000..940c46d0e984 --- /dev/null +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h @@ -0,0 +1,305 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef _BOARD_MX6SL_ARM2_H +#define _BOARD_MX6SL_ARM2_H +#include <mach/iomux-mx6sl.h> + +static iomux_v3_cfg_t mx6sl_arm2_pads[] = { + + /* AUDMUX */ + MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC, + MX6SL_PAD_AUD_TXD__AUDMUX_AUD3_TXD, + MX6SL_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS, + MX6SL_PAD_AUD_RXD__AUDMUX_AUD3_RXD, + MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT, + + /* Audio Codec */ + MX6SL_PAD_FEC_RX_ER__GPIO_4_19, /* HEADPHONE_DET */ + + /* UART1 */ + MX6SL_PAD_UART1_RXD__UART1_RXD, + MX6SL_PAD_UART1_TXD__UART1_TXD, + + /* USBOTG ID pin */ + MX6SL_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID, + + /* USBOTG POWER GPIO */ + MX6SL_PAD_KEY_COL4__GPIO_4_0, + MX6SL_PAD_KEY_COL5__GPIO_4_2, + /* USB OC pin */ + MX6SL_PAD_KEY_ROW4__USB_USBOTG1_OC, + MX6SL_PAD_ECSPI2_SCLK__USB_USBOTG2_OC, + /* USB HSIC pin */ + MX6SL_PAD_HSIC_STROBE__USB_H_STROBE, + MX6SL_PAD_HSIC_DAT__USB_H_DATA, + + /* SD1 */ + MX6SL_PAD_SD1_CLK__USDHC1_CLK, + MX6SL_PAD_SD1_CMD__USDHC1_CMD, + MX6SL_PAD_SD1_DAT0__USDHC1_DAT0, + MX6SL_PAD_SD1_DAT1__USDHC1_DAT1, + MX6SL_PAD_SD1_DAT2__USDHC1_DAT2, + MX6SL_PAD_SD1_DAT3__USDHC1_DAT3, + MX6SL_PAD_SD1_DAT4__USDHC1_DAT4, + MX6SL_PAD_SD1_DAT5__USDHC1_DAT5, + MX6SL_PAD_SD1_DAT6__USDHC1_DAT6, + MX6SL_PAD_SD1_DAT7__USDHC1_DAT7, + /* SD1 CD & WP */ + MX6SL_PAD_KEY_ROW7__GPIO_4_7, + MX6SL_PAD_KEY_COL7__GPIO_4_6, + /* SD2 */ + MX6SL_PAD_SD2_CLK__USDHC2_CLK, + MX6SL_PAD_SD2_CMD__USDHC2_CMD, + MX6SL_PAD_SD2_DAT0__USDHC2_DAT0, + MX6SL_PAD_SD2_DAT1__USDHC2_DAT1, + MX6SL_PAD_SD2_DAT2__USDHC2_DAT2, + MX6SL_PAD_SD2_DAT3__USDHC2_DAT3, + /* SD2 CD & WP */ + MX6SL_PAD_SD2_DAT7__GPIO_5_0, + MX6SL_PAD_SD2_DAT6__GPIO_4_29, + /* SD3 */ + MX6SL_PAD_SD3_CLK__USDHC3_CLK, + MX6SL_PAD_SD3_CMD__USDHC3_CMD, + MX6SL_PAD_SD3_DAT0__USDHC3_DAT0, + MX6SL_PAD_SD3_DAT1__USDHC3_DAT1, + MX6SL_PAD_SD3_DAT2__USDHC3_DAT2, + MX6SL_PAD_SD3_DAT3__USDHC3_DAT3, + /* SD3 CD */ + MX6SL_PAD_REF_CLK_32K__GPIO_3_22, + + /* FEC */ + MX6SL_PAD_FEC_MDC__FEC_MDC, + MX6SL_PAD_FEC_MDIO__FEC_MDIO, + MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT, /* clock from anatop */ + MX6SL_PAD_FEC_RX_ER__GPIO_4_19, + MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV, + MX6SL_PAD_FEC_RXD0__FEC_RDATA_0, + MX6SL_PAD_FEC_RXD1__FEC_RDATA_1, + MX6SL_PAD_FEC_TX_EN__FEC_TX_EN, + MX6SL_PAD_FEC_TXD0__FEC_TDATA_0, + MX6SL_PAD_FEC_TXD1__FEC_TDATA_1, + MX6SL_PAD_FEC_TX_CLK__GPIO_4_21, /* Phy power enable */ + + /* I2C */ + MX6SL_PAD_I2C1_SCL__I2C1_SCL, + MX6SL_PAD_I2C1_SDA__I2C1_SDA, + MX6SL_PAD_I2C2_SCL__I2C2_SCL, + MX6SL_PAD_I2C2_SDA__I2C2_SDA, + + /* ECSPI1 */ + MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO, + MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI, + MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK, + MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0, + MX6SL_PAD_ECSPI1_SS0__GPIO_4_11, /* SS0 */ + + /* LCD */ + MX6SL_PAD_LCD_CLK__LCDIF_CLK, + MX6SL_PAD_LCD_ENABLE__LCDIF_ENABLE, + MX6SL_PAD_LCD_HSYNC__LCDIF_HSYNC, + MX6SL_PAD_LCD_VSYNC__LCDIF_VSYNC, + MX6SL_PAD_LCD_RESET__LCDIF_RESET, + MX6SL_PAD_LCD_DAT0__LCDIF_DAT_0, + MX6SL_PAD_LCD_DAT1__LCDIF_DAT_1, + MX6SL_PAD_LCD_DAT2__LCDIF_DAT_2, + MX6SL_PAD_LCD_DAT3__LCDIF_DAT_3, + MX6SL_PAD_LCD_DAT4__LCDIF_DAT_4, + MX6SL_PAD_LCD_DAT5__LCDIF_DAT_5, + MX6SL_PAD_LCD_DAT6__LCDIF_DAT_6, + MX6SL_PAD_LCD_DAT7__LCDIF_DAT_7, + MX6SL_PAD_LCD_DAT8__LCDIF_DAT_8, + MX6SL_PAD_LCD_DAT9__LCDIF_DAT_9, + MX6SL_PAD_LCD_DAT10__LCDIF_DAT_10, + MX6SL_PAD_LCD_DAT11__LCDIF_DAT_11, + MX6SL_PAD_LCD_DAT12__LCDIF_DAT_12, + MX6SL_PAD_LCD_DAT13__LCDIF_DAT_13, + MX6SL_PAD_LCD_DAT14__LCDIF_DAT_14, + MX6SL_PAD_LCD_DAT15__LCDIF_DAT_15, + MX6SL_PAD_LCD_DAT16__LCDIF_DAT_16, + MX6SL_PAD_LCD_DAT17__LCDIF_DAT_17, + MX6SL_PAD_LCD_DAT18__LCDIF_DAT_18, + MX6SL_PAD_LCD_DAT19__LCDIF_DAT_19, + MX6SL_PAD_LCD_DAT20__LCDIF_DAT_20, + MX6SL_PAD_LCD_DAT21__LCDIF_DAT_21, + MX6SL_PAD_LCD_DAT22__LCDIF_DAT_22, + MX6SL_PAD_LCD_DAT23__LCDIF_DAT_23, + /* LCD brightness */ + MX6SL_PAD_PWM1__PWM1_PWMO, + /* LCD power on */ + MX6SL_PAD_KEY_ROW5__GPIO_4_3, +}; + +static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = { + /* EPDC */ + MX6SL_PAD_EPDC_D0__EPDC_SDDO_0, + MX6SL_PAD_EPDC_D1__EPDC_SDDO_1, + MX6SL_PAD_EPDC_D2__EPDC_SDDO_2, + MX6SL_PAD_EPDC_D3__EPDC_SDDO_3, + MX6SL_PAD_EPDC_D4__EPDC_SDDO_4, + MX6SL_PAD_EPDC_D5__EPDC_SDDO_5, + MX6SL_PAD_EPDC_D6__EPDC_SDDO_6, + MX6SL_PAD_EPDC_D7__EPDC_SDDO_7, + MX6SL_PAD_EPDC_D8__EPDC_SDDO_8, + MX6SL_PAD_EPDC_D9__EPDC_SDDO_9, + MX6SL_PAD_EPDC_D10__EPDC_SDDO_10, + MX6SL_PAD_EPDC_D11__EPDC_SDDO_11, + MX6SL_PAD_EPDC_D12__EPDC_SDDO_12, + MX6SL_PAD_EPDC_D13__EPDC_SDDO_13, + MX6SL_PAD_EPDC_D14__EPDC_SDDO_14, + MX6SL_PAD_EPDC_D15__EPDC_SDDO_15, + + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP, + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE, + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL, + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE, + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE, + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX6SL_PAD_EPDC_BDR0__EPDC_BDR_0, + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0, + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1, + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2, + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, +}; + +static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = { + /* EPDC */ + MX6SL_PAD_EPDC_D0__GPIO_1_7, + MX6SL_PAD_EPDC_D1__GPIO_1_8, + MX6SL_PAD_EPDC_D2__GPIO_1_9, + MX6SL_PAD_EPDC_D3__GPIO_1_10, + MX6SL_PAD_EPDC_D4__GPIO_1_11, + MX6SL_PAD_EPDC_D5__GPIO_1_12, + MX6SL_PAD_EPDC_D6__GPIO_1_13, + MX6SL_PAD_EPDC_D7__GPIO_1_14, + MX6SL_PAD_EPDC_D8__GPIO_1_15, + MX6SL_PAD_EPDC_D9__GPIO_1_16, + MX6SL_PAD_EPDC_D10__GPIO_1_17, + MX6SL_PAD_EPDC_D11__GPIO_1_18, + MX6SL_PAD_EPDC_D12__GPIO_1_19, + MX6SL_PAD_EPDC_D13__GPIO_1_20, + MX6SL_PAD_EPDC_D14__GPIO_1_21, + MX6SL_PAD_EPDC_D15__GPIO_1_22, + + MX6SL_PAD_EPDC_GDCLK__GPIO_1_31, + MX6SL_PAD_EPDC_GDSP__GPIO_2_2, + MX6SL_PAD_EPDC_GDOE__GPIO_2_0, + MX6SL_PAD_EPDC_GDRL__GPIO_2_1, + MX6SL_PAD_EPDC_SDCLK__GPIO_1_23, + MX6SL_PAD_EPDC_SDOE__GPIO_1_25, + MX6SL_PAD_EPDC_SDLE__GPIO_1_24, + MX6SL_PAD_EPDC_SDSHR__GPIO_1_26, + MX6SL_PAD_EPDC_BDR0__GPIO_2_5, + MX6SL_PAD_EPDC_SDCE0__GPIO_1_27, + MX6SL_PAD_EPDC_SDCE1__GPIO_1_28, + MX6SL_PAD_EPDC_SDCE2__GPIO_1_29, + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, +}; + +static iomux_v3_cfg_t mx6sl_arm2_spdc_enable_pads[] = { + /* SPDC data*/ + MX6SL_PAD_EPDC_D0__TCON_E_DATA_0, + MX6SL_PAD_EPDC_D1__TCON_E_DATA_1, + MX6SL_PAD_EPDC_D2__TCON_E_DATA_2, + MX6SL_PAD_EPDC_D3__TCON_E_DATA_3, + MX6SL_PAD_EPDC_D4__TCON_E_DATA_4, + MX6SL_PAD_EPDC_D5__TCON_E_DATA_5, + MX6SL_PAD_EPDC_D6__TCON_E_DATA_6, + MX6SL_PAD_EPDC_D7__TCON_E_DATA_7, + + MX6SL_PAD_EPDC_GDOE__TCON_YOEL, /* AUO panel SIPIX_YOE */ + + MX6SL_PAD_EPDC_D9__TCON_E_DATA_9, /* AUO panel SIPIX_PWR_RDY*/ + + MX6SL_PAD_EPDC_SDCE2__TCON_YDIOUR, /* AUO panel SIPIX_YDIO */ + MX6SL_PAD_EPDC_SDCE3__TCON_YDIODR, /* AUO panel SIPIX_YDIO */ + MX6SL_PAD_EPDC_GDRL__TCON_YDIOUL, /* AUO panel SIPIX_YDIO */ + MX6SL_PAD_EPDC_GDSP__TCON_YDIODL, /* SIPIX_YDIO/SIPIX2_SPV */ + + MX6SL_PAD_EPDC_GDCLK__TCON_YCKL, /* SIPIX_YCLK/SIPIX2_CKV */ + + MX6SL_PAD_EPDC_SDSHR__TCON_XDIOR, /* AUO panel SIPIX_XDIO */ + MX6SL_PAD_EPDC_SDOE__TCON_XDIOL, /* SIPIX_XDIO/SIPIX2_OE */ + + MX6SL_PAD_EPDC_SDLE__TCON_LD, /* SIPIX_LD/SIPIX2_LE */ + + MX6SL_PAD_EPDC_SDCE1__TCON_YOER, /* AUO panel SIPIX_SOE */ + MX6SL_PAD_EPDC_BDR0__TCON_RL, /* AUO panel SIPIX_SOE */ + MX6SL_PAD_EPDC_BDR1__TCON_UD, /* AUO panel SIPIX_SOE */ + + MX6SL_PAD_EPDC_SDCLK__TCON_CL, /* SIPIX_XCLK/SIPIX2_CL */ + + MX6SL_PAD_EPDC_D10__TCON_E_DATA_10, /* AUO panel SIPIX_SHD_N */ + + MX6SL_PAD_EPDC_SDCE0__TCON_YCKR, /* LG panel SIPIX2_CE */ + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, /* PMICA_CEN */ + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, +}; + +static iomux_v3_cfg_t mx6sl_arm2_spdc_disable_pads[] = { + MX6SL_PAD_EPDC_D0__GPIO_1_7, + MX6SL_PAD_EPDC_D1__GPIO_1_8, + MX6SL_PAD_EPDC_D2__GPIO_1_9, + MX6SL_PAD_EPDC_D3__GPIO_1_10, + MX6SL_PAD_EPDC_D4__GPIO_1_11, + MX6SL_PAD_EPDC_D5__GPIO_1_12, + MX6SL_PAD_EPDC_D6__GPIO_1_13, + MX6SL_PAD_EPDC_D7__GPIO_1_14, + + MX6SL_PAD_EPDC_SDCE1__GPIO_1_28, + MX6SL_PAD_EPDC_GDOE__GPIO_2_0, + MX6SL_PAD_EPDC_D9__GPIO_1_16, + MX6SL_PAD_EPDC_SDCE2__GPIO_1_29, + MX6SL_PAD_EPDC_SDCE3__GPIO_1_30, + MX6SL_PAD_EPDC_GDRL__GPIO_2_1, + MX6SL_PAD_EPDC_GDSP__GPIO_2_2, + MX6SL_PAD_EPDC_GDCLK__GPIO_1_31, + MX6SL_PAD_EPDC_SDSHR__GPIO_1_26, + MX6SL_PAD_EPDC_SDOE__GPIO_1_25, + MX6SL_PAD_EPDC_SDLE__GPIO_1_24, + MX6SL_PAD_EPDC_SDCE1__GPIO_1_28, + MX6SL_PAD_EPDC_BDR0__GPIO_2_5, + MX6SL_PAD_EPDC_BDR1__GPIO_2_6, + MX6SL_PAD_EPDC_SDCLK__GPIO_1_23, + MX6SL_PAD_EPDC_D10__GPIO_1_17, + MX6SL_PAD_EPDC_SDCE0__GPIO_1_27, + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, +}; + +#endif diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index b721bc0479f0..74289931b23b 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -49,6 +49,11 @@ #define LPAPM_CLK 24000000 #define DDR_MED_CLK 400000000 #define DDR3_NORMAL_CLK 528000000 +#define AXI_CLK_RATE 270000000 +#define GPC_PGC_GPU_PGCR_OFFSET 0x260 +#define GPC_CNTR_OFFSET 0x0 + + DEFINE_SPINLOCK(ddr_freq_lock); @@ -74,9 +79,10 @@ unsigned int ddr_normal_rate; int low_freq_bus_used(void); void set_ddr_freq(int ddr_freq); +extern int init_mmdc_settings(void); extern struct cpu_op *(*get_cpu_op)(int *op); extern int update_ddr_freq(int ddr_rate); - +extern void __iomem *gpc_base; struct mutex bus_freq_mutex; @@ -86,6 +92,9 @@ struct timeval end_time; static int cpu_op_nr; static struct cpu_op *cpu_op_tbl; static struct clk *pll2_400; +static struct clk *axi_clk; +static struct clk *periph_clk; +static struct clk *pll3_540; static struct clk *cpu_clk; static unsigned int org_ldo; static struct clk *pll3; @@ -117,6 +126,11 @@ static void reduce_bus_freq_handler(struct work_struct *work) return; } + /* Set the axi_clk to be sourced from the periph_clk. + * So that its frequency can be lowered down to 50MHz + * or 24MHz as the case may be. */ + clk_set_parent(axi_clk, periph_clk); + clk_enable(pll3); if (lp_audio_freq) { @@ -140,14 +154,41 @@ static void reduce_bus_freq_handler(struct work_struct *work) med_bus_freq_mode = 0; if (cpu_is_mx6q()) { + /* Disable the brown out detection since we are going to be + * disabling the LDO. + */ + reg = __raw_readl(ANA_MISC2_BASE_ADDR); + reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN; + __raw_writel(reg, ANA_MISC2_BASE_ADDR); + /* Power gate the PU LDO. */ + /* Power gate the PU domain first. */ + /* enable power down request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power down request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET); + /* Wait for power down to complete. */ + while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1) + ; + + /* Mask the ANATOP brown out interrupt in the GPC. */ + reg = __raw_readl(gpc_base + 0x14); + reg |= 0x80000000; + __raw_writel(reg, gpc_base + 0x14); + org_ldo = reg = __raw_readl(ANADIG_REG_CORE); reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET); __raw_writel(reg, ANADIG_REG_CORE); + + /* Clear the BO interrupt in the ANATOP. */ + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= 0x80000000; + __raw_writel(reg, ANADIG_MISC1_REG); } clk_disable(pll3); mutex_unlock(&bus_freq_mutex); - } /* Set the DDR, AHB to 24MHz. @@ -174,6 +215,8 @@ int set_low_bus_freq(void) */ int set_high_bus_freq(int high_bus_freq) { + unsigned long reg; + if (busfreq_suspended) return 0; @@ -196,10 +239,41 @@ int set_high_bus_freq(int high_bus_freq) } clk_enable(pll3); + if (clk_get_parent(axi_clk) != pll3_540) { + /* We need to set axi_clk to be sourced from PLL3_540MHz. */ + /* Ensure the divider is set to divide by 2 before changing the + * parent. */ + if (low_bus_freq_mode) + clk_set_rate(axi_clk, clk_get_rate(axi_clk) / 2); + clk_set_parent(axi_clk, pll3_540); + clk_set_rate(axi_clk, AXI_CLK_RATE); + } + /* Enable the PU LDO */ - if (cpu_is_mx6q() && low_bus_freq_mode) + if (cpu_is_mx6q() && low_bus_freq_mode) { __raw_writel(org_ldo, ANADIG_REG_CORE); + /* enable power up request */ + reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); + /* power up request */ + reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + __raw_writel(reg | 0x2, gpc_base + GPC_CNTR_OFFSET); + /* Wait for the power up bit to clear */ + while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x2) + ; + + /* Enable the Brown Out detection. */ + reg = __raw_readl(ANA_MISC2_BASE_ADDR); + reg |= ANADIG_ANA_MISC2_REG1_BO_EN; + __raw_writel(reg, ANA_MISC2_BASE_ADDR); + + /* Unmask the ANATOP brown out interrupt in the GPC. */ + reg = __raw_readl(gpc_base + 0x14); + reg &= ~0x80000000; + __raw_writel(reg, gpc_base + 0x14); + } + if (high_bus_freq) { update_ddr_freq(ddr_normal_rate); if (med_bus_freq_mode) @@ -308,7 +382,7 @@ static int __devinit busfreq_probe(struct platform_device *pdev) pll2_400 = clk_get(NULL, "pll2_pfd_400M"); if (IS_ERR(pll2_400)) { - printk(KERN_DEBUG "%s: failed to get axi_clk\n", + printk(KERN_DEBUG "%s: failed to get pll2_pfd_400M\n", __func__); return PTR_ERR(pll2_400); } @@ -321,6 +395,32 @@ static int __devinit busfreq_probe(struct platform_device *pdev) } pll3 = clk_get(NULL, "pll3_main_clk"); + if (IS_ERR(pll3)) { + printk(KERN_DEBUG "%s: failed to get pll3\n", + __func__); + return PTR_ERR(cpu_clk); + } + + axi_clk = clk_get(NULL, "axi_clk"); + if (IS_ERR(axi_clk)) { + printk(KERN_DEBUG "%s: failed to get axi_clk\n", + __func__); + return PTR_ERR(axi_clk); + } + + periph_clk = clk_get(NULL, "periph_clk"); + if (IS_ERR(periph_clk)) { + printk(KERN_DEBUG "%s: failed to get periph_clk\n", + __func__); + return PTR_ERR(periph_clk); + } + + pll3_540 = clk_get(NULL, "pll3_pfd_540M"); + if (IS_ERR(pll3_540)) { + printk(KERN_DEBUG "%s: failed to get periph_clk\n", + __func__); + return PTR_ERR(pll3_540); + } err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); if (err) { @@ -350,6 +450,8 @@ static int __devinit busfreq_probe(struct platform_device *pdev) mutex_init(&bus_freq_mutex); + init_mmdc_settings(); + return 0; } diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 4deeb8c50c14..465bd2313329 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -29,8 +29,8 @@ #include <mach/common.h> #include <mach/clock.h> #include <mach/mxc_dvfs.h> -#include <mach/mxc_hdmi.h> #include <mach/ahci_sata.h> +#include <mach/mxc_hdmi.h> #include "crm_regs.h" #include "cpu_op-mx6.h" #include "regs-anadig.h" @@ -47,9 +47,16 @@ extern struct regulator *cpu_regulator; extern struct cpu_op *(*get_cpu_op)(int *op); extern int lp_high_freq; extern int lp_med_freq; +extern int wait_mode_arm_podf; extern int lp_audio_freq; +extern int cur_arm_podf; +extern bool arm_mem_clked_in_wait; +extern bool enable_wait_mode; void __iomem *apll_base; +static struct clk ipu1_clk; +static struct clk ipu2_clk; +static struct clk axi_clk; static struct clk pll1_sys_main_clk; static struct clk pll2_528_bus_main_clk; static struct clk pll2_pfd_400M; @@ -66,6 +73,7 @@ static struct clk apbh_dma_clk; static struct clk openvg_axi_clk; static struct clk enfc_clk; static struct clk usdhc3_clk; +static struct clk ipg_clk; static struct cpu_op *cpu_op_tbl; static int cpu_op_nr; @@ -513,8 +521,21 @@ static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate) static void _clk_pll1_disable(struct clk *clk) { + void __iomem *pllbase; + u32 reg; + pll1_enabled = false; - _clk_pll_disable(clk); + + /* Set PLL1 in bypass mode only. */ + /* We need to be able to set the ARM-PODF bit + * when the system enters WAIT mode. And setting + * this bit requires PLL1_main to be enabled. + */ + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_BYPASS; + __raw_writel(reg, pllbase); } static int _clk_pll1_enable(struct clk *clk) @@ -780,6 +801,17 @@ static struct clk pll3_pfd_720M = { .round_rate = pfd_round_rate, }; +static int pfd_540M_set_rate(struct clk *clk, unsigned long rate) +{ + if ((clk_get_parent(&ipu1_clk) == clk) || + (clk_get_parent(&ipu2_clk) == clk) || + (clk_get_parent(&axi_clk) == clk)) + WARN(1, "CHANGING rate of 540M PFD when IPU and \ + AXI is sourced from it \n"); + + return pfd_set_rate(clk, rate); +} + static struct clk pll3_pfd_540M = { __INIT_CLK_DEBUG(pll3_pfd_540M) .parent = &pll3_usb_otg_main_clk, @@ -787,7 +819,7 @@ static struct clk pll3_pfd_540M = { .enable_shift = ANADIG_PFD1_FRAC_OFFSET, .enable = _clk_pfd_enable, .disable = _clk_pfd_disable, - .set_rate = pfd_set_rate, + .set_rate = pfd_540M_set_rate, .get_rate = pfd_get_rate, .round_rate = pfd_round_rate, .get_rate = pfd_get_rate, @@ -1171,6 +1203,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) u32 div; unsigned long parent_rate; unsigned long flags; + unsigned long ipg_clk_rate, max_arm_wait_clk; for (i = 0; i < cpu_op_nr; i++) { if (rate == cpu_op_tbl[i].cpu_rate) @@ -1215,6 +1248,32 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) } parent_rate = clk_get_rate(clk->parent); div = parent_rate / rate; + /* Calculate the ARM_PODF to be applied when the system + * enters WAIT state. The max ARM clk is decided by the + * ipg_clk and has to follow the ratio of ARM_CLK:IPG_CLK of 12:5. + * For ex, when IPG is at 66MHz, ARM_CLK cannot be greater + * than 158MHz. + * Pre-calculate the optimal divider now. + */ + ipg_clk_rate = clk_get_rate(&ipg_clk); + max_arm_wait_clk = (12 * ipg_clk_rate) / 5; + wait_mode_arm_podf = parent_rate / max_arm_wait_clk; + if (wait_mode_arm_podf > 7) { + /* IPG_CLK is too low and we cannot get a ARM_CLK + * that will satisfy the 12:5 ratio. + * Use the mem_ipg_stop_mask bit to ensure clocks to ARM + * memories are not gated during WAIT mode. + * This bit is NOT available on MX6DQ TO1.1/TO1.0 and + * MX6DL TO1.0. + * Else disable entry to WAIT mode. + */ + if ((mx6q_revision() > IMX_CHIP_REVISION_1_1) || + (mx6dl_revision() > IMX_CHIP_REVISION_1_0)) + arm_mem_clked_in_wait = true; + else + enable_wait_mode = false; + } + if (div == 0) div = 1; @@ -1225,11 +1284,12 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) spin_unlock_irqrestore(&clk_lock, flags); return -1; } - /* Need PLL1-MAIN to be ON to write to ARM-PODF bit. */ if (!pll1_enabled) pll1_sys_main_clk.enable(&pll1_sys_main_clk); + cur_arm_podf = div; + __raw_writel(div - 1, MXC_CCM_CACRR); while (__raw_readl(MXC_CCM_CDHIPR)) @@ -2061,7 +2121,7 @@ static struct clk vpu_clk[] = { .set_rate = _clk_vpu_axi_set_rate, .get_rate = _clk_vpu_axi_get_rate, .secondary = &vpu_clk[1], - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { .parent = &mmdc_ch0_axi_clk[0], @@ -2151,7 +2211,7 @@ static struct clk ipu1_clk = { .round_rate = _clk_ipu_round_rate, .set_rate = _clk_ipu1_set_rate, .get_rate = _clk_ipu1_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent) @@ -2212,7 +2272,7 @@ static struct clk ipu2_clk = { .round_rate = _clk_ipu_round_rate, .set_rate = _clk_ipu2_set_rate, .get_rate = _clk_ipu2_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static struct clk usdhc_dep_clk = { @@ -2785,7 +2845,7 @@ static struct clk ldb_di0_clk = { .set_rate = _clk_ldb_di0_set_rate, .round_rate = _clk_ldb_di_round_rate, .get_rate = _clk_ldb_di0_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static unsigned long _clk_ldb_di1_get_rate(struct clk *clk) @@ -2856,7 +2916,7 @@ static struct clk ldb_di1_clk = { .set_rate = _clk_ldb_di1_set_rate, .round_rate = _clk_ldb_di_round_rate, .get_rate = _clk_ldb_di1_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; @@ -3049,7 +3109,7 @@ static struct clk ipu1_di_clk[] = { .set_rate = _clk_ipu1_di0_set_rate, .round_rate = _clk_ipu_di_round_rate, .get_rate = _clk_ipu1_di0_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { __INIT_CLK_DEBUG(ipu1_di_clk_1) @@ -3063,7 +3123,7 @@ static struct clk ipu1_di_clk[] = { .set_rate = _clk_ipu1_di1_set_rate, .round_rate = _clk_ipu_di_round_rate, .get_rate = _clk_ipu1_di1_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, }; @@ -3226,7 +3286,7 @@ static struct clk ipu2_di_clk[] = { .set_rate = _clk_ipu2_di0_set_rate, .round_rate = _clk_ipu_di_round_rate, .get_rate = _clk_ipu2_di0_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { __INIT_CLK_DEBUG(ipu2_di_clk_1) @@ -3240,7 +3300,7 @@ static struct clk ipu2_di_clk[] = { .set_rate = _clk_ipu2_di1_set_rate, .round_rate = _clk_ipu_di_round_rate, .get_rate = _clk_ipu2_di1_get_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, }; @@ -4720,10 +4780,34 @@ static struct clk usboh3_clk[] = { }, }; +static int _clk_mlb_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, cbcmr = __raw_readl(MXC_CCM_CBCMR); + + /* + * In Rigel validatioin, the MLB sys_clock isn't using the + * right frequency after boot. + * In arik, the register CBCMR controls gpu2d clock, not mlb clock, + * mlb is sourced from axi clock. + * But In rigel, the axi clock is lower than in mx6q, so mlb need to + * find a new clock root. + * The gpu2d clock is the root of mlb clock in rigel. + * Thus we need to add below code in mx6dl. + * */ + sel = _get_mux(parent, &axi_clk, &pll3_sw_clk, + &pll2_pfd_352M, &pll2_pfd_400M); + + cbcmr &= ~MXC_CCM_CBCMR_MLB_CLK_SEL_MASK; + cbcmr |= sel << MXC_CCM_CBCMR_MLB_CLK_SEL_OFFSET; + __raw_writel(cbcmr, MXC_CCM_CBCMR); + + return 0; +} + static struct clk mlb150_clk = { __INIT_CLK_DEBUG(mlb150_clk) .id = 0, - .parent = &ipg_clk, + .set_parent = _clk_mlb_set_parent, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, .enable = _clk_enable, @@ -5094,7 +5178,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]), _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]), _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]), - _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]), + _REGISTER_CLOCK("enet.0", NULL, enet_clk[0]), _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]), _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk), @@ -5184,8 +5268,8 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, sata_clk[0].disable(&sata_clk[0]); pcie_clk[0].disable(&pcie_clk[0]); - /* Initialize Audio and Video PLLs to valid frequency (650MHz). */ - clk_set_rate(&pll4_audio_main_clk, 650000000); + /* Initialize Audio and Video PLLs to valid frequency. */ + clk_set_rate(&pll4_audio_main_clk, 176000000); clk_set_rate(&pll5_video_main_clk, 650000000); clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk); @@ -5214,12 +5298,23 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */ clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]); - /* set axi_clk parent to pll3_pfd_540M */ - clk_set_parent(&axi_clk, &pll3_pfd_540M); + /* pxp & epdc */ + clk_set_parent(&ipu2_clk, &pll2_pfd_400M); + clk_set_rate(&ipu2_clk, 200000000); + } else if (cpu_is_mx6q()) + /* Donot source IPU from MMDC clock, as it can be scaled. */ + clk_set_parent(&ipu2_clk, &pll3_pfd_540M); + + /* Donot source IPU from MMDC clock, as it can be scaled. */ + clk_set_parent(&ipu1_clk, &pll3_pfd_540M); + + /* set axi_clk parent to pll3_pfd_540M, don't source from + * periph_clk as it can be scaled. + */ + clk_set_parent(&axi_clk, &pll3_pfd_540M); + /* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */ + clk_enable(&axi_clk); - /* on mx6dl, max ipu clock is 274M */ - clk_set_parent(&ipu1_clk, &pll3_pfd_540M); - } if (cpu_is_mx6q()) clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk); @@ -5230,7 +5325,7 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&clko2_clk, &osc_clk); clk_set_rate(&clko2_clk, 2400000); - clk_set_parent(&clko_clk, &ipg_clk); + clk_set_parent(&clko_clk, &pll4_audio_main_clk); /* * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample * rate convertion and this clock frequency can not be too high, set @@ -5279,12 +5374,23 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, /* Lower the ipg_perclk frequency to 6MHz. */ clk_set_rate(&ipg_perclk, 6000000); - /* Set pll2_pfd_352M frequency to 528M for gpu2d core clock */ - clk_set_rate(&pll2_pfd_352M, 528000000); - /* S/PDIF */ clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M); + /* MLB150 SYS Clock */ + /* + * In Rigel validatioin, the MLB sys_clock isn't using the + * right frequency after boot. + * In arik, the register CBCMR controls gpu2d clock, not mlb clock, + * mlb is sourced from axi clock. + * But In rigel, the axi clock is lower than in mx6q, so mlb need to + * find a new clock root. + * The gpu2d clock is the root of mlb clock in rigel. + * Thus we need to add below code in mx6dl. + * */ + if (cpu_is_mx6dl()) + clk_set_parent(&mlb150_clk, &pll3_sw_clk); + if (mx6q_revision() == IMX_CHIP_REVISION_1_0) { gpt_clk[0].parent = &ipg_perclk; gpt_clk[0].get_rate = NULL; diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c new file mode 100755 index 000000000000..1d485c39ed38 --- /dev/null +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -0,0 +1,3821 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/types.h> +#include <linux/time.h> +#include <linux/hrtimer.h> +#include <linux/mm.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/clkdev.h> +#include <linux/regulator/consumer.h> +#include <asm/div64.h> +#include <mach/hardware.h> +#include <mach/common.h> +#include <mach/clock.h> +#include <mach/mxc_dvfs.h> +#include "crm_regs.h" +#include "cpu_op-mx6.h" +#include "regs-anadig.h" + +#ifdef CONFIG_CLK_DEBUG +#define __INIT_CLK_DEBUG(n) .name = #n, +#else +#define __INIT_CLK_DEBUG(n) +#endif + +extern u32 arm_max_freq; +extern int mxc_jtag_enabled; +extern struct regulator *cpu_regulator; +extern struct cpu_op *(*get_cpu_op)(int *op); +extern int lp_high_freq; +extern int lp_med_freq; +extern int wait_mode_arm_podf; +extern int mx6q_revision(void); +extern bool arm_mem_clked_in_wait; +extern int cur_arm_podf; + +static void __iomem *apll_base; +static struct clk pll1_sys_main_clk; +static struct clk pll2_528_bus_main_clk; +static struct clk pll2_pfd2_400M; +static struct clk pll3_usb_otg_main_clk; +static struct clk pll4_audio_main_clk; +static struct clk pll5_video_main_clk; +static struct clk pll6_enet_main_clk; /* Essentially same as PLL8 on MX6Q/DL */ +static struct clk pll7_usb_host_main_clk; +static struct clk usdhc3_clk; +static struct clk ipg_clk; + +static struct cpu_op *cpu_op_tbl; +static int cpu_op_nr; +static bool pll1_enabled; +static bool arm_needs_pll2_400; + +DEFINE_SPINLOCK(mx6sl_clk_lock); +#define SPIN_DELAY 1200000 /* in nanoseconds */ + +#define AUDIO_VIDEO_MIN_CLK_FREQ 650000000 +#define AUDIO_VIDEO_MAX_CLK_FREQ 1300000000 +#define MAX_ARM_CLK_IN_WAIT 158000000 + +/* We need to check the exp status again after timer expiration, + * as there might be interrupt coming between the first time exp + * and the time reading, then the time reading may be several ms + * after the exp checking due to the irq handle, so we need to + * check it to make sure the exp return the right value after + * timer expiration. */ +#define WAIT(exp, timeout) \ +({ \ + struct timespec nstimeofday; \ + struct timespec curtime; \ + int result = 1; \ + getnstimeofday(&nstimeofday); \ + while (!(exp)) { \ + getnstimeofday(&curtime); \ + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ + if (!(exp)) \ + result = 0; \ + break; \ + } \ + } \ + result; \ +}) + +/* External clock values passed-in by the board code */ +static unsigned long external_high_reference, external_low_reference; +static unsigned long oscillator_reference, ckih2_reference; +static unsigned long anaclk_1_reference, anaclk_2_reference; + +static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post) +{ + u32 min_pre, temp_pre, old_err, err; + + /* Some of the podfs are 3 bits while others are 6 bits. + * Handle both cases here. + */ + if (div >= 512 && (max_podf == 64)) { + /* For pre = 3bits and podf = 6 bits, max divider is 512. */ + *pre = 8; + *post = 64; + } else if (div >= 64 && (max_podf == 8)) { + /* For pre = 3bits and podf = 3 bits, max divider is 64. */ + *pre = 8; + *post = 8; + } else if (div >= 8) { + /* Find the minimum pre-divider for a max podf */ + if (max_podf == 64) + min_pre = (div - 1) / (1 << 6) + 1; + else + min_pre = (div - 1) / (1 << 3) + 1; + old_err = 8; + /* Now loop through to find the max pre-divider. */ + for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { + err = div % temp_pre; + if (err == 0) { + *pre = temp_pre; + break; + } + err = temp_pre - err; + if (err < old_err) { + old_err = err; + *pre = temp_pre; + } + } + *post = (div + *pre - 1) / *pre; + } else if (div < 8) { + *pre = div; + *post = 1; + } +} + +static int _clk_enable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + return 0; +} + +static void _clk_disable(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; +} + +static void _clk_disable_inwait(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); +} + +/* + * For the 4-to-1 muxed input clock + */ +static inline u32 _get_mux(struct clk *parent, struct clk *m0, + struct clk *m1, struct clk *m2, struct clk *m3) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else + BUG(); + + return 0; +} + +static inline void __iomem *_get_pll_base(struct clk *pll) +{ + if (pll == &pll1_sys_main_clk) + return PLL1_SYS_BASE_ADDR; + else if (pll == &pll2_528_bus_main_clk) + return PLL2_528_BASE_ADDR; + else if (pll == &pll3_usb_otg_main_clk) + return PLL3_480_USB1_BASE_ADDR; + else if (pll == &pll4_audio_main_clk) + return PLL4_AUDIO_BASE_ADDR; + else if (pll == &pll5_video_main_clk) + return PLL5_VIDEO_BASE_ADDR; + else if (pll == &pll6_enet_main_clk) + /* Essentially same as PLL8 on MX6Q/DL */ + return PLL8_ENET_BASE_ADDR; + else if (pll == &pll7_usb_host_main_clk) + return PLL7_480_USB2_BASE_ADDR; + else + BUG(); + return NULL; +} + + +/* + * For the 6-to-1 muxed input clock + */ +static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1, + struct clk *m2, struct clk *m3, struct clk *m4, + struct clk *m5) +{ + if (parent == m0) + return 0; + else if (parent == m1) + return 1; + else if (parent == m2) + return 2; + else if (parent == m3) + return 3; + else if (parent == m4) + return 4; + else if (parent == m5) + return 5; + else + BUG(); + + return 0; +} +static unsigned long get_high_reference_clock_rate(struct clk *clk) +{ + return external_high_reference; +} + +static unsigned long get_low_reference_clock_rate(struct clk *clk) +{ + return external_low_reference; +} + +static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) +{ + return oscillator_reference; +} + +static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) +{ + return ckih2_reference; +} + +static unsigned long _clk_anaclk_1_get_rate(struct clk *clk) +{ + return anaclk_1_reference; +} + +static int _clk_anaclk_1_set_rate(struct clk *clk, unsigned long rate) +{ + anaclk_1_reference = rate; + return 0; +} + +static unsigned long _clk_anaclk_2_get_rate(struct clk *clk) +{ + return anaclk_2_reference; +} + +static int _clk_anaclk_2_set_rate(struct clk *clk, unsigned long rate) +{ + anaclk_2_reference = rate; + return 0; +} + +/* External high frequency clock */ +static struct clk ckih_clk = { + __INIT_CLK_DEBUG(ckih_clk) + .get_rate = get_high_reference_clock_rate, +}; + +static struct clk ckih2_clk = { + __INIT_CLK_DEBUG(ckih2_clk) + .get_rate = get_ckih2_reference_clock_rate, +}; + +static struct clk osc_clk = { + __INIT_CLK_DEBUG(osc_clk) + .get_rate = get_oscillator_reference_clock_rate, +}; + +/* External low frequency (32kHz) clock */ +static struct clk ckil_clk = { + __INIT_CLK_DEBUG(ckil_clk) + .get_rate = get_low_reference_clock_rate, +}; + +static struct clk anaclk_1 = { + __INIT_CLK_DEBUG(anaclk_1) + .get_rate = _clk_anaclk_1_get_rate, + .set_rate = _clk_anaclk_1_set_rate, +}; + +static struct clk anaclk_2 = { + __INIT_CLK_DEBUG(anaclk_2) + .get_rate = _clk_anaclk_2_get_rate, + .set_rate = _clk_anaclk_2_set_rate, +}; + +static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + + tmp = (u64)clk_get_rate(clk->parent) * 18; + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + tmp = (u64)clk_get_rate(clk->parent) * 18; + do_div(tmp, frac); + return tmp; +} + +static unsigned long pfd_get_rate(struct clk *clk) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) & + ANADIG_PFD_FRAC_MASK; + + do_div(tmp, frac); + + return tmp; +} + +static int pfd_set_rate(struct clk *clk, unsigned long rate) +{ + u32 frac; + u64 tmp; + tmp = (u64)clk_get_rate(clk->parent) * 18; + + /* Round up the divider so that we don't set a rate + * higher than what is requested. */ + tmp += rate/2; + do_div(tmp, rate); + frac = tmp; + frac = frac < 12 ? 12 : frac; + frac = frac > 35 ? 35 : frac; + /* clear clk frac bits */ + __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift, + (int)clk->enable_reg + 8); + /* set clk frac bits */ + __raw_writel(frac << clk->enable_shift, + (int)clk->enable_reg + 4); + + return 0; +} + +static int _clk_pfd_enable(struct clk *clk) +{ + /* clear clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + (int)clk->enable_reg + 8); + + return 0; +} + +static void _clk_pfd_disable(struct clk *clk) +{ + /* set clk gate bit */ + __raw_writel((1 << (clk->enable_shift + 7)), + (int)clk->enable_reg + 4); +} + +static int _clk_pll_enable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg &= ~ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_POWER_DOWN; + + /* The 480MHz PLLs have the opposite definition for power bit. */ + if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk) + reg |= ANADIG_PLL_POWER_DOWN; + + __raw_writel(reg, pllbase); + + /* It will power on pll3 */ + if (clk == &pll3_usb_otg_main_clk) + __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR); + + /* Wait for PLL to lock */ + if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll enable failed\n"); + + /* Enable the PLL output now*/ + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, pllbase); + + return 0; +} + +static void _clk_pll_disable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pllbase = _get_pll_base(clk); + + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + + __raw_writel(reg, pllbase); + + /* + * It will power off PLL3's power, it is the TO1.1 fix + * Please see TKT064178 for detail. + */ + if (clk == &pll3_usb_otg_main_clk) + __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET); +} + +static unsigned long _clk_pll1_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK; + val = (clk_get_rate(clk->parent) * div) / 2; + return val; +} + +static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ) + return -EINVAL; + + div = (rate * 2) / clk_get_rate(clk->parent); + + /* Update div */ + reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, PLL1_SYS_BASE_ADDR); + + /* Wait for PLL1 to lock */ + if (!WAIT(__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_LOCK, + SPIN_DELAY)) + panic("pll1 enable failed\n"); + + return 0; +} + +static int _clk_pll1_main_enable(struct clk *clk) +{ + pll1_enabled = true; + _clk_pll_enable(clk); + return 0; +} + +static void _clk_pll1_main_disable(struct clk *clk) +{ + unsigned int reg; + void __iomem *pllbase; + + pll1_enabled = false; + pllbase = _get_pll_base(clk); + + /* Set the PLL is bypass mode only. + * We need to be able to set the ARM_PODF bit + * in WAIT mode. Setting the ARM_PODF bit + * requires PLL1 to be enabled. + */ + reg = __raw_readl(pllbase); + reg |= ANADIG_PLL_BYPASS; + + __raw_writel(reg, pllbase); +} + +static struct clk pll1_sys_main_clk = { + __INIT_CLK_DEBUG(pll1_sys_main_clk) + .parent = &osc_clk, + .get_rate = _clk_pll1_main_get_rate, + .set_rate = _clk_pll1_main_set_rate, + .enable = _clk_pll1_main_enable, + .disable = _clk_pll1_main_disable, +}; + +static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCSR); + + if (parent == &pll1_sys_main_clk) { + reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + /* Set the step_clk parent to be lp_apm, to save power. */ + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL); + } else { + /* Set STEP_CLK to be the parent*/ + if (parent == &osc_clk) { + /* Set STEP_CLK to be sourced from LPAPM. */ + reg = __raw_readl(MXC_CCM_CCSR); + reg = (reg & ~MXC_CCM_CCSR_STEP_SEL); + __raw_writel(reg, MXC_CCM_CCSR); + } else { + /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */ + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_STEP_SEL; + __raw_writel(reg, MXC_CCM_CCSR); + + } + reg = __raw_readl(MXC_CCM_CCSR); + reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; + } + __raw_writel(reg, MXC_CCM_CCSR); + + return 0; +} + +static unsigned long _clk_pll1_sw_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +static struct clk pll1_sw_clk = { + __INIT_CLK_DEBUG(pll1_sw_clk) + .parent = &pll1_sys_main_clk, + .set_parent = _clk_pll1_sw_set_parent, + .get_rate = _clk_pll1_sw_get_rate, +}; + +static unsigned long _clk_pll2_main_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + + else + val = clk_get_rate(clk->parent) * 20; + + return val; +} + +static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL2_528_BASE_ADDR); + reg &= ~ANADIG_PLL_528_DIV_SELECT; + reg |= div; + __raw_writel(reg, PLL2_528_BASE_ADDR); + + return 0; +} + +static struct clk pll2_528_bus_main_clk = { + __INIT_CLK_DEBUG(pll2_528_bus_main_clk) + .parent = &osc_clk, + .get_rate = _clk_pll2_main_get_rate, + .set_rate = _clk_pll2_main_set_rate, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static void _clk_pll2_pfd2_400M_disable(struct clk *clk) +{ + if (!arm_needs_pll2_400) + _clk_pfd_disable(clk); +} + +static struct clk pll2_pfd2_400M = { + __INIT_CLK_DEBUG(pll2_pfd2_400M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = ANADIG_PFD2_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pll2_pfd2_400M_disable, + .get_rate = pfd_get_rate, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd0_352M = { + __INIT_CLK_DEBUG(pll2_pfd0_352M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = ANADIG_PFD0_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll2_pfd1_594M = { + __INIT_CLK_DEBUG(pll2_pfd1_594M) + .parent = &pll2_528_bus_main_clk, + .enable_reg = (void *)PFD_528_BASE_ADDR, + .enable_shift = ANADIG_PFD1_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static unsigned long _clk_pll2_200M_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static struct clk pll2_200M = { + __INIT_CLK_DEBUG(pll2_200M) + .parent = &pll2_pfd2_400M, + .get_rate = _clk_pll2_200M_get_rate, +}; + +static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL3_480_USB1_BASE_ADDR) + & ANADIG_PLL_480_DIV_SELECT_MASK; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + else + val = clk_get_rate(clk->parent) * 20; + return val; +} + +static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL3_480_USB1_BASE_ADDR); + reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, PLL3_480_USB1_BASE_ADDR); + + return 0; +} + + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_usb_otg_main_clk = { + __INIT_CLK_DEBUG(pll3_usb_otg_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +/* for USB OTG */ +static struct clk usb_phy1_clk = { + __INIT_CLK_DEBUG(usb_phy1_clk) + .parent = &pll3_usb_otg_main_clk, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +/* For HSIC port 1 */ +static struct clk usb_phy3_clk = { + __INIT_CLK_DEBUG(usb_phy3_clk) + .parent = &pll3_usb_otg_main_clk, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +/* For HSIC port 2 */ +static struct clk usb_phy4_clk = { + __INIT_CLK_DEBUG(usb_phy4_clk) + .parent = &pll3_usb_otg_main_clk, + .set_rate = _clk_pll3_usb_otg_set_rate, + .get_rate = _clk_pll3_usb_otg_get_rate, +}; + +static struct clk pll3_pfd2_508M = { + __INIT_CLK_DEBUG(pll3_pfd2_508M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = ANADIG_PFD2_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd3_454M = { + __INIT_CLK_DEBUG(pll3_pfd3_454M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = ANADIG_PFD3_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd0_720M = { + __INIT_CLK_DEBUG(pll3_pfd0_720M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = ANADIG_PFD0_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, +}; + +static struct clk pll3_pfd1_540M = { + __INIT_CLK_DEBUG(pll3_pfd1_540M) + .parent = &pll3_usb_otg_main_clk, + .enable_reg = (void *)PFD_480_BASE_ADDR, + .enable_shift = ANADIG_PFD1_FRAC_OFFSET, + .enable = _clk_pfd_enable, + .disable = _clk_pfd_disable, + .set_rate = pfd_set_rate, + .get_rate = pfd_get_rate, + .round_rate = pfd_round_rate, + .get_rate = pfd_get_rate, +}; + +static unsigned long _clk_pll3_sw_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +/* same as pll3_main_clk. These two clocks should always be the same */ +static struct clk pll3_sw_clk = { + __INIT_CLK_DEBUG(pll3_sw_clk) + .parent = &pll3_usb_otg_main_clk, + .get_rate = _clk_pll3_sw_get_rate, +}; + +static unsigned long _clk_pll3_120M_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 4; +} + +static struct clk pll3_120M = { + __INIT_CLK_DEBUG(pll3_120M) + .parent = &pll3_sw_clk, + .get_rate = _clk_pll3_120M_get_rate, +}; + +static unsigned long _clk_pll3_80M_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 6; +} + +static struct clk pll3_80M = { + __INIT_CLK_DEBUG(pll3_80M) + .parent = &pll3_sw_clk, + .get_rate = _clk_pll3_80M_get_rate, +}; + +static unsigned long _clk_pll3_60M_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 8; +} + +static struct clk pll3_60M = { + __INIT_CLK_DEBUG(pll3_60M) + .parent = &pll3_sw_clk, + .get_rate = _clk_pll3_60M_get_rate, +}; + +static unsigned long _clk_audio_video_get_rate(struct clk *clk) +{ + unsigned int div, mfn, mfd; + unsigned long rate; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + unsigned int test_div_sel, control3, post_div; + + pllbase = _get_pll_base(clk); + + test_div_sel = (__raw_readl(pllbase) + & ANADIG_PLL_AV_TEST_DIV_SEL_MASK) + >> ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET; + /* post_div = 4 - test_div_sel; */ + if (test_div_sel == 0) + post_div = 4; + else if (test_div_sel == 1) + post_div = 2; + else + post_div = 1; + + /* PMU_REG_MISC2 in RM */ + if (clk == &pll5_video_main_clk) { + control3 = (__raw_readl(ANA_MISC2_BASE_ADDR) + & ANADIG_ANA_MISC2_CONTROL3_MASK) + >> ANADIG_ANA_MISC2_CONTROL3_OFFSET; + if (control3 == 1) + post_div *= 2; + else if (control3 == 3) + post_div *= 4; + } + + div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK; + mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET); + mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET); + + rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + rate = rate / post_div; + + return rate; +} + +static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + void __iomem *pllbase; + unsigned long min_clk_rate, pre_div_rate; + u32 test_div_sel = 2; + u32 control3 = 0; + + if (clk == &pll4_audio_main_clk) + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4; + else + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16; + + if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ)) + return -EINVAL; + + pllbase = _get_pll_base(clk); + + pre_div_rate = rate; + while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) { + pre_div_rate *= 2; + /* + * test_div_sel field values: + * 2 -> Divide by 1 + * 1 -> Divide by 2 + * 0 -> Divide by 4 + * + * control3 field values: + * 0 -> Divide by 1 + * 1 -> Divide by 2 + * 3 -> Divide by 4 + */ + if (test_div_sel != 0) + test_div_sel--; + else { + control3++; + if (control3 == 2) + control3++; + } + } + + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + reg = __raw_readl(pllbase) + & ~ANADIG_PLL_SYS_DIV_SELECT_MASK + & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK; + reg |= div | + (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET); + __raw_writel(reg, pllbase); + __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET); + __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET); + + reg = __raw_readl(ANA_MISC2_BASE_ADDR) + & ~ANADIG_ANA_MISC2_CONTROL3_MASK; + reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET; + __raw_writel(reg, ANA_MISC2_BASE_ADDR); + + return 0; +} + +static unsigned long _clk_audio_video_round_rate(struct clk *clk, + unsigned long rate) +{ + unsigned long min_clk_rate; + unsigned int div, post_div = 1; + unsigned int mfn, mfd = 1000000; + s64 temp64; + unsigned int parent_rate = clk_get_rate(clk->parent); + unsigned long pre_div_rate; + u32 test_div_sel = 2; + u32 control3 = 0; + unsigned long final_rate; + + if (clk == &pll4_audio_main_clk) + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4; + else + min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16; + + if (rate < min_clk_rate) + return min_clk_rate; + + if (rate > AUDIO_VIDEO_MAX_CLK_FREQ) + return AUDIO_VIDEO_MAX_CLK_FREQ; + + pre_div_rate = rate; + while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) { + pre_div_rate *= 2; + post_div *= 2; + if (test_div_sel != 0) + test_div_sel--; + else { + control3++; + if (control3 == 2) + control3++; + } + } + + div = pre_div_rate / parent_rate; + temp64 = (u64) (pre_div_rate - (div * parent_rate)); + temp64 *= mfd; + do_div(temp64, parent_rate); + mfn = temp64; + + final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); + final_rate = final_rate / post_div; + + return final_rate; +} + +static int _clk_audio_video_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + void __iomem *pllbase; + + if (clk == &pll4_audio_main_clk) + pllbase = PLL4_AUDIO_BASE_ADDR; + else + pllbase = PLL5_VIDEO_BASE_ADDR; + + reg = __raw_readl(pllbase) & ~ANADIG_PLL_BYPASS_CLK_SRC_MASK; + mux = _get_mux6(parent, &osc_clk, &anaclk_1, &anaclk_2, + NULL, NULL, NULL); + reg |= mux << ANADIG_PLL_BYPASS_CLK_SRC_OFFSET; + __raw_writel(reg, pllbase); + + /* Set anaclk_x as input */ + if (parent == &anaclk_1) { + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= (ANATOP_LVDS_CLK1_IBEN_MASK & + ~ANATOP_LVDS_CLK1_OBEN_MASK); + __raw_writel(reg, ANADIG_MISC1_REG); + } else if (parent == &anaclk_2) { + reg = __raw_readl(ANADIG_MISC1_REG); + reg |= (ANATOP_LVDS_CLK2_IBEN_MASK & + ~ANATOP_LVDS_CLK2_OBEN_MASK); + __raw_writel(reg, ANADIG_MISC1_REG); + } + + return 0; +} + +static struct clk pll4_audio_main_clk = { + __INIT_CLK_DEBUG(pll4_audio_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + +static struct clk pll5_video_main_clk = { + __INIT_CLK_DEBUG(pll5_video_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_audio_video_set_rate, + .get_rate = _clk_audio_video_get_rate, + .round_rate = _clk_audio_video_round_rate, + .set_parent = _clk_audio_video_set_parent, +}; + +static struct clk pll6_enet_main_clk = { + __INIT_CLK_DEBUG(pll6_enet_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, +}; + +static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk) +{ + unsigned int div; + unsigned long val; + + div = __raw_readl(PLL7_480_USB2_BASE_ADDR) + & ANADIG_PLL_480_DIV_SELECT_MASK; + + if (div == 1) + val = clk_get_rate(clk->parent) * 22; + else + val = clk_get_rate(clk->parent) * 20; + return val; +} + +static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div; + + if (rate == 528000000) + div = 1; + else if (rate == 480000000) + div = 0; + else + return -EINVAL; + + reg = __raw_readl(PLL7_480_USB2_BASE_ADDR); + reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK; + reg |= div; + __raw_writel(reg, PLL7_480_USB2_BASE_ADDR); + + return 0; +} + +static struct clk pll7_usb_host_main_clk = { + __INIT_CLK_DEBUG(pll7_usb_host_main_clk) + .parent = &osc_clk, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .set_rate = _clk_pll7_usb_otg_set_rate, + .get_rate = _clk_pll7_usb_otg_get_rate, + +}; + +static unsigned long _clk_arm_get_rate(struct clk *clk) +{ + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) +{ + int i; + u32 div; + u32 parent_rate; + unsigned long ipg_clk_rate, max_arm_wait_clk; + unsigned long flags; + + for (i = 0; i < cpu_op_nr; i++) { + if (rate == cpu_op_tbl[i].cpu_rate) + break; + } + if (i >= cpu_op_nr) + return -EINVAL; + + spin_lock_irqsave(&mx6sl_clk_lock, flags); + + if (rate <= clk_get_rate(&pll2_pfd2_400M)) { + /* Source pll1_sw_clk from step_clk which is sourced from + * PLL2_PFD2_400M. + */ + if (pll1_sw_clk.parent != &pll2_pfd2_400M) { + pll2_pfd2_400M.enable(&pll2_pfd2_400M); + arm_needs_pll2_400 = true; + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd2_400M); + pll1_sw_clk.parent = &pll2_pfd2_400M; + } + } else { + if (pll1_sw_clk.parent != &pll1_sys_main_clk) { + /* pll1_sw_clk was being sourced from pll2_400M. */ + /* Enable PLL1 and set pll1_sw_clk parent as PLL1 */ + if (!pll1_enabled) + pll1_sys_main_clk.enable(&pll1_sys_main_clk); + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk); + pll1_sw_clk.parent = &pll1_sys_main_clk; + arm_needs_pll2_400 = false; + if (pll2_pfd2_400M.usecount == 0) + pll2_pfd2_400M.disable(&pll2_pfd2_400M); + } + if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) { + /* Change the PLL1 rate. */ + if (pll2_pfd2_400M.usecount != 0) + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd2_400M); + else + pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk); + pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate); + pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk); + } + } + parent_rate = clk_get_rate(clk->parent); + div = parent_rate / rate; + /* Calculate the ARM_PODF to be applied when the system + * enters WAIT state. + * The max ARM clk is decided by the ipg_clk and has to + * follow the ratio of ARM_CLK:IPG_CLK of 12:5. + * For ex, when IPG is at 66MHz, ARM_CLK cannot be greater + * than 158MHz. Pre-calculate the optimal divider now. + */ + ipg_clk_rate = clk_get_rate(&ipg_clk); + max_arm_wait_clk = (12 * ipg_clk_rate) / 5; + wait_mode_arm_podf = parent_rate / max_arm_wait_clk; + if (wait_mode_arm_podf > 7) + /* IPG_CLK is too low and we cannot get a ARM_CLK + * that will satisfy the 12:5 ratio. + * Use the mem_ipg_stop_mask bit to ensure clocks + * to ARM memories are not gated during WAIT mode. + * Else disable entry to WAIT mode. + */ + arm_mem_clked_in_wait = true; + else + arm_mem_clked_in_wait = false; + + if (div == 0) + div = 1; + + if ((parent_rate / div) > rate) + div++; + + if (div > 8) { + spin_unlock_irqrestore(&mx6sl_clk_lock, flags); + return -1; + } + + if (!pll1_enabled) + pll1_sys_main_clk.enable(&pll1_sys_main_clk); + + cur_arm_podf = div; + + __raw_writel(div - 1, MXC_CCM_CACRR); + + while (__raw_readl(MXC_CCM_CDHIPR)) + ; + + if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400) + pll1_sys_main_clk.disable(&pll1_sys_main_clk); + + spin_unlock_irqrestore(&mx6sl_clk_lock, flags); + + return 0; +} + +static struct clk cpu_clk = { + __INIT_CLK_DEBUG(cpu_clk) + .parent = &pll1_sw_clk, + .set_rate = _clk_arm_set_rate, + .get_rate = _clk_arm_get_rate, +}; + +static unsigned long _clk_twd_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent) / 2; +} + +static int _clk_ipg_perclk_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR1); + + if (parent == &osc_clk) + reg |= 0x1 << MXC_CCM_CSCMR1_PERCLK_CLK_SEL_OFFSET; + else + reg &= ~(0x1 << MXC_CCM_CSCMR1_PERCLK_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} +static struct clk twd_clk = { + __INIT_CLK_DEBUG(twd_clk) + .parent = &cpu_clk, + .get_rate = _clk_twd_get_rate, +}; + +static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd2_400M, + &pll2_pfd0_352M, &pll2_200M, &pll3_sw_clk, &osc_clk); + + if (mux <= 3) { + /* Set the pre_periph_clk multiplexer */ + reg = __raw_readl(MXC_CCM_CBCMR); + reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + /* Set the periph_clk_sel multiplexer. */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + __raw_writel(reg, MXC_CCM_CBCDR); + } else { + reg = __raw_readl(MXC_CCM_CBCDR); + /* Set the periph_clk2_podf divider to divide by 1. */ + reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK; + __raw_writel(reg, MXC_CCM_CBCDR); + + /* Set the periph_clk2_sel mux. */ + reg = __raw_readl(MXC_CCM_CBCMR); + reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK; + reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCMR); + + while (__raw_readl(MXC_CCM_CDHIPR)) + ; + + reg = __raw_readl(MXC_CCM_CBCDR); + /* Set periph_clk_sel to select periph_clk2. */ + reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; + __raw_writel(reg, MXC_CCM_CBCDR); + } + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY)) + panic("_clk_periph_set_parent failed\n"); + + return 0; +} + +static unsigned long _clk_periph_get_rate(struct clk *clk) +{ + u32 div = 1; + u32 reg; + unsigned long val; + + if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) { + reg = __raw_readl(MXC_CCM_CBCDR) + & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK; + div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1; + } + val = clk_get_rate(clk->parent) / div; + return val; +} + +static struct clk periph_clk = { + __INIT_CLK_DEBUG(periph_clk) + .parent = &pll2_528_bus_main_clk, + .set_parent = _clk_periph_set_parent, + .get_rate = _clk_periph_get_rate, +}; + +static unsigned long _clk_axi_get_rate(struct clk *clk) +{ + u32 div, reg; + unsigned long val; + + reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK; + div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET); + + val = clk_get_rate(clk->parent) / (div + 1); + return val; +} + +static int _clk_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY)) + panic("pll _clk_axi_a_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum + * value for the clock. + * Also prevent a div of 0. + */ + + if (div > 8) + div = 8; + else if (div == 0) + div++; + + return parent_rate / div; +} + +static int _clk_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + int mux; + + mux = _get_mux6(parent, &periph_clk, &pll2_pfd2_400M, + &pll3_pfd1_540M, NULL, NULL, NULL); + + if (mux == 0) { + /* Set the AXI_SEL mux */ + reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL; + __raw_writel(reg, MXC_CCM_CBCDR); + } else { + /* Set the AXI_ALT_SEL mux. */ + reg = __raw_readl(MXC_CCM_CBCDR) + & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK; + reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + /* Set the AXI_SEL mux */ + reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL; + reg |= MXC_CCM_CBCDR_AXI_SEL; + __raw_writel(reg, MXC_CCM_CBCDR); + } + return 0; +} + +static struct clk axi_clk = { + __INIT_CLK_DEBUG(axi_clk) + .parent = &periph_clk, + .set_parent = _clk_axi_set_parent, + .set_rate = _clk_axi_set_rate, + .get_rate = _clk_axi_get_rate, + .round_rate = _clk_axi_round_rate, +}; + +static unsigned long _clk_ahb_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY), + SPIN_DELAY)) + panic("_clk_ahb_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_ahb_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk ahb_clk = { + __INIT_CLK_DEBUG(ahb_clk) + .parent = &periph_clk, + .get_rate = _clk_ahb_get_rate, + .set_rate = _clk_ahb_set_rate, + .round_rate = _clk_ahb_round_rate, +}; + +static unsigned long _clk_ipg_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + + +static struct clk ipg_clk = { + __INIT_CLK_DEBUG(ipg_clk) + .parent = &ahb_clk, + .get_rate = _clk_ipg_get_rate, +}; + +static struct clk tzasc1_clk = { + __INIT_CLK_DEBUG(tzasc1_clk) + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk tzasc2_clk = { + __INIT_CLK_DEBUG(tzasc2_clk) + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk mx6fast1_clk = { + __INIT_CLK_DEBUG(mx6fast1_clk) + .id = 0, + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk mx6per1_clk = { + __INIT_CLK_DEBUG(mx6per1_clk) + .id = 0, + .parent = &ahb_clk, + .secondary = &mx6fast1_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk mx6per2_clk = { + __INIT_CLK_DEBUG(mx6per2_clk) + .id = 0, + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> + MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + + if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) + & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY)) + panic("_clk_mmdc_ch1_axi_set_rate failed\n"); + + return 0; +} + +static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk mmdc_ch1_axi_clk[] = { + { + __INIT_CLK_DEBUG(mmdc_ch1_axi_clk) + .id = 0, + .parent = &pll2_pfd2_400M, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .secondary = &mmdc_ch1_axi_clk[1], + .get_rate = _clk_mmdc_ch1_axi_get_rate, + .set_rate = _clk_mmdc_ch1_axi_set_rate, + .round_rate = _clk_mmdc_ch1_axi_round_rate, + }, + { + .id = 1, + __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk) + .parent = &ipg_clk, + .enable = _clk_enable, + .disable = _clk_disable, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .secondary = &tzasc2_clk, + }, +}; + +static struct clk ocram_clk = { + __INIT_CLK_DEBUG(ocram_clk) + .id = 0, + .parent = &axi_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >> + MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 64)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + + +static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; +} + +static struct clk ipg_perclk = { + __INIT_CLK_DEBUG(ipg_perclk) + .parent = &osc_clk, + .set_parent = _clk_ipg_perclk_set_parent, + .get_rate = _clk_ipg_perclk_get_rate, + .set_rate = _clk_ipg_perclk_set_rate, + .round_rate = _clk_ipg_perclk_round_rate, +}; + +static struct clk spba_clk = { + __INIT_CLK_DEBUG(spba_clk) + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +}; + +static struct clk sdma_clk[] = { + { + __INIT_CLK_DEBUG(sdma_clk) + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &sdma_clk[1], + }, + { + .parent = &mx6per1_clk, +#ifdef CONFIG_SDMA_IRAM + .secondary = &ocram_clk, +#else + .secondary = &mmdc_ch1_axi_clk[0], +#endif + }, +}; + +static unsigned long _clk_gpt_get_rate(struct clk *clk) +{ + unsigned long rate; + + if (mx6q_revision() == IMX_CHIP_REVISION_1_0) + return clk_get_rate(clk->parent); + + rate = mx6_timer_rate(); + if (!rate) + return clk_get_rate(clk->parent); + + return rate; +} + +static struct clk gpt_clk[] = { + { + __INIT_CLK_DEBUG(gpt_clk) + .parent = &osc_clk, + .id = 0, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .get_rate = _clk_gpt_get_rate, + }, +}; + +static unsigned long _clk_iim_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +static struct clk iim_clk = { + __INIT_CLK_DEBUG(iim_clk) + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, + .disable = _clk_disable, + .get_rate = _clk_iim_get_rate, +}; + +static struct clk i2c_clk[] = { + { + __INIT_CLK_DEBUG(i2c_clk_0) + .id = 0, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + __INIT_CLK_DEBUG(i2c_clk_1) + .id = 1, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + __INIT_CLK_DEBUG(i2c_clk_2) + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR2, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCDR3) + & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK; + + mux = _get_mux6(parent, &osc_clk, + &pll2_pfd2_400M, &pll3_120M, &pll3_pfd1_540M, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static unsigned long _clk_ipu1_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR3); + div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >> + MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static unsigned long _clk_ipu_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static struct clk ipu1_clk = { + __INIT_CLK_DEBUG(ipu1_clk) + .parent = &pll2_pfd2_400M, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ipu1_set_parent, + .round_rate = _clk_ipu_round_rate, + .set_rate = _clk_ipu1_set_rate, + .get_rate = _clk_ipu1_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCDR3) + & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, + &pll2_pfd2_400M, &pll3_sw_clk, &pll3_pfd1_540M, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static unsigned long _clk_ipu2_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR3); + div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >> + MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR3); + reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR3); + + return 0; +} + +static struct clk ipu2_clk = { + __INIT_CLK_DEBUG(elcdif_axi_clk) + .parent = &pll2_pfd2_400M, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ipu2_set_parent, + .round_rate = _clk_ipu_round_rate, + .set_rate = _clk_ipu2_set_rate, + .get_rate = _clk_ipu2_get_rate, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk usdhc_dep_clk = { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &mx6per1_clk, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }; + +static unsigned long _clk_usdhc_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL; + + if (parent == &pll2_pfd0_352M) + reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_usdhc1_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static struct clk usdhc1_clk = { + __INIT_CLK_DEBUG(usdhc1_clk) + .id = 0, + .parent = &pll2_pfd2_400M, + .secondary = &usdhc_dep_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_usdhc1_set_parent, + .round_rate = _clk_usdhc_round_rate, + .set_rate = _clk_usdhc1_set_rate, + .get_rate = _clk_usdhc1_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL; + + if (parent == &pll2_pfd0_352M) + reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_usdhc2_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static struct clk usdhc2_clk = { + __INIT_CLK_DEBUG(usdhc2_clk) + .id = 1, + .parent = &pll2_pfd2_400M, + .secondary = &usdhc_dep_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_usdhc2_set_parent, + .round_rate = _clk_usdhc_round_rate, + .set_rate = _clk_usdhc2_set_rate, + .get_rate = _clk_usdhc2_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL; + + if (parent == &pll2_pfd0_352M) + reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_usdhc3_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + + +static struct clk usdhc3_clk = { + __INIT_CLK_DEBUG(usdhc3_clk) + .id = 2, + .parent = &pll2_pfd2_400M, + .secondary = &usdhc_dep_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_usdhc3_set_parent, + .round_rate = _clk_usdhc_round_rate, + .set_rate = _clk_usdhc3_set_rate, + .get_rate = _clk_usdhc3_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL; + + if (parent == &pll2_pfd0_352M) + reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_usdhc4_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >> + MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + + +static struct clk usdhc4_clk = { + __INIT_CLK_DEBUG(usdhc4_clk) + .id = 3, + .parent = &pll2_pfd2_400M, + .secondary = &usdhc_dep_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_usdhc4_set_parent, + .round_rate = _clk_usdhc_round_rate, + .set_rate = _clk_usdhc4_set_rate, + .get_rate = _clk_usdhc4_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long _clk_ssi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(1 << 6, div, &pre, &post); + + return parent_rate / (pre * post); +} + +static unsigned long _clk_ssi1_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) + >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) + >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(1 << 6, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK | + MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static unsigned long _clk_extern_audio_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_extern_audio_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd2_508M, + &pll3_pfd3_454M, &pll3_sw_clk, NULL, NULL); + reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCMR2); + + return 0; +} + +static unsigned long _clk_extern_audio_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + + pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK) + >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) + >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (pred * podf); +} + +static int _clk_extern_audio_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 64) + return -EINVAL; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK| + MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET; + + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static struct clk extern_audio_clk = { + __INIT_CLK_DEBUG(extern_audio_clk) + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_rate = _clk_extern_audio_set_rate, + .get_rate = _clk_extern_audio_get_rate, + .set_parent = _clk_extern_audio_set_parent, + .round_rate = _clk_extern_audio_round_rate, +}; + + +static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll3_pfd2_508M, &pll3_pfd3_454M, + &pll4_audio_main_clk, NULL, NULL, NULL); + reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi1_clk = { + __INIT_CLK_DEBUG(ssi1_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi1_set_parent, + .set_rate = _clk_ssi1_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi1_get_rate, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &ocram_clk, +#else + .secondary = &mmdc_ch1_axi_clk[0], +#endif +}; + +static unsigned long _clk_ssi2_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS2CDR); + + prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK) + >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK) + >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(1 << 6, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + + __raw_writel(reg, MXC_CCM_CS2CDR); + + return 0; +} + + +static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll3_pfd2_508M, &pll3_pfd3_454M, + &pll4_audio_main_clk, NULL, NULL, NULL); + reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi2_clk = { + __INIT_CLK_DEBUG(ssi2_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi2_set_parent, + .set_rate = _clk_ssi2_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi2_get_rate, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &ocram_clk, +#else + .secondary = &mmdc_ch1_axi_clk[0], +#endif +}; + +static unsigned long _clk_ssi3_get_rate(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + + prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK) + >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK) + >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (prediv * podf); +} + +static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 512) + return -EINVAL; + + __calc_pre_post_dividers(1 << 6, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK| + MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK); + reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET; + + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + + +static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll3_pfd2_508M, &pll3_pfd3_454M, + &pll4_audio_main_clk, NULL, NULL, NULL); + reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk ssi3_clk = { + __INIT_CLK_DEBUG(ssi3_clk) + .parent = &pll3_pfd2_508M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ssi3_set_parent, + .set_rate = _clk_ssi3_set_rate, + .round_rate = _clk_ssi_round_rate, + .get_rate = _clk_ssi3_get_rate, +#ifdef CONFIG_SND_MXC_SOC_IRAM + .secondary = &ocram_clk, +#else + .secondary = &mmdc_ch1_axi_clk[0], +#endif +}; + +static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + /* Round to closest divisor */ + if ((parent_rate % rate) > (rate / 2)) + div++; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 64) + div = 64; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + return parent_rate / (pre * post); +} + +static unsigned long _clk_pxp_epdc_axi_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + /* Round to closest divisor */ + if ((parent_rate % rate) > (rate / 2)) + div++; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static unsigned long _clk_pxp_axi_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CHSCCDR); + + div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >> + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_pxp_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CHSCCDR); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CHSCCDR); + + return 0; +} + +static int _clk_pxp_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CHSCCDR) + & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, + &pll3_usb_otg_main_clk, &pll5_video_main_clk, + &pll2_pfd0_352M, &pll2_pfd2_400M, &pll3_pfd1_540M); + reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CHSCCDR); + + /* Derive clock from divided pre-muxed pxp_axi clock.*/ + mux = 0; + reg = __raw_readl(MXC_CCM_CHSCCDR) + & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK; + __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET), + MXC_CCM_CHSCCDR); + + return 0; +} + +static unsigned long _clk_epdc_axi_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CHSCCDR); + + div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK) + >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_epdc_axi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CHSCCDR); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CHSCCDR); + + return 0; +} + +static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CHSCCDR) + & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, + &pll3_usb_otg_main_clk, &pll5_video_main_clk, + &pll2_pfd0_352M, &pll2_pfd2_400M, &pll3_pfd1_540M); + reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CHSCCDR); + + /* Derive clock from divided pre-muxed ipu1_di0 clock.*/ + mux = 0; + reg = __raw_readl(MXC_CCM_CHSCCDR) + & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK; + __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET), + MXC_CCM_CHSCCDR); + + return 0; +} + +static struct clk pxp_axi_clk = { + __INIT_CLK_DEBUG(pxp_axi_clk) + .id = 0, + .parent = &pll5_video_main_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_pxp_axi_set_parent, + .set_rate = _clk_pxp_axi_set_rate, + .round_rate = _clk_pxp_epdc_axi_round_rate, + .get_rate = _clk_pxp_axi_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk epdc_axi_clk = { + __INIT_CLK_DEBUG(epdc_axi_clk) + .id = 0, + .parent = &pll5_video_main_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_epdc_axi_set_parent, + .set_rate = _clk_epdc_axi_set_rate, + .round_rate = _clk_pxp_epdc_axi_round_rate, + .get_rate = _clk_epdc_axi_get_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static unsigned long _clk_lcdif_pix_get_rate(struct clk *clk) +{ + u32 reg, pre, post; + + reg = __raw_readl(MXC_CCM_CSCDR2); + + pre = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >> + MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1; + + reg = __raw_readl(MXC_CCM_CSCMR1); + post = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >> + MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (pre * post); +} + +static int _clk_lcdif_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 64)) + return -EINVAL; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2); + reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK; + reg |= (pre - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + /* + * fixup: + * Bits 22 and 21 of the divide value are inverted before + * going into the divider port. + */ + post = (post - 1) ^ 0x6; + + reg = __raw_readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK; + reg |= post << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static int _clk_lcdif_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCDR2) + & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, + &pll3_usb_otg_main_clk, &pll5_video_main_clk, + &pll2_pfd0_352M, &pll3_pfd0_720M, &pll3_pfd1_540M); + reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCDR2); + + /* Derive clock from divided pre-muxed lcdif_pix clock.*/ + mux = 0; + reg = __raw_readl(MXC_CCM_CSCDR2) + & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK; + __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET), + MXC_CCM_CSCDR2); + + return 0; +} + +static unsigned long _clk_epdc_pix_get_rate(struct clk *clk) +{ + u32 reg, pre, post; + + reg = __raw_readl(MXC_CCM_CSCDR2); + + pre = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK) >> + MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1; + + reg = __raw_readl(MXC_CCM_CBCMR); + post = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >> + MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1; + + + return clk_get_rate(clk->parent) / (pre * post); +} + +static int _clk_epdc_pix_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + + if (((parent_rate / div) != rate) || (div > 64)) + return -EINVAL; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2); + reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK; + reg |= (pre - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + reg = __raw_readl(MXC_CCM_CBCMR); + reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK; + reg |= (post - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCMR); + + return 0; +} + +static int _clk_epdc_pix_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCDR2) + & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll2_528_bus_main_clk, + &pll3_usb_otg_main_clk, &pll5_video_main_clk, + &pll2_pfd0_352M, &pll2_pfd1_594M, &pll3_pfd1_540M); + reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static struct clk lcdif_pix_clk = { + __INIT_CLK_DEBUG(lcdif_pix_clk) + .id = 0, + .parent = &pll5_video_main_clk, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_lcdif_pix_set_parent, + .set_rate = _clk_lcdif_pix_set_rate, + .round_rate = _clk_epdc_lcdif_pix_round_rate, + .get_rate = _clk_lcdif_pix_get_rate, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; + +static struct clk epdc_pix_clk = { + __INIT_CLK_DEBUG(epdc_pix_clk) + .id = 0, + .parent = &pll3_pfd1_540M, + .enable_reg = MXC_CCM_CCGR3, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_epdc_pix_set_parent, + .set_rate = _clk_epdc_pix_set_rate, + .round_rate = _clk_epdc_lcdif_pix_round_rate, + .get_rate = _clk_epdc_pix_get_rate, + .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, +}; +static unsigned long _clk_spdif_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (parent_rate % rate) + div++; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + return parent_rate / (pre * post); +} + +static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CDCDR) + & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK; + + mux = _get_mux6(parent, &pll4_audio_main_clk, + &pll3_pfd2_508M, &pll3_pfd3_454M, + &pll3_sw_clk, NULL, NULL); + reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CDCDR); + + return 0; +} + +static unsigned long _clk_spdif0_get_rate(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CDCDR); + + pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK) + >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK) + >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / (pred * podf); +} + +static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || div > 64) + return -EINVAL; + + __calc_pre_post_dividers(1 << 3, div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK| + MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET; + + __raw_writel(reg, MXC_CCM_CDCDR); + + return 0; +} + +static struct clk spdif0_clk[] = { + { + __INIT_CLK_DEBUG(spdif0_clk_0) + .id = 0, + .parent = &pll3_sw_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, + .disable = _clk_disable, + .secondary = &spdif0_clk[1], + .set_rate = _clk_spdif0_set_rate, + .get_rate = _clk_spdif0_get_rate, + .set_parent = _clk_spdif0_set_parent, + .round_rate = _clk_spdif_round_rate, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + __INIT_CLK_DEBUG(spdif0_clk_1) + .id = 1, + .parent = &ipg_clk, + .secondary = &spba_clk, + }, +}; + +static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCDR2) & ~MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK; + + if (parent == &pll3_60M) + mux = 0; + else + mux = 1; /* osc */ + + reg |= mux << MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + +static int _clk_fec_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned int reg, div = 1; + + switch (rate) { + case 25000000: + div = 0; + break; + case 50000000: + div = 1; + break; + case 100000000: + div = 2; + break; + case 125000000: + div = 3; + break; + default: + return -EINVAL; + } + reg = __raw_readl(PLL8_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK; + reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET); + __raw_writel(reg, PLL8_ENET_BASE_ADDR); + + return 0; +} + +static unsigned long _clk_fec_get_rate(struct clk *clk) +{ + unsigned int div; + + div = (__raw_readl(PLL8_ENET_BASE_ADDR)) + & ANADIG_PLL_ENET_DIV_SELECT_MASK; + + switch (div) { + case 0: + div = 20; + break; + case 1: + div = 10; + break; + case 3: + div = 5; + break; + case 4: + div = 4; + break; + } + + return 500000000 / div; +} + +static int _clk_fec_enable(struct clk *clk) +{ + unsigned int reg; + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL8_ENET_BASE_ADDR); + reg &= ~ANADIG_PLL_BYPASS; + reg |= ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL8_ENET_BASE_ADDR); + + _clk_enable(clk); + return 0; +} + +static void _clk_fec_disable(struct clk *clk) +{ + unsigned int reg; + + _clk_disable(clk); + + /* Enable ENET ref clock */ + reg = __raw_readl(PLL8_ENET_BASE_ADDR); + reg |= ANADIG_PLL_BYPASS; + reg &= ~ANADIG_PLL_ENABLE; + __raw_writel(reg, PLL8_ENET_BASE_ADDR); +} + +static struct clk fec_clk[] = { + { + __INIT_CLK_DEBUG(fec_clk) + .id = 0, + .parent = &pll6_enet_main_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_fec_enable, + .disable = _clk_fec_disable, + .set_rate = _clk_fec_set_rate, + .get_rate = _clk_fec_get_rate, + .secondary = &fec_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &mx6per1_clk, + }, +}; + +static struct clk ecspi_clk[] = { + { + __INIT_CLK_DEBUG(ecspi0_clk) + .id = 0, + .parent = &pll3_60M, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ecspi_set_parent, + }, + { + __INIT_CLK_DEBUG(ecspi1_clk) + .id = 1, + .parent = &pll3_60M, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ecspi_set_parent, + }, + { + __INIT_CLK_DEBUG(ecspi2_clk) + .id = 2, + .parent = &pll3_60M, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ecspi_set_parent, + }, + { + __INIT_CLK_DEBUG(ecspi3_clk) + .id = 3, + .parent = &pll3_60M, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ecspi_set_parent, + }, + { + __INIT_CLK_DEBUG(ecspi4_clk) + .id = 4, + .parent = &pll3_60M, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_parent = _clk_ecspi_set_parent, + }, +}; + +static unsigned long _clk_emi_slow_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 8) + div = 8; + + return parent_rate / div; +} + +static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK; + + mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk, + &pll2_pfd2_400M, &pll3_pfd0_720M, NULL, NULL); + reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET); + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_emi_slow_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCMR1); + div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >> + MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCMR1); + reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static struct clk emi_slow_clk = { + __INIT_CLK_DEBUG(emi_slow_clk) + .id = 0, + .parent = &axi_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .set_rate = _clk_emi_slow_set_rate, + .get_rate = _clk_emi_slow_get_rate, + .round_rate = _clk_emi_slow_round_rate, + .set_parent = _clk_emi_slow_set_parent, +}; + +static unsigned long _clk_uart_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + + if (div > 64) + div = 64; + + return parent_rate / div; +} + +static int _clk_uart_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 64)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static unsigned long _clk_uart_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned long val; + + reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; + div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; + val = clk_get_rate(clk->parent) / div; + + return val; +} + +static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCDR1) & ~MXC_CCM_CSCDR1_UART_CLK_SEL_MASK; + + if (parent == &osc_clk) + mux = 1; + else + mux = 0; /* osc */ + + reg |= mux << MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET; + + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static struct clk uart_clk[] = { + { + __INIT_CLK_DEBUG(uart_clk) + .id = 0, + .parent = &pll3_80M, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &uart_clk[1], + .set_rate = _clk_uart_set_rate, + .get_rate = _clk_uart_get_rate, + .round_rate = _clk_uart_round_rate, + .set_parent = _clk_uart_set_parent, + }, + { + __INIT_CLK_DEBUG(uart_serial_clk) + .id = 1, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk aips_tz2_clk = { + __INIT_CLK_DEBUG(aips_tz2_clk) + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +static struct clk aips_tz1_clk = { + __INIT_CLK_DEBUG(aips_tz1_clk) + .parent = &ahb_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, +}; + +/* set the parent by the ipcg table */ + +static struct clk pwm_clk[] = { + { + __INIT_CLK_DEBUG(pwm_clk_0) + .parent = &ipg_perclk, + .id = 0, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + __INIT_CLK_DEBUG(pwm_clk_1) + .parent = &ipg_perclk, + .id = 1, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + __INIT_CLK_DEBUG(pwm_clk_2) + .parent = &ipg_perclk, + .id = 2, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + __INIT_CLK_DEBUG(pwm_clk_3) + .parent = &ipg_perclk, + .id = 3, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk usboh3_clk[] = { + { + __INIT_CLK_DEBUG(usboh3_clk) + .parent = &ahb_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, + .secondary = &usboh3_clk[1], + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + .parent = &mmdc_ch1_axi_clk[0], + .secondary = &mx6per1_clk, + }, +}; + +static int _clk_enable1(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg |= 1 << clk->enable_shift; + __raw_writel(reg, clk->enable_reg); + + return 0; +} + +static void _clk_disable1(struct clk *clk) +{ + u32 reg; + reg = __raw_readl(clk->enable_reg); + reg &= ~(1 << clk->enable_shift); + __raw_writel(reg, clk->enable_reg); +} + +static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &pll3_usb_otg_main_clk) + sel = 0; + else if (parent == &pll2_528_bus_main_clk) + sel = 1; + else if (parent == &pll1_sys_main_clk) + sel = 2; + else if (parent == &pll5_video_main_clk) + sel = 3; + else if (parent == &axi_clk) + sel = 5; + else if (parent == &pxp_axi_clk) + sel = 7; + else if (parent == &epdc_axi_clk) + sel = 8; + else if (parent == &lcdif_pix_clk) + sel = 9; + else if (parent == &epdc_pix_clk) + sel = 10; + else if (parent == &ahb_clk) + sel = 11; + else if (parent == &ipg_clk) + sel = 12; + else if (parent == &ipg_perclk) + sel = 13; + else if (parent == &ckil_clk) + sel = 14; + else if (parent == &pll4_audio_main_clk) + sel = 15; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK; + reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long _clk_clko_get_rate(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCOSR); + u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >> + MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long _clk_clko_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (div > 8) + div = 8; + return parent_rate / div; +} + +static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &mmdc_ch1_axi_clk[0]) + sel = 0; + else if (parent == &usdhc4_clk) + sel = 2; + else if (parent == &usdhc1_clk) + sel = 3; + else if (parent == &ecspi_clk[0]) + sel = 6; + else if (parent == &usdhc3_clk) + sel = 8; + else if (parent == &ipu1_clk) + sel = 11; + else if (parent == &ipu2_clk) + sel = 12; + + else if (parent == &osc_clk) + sel = 14; + else if (parent == &usdhc2_clk) + sel = 17; + else if (parent == &ssi1_clk) + sel = 18; + else if (parent == &ssi2_clk) + sel = 19; + else if (parent == &ssi3_clk) + sel = 20; + else if (parent == &uart_clk[0]) + sel = 28; + else if (parent == &spdif0_clk[0]) + sel = 29; + else if (parent == &spdif0_clk[1]) + sel = 30; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK; + reg |= sel << MXC_CCM_CCOSR_CKO2_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long _clk_clko2_get_rate(struct clk *clk) +{ + u32 reg = __raw_readl(MXC_CCM_CCOSR); + u32 div = ((reg & MXC_CCM_CCOSR_CKO2_DIV_MASK) >> + MXC_CCM_CCOSR_CKO2_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} + +static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 parent_rate = clk_get_rate(clk->parent); + u32 div = parent_rate / rate; + + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CCOSR_CKO2_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static struct clk clko_clk = { + __INIT_CLK_DEBUG(clko_clk) + .parent = &pll2_528_bus_main_clk, + .enable = _clk_enable1, + .enable_reg = MXC_CCM_CCOSR, + .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET, + .disable = _clk_disable1, + .set_parent = _clk_clko_set_parent, + .set_rate = _clk_clko_set_rate, + .get_rate = _clk_clko_get_rate, + .round_rate = _clk_clko_round_rate, +}; + +static struct clk clko2_clk = { + __INIT_CLK_DEBUG(clko2_clk) + .parent = &usdhc4_clk, + .enable = _clk_enable1, + .enable_reg = MXC_CCM_CCOSR, + .enable_shift = MXC_CCM_CCOSR_CKO2_EN_OFFSET, + .disable = _clk_disable1, + .set_parent = _clk_clko2_set_parent, + .set_rate = _clk_clko2_set_rate, + .get_rate = _clk_clko2_get_rate, + .round_rate = _clk_clko_round_rate, +}; + +static struct clk perfmon0_clk = { + __INIT_CLK_DEBUG(perfmon0_clk) + .parent = &mmdc_ch1_axi_clk[0], + .enable = _clk_enable1, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable1, +}; + +static struct clk perfmon1_clk = { + __INIT_CLK_DEBUG(perfmon1_clk) + .parent = &ipu1_clk, + .enable = _clk_enable1, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable1, +}; + +static struct clk perfmon2_clk = { + __INIT_CLK_DEBUG(perfmon2_clk) + .parent = &mmdc_ch1_axi_clk[0], + .enable = _clk_enable1, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, + .disable = _clk_disable1, +}; + +static struct clk dummy_clk = { + .id = 0, +}; + +#define _REGISTER_CLOCK(d, n, c) \ + { \ + .dev_id = d, \ + .con_id = n, \ + .clk = &c, \ + } + + +static struct clk_lookup lookups[] = { + _REGISTER_CLOCK(NULL, "osc", osc_clk), + _REGISTER_CLOCK(NULL, "ckih", ckih_clk), + _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk), + _REGISTER_CLOCK(NULL, "ckil", ckil_clk), + _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk), + _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk), + _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk), + _REGISTER_CLOCK(NULL, "pll2_pfd2_400M", pll2_pfd2_400M), + _REGISTER_CLOCK(NULL, "pll2_pfd0_352M", pll2_pfd0_352M), + _REGISTER_CLOCK(NULL, "pll2_pfd1_594M", pll2_pfd1_594M), + _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M), + _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk), + _REGISTER_CLOCK(NULL, "pll3_pfd2_508M", pll3_pfd2_508M), + _REGISTER_CLOCK(NULL, "pll3_pfd3_454M", pll3_pfd3_454M), + _REGISTER_CLOCK(NULL, "pll3_pfd0_720M", pll3_pfd0_720M), + _REGISTER_CLOCK(NULL, "pll3_pfd1_540M", pll3_pfd1_540M), + _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk), + _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M), + _REGISTER_CLOCK(NULL, "pll3_80M", pll3_80M), + _REGISTER_CLOCK(NULL, "pll3_60M", pll3_60M), + _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk), + _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk), + _REGISTER_CLOCK(NULL, "pll6", pll6_enet_main_clk), + _REGISTER_CLOCK(NULL, "extern_audio_clk", extern_audio_clk), + _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), + _REGISTER_CLOCK("smp_twd", NULL, twd_clk), + _REGISTER_CLOCK(NULL, "periph_clk", periph_clk), + _REGISTER_CLOCK(NULL, "axi_clk", axi_clk), + _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch1_axi_clk[0]), + _REGISTER_CLOCK(NULL, "ahb", ahb_clk), + _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk), + _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk), + _REGISTER_CLOCK(NULL, "spba", spba_clk), + _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]), + _REGISTER_CLOCK(NULL, "iim_clk", iim_clk), + _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]), + _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]), + _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]), + _REGISTER_CLOCK(NULL, "csi_clk", ipu1_clk), + _REGISTER_CLOCK(NULL, "elcdif_axi", ipu2_clk), + _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk), + _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk), + _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk), + _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk), + _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk), + _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk), + _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk), + _REGISTER_CLOCK(NULL, "pxp_axi", pxp_axi_clk), + _REGISTER_CLOCK(NULL, "epdc_axi", epdc_axi_clk), + _REGISTER_CLOCK(NULL, "epdc_pix", epdc_pix_clk), + _REGISTER_CLOCK(NULL, "elcdif_pix", lcdif_pix_clk), + _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]), + _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]), + _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]), + _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]), + _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]), + _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]), + _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk), + _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]), + _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]), + _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]), + _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]), + _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]), + _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]), + _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]), + _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]), + _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]), + _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), + _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), + _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk), + _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk), + _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk), + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk), + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk), + _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk), + _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk), + _REGISTER_CLOCK(NULL, "clko_clk", clko_clk), + _REGISTER_CLOCK(NULL, "clko2_clk", clko2_clk), + _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk), + _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk), + _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk), + _REGISTER_CLOCK(NULL, "anaclk_1", anaclk_1), + _REGISTER_CLOCK(NULL, "anaclk_2", anaclk_2), +}; + +static void clk_tree_init(void) + +{ + unsigned int reg; + + reg = __raw_readl(MMDC_MDMISC_OFFSET); + /* + * For lpddr2 board, current freq only support up to 400MHz, + * in this case, periph clk will set to 400MHz in uboot, + * so in clock init, we need to check whether the ddr clock + * is set to 400MHz, if yes, then we should set periph clk + * parent to pll2_pfd2_400M. + */ + if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) == + (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) { + clk_set_parent(&periph_clk, &pll2_pfd2_400M); + printk(KERN_INFO "Set periph_clk's parent to pll2_pfd2_400M!\n"); + } +} + + +int __init mx6sl_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2) +{ + __iomem void *base; + int i; + + external_low_reference = ckil; + external_high_reference = ckih1; + ckih2_reference = ckih2; + oscillator_reference = osc; + + apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K); + + for (i = 0; i < ARRAY_SIZE(lookups); i++) { + clkdev_add(&lookups[i]); + clk_debug_register(lookups[i].clk); + } + + /* Disable un-necessary PFDs & PLLs */ + + /* keep correct count. */ + clk_enable(&cpu_clk); + clk_enable(&periph_clk); + + clk_tree_init(); + + /* Set AHB to 132MHz. */ + clk_set_rate(&ahb_clk, clk_round_rate(&ahb_clk, 132000000)); + + pll2_pfd0_352M.disable(&pll2_pfd0_352M); + pll2_pfd1_594M.disable(&pll2_pfd1_594M); + + pll3_pfd3_454M.disable(&pll3_pfd3_454M); + pll3_pfd2_508M.disable(&pll3_pfd2_508M); + pll3_pfd1_540M.disable(&pll3_pfd1_540M); + pll3_pfd0_720M.disable(&pll3_pfd0_720M); + + pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk); + pll4_audio_main_clk.disable(&pll4_audio_main_clk); + pll5_video_main_clk.disable(&pll5_video_main_clk); + pll6_enet_main_clk.disable(&pll6_enet_main_clk); + + /* Initialize Audio and Video PLLs to valid frequency (650MHz). */ + clk_set_rate(&pll4_audio_main_clk, 650000000); + clk_set_rate(&pll5_video_main_clk, 650000000); + + clk_set_parent(&clko_clk, &ipg_clk); + + mx6_cpu_op_init(); + cpu_op_tbl = get_cpu_op(&cpu_op_nr); + + /* Gate off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG2_OFFSET | + 3 << MXC_CCM_CCGRx_CG1_OFFSET | + 3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0); + } + __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET, MXC_CCM_CCGR1); + __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET | + 1 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET | + 3 << MXC_CCM_CCGRx_CG9_OFFSET | + 3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2); + __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET | + 3 << MXC_CCM_CCGRx_CG13_OFFSET | + 3 << MXC_CCM_CCGRx_CG12_OFFSET | + 3 << MXC_CCM_CCGRx_CG11_OFFSET | + 3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3); + __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET | + 1 << MXC_CCM_CCGRx_CG6_OFFSET | + 1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4); + __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(0, MXC_CCM_CCGR6); + + /* S/PDIF */ + clk_set_parent(&spdif0_clk[0], &pll3_pfd3_454M); + + /* pxp & epdc axi */ + clk_set_parent(&pxp_axi_clk, &pll2_pfd2_400M); + clk_set_rate(&pxp_axi_clk, 198000000); + clk_set_parent(&epdc_axi_clk, &pll2_pfd2_400M); + clk_set_rate(&epdc_axi_clk, 198000000); + + /* epdc pix - PLL5 as parent */ + clk_set_parent(&epdc_pix_clk, &pll5_video_main_clk); + /* lcdif pix - PLL5 as parent */ + clk_set_parent(&lcdif_pix_clk, &pll5_video_main_clk); + + gpt_clk[0].parent = &ipg_perclk; + gpt_clk[0].get_rate = NULL; + + /* GPT will source from perclk, hence ipg_perclk + * should be from OSC24M */ + clk_set_parent(&ipg_perclk, &osc_clk); + + base = ioremap(GPT_BASE_ADDR, SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + + lp_high_freq = 0; + lp_med_freq = 0; + + return 0; + +} diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c index 6f3765e23523..2822d2d7f17c 100644 --- a/arch/arm/mach-mx6/cpu.c +++ b/arch/arm/mach-mx6/cpu.c @@ -31,50 +31,42 @@ #include "crm_regs.h" #include "cpu_op-mx6.h" -extern unsigned int num_cpu_idle_lock; - -void *mx6_wait_in_iram_base; -void (*mx6_wait_in_iram)(void); -extern void mx6_wait(void); -extern int init_mmdc_settings(void); - struct cpu_op *(*get_cpu_op)(int *op); -bool enable_wait_mode; +bool enable_wait_mode = true; u32 arm_max_freq = CPU_AT_1GHz; +bool mem_clk_on_in_wait; void __iomem *gpc_base; void __iomem *ccm_base; +extern unsigned int num_cpu_idle_lock; + static int cpu_silicon_rev = -1; -#define SI_REV_OFFSET 0x48 +#define MX6_USB_ANALOG_DIGPROG 0x260 +#define MX6SL_USB_ANALOG_DIGPROG 0x280 -static int get_mx6q_srev(void) +static int mx6_get_srev(void) { - void __iomem *romcp = ioremap(BOOT_ROM_BASE_ADDR, SZ_8K); + void __iomem *anatop = MX6_IO_ADDRESS(ANATOP_BASE_ADDR); u32 rev; + if (cpu_is_mx6sl()) + rev = __raw_readl(anatop + MX6SL_USB_ANALOG_DIGPROG); + else + rev = __raw_readl(anatop + MX6_USB_ANALOG_DIGPROG); - if (!romcp) { - cpu_silicon_rev = -EINVAL; - return 0; - } - - rev = __raw_readl(romcp + SI_REV_OFFSET); rev &= 0xff; - iounmap(romcp); - if (rev == 0x10) + if (rev == 0) return IMX_CHIP_REVISION_1_0; - else if (rev == 0x11) + else if (rev == 1) return IMX_CHIP_REVISION_1_1; - else if (rev == 0x20) - return IMX_CHIP_REVISION_2_0; - return 0; + + return IMX_CHIP_REVISION_UNKNOWN; } /* * Returns: * the silicon revision of the cpu - * -EINVAL - not a mx50 */ int mx6q_revision(void) { @@ -82,12 +74,44 @@ int mx6q_revision(void) return -EINVAL; if (cpu_silicon_rev == -1) - cpu_silicon_rev = get_mx6q_srev(); + cpu_silicon_rev = mx6_get_srev(); return cpu_silicon_rev; } EXPORT_SYMBOL(mx6q_revision); +/* + * Returns: + * the silicon revision of the cpu + */ +int mx6dl_revision(void) +{ + if (!cpu_is_mx6dl()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = mx6_get_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx6dl_revision); + +/* + * Returns: + * the silicon revision of the cpu + */ +int mx6sl_revision(void) +{ + if (!cpu_is_mx6sl()) + return -EINVAL; + + if (cpu_silicon_rev == -1) + cpu_silicon_rev = mx6_get_srev(); + + return cpu_silicon_rev; +} +EXPORT_SYMBOL(mx6sl_revision); + static int __init post_cpu_init(void) { unsigned int reg; @@ -113,13 +137,11 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x50); iounmap(base); - if (enable_wait_mode) { - /* Allow SCU_CLK to be disabled when all cores are in WFI*/ - base = IO_ADDRESS(SCU_BASE_ADDR); - reg = __raw_readl(base); - reg |= 0x20; - __raw_writel(reg, base); - } + /* Allow SCU_CLK to be disabled when all cores are in WFI*/ + base = IO_ADDRESS(SCU_BASE_ADDR); + reg = __raw_readl(base); + reg |= 0x20; + __raw_writel(reg, base); /* Disable SRC warm reset to work aound system reboot issue */ base = IO_ADDRESS(SRC_BASE_ADDR); @@ -131,8 +153,34 @@ static int __init post_cpu_init(void) ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR); num_cpu_idle_lock = 0x0; + if (cpu_is_mx6dl()) + num_cpu_idle_lock = 0xffff0000; + +#ifdef CONFIG_SMP + switch (setup_max_cpus) { + case 3: + num_cpu_idle_lock = 0xff000000; + break; + case 2: + num_cpu_idle_lock = 0xffff0000; + break; + case 1: + case 0: + num_cpu_idle_lock = 0xffffff00; + break; + } +#endif + /* + * The option to keep ARM memory clocks enabled during WAIT + * is only available on MX6SL, MX6DQ TO1.2 (or later) and + * MX6DL TO1.1 (or later) + * So if the user specifies "mem_clk_on" on any other chip, + * ensure that it is disabled. + */ + if (!cpu_is_mx6sl() && (mx6q_revision() < IMX_CHIP_REVISION_1_2) && + (mx6dl_revision() < IMX_CHIP_REVISION_1_1)) + mem_clk_on_in_wait = false; - init_mmdc_settings(); return 0; } postcore_initcall(post_cpu_init); @@ -167,4 +215,14 @@ static int __init arm_core_max(char *p) early_param("arm_freq", arm_core_max); +static int __init enable_mem_clk_in_wait(char *p) +{ + mem_clk_on_in_wait = true; + + return 0; +} + +early_param("mem_clk_on", enable_mem_clk_in_wait); + + diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index 76229926cbd7..188dbaebd57f 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -141,6 +141,7 @@ #define ANADIG_REG0_CORE_TARGET_OFFSET 0 /* ANA MISC2 register defines */ +#define ANADIG_ANA_MISC2_REG1_BO_EN (1 << 13) #define ANADIG_ANA_MISC2_CONTROL3_MASK 0xC0000000 #define ANADIG_ANA_MISC2_CONTROL3_OFFSET 30 @@ -257,6 +258,8 @@ #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET (18) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (16) +#define MXC_CCM_CBCMR_MLB_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CBCMR_MLB_CLK_SEL_OFFSET (16) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) @@ -289,6 +292,8 @@ #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (10) +#define MXC_CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x1 << 6) +#define MXC_CCM_CSCMR1_PERCLK_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F) #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET (0) @@ -314,6 +319,8 @@ #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) +#define MXC_CCM_CSCDR1_UART_CLK_SEL_MASK (0x1 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F) #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) @@ -382,6 +389,8 @@ /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_OFFSET (18) #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET (15) #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << 12) @@ -478,6 +487,7 @@ #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1) +#define MXC_CCM_CGPR_MEM_IPG_STOP_MASK (1 << 1) /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGRx_CG_MASK 0x3 diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h index 69b2ad2e5500..6ecc42c16965 100644 --- a/arch/arm/mach-mx6/devices-imx6q.h +++ b/arch/arm/mach-mx6/devices-imx6q.h @@ -27,6 +27,10 @@ extern const struct imx_snvs_rtc_data imx6q_imx_snvs_rtc_data __initconst; #define imx6q_add_imx_snvs_rtc() \ imx_add_snvs_rtc(&imx6q_imx_snvs_rtc_data) +extern const struct imx_caam_data imx6q_imx_caam_data __initconst; +#define imx6q_add_imx_caam() \ + imx_add_caam(&imx6q_imx_caam_data) + extern const struct imx_anatop_thermal_imx_data imx6q_anatop_thermal_imx_data __initconst; #define imx6q_add_anatop_thermal_imx(id, pdata) \ @@ -40,6 +44,9 @@ extern const struct imx_dma_data imx6q_dma_data __initconst; extern const struct imx_fec_data imx6q_fec_data __initconst; #define imx6q_add_fec(pdata) \ imx_add_fec(&imx6q_fec_data, pdata) +extern const struct imx_fec_data imx6sl_fec_data __initconst; +#define imx6sl_add_fec(pdata) \ + imx_add_fec(&imx6sl_fec_data, pdata) extern const struct imx_sdhci_esdhc_imx_data imx6q_sdhci_usdhc_imx_data[] __initconst; @@ -66,6 +73,10 @@ extern const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst; #define imx6q_add_fsl_ehci_hs(id, pdata) \ imx_add_fsl_ehci(&imx6q_mxc_ehci_hs_data[id - 1], pdata) +extern const struct imx_mxc_ehci_data imx6sl_mxc_ehci_hs_data[] __initconst; +#define imx6sl_add_fsl_ehci_hs(id, pdata) \ + imx_add_fsl_ehci(&imx6sl_mxc_ehci_hs_data[id - 1], pdata) + extern const struct imx_fsl_usb2_otg_data imx6q_fsl_usb2_otg_data __initconst; #define imx6q_add_fsl_usb2_otg(pdata) \ imx_add_fsl_usb2_otg(&imx6q_fsl_usb2_otg_data, pdata) @@ -78,6 +89,10 @@ extern const struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] __initco #define imx6q_add_fsl_usb2_hs_wakeup(id, pdata) \ imx_add_fsl_usb2_wakeup(&imx6q_fsl_hs_wakeup_data[id - 1], pdata) +extern const struct imx_fsl_usb2_wakeup_data imx6sl_fsl_hs_wakeup_data[] __initconst; +#define imx6sl_add_fsl_usb2_hs_wakeup(id, pdata) \ + imx_add_fsl_usb2_wakeup(&imx6sl_fsl_hs_wakeup_data[id - 1], pdata) + extern const struct imx_imx_esai_data imx6q_imx_esai_data[] __initconst; #define imx6q_add_imx_esai(id, pdata) \ imx_add_imx_esai(&imx6q_imx_esai_data[id], pdata) @@ -108,9 +123,9 @@ extern const struct imx_ldb_data imx6q_ldb_data __initconst; platform_device_register_resndata(NULL, "mxc_v4l2_output",\ id, NULL, 0, NULL, 0); -#define imx6q_add_v4l2_capture(id) \ +#define imx6q_add_v4l2_capture(id, pdata) \ platform_device_register_resndata(NULL, "mxc_v4l2_capture",\ - id, NULL, 0, NULL, 0); + id, NULL, 0, pdata, sizeof(*pdata)); extern const struct imx_mxc_hdmi_data imx6q_mxc_hdmi_data __initconst; #define imx6q_add_mxc_hdmi(pdata) \ @@ -208,6 +223,14 @@ extern const struct imx_pxp_data imx6dl_pxp_data __initconst; extern const struct imx_epdc_data imx6dl_epdc_data __initconst; #define imx6dl_add_imx_epdc(pdata) \ imx_add_imx_epdc(&imx6dl_epdc_data, pdata) + +extern const struct imx_epdc_data imx6sl_spdc_data __initconst; +#define imx6sl_add_imx_spdc(pdata) \ + imx_add_imx_spdc(&imx6sl_spdc_data, pdata) + +extern const struct imx_elcdif_data imx6dl_elcdif_data __initconst; +#define imx6dl_add_imx_elcdif(pdata) \ + imx_add_imx_elcdif(&imx6dl_elcdif_data, pdata) extern const struct imx_vdoa_data imx6q_vdoa_data __initconst; #define imx6q_add_vdoa() imx_add_vdoa(&imx6q_vdoa_data) diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c index 6e80f0aa11a3..3cf6b226fca6 100644 --- a/arch/arm/mach-mx6/mm.c +++ b/arch/arm/mach-mx6/mm.c @@ -30,6 +30,7 @@ #include <mach/common.h> #include <mach/iomux-v3.h> #include <asm/hardware/cache-l2x0.h> +#include "crm_regs.h" /*! * This structure defines the MX6 memory map. @@ -59,14 +60,24 @@ static struct map_desc mx6_io_desc[] __initdata = { static void mx6_set_cpu_type(void) { - u32 cpu_type = readl(IO_ADDRESS(ANATOP_BASE_ADDR + 0x260)); + u32 cpu_type = readl(IO_ADDRESS(ANATOP_BASE_ADDR + 0x280)); cpu_type >>= 16; - if (cpu_type == 0x63) + if (cpu_type == 0x60) { + mxc_set_cpu_type(MXC_CPU_MX6SL); + imx_print_silicon_rev("i.MX6SoloLite", mx6sl_revision()); + return; + } + + cpu_type = readl(IO_ADDRESS(ANATOP_BASE_ADDR + 0x260)); + cpu_type >>= 16; + if (cpu_type == 0x63) { mxc_set_cpu_type(MXC_CPU_MX6Q); - else if (cpu_type == 0x61) + imx_print_silicon_rev("i.MX6Q", mx6q_revision()); + } else if (cpu_type == 0x61) { mxc_set_cpu_type(MXC_CPU_MX6DL); - else + imx_print_silicon_rev("i.MX6DL/SOLO", mx6dl_revision()); + } else pr_err("Unknown CPU type: %x\n", cpu_type); } @@ -88,6 +99,15 @@ int mxc_init_l2x0(void) { unsigned int val; + #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 + + val = readl(IOMUXC_GPR11); + if (cpu_is_mx6sl() && (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM)) { + /* L2 cache configured as OCRAM, reset it */ + val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; + writel(val, IOMUXC_GPR11); + } + writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL)); writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL)); diff --git a/arch/arm/mach-mx6/mx6_ddr_freq.S b/arch/arm/mach-mx6/mx6_ddr_freq.S index 85af2a402e68..fbaa44df8cdc 100644 --- a/arch/arm/mach-mx6/mx6_ddr_freq.S +++ b/arch/arm/mach-mx6/mx6_ddr_freq.S @@ -27,7 +27,7 @@ ldr r0, [r6, #0x14] and r0, r0, #0x2000000 cmp r0, #0x2000000 - beq switch_pre_periph_clk_528 + beq set_ahb_podf_before_switch /* Step 1: Change periph_clk to be sourced from pll3_clk. */ /* Ensure PLL3 is the source and set the divider to 1. */ @@ -39,6 +39,20 @@ bic r0, r0, #0x38000000 str r0, [r6, #0x14] + /* Set the AHB dividers before the switch. */ + /* Don't change AXI clock divider. */ + /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */ + ldr r0, [r6, #0x14] + ldr r2, =0x381D00 + bic r0, r0, r2 + orr r0, r0, #0xD00 + str r0, [r6, #0x14] + +wait_div_update528: + ldr r0, [r6, #0x48] + cmp r0, #0 + bne wait_div_update528 + /* Now switch periph_clk to pll3_main_clk. */ ldr r0, [r6, #0x14] orr r0, r0, #0x2000000 @@ -49,25 +63,33 @@ periph_clk_switch3: cmp r0, #0 bne periph_clk_switch3 -switch_pre_periph_clk_528: + b switch_pre_periph_clk_528 - /* Now switch pre_periph_clk to PLL2_528MHz. */ - ldr r0, [r6, #0x18] - bic r0, r0, #0xC0000 - str r0, [r6, #0x18] - - /* Set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4 (need to maintain GPT divider). */ +set_ahb_podf_before_switch: + /* Set the AHB dividers before the switch. */ + /* Especially if the AHB is at 24MHz, divider + * would be at divide by 1 and clock + * would be too fast when switching to PLL3. + */ + /* Don't change AXI clock divider. */ + /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */ ldr r0, [r6, #0x14] - ldr r2, =0x3F1D00 + ldr r2, =0x381D00 bic r0, r0, r2 - orr r0, r0, #0x10000 orr r0, r0, #0xD00 str r0, [r6, #0x14] -wait_div_update1: +wait_div_update528_1: ldr r0, [r6, #0x48] cmp r0, #0 - bne wait_div_update1 + bne wait_div_update528_1 + +switch_pre_periph_clk_528: + + /* Now switch pre_periph_clk to PLL2_528MHz. */ + ldr r0, [r6, #0x18] + bic r0, r0, #0xC0000 + str r0, [r6, #0x18] /* Now switch periph_clk back. */ ldr r0, [r6, #0x14] @@ -82,18 +104,17 @@ periph_clk_switch4: /* Change the GPT divider so that its at 6MHz. */ ldr r0, [r6, #0x1C] bic r0, r0, #0x3F - orr r0, r0, #0xB + orr r0, r0, #0xA str r0, [r6, #0x1C] - .endm .macro switch_to_400MHz /* check if periph_clk_sel is already set */ - ldr r0, [r6, #0x14] - and r0, r0, #0x2000000 - cmp r0, #0x2000000 - beq switch_pre_periph_clk_400 + ldr r0, [r6, #0x14] + and r0, r0, #0x2000000 + cmp r0, #0x2000000 + beq set_ahb_podf_before_switch1 /* Step 1: Change periph_clk to be sourced from pll3_clk. */ /* Ensure PLL3 is the source and set the divider to 1. */ @@ -115,26 +136,34 @@ periph_clk_switch5: cmp r0, #0 bne periph_clk_switch5 -switch_pre_periph_clk_400: + b switch_pre_periph_clk_400 - /* Now switch pre_periph_clk to PFD_400MHz. */ - ldr r0, [r6, #0x18] - bic r0, r0, #0xC0000 - orr r0, r0, #0x40000 - str r0, [r6, #0x18] - - /* Set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=3 (need to maintain GPT divider). */ +set_ahb_podf_before_switch1: + /* Set the AHB dividers before the switch. */ + /* Especially if the AHB is at 24MHz, divider + * would be at divide by 1 and clock + * would be too fast when switching to PLL3. + */ + /* Don't change AXI clock divider. */ + /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */ ldr r0, [r6, #0x14] - ldr r2, =0x3F1D00 + ldr r2, =0x381D00 bic r0, r0, r2 - orr r0, r0, #0x10000 - orr r0, r0, #0x900 + orr r0, r0, #0xD00 str r0, [r6, #0x14] -wait_div_update400: +wait_div_update400_1: ldr r0, [r6, #0x48] cmp r0, #0 - bne wait_div_update400 + bne wait_div_update400_1 + +switch_pre_periph_clk_400: + + /* Now switch pre_periph_clk to PFD_400MHz. */ + ldr r0, [r6, #0x18] + bic r0, r0, #0xC0000 + orr r0, r0, #0x40000 + str r0, [r6, #0x18] /* Now switch periph_clk back. */ ldr r0, [r6, #0x14] @@ -146,10 +175,24 @@ periph_clk_switch6: cmp r0, #0 bne periph_clk_switch6 + /* Change AHB divider so that we are at 400/3=133MHz. */ + /* Don't change AXI clock divider. */ + /* Set the MMDC_DIV=1, AHB_DIV=3 (need to maintain GPT divider). */ + ldr r0, [r6, #0x14] + ldr r2, =0x381D00 + bic r0, r0, r2 + orr r0, r0, #0x900 + str r0, [r6, #0x14] + +wait_div_update400_2: + ldr r0, [r6, #0x48] + cmp r0, #0 + bne wait_div_update400_2 + /* Change the GPT divider so that its at 6MHz. */ ldr r0, [r6, #0x1C] bic r0, r0, #0x3F - orr r0, r0, #0xB + orr r0, r0, #0xA str r0, [r6, #0x1C] .endm @@ -346,6 +389,19 @@ ddr_freq_change: bic r0, r0, #0xff00 str r0, [r5, #0x4] +/* Delay for a while */ + ldr r1, =4 +delay1: + ldr r2, =0 +cont1: + ldr r0, [r5, r2] + add r2, r2, #4 + cmp r2, #16 + bne cont1 + sub r1, r1, #1 + cmp r1, #0 + bgt delay1 + /* set CON_REG */ ldr r0, =0x8000 str r0, [r5, #0x1C] @@ -614,7 +670,7 @@ switch_freq_528: continue_dll_on: - /* set step-by-step mode */ + /* set SBS step-by-step mode */ ldr r0, [r5, #0x410] orr r0, r0, #0x100 str r0, [r5, #0x410] @@ -668,7 +724,6 @@ cont5: sub r1, r1, #1 cmp r1, #0 bgt delay5 - /* Disable dqs pull down in the IOMUX. */ /* setmem /32 0x020e05a8 = 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE=110 diff --git a/arch/arm/mach-mx6/mx6_fec.c b/arch/arm/mach-mx6/mx6_fec.c index b2aa45b3c510..935ba2644831 100644 --- a/arch/arm/mach-mx6/mx6_fec.c +++ b/arch/arm/mach-mx6/mx6_fec.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,5 +49,8 @@ void __init imx6_init_fec(struct fec_platform_data fec_data) if (!is_valid_ether_addr(fec_data.mac)) random_ether_addr(fec_data.mac); - imx6q_add_fec(&fec_data); + if (cpu_is_mx6sl()) + imx6sl_add_fec(&fec_data); + else + imx6q_add_fec(&fec_data); } diff --git a/arch/arm/mach-mx6/mx6_mmdc.c b/arch/arm/mach-mx6/mx6_mmdc.c index 2498f01e0889..c4f232f0e56d 100644 --- a/arch/arm/mach-mx6/mx6_mmdc.c +++ b/arch/arm/mach-mx6/mx6_mmdc.c @@ -227,7 +227,6 @@ int update_ddr_freq(int ddr_rate) /* Set the interrupt to be pending in the GIC. */ reg = 1 << (irq_used[cpu] % 32); writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET + (irq_used[cpu] / 32) * 4); - udelay(10); } } while (cpus_in_wfe != online_cpus) @@ -343,6 +342,8 @@ int init_mmdc_settings(void) memcpy(ddr_freq_change_iram_base, mx6_ddr_freq_change, SZ_8K); mx6_change_ddr_freq = (void *)ddr_freq_change_iram_base; + curr_ddr_rate = ddr_normal_rate; + for_each_online_cpu(cpu) { /* Set up a reserved interrupt to get all the active cores into a WFE state * before changing the DDR frequency. diff --git a/arch/arm/mach-mx6/mx6q_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index e52c66ad0151..d276320c374a 100644 --- a/arch/arm/mach-mx6/mx6q_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -35,7 +35,7 @@ #define IRAM_SUSPEND_SIZE (1 << 12) /************************************************************* -mx6q_suspend: +mx6_suspend: Suspend the processor (eg, wait for interrupt). Set the DDR into Self Refresh @@ -50,6 +50,123 @@ see define in include/linux/suspend.h r1: iram_paddr r2: suspend_iram_base *************************************************************/ + .macro sl_ddr_io_save + + ldr r4, [r1, #0x30c] /* DRAM_DQM0 */ + ldr r5, [r1, #0x310] /* DRAM_DQM1 */ + ldr r6, [r1, #0x314] /* DRAM_DQM2 */ + ldr r7, [r1, #0x318] /* DRAM_DQM3 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x344] /* DRAM_SDQS0 */ + ldr r5, [r1, #0x348] /* DRAM_SDQS1 */ + ldr r6, [r1, #0x34c] /* DRAM_SDQS2 */ + ldr r7, [r1, #0x350] /* DRAM_SDQS3 */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x5c4] /* GPR_B0DS */ + ldr r5, [r1, #0x5cc] /* GPR_B1DS */ + ldr r6, [r1, #0x5d4] /* GPR_B2DS */ + ldr r7, [r1, #0x5d8] /* GPR_B3DS */ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x300] /* DRAM_CAS */ + ldr r5, [r1, #0x31c] /* DRAM_RAS */ + ldr r6, [r1, #0x338] /* DRAM_SDCLK_0 */ + ldr r7, [r1, #0x5ac] /* GPR_ADDS*/ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x5b0] /* DDRMODE_CTL */ + ldr r5, [r1, #0x5c0] /* DDRMODE */ + ldr r6, [r1, #0x33c] /* DRAM_SODT0*/ + ldr r7, [r1, #0x340] /* DRAM_SODT1*/ + stmfd r0!, {r4-r7} + + ldr r4, [r1, #0x330] /* DRAM_SDCKE0 */ + ldr r5, [r1, #0x334] /* DRAM_SDCKE1 */ + ldr r6, [r1, #0x320] /* DRAM_RESET */ + ldr r7, [r1, #0x5c8] /* GPR_CTLDS */ + stmfd r0!, {r4-r7} + + .endm + + .macro sl_ddr_io_restore + + ldmea r0!, {r4-r7} + str r4, [r1, #0x30c] /* DRAM_DQM0 */ + str r5, [r1, #0x310] /* DRAM_DQM1 */ + str r6, [r1, #0x314] /* DRAM_DQM2 */ + str r7, [r1, #0x318] /* DRAM_DQM3 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x344] /* DRAM_SDQS0 */ + str r5, [r1, #0x348] /* DRAM_SDQS1 */ + str r6, [r1, #0x34c] /* DRAM_SDQS2 */ + str r7, [r1, #0x350] /* DRAM_SDQS3 */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x5c4] /* GPR_B0DS */ + str r5, [r1, #0x5cc] /* GPR_B1DS */ + str r6, [r1, #0x5d4] /* GPR_B2DS */ + str r7, [r1, #0x5d8] /* GPR_B3DS */ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x300] /* DRAM_CAS */ + str r5, [r1, #0x31c] /* DRAM_RAS */ + str r6, [r1, #0x338] /* DRAM_SDCLK_0 */ + str r7, [r1, #0x5ac] /* GPR_ADDS*/ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x5b0] /* DDRMODE_CTL */ + str r5, [r1, #0x5c0] /* DDRMODE */ + str r6, [r1, #0x33c] /* DRAM_SODT0*/ + str r7, [r1, #0x340] /* DRAM_SODT1*/ + + ldmea r0!, {r4-r7} + str r4, [r1, #0x330] /* DRAM_SDCKE0 */ + str r5, [r1, #0x334] /* DRAM_SDCKE1 */ + str r6, [r1, #0x320] /* DRAM_RESET */ + str r7, [r1, #0x5c8] /* GPR_CTLDS */ + + .endm + + .macro sl_ddr_io_set_lpm + + mov r0, #0 + str r0, [r1, #0x30c] /* DRAM_DQM0 */ + str r0, [r1, #0x310] /* DRAM_DQM1 */ + str r0, [r1, #0x314] /* DRAM_DQM2 */ + str r0, [r1, #0x318] /* DRAM_DQM3 */ + + str r0, [r1, #0x344] /* DRAM_SDQS0 */ + str r0, [r1, #0x348] /* DRAM_SDQS1 */ + str r0, [r1, #0x34c] /* DRAM_SDQS2 */ + str r0, [r1, #0x350] /* DRAM_SDQS3 */ + + str r0, [r1, #0x5c4] /* GPR_B0DS */ + str r0, [r1, #0x5cc] /* GPR_B1DS */ + str r0, [r1, #0x5d4] /* GPR_B2DS */ + str r0, [r1, #0x5d8] /* GPR_B3DS */ + + str r0, [r1, #0x300] /* DRAM_CAS */ + str r0, [r1, #0x31c] /* DRAM_RAS */ + str r0, [r1, #0x338] /* DRAM_SDCLK_0 */ + str r0, [r1, #0x5ac] /* GPR_ADDS*/ + + str r0, [r1, #0x5b0] /* DDRMODE_CTL */ + str r0, [r1, #0x5c0] /* DDRMODE */ + str r0, [r1, #0x33c] /* DRAM_SODT0*/ + str r0, [r1, #0x340] /* DRAM_SODT1*/ + + str r0, [r1, #0x5c8] /* GPR_CTLDS */ + mov r0, #0x80000 + str r0, [r1, #0x320] /* DRAM_RESET */ + mov r0, #0x1000 + str r0, [r1, #0x330] /* DRAM_SDCKE0 */ + str r0, [r1, #0x334] /* DRAM_SDCKE1 */ + + .endm + .macro dl_ddr_io_save ldr r4, [r1, #0x470] /* DRAM_DQM0 */ @@ -455,11 +572,12 @@ Flush and disable L1 dcache .endm -ENTRY(mx6q_suspend) +ENTRY(mx6_suspend) stmfd sp!, {r0-r12} @ Save registers /************************************************************* suspend mode entry *************************************************************/ + mov r12, r3 /* Save CPU type to r12*/ cmp r0, #0x1 bne dormant /* dormant mode */ @@ -537,21 +655,34 @@ saved register and context as below: CPSR SCTLR ************************************************************/ -ddr_iomux_save: /* save mmdc iomux setting, stack is from the tail of iram_suspend base */ mov r0, r2 /* get suspend_iram_base */ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ + + mov r4, sp @ Store sp + mrs r5, spsr @ Store spsr + mov r6, lr @ Store lr + mov r7, r12 @ Store cpu type + stmfd r0!, {r4-r7} + ldr r1, =MX6Q_IOMUXC_BASE_ADDR add r1, r1, #PERIPBASE_VIRT + cmp r12, #MXC_CPU_MX6Q + bne dl_io_save dq_ddr_io_save + b ddr_io_save_done +dl_io_save: + cmp r12, #MXC_CPU_MX6DL + bne sl_io_save + dl_ddr_io_save + b ddr_io_save_done +sl_io_save: + sl_ddr_io_save - mov r4, sp @ Store sp - mrs r5, spsr @ Store spsr - mov r6, lr @ Store lr - stmfd r0!, {r4-r6} +ddr_io_save_done: /* c1 and c2 registers */ mrc p15, 0, r4, c1, c0, 2 @ CPACR @@ -614,11 +745,24 @@ refresh: ldr r1, =MX6Q_IOMUXC_BASE_ADDR add r1, r1, #PERIPBASE_VIRT + cmp r12, #MXC_CPU_MX6Q + bne dl_io_set_lpm dq_ddr_io_set_lpm + b ddr_io_set_lpm_done +dl_io_set_lpm: + cmp r12, #MXC_CPU_MX6DL + bne sl_io_set_lpm + dl_ddr_io_set_lpm + b ddr_io_set_lpm_done +sl_io_set_lpm: + sl_ddr_io_set_lpm + +ddr_io_set_lpm_done: + /**************************************************************** save resume pointer into SRC_GPR1 ****************************************************************/ - ldr r0, =mx6q_suspend + ldr r0, =mx6_suspend ldr r1, =resume sub r1, r1, r0 add r3, r3, r1 @@ -645,7 +789,19 @@ system immediately. ldr r1, =MX6Q_IOMUXC_BASE_ADDR add r1, r1, #PERIPBASE_VIRT + cmp r12, #MXC_CPU_MX6Q + bne dl_io_restore dq_ddr_io_restore + b ddr_io_restore_done +dl_io_restore: + cmp r12, #MXC_CPU_MX6DL + bne sl_io_restore + dl_ddr_io_restore + b ddr_io_restore_done +sl_io_restore: + sl_ddr_io_restore + +ddr_io_restore_done: mrc p15, 0, r1, c1, c0, 0 orr r1, r1, #(1 << 2) @ Enable the C bit @@ -665,14 +821,29 @@ resume: str r1, [r0, #SRC_GPR1_OFFSET] /* clear SRC_GPR1 */ ldr r0, [r0, #SRC_GPR2_OFFSET] + /* Restore cp15 registers and cpu type */ + ldmea r0!, {r4-r7} + mov sp, r4 @ Restore sp + msr spsr_cxsf, r5 @ Restore spsr + mov lr, r6 @ Restore lr + mov r12, r7 @ Restore cpu type + + /* Restore DDR IO */ ldr r1, =MX6Q_IOMUXC_BASE_ADDR + + cmp r12, #MXC_CPU_MX6Q + bne dl_io_dsm_restore dq_ddr_io_restore + b ddr_io_restore_dsm_done +dl_io_dsm_restore: + cmp r12, #MXC_CPU_MX6DL + bne sl_io_dsm_restore + dl_ddr_io_restore + b ddr_io_restore_dsm_done +sl_io_dsm_restore: + sl_ddr_io_restore - /* Restore cp15 registers */ - ldmea r0!, {r4-r6} - mov sp, r4 - msr spsr_cxsf, r5 @ Restore spsr - mov lr, r6 @ Restore lr +ddr_io_restore_dsm_done: /* c1 and c2 registers */ ldmea r0!, {r4-r7} @@ -798,7 +969,15 @@ restore control register to enable cache * enabling MMU. */ ldr r4, =PAGE_OFFSET + + cmp r12, #MXC_CPU_MX6SL + bne dq_dl_phy_offset + ldr r5, =MX6SL_PHYS_OFFSET + b get_phy_offset_done +dq_dl_phy_offset: ldr r5, =MX6_PHYS_OFFSET +get_phy_offset_done: + sub r4, r4, r5 add r4, r4, r10 str r9, [r4] @@ -825,8 +1004,7 @@ out: ldmfd sp!, {r0-r12} mov pc, lr - .equ va2pa_offset, (PAGE_OFFSET - MX6_PHYS_OFFSET) - .type mx6q_do_suspend, #object -ENTRY(mx6q_do_suspend) - .word mx6q_suspend - .size mx6q_suspend, . - mx6q_suspend + .type mx6_do_suspend, #object +ENTRY(mx6_do_suspend) + .word mx6_suspend + .size mx6_suspend, . - mx6_suspend diff --git a/arch/arm/mach-mx6/mx6_wfi.S b/arch/arm/mach-mx6/mx6_wfi.S index 6e2972faa293..a616dabc4a80 100644 --- a/arch/arm/mach-mx6/mx6_wfi.S +++ b/arch/arm/mach-mx6/mx6_wfi.S @@ -28,13 +28,20 @@ */ ENTRY(mx6_wait) - push {r4, r5, r6} + push {r4, r5, r6, r7, r8} + + mov r7, r2 /* Store the arm_podf to be used. */ + mov r6, r3 + + ldr r2, =ANATOP_BASE_ADDR + add r2, r2, #PERIPBASE_VIRT + + ldr r8, =CCM_BASE_ADDR + add r8, r8, #PERIPBASE_VIRT - ldr r2, =ANATOP_BASE_ADDR - add r2, r2, #PERIPBASE_VIRT /* get the flags variables into the cache */ - ldr r3, [r0] + ldr r3, [r0] /* get CPU ID */ mrc p15,0,r5,c0,c0,5 @@ -59,11 +66,27 @@ ENTRY(mx6_wait) mov r3, #0xff + /* Check to see if we need to switch to 24MHz */ + cmp r7, #0 + bne use_podf ldr r6, =(1 << 16) str r6, [r2, #0x04] + b cont + +use_podf: + /* Change ARM_PODF to the max possible podf + * so that ARM_CLK to IPG_CLK is in 12:5 ratio. + */ + str r7, [r8, #0x10] + /* Loop till podf is accepted. */ +podf_loop: + ldr r4, [r8, #0x48] + cmp r4, #0x0 + bne podf_loop /* dmb */ +cont: str r3, [r1] dsb @@ -71,9 +94,18 @@ ENTRY(mx6_wait) mvn r4, #0x0 ldr r3, [r0] cmp r3, r4 - movne r3, #0x0 - strne r6, [r2, #0x08] - strne r3, [r1] + beq DO_WFI + + mov r3, #0x0 + /* Switch to 24MHz or use ARM_PODF. */ + cmp r7, #0x0 + bne use_podf1 + str r6, [r2, #0x08] + b DO_WFI +use_podf1: + str r6, [r8, #0x10] + + str r3, [r1] DO_WFI: dsb @@ -90,15 +122,22 @@ DO_WFI: bne DONE mov r4, #0x0 + cmp r7, #0x0 + bne use_podf2 ldr r6, =(1 << 16) - str r6, [r2, #0x08] + str r6, [r2, #0x08] + b cont1 + +use_podf2: + str r6, [r8, #0x10] +cont1: mov r3, #0x0 str r3, [r1] DONE: - pop {r4,r5, r6} + pop {r4,r5, r6, r7, r8} /* Restore registers */ mov pc, lr diff --git a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c index 2d3863beba31..ed6bfb115d31 100644 --- a/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c +++ b/arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c @@ -65,6 +65,14 @@ #define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) +#ifdef CONFIG_MX6_INTER_LDO_BYPASS +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "VDDCORE", + } +}; +#endif + static struct regulator_consumer_supply sw2_consumers[] = { { .supply = "MICVDD", @@ -139,6 +147,11 @@ static struct regulator_init_data sw1a_init = { .boot_on = 1, .always_on = 1, }, + + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, + #endif }; static struct regulator_init_data sw1b_init = { @@ -368,11 +381,6 @@ static int pfuze100_init(struct mc_pfuze *pfuze) PFUZE100_SW1ASTANDBY_STBY_VAL); if (ret) goto err; - ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY, - PFUZE100_SW1BSTANDBY_STBY_M, - PFUZE100_SW1BSTANDBY_STBY_VAL); - if (ret) - goto err; ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, PFUZE100_SW1CSTANDBY_STBY_M, PFUZE100_SW1CSTANDBY_STBY_VAL); diff --git a/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c new file mode 100644 index 000000000000..0d5a37cb0df0 --- /dev/null +++ b/arch/arm/mach-mx6/mx6sl_arm2_pmic_pfuze100.c @@ -0,0 +1,424 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/err.h> +#include <linux/i2c.h> +#include <linux/gpio.h> +#include <linux/regulator/machine.h> +#include <linux/mfd/pfuze.h> +#include <mach/irqs.h> + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +#define PFUZE100_I2C_DEVICE_NAME "pfuze100" +/* 7-bit I2C bus slave address */ +#define PFUZE100_I2C_ADDR (0x08) + /*SWBST*/ +#define PFUZE100_SW1ASTANDBY 33 +#define PFUZE100_SW1ASTANDBY_STBY_VAL (0x16) +#define PFUZE100_SW1ASTANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW1BSTANDBY 40 +#define PFUZE100_SW1BSTANDBY_STBY_VAL (0x16) +#define PFUZE100_SW1BSTANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW1CSTANDBY 47 +#define PFUZE100_SW1CSTANDBY_STBY_VAL (0x16) +#define PFUZE100_SW1CSTANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW2STANDBY 54 +#define PFUZE100_SW2STANDBY_STBY_VAL 0x0 +#define PFUZE100_SW2STANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW3ASTANDBY 61 +#define PFUZE100_SW3ASTANDBY_STBY_VAL 0x0 +#define PFUZE100_SW3ASTANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW3BSTANDBY 68 +#define PFUZE100_SW3BSTANDBY_STBY_VAL 0x0 +#define PFUZE100_SW3BSTANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SW4STANDBY 75 +#define PFUZE100_SW4STANDBY_STBY_VAL 0 +#define PFUZE100_SW4STANDBY_STBY_M (0x3f<<0) +#define PFUZE100_SWBSTCON1 102 +#define PFUZE100_SWBSTCON1_SWBSTMOD_VAL (0x1<<2) +#define PFUZE100_SWBSTCON1_SWBSTMOD_M (0x3<<2) + + +static struct regulator_consumer_supply sw2_consumers[] = { + { + .supply = "MICVDD", + .dev_name = "1-001a", + }, + { + .supply = "DBVDD", + .dev_name = "1-001a", + } + +}; +static struct regulator_consumer_supply sw4_consumers[] = { + { + .supply = "AUD_1V8", + } +}; +static struct regulator_consumer_supply swbst_consumers[] = { + { + .supply = "SWBST_5V", + } +}; +static struct regulator_consumer_supply vgen1_consumers[] = { + { + .supply = "VGEN1_1V5", + } +}; +static struct regulator_consumer_supply vgen2_consumers[] = { + { + .supply = "VGEN2_1V5", + } +}; +static struct regulator_consumer_supply vgen4_consumers[] = { + { + .supply = "AVDD", + .dev_name = "1-001a", + }, + { + .supply = "DCVDD", + .dev_name = "1-001a", + }, + { + .supply = "CPVDD", + .dev_name = "1-001a", + }, + { + .supply = "PLLVDD", + .dev_name = "1-001a", + } +}; +static struct regulator_consumer_supply vgen5_consumers[] = { + { + .supply = "VGEN5_2V8", + } +}; +static struct regulator_consumer_supply vgen6_consumers[] = { + { + .supply = "VGEN6_3V3", + } +}; + +static struct regulator_init_data sw1a_init = { + .constraints = { + .name = "PFUZE100_SW1A", +#ifdef PFUZE100_FIRST_VERSION + .min_uV = 650000, + .max_uV = 1437500, +#else + .min_uV = 300000, + .max_uV = 1875000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .boot_on = 1, + .always_on = 1, + }, +}; + +static struct regulator_init_data sw1b_init = { + .constraints = { + .name = "PFUZE100_SW1B", + .min_uV = 300000, + .max_uV = 1875000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data sw1c_init = { + .constraints = { + .name = "PFUZE100_SW1C", + .min_uV = 300000, + .max_uV = 1875000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "PFUZE100_SW2", +#if PFUZE100_SW2_VOL6 + .min_uV = 800000, + .max_uV = 3950000, +#else + .min_uV = 400000, + .max_uV = 1975000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(sw2_consumers), + .consumer_supplies = sw2_consumers, +}; + +static struct regulator_init_data sw3a_init = { + .constraints = { + .name = "PFUZE100_SW3A", +#if PFUZE100_SW3_VOL6 + .min_uV = 800000, + .max_uV = 3950000, +#else + .min_uV = 400000, + .max_uV = 1975000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data sw3b_init = { + .constraints = { + .name = "PFUZE100_SW3B", +#if PFUZE100_SW3_VOL6 + .min_uV = 800000, + .max_uV = 3950000, +#else + .min_uV = 400000, + .max_uV = 1975000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "PFUZE100_SW4", +#if PFUZE100_SW4_VOL6 + .min_uV = 800000, + .max_uV = 3950000, +#else + .min_uV = 400000, + .max_uV = 1975000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(sw4_consumers), + .consumer_supplies = sw4_consumers, +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "PFUZE100_SWBST", + .min_uV = 5000000, + .max_uV = 5150000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, + .num_consumer_supplies = ARRAY_SIZE(swbst_consumers), + .consumer_supplies = swbst_consumers, +}; + +static struct regulator_init_data vsnvs_init = { + .constraints = { + .name = "PFUZE100_VSNVS", + .min_uV = 1200000, + .max_uV = 3000000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data vrefddr_init = { + .constraints = { + .name = "PFUZE100_VREFDDR", + .always_on = 1, + .boot_on = 1, + }, +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "PFUZE100_VGEN1", +#ifdef PFUZE100_FIRST_VERSION + .min_uV = 1200000, + .max_uV = 1550000, +#else + .min_uV = 800000, + .max_uV = 1550000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + .always_on = 0, + .boot_on = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen1_consumers), + .consumer_supplies = vgen1_consumers, +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "PFUZE100_VGEN2", +#ifdef PFUZE100_FIRST_VERSION + .min_uV = 1200000, + .max_uV = 1550000, +#else + .min_uV = 800000, + .max_uV = 1550000, +#endif + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen2_consumers), + .consumer_supplies = vgen2_consumers, + +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "PFUZE100_VGEN3", + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + .always_on = 0, + .boot_on = 0, + }, +}; + +static struct regulator_init_data vgen4_init = { + .constraints = { + .name = "PFUZE100_VGEN4", + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen4_consumers), + .consumer_supplies = vgen4_consumers, +}; + +static struct regulator_init_data vgen5_init = { + .constraints = { + .name = "PFUZE100_VGEN5", + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen5_consumers), + .consumer_supplies = vgen5_consumers, +}; + +static struct regulator_init_data vgen6_init = { + .constraints = { + .name = "PFUZE100_VGEN6", + .min_uV = 1800000, + .max_uV = 3300000, + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + .valid_modes_mask = 0, + }, + .num_consumer_supplies = ARRAY_SIZE(vgen6_consumers), + .consumer_supplies = vgen6_consumers, +}; + +static int pfuze100_init(struct mc_pfuze *pfuze) +{ + int ret; + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1ASTANDBY, + PFUZE100_SW1ASTANDBY_STBY_M, + PFUZE100_SW1ASTANDBY_STBY_VAL); + if (ret) + goto err; + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1BSTANDBY, + PFUZE100_SW1BSTANDBY_STBY_M, + PFUZE100_SW1BSTANDBY_STBY_VAL); + if (ret) + goto err; + ret = pfuze_reg_rmw(pfuze, PFUZE100_SW1CSTANDBY, + PFUZE100_SW1CSTANDBY_STBY_M, + PFUZE100_SW1CSTANDBY_STBY_VAL); + if (ret) + goto err; + return 0; +err: + printk(KERN_ERR "pfuze100 init error!\n"); + return -1; +} + +static struct pfuze_regulator_init_data mx6q_sabreauto_pfuze100_regulators[] = { + {.id = PFUZE100_SW1A, .init_data = &sw1a_init}, + {.id = PFUZE100_SW1B, .init_data = &sw1b_init}, + {.id = PFUZE100_SW1C, .init_data = &sw1c_init}, + {.id = PFUZE100_SW2, .init_data = &sw2_init}, + {.id = PFUZE100_SW3A, .init_data = &sw3a_init}, + {.id = PFUZE100_SW3B, .init_data = &sw3b_init}, + {.id = PFUZE100_SW4, .init_data = &sw4_init}, + {.id = PFUZE100_SWBST, .init_data = &swbst_init}, + {.id = PFUZE100_VSNVS, .init_data = &vsnvs_init}, + {.id = PFUZE100_VREFDDR, .init_data = &vrefddr_init}, + {.id = PFUZE100_VGEN1, .init_data = &vgen1_init}, + {.id = PFUZE100_VGEN2, .init_data = &vgen2_init}, + {.id = PFUZE100_VGEN3, .init_data = &vgen3_init}, + {.id = PFUZE100_VGEN4, .init_data = &vgen4_init}, + {.id = PFUZE100_VGEN5, .init_data = &vgen5_init}, + {.id = PFUZE100_VGEN6, .init_data = &vgen6_init}, +}; + +static struct pfuze_platform_data pfuze100_plat = { + .flags = PFUZE_USE_REGULATOR, + .num_regulators = ARRAY_SIZE(mx6q_sabreauto_pfuze100_regulators), + .regulators = mx6q_sabreauto_pfuze100_regulators, + .pfuze_init = pfuze100_init, +}; + +static struct i2c_board_info __initdata pfuze100_i2c_device = { + I2C_BOARD_INFO(PFUZE100_I2C_DEVICE_NAME, PFUZE100_I2C_ADDR), + .platform_data = &pfuze100_plat, +}; + +int __init mx6sl_arm2_init_pfuze100(u32 int_gpio) +{ + if (int_gpio) + pfuze100_i2c_device.irq = gpio_to_irq(int_gpio); /*update INT gpio */ + return i2c_register_board_info(0, &pfuze100_i2c_device, 1); +} diff --git a/arch/arm/mach-mx6/plat_hotplug.c b/arch/arm/mach-mx6/plat_hotplug.c index 3cd6bb5aec35..20a33329f472 100644 --- a/arch/arm/mach-mx6/plat_hotplug.c +++ b/arch/arm/mach-mx6/plat_hotplug.c @@ -27,6 +27,7 @@ #include <linux/sched.h> #include <asm/cacheflush.h> +extern unsigned int num_cpu_idle_lock; void __iomem *src_base = IO_ADDRESS(SRC_BASE_ADDR); int platform_cpu_kill(unsigned int cpu) @@ -128,5 +129,6 @@ int platform_cpu_disable(unsigned int cpu) * we don't allow CPU 0 to be shutdown (it is still too special * e.g. clock tick interrupts) */ + *((char *)(&num_cpu_idle_lock) + (u8)cpu) = 0xff; return cpu == 0 ? -EPERM : 0; } diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c index 03ff88000052..229de6651266 100644 --- a/arch/arm/mach-mx6/pm.c +++ b/arch/arm/mach-mx6/pm.c @@ -49,6 +49,7 @@ #define GPC_ISR3_OFFSET 0x20 #define GPC_ISR4_OFFSET 0x24 #define GPC_CNTR_OFFSET 0x0 +#define GPC_PGC_DISP_PGCR_OFFSET 0x240 #define GPC_PGC_GPU_PGCR_OFFSET 0x260 #define GPC_PGC_CPU_PDN_OFFSET 0x2a0 #define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 @@ -65,12 +66,16 @@ #define ANATOP_REG_CORE_OFFSET 0x140 static struct clk *cpu_clk; +static struct clk *axi_clk; +static struct clk *periph_clk; +static struct clk *axi_org_parent; + static struct pm_platform_data *pm_data; #if defined(CONFIG_CPU_FREQ) extern int set_cpu_freq(int wp); #endif -extern void mx6q_suspend(suspend_state_t state); +extern void mx6_suspend(suspend_state_t state); extern void mx6_init_irq(void); extern unsigned int gpc_wake_irq[4]; @@ -86,11 +91,11 @@ static void __iomem *anatop_base; static void *suspend_iram_base; static void (*suspend_in_iram)(suspend_state_t state, - unsigned long iram_paddr, unsigned long suspend_iram_base) = NULL; + unsigned long iram_paddr, unsigned long suspend_iram_base, unsigned int cpu_type) = NULL; static unsigned long iram_paddr, cpaddr; static u32 ccm_ccr, ccm_clpcr, scu_ctrl; -static u32 gpc_imr[4], gpc_cpu_pup, gpc_cpu_pdn, gpc_cpu, gpc_ctr; +static u32 gpc_imr[4], gpc_cpu_pup, gpc_cpu_pdn, gpc_cpu, gpc_ctr, gpc_disp; static u32 anatop[2], ccgr1, ccgr2, ccgr3, ccgr6; static u32 ccm_analog_pfd528; static bool usb_vbus_wakeup_enabled; @@ -236,6 +241,8 @@ static void mx6_suspend_store(void) gpc_cpu_pdn = __raw_readl(gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); gpc_cpu = __raw_readl(gpc_base + GPC_PGC_CPU_PDN_OFFSET); gpc_ctr = __raw_readl(gpc_base + GPC_CNTR_OFFSET); + if (cpu_is_mx6sl()) + gpc_disp = __raw_readl(gpc_base + GPC_PGC_DISP_PGCR_OFFSET); anatop[0] = __raw_readl(anatop_base + ANATOP_REG_2P5_OFFSET); anatop[1] = __raw_readl(anatop_base + ANATOP_REG_CORE_OFFSET); } @@ -261,7 +268,8 @@ static void mx6_suspend_restore(void) __raw_writel(gpc_cpu_pup, gpc_base + GPC_PGC_CPU_PUPSCR_OFFSET); __raw_writel(gpc_cpu_pdn, gpc_base + GPC_PGC_CPU_PDNSCR_OFFSET); __raw_writel(gpc_cpu, gpc_base + GPC_PGC_CPU_PDN_OFFSET); - + if (cpu_is_mx6sl()) + __raw_writel(gpc_disp, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); __raw_writel(ccgr1, MXC_CCM_CCGR1); __raw_writel(ccgr2, MXC_CCM_CCGR2); __raw_writel(ccgr3, MXC_CCM_CCGR3); @@ -272,9 +280,17 @@ static void mx6_suspend_restore(void) static int mx6_suspend_enter(suspend_state_t state) { unsigned int wake_irq_isr[4]; + unsigned int cpu_type; struct gic_dist_state gds; struct gic_cpu_state gcs; + if (cpu_is_mx6q()) + cpu_type = MXC_CPU_MX6Q; + else if (cpu_is_mx6dl()) + cpu_type = MXC_CPU_MX6DL; + else + cpu_type = MXC_CPU_MX6SL; + wake_irq_isr[0] = __raw_readl(gpc_base + GPC_ISR1_OFFSET) & gpc_wake_irq[0]; wake_irq_isr[1] = __raw_readl(gpc_base + @@ -294,8 +310,10 @@ static int mx6_suspend_enter(suspend_state_t state) mx6_suspend_store(); /* i.MX6dl TO1.0 TKT094231: can't support ARM_POWER_OFF mode */ - if (state == PM_SUSPEND_MEM && cpu_is_mx6dl()) + if (state == PM_SUSPEND_MEM && + (mx6dl_revision() == IMX_CHIP_REVISION_1_0)) { state = PM_SUSPEND_STANDBY; + } switch (state) { case PM_SUSPEND_MEM: @@ -310,6 +328,9 @@ static int mx6_suspend_enter(suspend_state_t state) return -EINVAL; } + axi_org_parent = clk_get_parent(axi_clk); + clk_set_parent(axi_clk, periph_clk); + if (state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY) { if (pm_data && pm_data->suspend_enter) pm_data->suspend_enter(); @@ -324,7 +345,7 @@ static int mx6_suspend_enter(suspend_state_t state) } suspend_in_iram(state, (unsigned long)iram_paddr, - (unsigned long)suspend_iram_base); + (unsigned long)suspend_iram_base, cpu_type); if (state == PM_SUSPEND_MEM) { /* restore gic registers */ @@ -333,6 +354,7 @@ static int mx6_suspend_enter(suspend_state_t state) usb_power_up_handler(); gpu_power_up(); } + mx6_suspend_restore(); if (pm_data && pm_data->suspend_exit) @@ -340,6 +362,7 @@ static int mx6_suspend_enter(suspend_state_t state) } else { cpu_do_idle(); } + clk_set_parent(axi_clk, axi_org_parent); return 0; } @@ -426,7 +449,7 @@ static int __init pm_init(void) * Need to run the suspend code from IRAM as the DDR needs * to be put into low power mode manually. */ - memcpy((void *)cpaddr, mx6q_suspend, SZ_4K); + memcpy((void *)cpaddr, mx6_suspend, SZ_4K); suspend_in_iram = (void *)suspend_iram_base; @@ -435,6 +458,17 @@ static int __init pm_init(void) printk(KERN_DEBUG "%s: failed to get cpu_clk\n", __func__); return PTR_ERR(cpu_clk); } + axi_clk = clk_get(NULL, "axi_clk"); + if (IS_ERR(axi_clk)) { + printk(KERN_DEBUG "%s: failed to get axi_clk\n", __func__); + return PTR_ERR(axi_clk); + } + periph_clk = clk_get(NULL, "periph_clk"); + if (IS_ERR(periph_clk)) { + printk(KERN_DEBUG "%s: failed to get periph_clk\n", __func__); + return PTR_ERR(periph_clk); + } + printk(KERN_INFO "PM driver module loaded\n"); return 0; diff --git a/arch/arm/mach-mx6/system.c b/arch/arm/mach-mx6/system.c index 14601a04731e..34d82e2bb3d3 100644 --- a/arch/arm/mach-mx6/system.c +++ b/arch/arm/mach-mx6/system.c @@ -23,6 +23,8 @@ #include <linux/regulator/consumer.h> #include <linux/pmic_external.h> #include <linux/clockchips.h> +#include <linux/hrtimer.h> +#include <linux/tick.h> #include <asm/io.h> #include <mach/hardware.h> #include <mach/clock.h> @@ -37,6 +39,7 @@ #define SCU_INVALIDATE 0x0c #define SCU_FPGA_REVISION 0x10 #define GPC_CNTR_OFFSET 0x0 +#define GPC_PGC_DISP_PGCR_OFFSET 0x240 #define GPC_PGC_GPU_PGCR_OFFSET 0x260 #define GPC_PGC_CPU_PDN_OFFSET 0x2a0 #define GPC_PGC_CPU_PUPSCR_OFFSET 0x2a4 @@ -46,17 +49,24 @@ #define MODULE_SFTRST (1 << 31) extern unsigned int gpc_wake_irq[4]; -extern int mx6q_revision(void); static unsigned int cpu_idle_mask; static void __iomem *gpc_base = IO_ADDRESS(GPC_BASE_ADDR); +int wait_mode_arm_podf; volatile unsigned int num_cpu_idle; volatile unsigned int num_cpu_idle_lock = 0x0; +int wait_mode_arm_podf; +int cur_arm_podf; +bool arm_mem_clked_in_wait; -extern void mx6_wait(void *num_cpu_idle_lock, void *num_cpu_idle); +extern void mx6_wait(void *num_cpu_idle_lock, void *num_cpu_idle, \ + int wait_arm_podf, int cur_arm_podf); extern bool enable_wait_mode; +extern int low_bus_freq_mode; +extern int audio_bus_freq_mode; +extern bool mem_clk_on_in_wait; void gpc_set_wakeup(unsigned int irq[4]) { @@ -74,7 +84,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) int stop_mode = 0; void __iomem *anatop_base = IO_ADDRESS(ANATOP_BASE_ADDR); - u32 ccm_clpcr, anatop_val; + u32 ccm_clpcr, anatop_val, reg; ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); @@ -91,21 +101,33 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; ccm_clpcr |= 0x1 << MXC_CCM_CLPCR_LPM_OFFSET; - ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + if (cpu_is_mx6sl()) { + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS; + ccm_clpcr |= MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY; + } else + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; stop_mode = 0; } else if (mode == STOP_POWER_OFF) { ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; - ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + if (cpu_is_mx6sl()) { + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS; + ccm_clpcr |= MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY; + } else + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; stop_mode = 1; } else { ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; ccm_clpcr |= 0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET; ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; - ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; + if (cpu_is_mx6sl()) { + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS; + ccm_clpcr |= MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY; + } else + ccm_clpcr |= MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS; stop_mode = 2; } break; @@ -129,7 +151,11 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(0x1, gpc_base + GPC_PGC_CPU_PDN_OFFSET); __raw_writel(0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET); __raw_writel(0x1, gpc_base + GPC_CNTR_OFFSET); - if (cpu_is_mx6q()) { + if (cpu_is_mx6sl()) { + __raw_writel(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); + __raw_writel(0x10, gpc_base + GPC_CNTR_OFFSET); + } + if (cpu_is_mx6q() || cpu_is_mx6dl()) { /* Enable weak 2P5 linear regulator */ anatop_val = __raw_readl(anatop_base + HW_ANADIG_REG_2P5); @@ -144,8 +170,24 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(anatop_val, anatop_base + HW_ANADIG_REG_CORE); } + } else { + /* Disable VDDHIGH_IN to VDDSNVS_IN power path, + * only used when VDDSNVS_IN is powered by dedicated + * power rail */ + anatop_val = __raw_readl(anatop_base + + HW_ANADIG_ANA_MISC0); + anatop_val |= BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN; + __raw_writel(anatop_val, anatop_base + + HW_ANADIG_ANA_MISC0); + /* We need to allow the memories to be clock gated + * in STOP mode, else the power consumption will + * be very high. */ + reg = __raw_readl(MXC_CCM_CGPR); + reg |= MXC_CCM_CGPR_MEM_IPG_STOP_MASK; + __raw_writel(reg, MXC_CCM_CGPR); } - if (cpu_is_mx6q()) + + if (!cpu_is_mx6dl()) __raw_writel(__raw_readl(MXC_CCM_CCR) | MXC_CCM_CCR_RBC_EN, MXC_CCM_CCR); /* Make sure we clear WB_COUNT and re-config it */ @@ -156,30 +198,78 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) MXC_CCM_CCR_WB_COUNT_OFFSET), MXC_CCM_CCR); ccm_clpcr |= MXC_CCM_CLPCR_WB_PER_AT_LPM; } + if (cpu_is_mx6sl() || + (mx6q_revision() > IMX_CHIP_REVISION_1_1) || + (mx6dl_revision() > IMX_CHIP_REVISION_1_0)) { + u32 reg; + /* We need to allow the memories to be clock gated + * in STOP mode, else the power consumption will + * be very high. + */ + reg = __raw_readl(MXC_CCM_CGPR); + reg |= MXC_CCM_CGPR_MEM_IPG_STOP_MASK; + __raw_writel(reg, MXC_CCM_CGPR); + } } __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); } extern int tick_broadcast_oneshot_active(void); -void arch_idle(void) + void arch_idle(void) { if (enable_wait_mode) { -#ifdef CONFIG_LOCAL_TIMERS + u32 reg; int cpu = smp_processor_id(); - if (!tick_broadcast_oneshot_active()) - return; + *((char *)(&num_cpu_idle_lock) + (char)cpu) = 0x0; + mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); + if (arm_mem_clked_in_wait || mem_clk_on_in_wait) { + reg = __raw_readl(MXC_CCM_CGPR); + reg &= ~MXC_CCM_CGPR_MEM_IPG_STOP_MASK; + __raw_writel(reg, MXC_CCM_CGPR); + + cpu_do_idle(); + } else if (num_possible_cpus() == 1) { + /* We can directly use the divider to drop the ARM + * core freq in a single core environment. + */ + u32 podf = wait_mode_arm_podf; + /* Set the ARM_PODF to get the max freq possible + * to avoid the WAIT mode issue when IPG is at 66MHz. + */ + if (low_bus_freq_mode) + podf = 7; + + __raw_writel(podf, MXC_CCM_CACRR); + while (__raw_readl(MXC_CCM_CDHIPR)) + ; + cpu_do_idle(); + + __raw_writel(cur_arm_podf - 1, MXC_CCM_CACRR); + } else { +#ifdef CONFIG_LOCAL_TIMERS + if (!tick_broadcast_oneshot_active() + || !tick_oneshot_mode_active()) + return; - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); #endif - *((char *)(&num_cpu_idle_lock) + smp_processor_id()) = 0x0; - mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); - mx6_wait((void *)&num_cpu_idle_lock, (void *)&num_cpu_idle); + if (low_bus_freq_mode || audio_bus_freq_mode) + mx6_wait((void *)&num_cpu_idle_lock, + (void *)&num_cpu_idle, + 7, cur_arm_podf - 1); + else + mx6_wait((void *)&num_cpu_idle_lock, + (void *)&num_cpu_idle, + wait_mode_arm_podf, cur_arm_podf - 1); #ifdef CONFIG_LOCAL_TIMERS - clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); #endif - } else + } + } else { + mxc_cpu_lp_set(WAIT_CLOCKED); cpu_do_idle(); + } } static int __mxs_reset_block(void __iomem *hwreg, int just_enable) diff --git a/arch/arm/mach-mx6/usb_dr.c b/arch/arm/mach-mx6/usb_dr.c index 24c8cb9c4d31..0a15a8ce3327 100644 --- a/arch/arm/mach-mx6/usb_dr.c +++ b/arch/arm/mach-mx6/usb_dr.c @@ -32,6 +32,7 @@ static int usbotg_init_ext(struct platform_device *pdev); static void usbotg_uninit_ext(struct platform_device *pdev); static void usbotg_clock_gate(bool on); static void _dr_discharge_line(bool enable); +extern bool usb_icbug_swfix_need(void); /* The usb_phy1_clk do not have enable/disable function at clock.c * and PLL output for usb1's phy should be always enabled. @@ -160,6 +161,9 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) , phy_reg + HW_USBPHY_CTRL_SET); } + if (!usb_icbug_swfix_need()) + __raw_writel(((1 << 17) | (1 << 18)), + phy_reg + HW_USBPHY_IP_SET); return 0; } /* Notes: configure USB clock*/ @@ -553,6 +557,7 @@ void __init mx6_usb_dr_init(void) { struct platform_device *pdev, *pdev_wakeup; static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR); + #ifdef CONFIG_USB_OTG /* wake_up_enable is useless, just for usb_register_remote_wakeup execution*/ dr_utmi_config.wake_up_enable = _device_wakeup_enable; @@ -564,8 +569,13 @@ void __init mx6_usb_dr_init(void) #ifdef CONFIG_USB_EHCI_ARC_OTG dr_utmi_config.operating_mode = DR_HOST_MODE; dr_utmi_config.wake_up_enable = _host_wakeup_enable; - dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend; - dr_utmi_config.platform_rh_resume = _host_platform_rh_resume; + if (usb_icbug_swfix_need()) { + dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend; + dr_utmi_config.platform_rh_resume = _host_platform_rh_resume; + } else { + dr_utmi_config.platform_rh_suspend = NULL; + dr_utmi_config.platform_rh_resume = NULL; + } dr_utmi_config.platform_set_disconnect_det = fsl_platform_otg_set_usb_phy_dis; dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; dr_utmi_config.is_wakeup_event = _is_host_wakeup; diff --git a/arch/arm/mach-mx6/usb_h1.c b/arch/arm/mach-mx6/usb_h1.c index 478ead40cf0d..bff9a29aef02 100644 --- a/arch/arm/mach-mx6/usb_h1.c +++ b/arch/arm/mach-mx6/usb_h1.c @@ -34,6 +34,7 @@ static struct clk *usb_oh3_clk; extern int clk_get_usecount(struct clk *clk); static struct fsl_usb2_platform_data usbh1_config; +extern bool usb_icbug_swfix_need(void); static void fsl_platform_h1_set_usb_phy_dis( struct fsl_usb2_platform_data *pdata, bool enable) @@ -124,6 +125,9 @@ static int usb_phy_enable(struct fsl_usb2_platform_data *pdata) tmp |= (BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3); __raw_writel(tmp, phy_reg + HW_USBPHY_CTRL); + if (!usb_icbug_swfix_need()) + __raw_writel(((1 << 17) | (1 << 18)), + phy_reg + HW_USBPHY_IP_SET); return 0; } static int fsl_usb_host_init_ext(struct platform_device *pdev) @@ -329,8 +333,6 @@ static struct fsl_usb2_platform_data usbh1_config = { .power_budget = 500, /* 500 mA max power */ .wake_up_enable = _wake_up_enable, .usb_clock_for_pm = usbh1_clock_gate, - .platform_rh_suspend = usbh1_platform_rh_suspend, - .platform_rh_resume = usbh1_platform_rh_resume, .platform_set_disconnect_det = fsl_platform_h1_set_usb_phy_dis, .phy_lowpower_suspend = _phy_lowpower_suspend, .is_wakeup_event = _is_usbh1_wakeup, @@ -349,12 +351,27 @@ void __init mx6_usb_h1_init(void) { struct platform_device *pdev, *pdev_wakeup; static void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR); + usbh1_config.wakeup_pdata = &usbh1_wakeup_config; - pdev = imx6q_add_fsl_ehci_hs(1, &usbh1_config); + if (usb_icbug_swfix_need()) { + usbh1_config.platform_rh_suspend = usbh1_platform_rh_suspend; + usbh1_config.platform_rh_resume = usbh1_platform_rh_resume; + } else { + usbh1_config.platform_rh_suspend = NULL; + usbh1_config.platform_rh_resume = NULL; + } + if (cpu_is_mx6sl()) + pdev = imx6sl_add_fsl_ehci_hs(1, &usbh1_config); + else + pdev = imx6q_add_fsl_ehci_hs(1, &usbh1_config); usbh1_wakeup_config.usb_pdata[0] = pdev->dev.platform_data; - pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config); + if (cpu_is_mx6sl()) + pdev_wakeup = imx6sl_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config); + else + pdev_wakeup = imx6q_add_fsl_usb2_hs_wakeup(1, &usbh1_wakeup_config); ((struct fsl_usb2_platform_data *)(pdev->dev.platform_data))->wakeup_pdata = (struct fsl_usb2_wakeup_platform_data *)(pdev_wakeup->dev.platform_data); + /* Some phy and power's special controls for host1 * 1. The external charger detector needs to be disabled * or the signal at DP will be poor diff --git a/arch/arm/mach-mx6/usb_h2.c b/arch/arm/mach-mx6/usb_h2.c index a671a958da75..24083fd52d72 100644 --- a/arch/arm/mach-mx6/usb_h2.c +++ b/arch/arm/mach-mx6/usb_h2.c @@ -31,6 +31,7 @@ #include <mach/hardware.h> #include <mach/iomux-mx6q.h> #include <mach/iomux-mx6dl.h> +#include <mach/iomux-mx6sl.h> #include "devices-imx6q.h" #include "regs-anadig.h" #include "usb.h" @@ -185,6 +186,9 @@ static void hsic_start(void) else if (cpu_is_mx6dl()) mxc_iomux_v3_setup_pad( MX6DL_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE_START); + else if (cpu_is_mx6sl()) + mxc_iomux_v3_setup_pad( + MX6SL_PAD_HSIC_STROBE__USB_H_STROBE_START); } static void hsic_device_connected(void) diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c index 8933cacb8cb3..c36ddb34c905 100644 --- a/arch/arm/plat-mxc/audmux-v2.c +++ b/arch/arm/plat-mxc/audmux-v2.c @@ -186,13 +186,11 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); static int mxc_audmux_v2_init(void) { - int ret; + int ret = -1; #if defined(CONFIG_ARCH_MX6) - if (cpu_is_mx6q() || cpu_is_mx6dl()) { - audmux_base = MX6_IO_ADDRESS(MX6Q_AUDMUX_BASE_ADDR); - ret = 0; - } + audmux_base = MX6_IO_ADDRESS(MX6Q_AUDMUX_BASE_ADDR); + ret = 0; #endif #if defined(CONFIG_ARCH_MX5) if (cpu_is_mx51()) { diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c index 143a9b7b0aaa..073c237cc387 100755 --- a/arch/arm/plat-mxc/cpu.c +++ b/arch/arm/plat-mxc/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,6 +18,7 @@ #include <linux/module.h> #include <mach/clock.h> +#include <mach/hardware.h> unsigned int __mxc_cpu_type; EXPORT_SYMBOL(__mxc_cpu_type); @@ -29,6 +30,15 @@ void mxc_set_cpu_type(unsigned int type) __mxc_cpu_type = type; } +void imx_print_silicon_rev(const char *cpu, int srev) +{ + if (srev == IMX_CHIP_REVISION_UNKNOWN) + pr_info("CPU identified as %s, unknown revision\n", cpu); + else + pr_info("CPU identified as %s, silicon rev %d.%d\n", + cpu, (srev >> 4) & 0xf, srev & 0xf); +} + int mxc_jtag_enabled; /* OFF: 0 (default), ON: 1 */ int uart_at_24; /* OFF: 0 (default); ON: 1 */ /* diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index 9dfdd39be28c..3a0b818f5b22 100755 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -22,7 +22,7 @@ #include <linux/slab.h> #include <linux/regulator/consumer.h> #include <linux/delay.h> - +#include <linux/io.h> #include <asm/smp_plat.h> #include <asm/cpu.h> @@ -32,6 +32,47 @@ #define CLK32_FREQ 32768 #define NANOSECOND (1000 * 1000 * 1000) +/*If using cpu internal ldo bypass,we need config pmic by I2C in suspend +interface, but cpufreq driver as sys_dev is more later to suspend than I2C +driver, so we should implement another I2C operate function which isolated +with kernel I2C driver, these code is copied from u-boot*/ +#ifdef CONFIG_MX6_INTER_LDO_BYPASS +#define IADR 0x00 +#define IFDR 0x04 +#define I2CR 0x08 +#define I2SR 0x0c +#define I2DR 0x10 + +#define I2CR_IEN (1 << 7) +#define I2CR_IIEN (1 << 6) +#define I2CR_MSTA (1 << 5) +#define I2CR_MTX (1 << 4) +#define I2CR_TX_NO_AK (1 << 3) +#define I2CR_RSTA (1 << 2) + +#define I2SR_ICF (1 << 7) +#define I2SR_IBB (1 << 5) +#define I2SR_IIF (1 << 1) +#define I2SR_RX_NO_AK (1 << 0) + +#define I2C_MAX_TIMEOUT 100000 +#define I2C_TIMEOUT_TICKET 1 +#define CCM_CCGR2 0x70 + +/*#define MX6_I2CRAW_DEBUG*/ +#ifdef MX6_I2CRAW_DEBUG +#define DPRINTF(args...) printk(args) +#else +#define DPRINTF(args...) +#endif + +/*judge for pfuze regulator driver suspend or not, after pfuze regulator +suspend and before resume, should use i2c raw read/write to configure +voltage, it's safe enough, otherwise mxc_cpufreq_suspend will be failed +since i2c/pfuze have been suspend firstly.*/ +extern int cpu_freq_suspend_in; +#endif + static int cpu_freq_khz_min; static int cpu_freq_khz_max; @@ -51,11 +92,108 @@ extern int set_low_bus_freq(void); extern int set_high_bus_freq(int high_bus_speed); extern int low_freq_bus_used(void); +#ifdef CONFIG_MX6_INTER_LDO_BYPASS +static void __iomem *i2c_base;/*i2c for pmic*/ +static void __iomem *ccm_base;/*ccm_base*/ +static int wait_busy(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((!(readb(i2c_base + I2SR) & I2SR_IBB) && (--timeout))) { + writeb(0, i2c_base + I2SR); + udelay(I2C_TIMEOUT_TICKET); + } + return timeout ? timeout : (readb(i2c_base + I2SR) & I2SR_IBB); +} + +static int wait_complete(void) +{ + int timeout = I2C_MAX_TIMEOUT; + + while ((!(readb(i2c_base + I2SR) & I2SR_ICF)) && (--timeout)) { + writeb(0, i2c_base + I2SR); + udelay(I2C_TIMEOUT_TICKET); + } + DPRINTF("%s:%x\n", __func__, readb(i2c_base + I2SR)); + { + int i; + for (i = 0; i < 200; i++) + udelay(10); + + } + writeb(0, i2c_base + I2SR); /* clear interrupt */ + + return timeout; +} + +static int tx_byte(u8 byte) +{ + writeb(byte, i2c_base + I2DR); + + if (!wait_complete() || readb(i2c_base + I2SR) & I2SR_RX_NO_AK) { + DPRINTF("%s:%x <= %x\n", __func__, readb(i2c_base + I2SR), + byte); + return -1; + } + DPRINTF("%s:%x\n", __func__, byte); + return 0; +} + +static int i2c_addr(unsigned char chip, u32 addr, int alen) +{ + writeb(I2CR_IEN | I2CR_MSTA | I2CR_MTX, i2c_base + I2CR); + if (!wait_busy()) { + DPRINTF("%s:trigger start fail(%x)\n", + __func__, readb(i2c_base + I2SR)); + return -1; + } + if (tx_byte(chip << 1) || (readb(i2c_base + I2SR) & I2SR_RX_NO_AK)) { + DPRINTF("%s:chip address cycle fail(%x)\n", + __func__, readb(i2c_base + I2SR)); + return -1; + } + while (alen--) + if (tx_byte((addr >> (alen * 8)) & 0xff) || + (readb(i2c_base + I2SR) & I2SR_RX_NO_AK)) { + DPRINTF("%s:device address cycle fail(%x)\n", + __func__, readb(i2c_base + I2SR)); + return -1; + } + return 0; +} + + +static int i2c_write(unsigned char chip, u32 addr, int alen, unsigned char *buf, + int len) +{ + int timeout = I2C_MAX_TIMEOUT; + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", + __func__, chip, addr, alen, len); + + if (i2c_addr(chip, addr, alen)) + return -1; + + while (len--) + if (tx_byte(*buf++)) + return -1; + + writeb(I2CR_IEN, i2c_base + I2CR); + + while (readb(i2c_base + I2SR) & I2SR_IBB && --timeout) + udelay(I2C_TIMEOUT_TICKET); + + return 0; +} + +#endif int set_cpu_freq(int freq) { int i, ret = 0; int org_cpu_rate; int gp_volt = 0; + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + unsigned char data; + #endif org_cpu_rate = clk_get_rate(cpu_clk); if (org_cpu_rate == freq) @@ -68,13 +206,56 @@ int set_cpu_freq(int freq) if (gp_volt == 0) return ret; + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + if (cpu_freq_suspend_in) { + u32 value; + /*init I2C*/ + value = __raw_readl(ccm_base + CCM_CCGR2); + __raw_writel(value | 0x300, ccm_base + CCM_CCGR2); + udelay(1); + value = readb(i2c_base + I2CR); + writeb(value | (1 << 7), i2c_base + I2CR); + value = readb(i2c_base + I2SR); + writeb(0, i2c_base + I2SR); + switch (freq) { + case 1200000000:/*1.275*/ + data = 0x27; + break; + case 996000000:/*1.225V*/ + data = 0x25; + break; + case 792000000:/*1.1V*/ + case 672000000: + data = 0x20; + break; + case 396000000:/*0.95V*/ + data = 0x1a; + break; + case 198000000:/*0.85V*/ + data = 0x16; + break; + default: + printk(KERN_ERR "suspend freq error:%d!!!\n", freq); + break; + } + } + #endif /*Set the voltage for the GP domain. */ if (freq > org_cpu_rate) { if (low_bus_freq_mode) set_high_bus_freq(0); + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + if (cpu_freq_suspend_in) { + ret = i2c_write(0x8, 0x20, 1, &data, 1); + udelay(10); + } else + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + #else ret = regulator_set_voltage(cpu_regulator, gp_volt, gp_volt); + #endif if (ret < 0) { printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); return ret; @@ -89,8 +270,18 @@ int set_cpu_freq(int freq) } if (freq < org_cpu_rate) { + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + + if (cpu_freq_suspend_in) { + ret = i2c_write(0x8, 0x20, 1, &data, 1); + udelay(10); + } else + ret = regulator_set_voltage(cpu_regulator, gp_volt, + gp_volt); + #else ret = regulator_set_voltage(cpu_regulator, gp_volt, gp_volt); + #endif if (ret < 0) { printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); return ret; @@ -184,8 +375,17 @@ static int mxc_cpufreq_suspend(struct cpufreq_policy *policy) { pre_suspend_rate = clk_get_rate(cpu_clk); /* Set to max freq and voltage */ + /*There should be *1000, but if fix the typo error, found + hard to pass streng test, it means we didn't move cpu freq + to highest freq in suspend, but if we choose bypass, we + have to do this, so use macro to decrease the impact on + released code, the 1Ghz issue should be fixed in the future*/ if (pre_suspend_rate != (imx_freq_table[0].frequency * 1000)) + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + set_cpu_freq(imx_freq_table[0].frequency * 1000); + #else set_cpu_freq(imx_freq_table[0].frequency); + #endif return 0; } @@ -194,7 +394,6 @@ static int mxc_cpufreq_resume(struct cpufreq_policy *policy) { if (clk_get_rate(cpu_clk) != pre_suspend_rate) set_cpu_freq(pre_suspend_rate); - return 0; } @@ -301,8 +500,14 @@ static struct cpufreq_driver mxc_driver = { .name = "imx", }; +extern void mx6_cpu_regulator_init(void); static int __init mxc_cpufreq_driver_init(void) { + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + mx6_cpu_regulator_init(); + i2c_base = MX6_IO_ADDRESS(MX6Q_I2C2_BASE_ADDR); + ccm_base = MX6_IO_ADDRESS(CCM_BASE_ADDR); + #endif return cpufreq_register_driver(&mxc_driver); } diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig index 47d19921c6b5..bdea66b7a1f4 100755 --- a/arch/arm/plat-mxc/devices/Kconfig +++ b/arch/arm/plat-mxc/devices/Kconfig @@ -37,6 +37,10 @@ config IMX_HAVE_PLATFORM_IMX_SRTC config IMX_HAVE_PLATFORM_IMX_SNVS_RTC bool +config IMX_HAVE_PLATFORM_IMX_CAAM + bool + default y if SOC_IMX6Q + config IMX_HAVE_PLATFORM_IMX_FB bool select HAVE_FB_IMX @@ -137,9 +141,15 @@ config IMX_HAVE_PLATFORM_LDB config IMX_HAVE_PLATFORM_IMX_PXP bool +config IMX_HAVE_PLATFORM_IMX_ELCDIF + bool + config IMX_HAVE_PLATFORM_IMX_EPDC bool +config IMX_HAVE_PLATFORM_IMX_SPDC + bool + config IMX_HAVE_PLATFORM_IMX_SPDIF bool diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile index be2b0a674825..386b9cb4e29c 100755 --- a/arch/arm/plat-mxc/devices/Makefile +++ b/arch/arm/plat-mxc/devices/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SRTC) += platform-imx_srtc.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SNVS_RTC) += platform-imx_snvs_rtc.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_CAAM) += platform-imx-caam.o obj-y += platform-imx-dma.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o @@ -46,6 +47,8 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_LDB) += platform-imx_ldb.o obj-y += platform-imx-scc2.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_PXP) += platform-imx-pxp.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_EPDC) += platform-imx-epdc-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDC) += platform-imx-spdc-fb.o +obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_ELCDIF) += platform-imx-elcdif-fb.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-dai.o obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SPDIF) += platform-imx-spdif-audio.o diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c index b5e98576992f..20422cf6e76f 100644 --- a/arch/arm/plat-mxc/devices/platform-fec.c +++ b/arch/arm/plat-mxc/devices/platform-fec.c @@ -6,52 +6,56 @@ * the terms of the GNU General Public License version 2 as published by the * Free Software Foundation. * - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. */ #include <linux/dma-mapping.h> #include <asm/sizes.h> #include <mach/hardware.h> #include <mach/devices-common.h> -#define imx_fec_data_entry_single(soc) \ +#define imx_fec_data_entry_single(soc, _devid) \ { \ .iobase = soc ## _FEC_BASE_ADDR, \ .irq = soc ## _INT_FEC, \ + .devid = _devid, \ } #ifdef CONFIG_SOC_IMX25 const struct imx_fec_data imx25_fec_data __initconst = - imx_fec_data_entry_single(MX25); + imx_fec_data_entry_single(MX25, "imx28-fec"); #endif /* ifdef CONFIG_SOC_IMX25 */ #ifdef CONFIG_SOC_IMX27 const struct imx_fec_data imx27_fec_data __initconst = - imx_fec_data_entry_single(MX27); + imx_fec_data_entry_single(MX27, "imx28-fec"); #endif /* ifdef CONFIG_SOC_IMX27 */ #ifdef CONFIG_SOC_IMX35 const struct imx_fec_data imx35_fec_data __initconst = - imx_fec_data_entry_single(MX35); + imx_fec_data_entry_single(MX35, "imx28-fec"); #endif #ifdef CONFIG_SOC_IMX50 const struct imx_fec_data imx50_fec_data __initconst = - imx_fec_data_entry_single(MX50); + imx_fec_data_entry_single(MX50, "fec"); #endif #ifdef CONFIG_SOC_IMX51 const struct imx_fec_data imx51_fec_data __initconst = - imx_fec_data_entry_single(MX51); + imx_fec_data_entry_single(MX51, "fec"); #endif #ifdef CONFIG_SOC_IMX53 const struct imx_fec_data imx53_fec_data __initconst = - imx_fec_data_entry_single(MX53); + imx_fec_data_entry_single(MX53, "fec"); #endif #ifdef CONFIG_SOC_IMX6Q const struct imx_fec_data imx6q_fec_data __initconst = - imx_fec_data_entry_single(MX6Q); + imx_fec_data_entry_single(MX6Q, "enet"); + +const struct imx_fec_data imx6sl_fec_data __initconst = + imx_fec_data_entry_single(MX6DL, "fec"); #endif struct platform_device *__init imx_add_fec( @@ -70,7 +74,7 @@ struct platform_device *__init imx_add_fec( }, }; - return imx_add_platform_device_dmamask("fec", 0, + return imx_add_platform_device_dmamask(data->devid, 0, res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); } diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c index 523c5d4599e1..986b766fabde 100644 --- a/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c +++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-wakeup.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * Copyright (C) 2010 Pengutronix * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> @@ -25,6 +25,12 @@ const struct imx_fsl_usb2_wakeup_data imx6q_fsl_hs_wakeup_data[] __initconst = { imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 2, HS2), imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 3, HS3), }; + +const struct imx_fsl_usb2_wakeup_data imx6sl_fsl_hs_wakeup_data[] __initconst = { + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 1, HS1), + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 2, HS2), + imx_fsl_usb2_wakeup_data_entry_single(MX6SL, 3, HS3), +}; #endif /* ifdef CONFIG_SOC_IMX6Q */ struct platform_device *__init imx_add_fsl_usb2_wakeup( diff --git a/arch/arm/plat-mxc/devices/platform-imx-caam.c b/arch/arm/plat-mxc/devices/platform-imx-caam.c new file mode 100644 index 000000000000..316249032a8d --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-caam.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +/* + * security violation interrupt is used as CAAM base _INT_SNVS_SEC + * SNVS consolidated = _INT_SNVS + * JR0 = MXC_INT_CAAM_INT0_NUM + * JR1 = MXC_INT_CAAM_INT1_NUM + */ + +const struct imx_caam_data imx6q_imx_caam_data __initconst = { + .iobase_caam = MXC_CAAM_BASE_ADDR, + .irq_sec_vio = MXC_INT_SNVS_SEC, + .irq_snvs = MX6Q_INT_SNVS, + .jr[0].offset_jr = 0x1000, + .jr[0].irq_jr = MXC_INT_CAAM_INT0_NUM, + .jr[1].offset_jr = 0x2000, + .jr[1].irq_jr = MXC_INT_CAAM_INT1_NUM, +}; + +struct platform_device *__init imx_add_caam( + const struct imx_caam_data *data) +{ + u32 res_count = 0; + struct resource res[] = { + { + /* Define base range for entire CAAM register map */ + .name = "iobase_caam", + .start = data->iobase_caam, + .end = data->iobase_caam + SZ_64K - 1, + .flags = IORESOURCE_MEM, + }, { + /* Define interrupt for security violations */ + .name = "irq_sec_vio", + .start = data->irq_sec_vio, + .end = data->irq_sec_vio, + .flags = IORESOURCE_IRQ, + }, { + /* Define general SNVS interrupt */ + .name = "irq_snvs", + .start = data->irq_snvs, + .end = data->irq_snvs, + .flags = IORESOURCE_IRQ, + }, { + .name = "offset_jr0", + .start = data->jr[0].offset_jr, + .end = data->jr[0].offset_jr, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_jr0", + .start = data->jr[0].irq_jr, + .end = data->jr[0].irq_jr, + .flags = IORESOURCE_IRQ, + }, { + .name = "offset_jr1", + .start = data->jr[1].offset_jr, + .end = data->jr[1].offset_jr, + .flags = IORESOURCE_MEM, + }, { + .name = "irq_jr1", + .start = data->jr[1].irq_jr, + .end = data->jr[1].irq_jr, + .flags = IORESOURCE_IRQ, + }, + }; + + res_count = ARRAY_SIZE(res); + BUG_ON(!res_count); + + return imx_add_platform_device("caam", 0, + res, ARRAY_SIZE(res), NULL, 0); +} diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c index 65a71ac8b9e9..e7caaf4ce36f 100755 --- a/arch/arm/plat-mxc/devices/platform-imx-dma.c +++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c @@ -260,15 +260,17 @@ static int __init imxXX_add_imx_dma(void) ret = imx_add_imx_sdma(&imx53_imx_sdma_data); } else #endif -#if defined(CONFIG_SOC_IMX6Q) - if (cpu_is_mx6q() || cpu_is_mx6dl()) { - int to_version = 1; - imx6q_imx_sdma_data.pdata.to_version = to_version; - if (to_version == 1) - imx6q_imx_sdma_data.pdata.script_addrs = - &addr_imx6q_to1; - ret = imx_add_imx_sdma(&imx6q_imx_sdma_data); - } else +#if defined(CONFIG_ARCH_MX6) + int to_version = 1; + imx6q_imx_sdma_data.pdata.to_version = to_version; + if (to_version == 1) + imx6q_imx_sdma_data.pdata.script_addrs = + &addr_imx6q_to1; + ret = imx_add_imx_sdma(&imx6q_imx_sdma_data); + if (IS_ERR(ret)) + return PTR_ERR(ret); + + return 0; #endif ret = ERR_PTR(-ENODEV); diff --git a/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c b/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c new file mode 100644 index 000000000000..09a59ef90b09 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-elcdif-fb.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_elcdif_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _ELCDIF_BASE_ADDR, \ + .irq = soc ## _INT_ELCDIF, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_elcdif_data imx6dl_elcdif_data __initconst = + imx_elcdif_data_entry_single(MX6DL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_elcdif( + const struct imx_elcdif_data *data, + const struct mxc_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("mxc_elcdif_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c b/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c new file mode 100644 index 000000000000..72010e29d7e6 --- /dev/null +++ b/arch/arm/plat-mxc/devices/platform-imx-spdc-fb.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <asm/sizes.h> +#include <mach/hardware.h> +#include <mach/devices-common.h> + +#define imx_spdc_data_entry_single(soc, size) \ + { \ + .iobase = soc ## _SIPIX_BASE_ADDR, \ + .irq = soc ## _INT_SPDC, \ + .iosize = size, \ + } + +#ifdef CONFIG_SOC_IMX6SL +const struct imx_epdc_data imx6sl_spdc_data __initconst = + imx_spdc_data_entry_single(MX6SL, SZ_16K); +#endif + +struct platform_device *__init imx_add_imx_spdc( + const struct imx_epdc_data *data, + const struct imx_spdc_fb_platform_data *pdata) +{ + struct resource res[] = { + { + .start = data->iobase, + .end = data->iobase + data->iosize - 1, + .flags = IORESOURCE_MEM, + }, { + .start = data->irq, + .end = data->irq, + .flags = IORESOURCE_IRQ, + }, + }; + + return imx_add_platform_device_dmamask("imx_spdc_fb", -1, + res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32)); +} + diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c index 700cf468ea8e..c39f6d7561c6 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c +++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c @@ -56,6 +56,12 @@ const struct imx_mxc_ehci_data imx6q_mxc_ehci_hs_data[] __initconst = { imx_mxc_ehci_data_entry_single(MX6Q, 2, HS2), imx_mxc_ehci_data_entry_single(MX6Q, 3, HS3), }; + +const struct imx_mxc_ehci_data imx6sl_mxc_ehci_hs_data[] __initconst = { + imx_mxc_ehci_data_entry_single(MX6SL, 1, HS1), + imx_mxc_ehci_data_entry_single(MX6SL, 2, HS2), + imx_mxc_ehci_data_entry_single(MX6SL, 3, HS3), +}; #endif /* ifdef CONFIG_SOC_IMX6Q */ struct platform_device *__init imx_add_mxc_ehci( diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index d52f7b6eb039..a31ee9a71940 100755 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -427,7 +427,7 @@ static int set_cpu_freq(int op) { int ret = 0; - if (cpu_is_mx6q() || cpu_is_mx6dl()) + if (cpu_is_mx6()) ret = mx6_set_cpu_freq(op); else ret = mx5_set_cpu_freq(op); @@ -476,7 +476,7 @@ static int start_dvfs(void) /* GPCIRQ=1, select ARM IRQ */ reg |= MXC_GPCCNTR_GPCIRQ_ARM; /* ADU=1, select ARM domain */ - if (!(cpu_is_mx6q() || cpu_is_mx6dl())) + if (!cpu_is_mx6()) reg |= MXC_GPCCNTR_ADU; __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); @@ -509,7 +509,7 @@ static int start_dvfs(void) __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); /* Enable DVFS */ - if (cpu_is_mx6q() || cpu_is_mx6dl()) { + if (cpu_is_mx6()) { unsigned long cpu_wfi = 0; int num_cpus = num_possible_cpus(); reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_EMAC); @@ -947,7 +947,7 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) printk(KERN_ERR "%s: failed to get cpu clock\n", __func__); return PTR_ERR(cpu_clk); } - if (!(cpu_is_mx6q() || cpu_is_mx6dl())) { + if (!cpu_is_mx6()) { dvfs_clk = clk_get(NULL, dvfs_data->clk2_id); if (IS_ERR(dvfs_clk)) { printk(KERN_ERR "%s: failed to get dvfs clock\n", __func__); diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index f84aa75cdbba..82b70d537df9 100755 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c @@ -346,7 +346,7 @@ int mxc_gpio_init(struct mxc_gpio_port *port, int cnt) if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx6q() || - cpu_is_mx6dl()) { + cpu_is_mx6dl() || cpu_is_mx6sl()) { /* setup one handler for each entry */ irq_set_chained_handler(port[i].irq, mx3_gpio_irq_handler); diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 89bc884873f8..4edcaea09b14 100755 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -74,6 +74,8 @@ extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1); extern int mx6_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx6sl_clocks_init(unsigned long ckil, unsigned long osc, + unsigned long ckih1, unsigned long ckih2); extern void imx6_init_fec(struct fec_platform_data fec_data); extern int mxc91231_clocks_init(unsigned long fref); extern int mxc_register_gpios(void); @@ -93,4 +95,5 @@ extern void early_console_setup(unsigned long base, struct clk *clk); extern void mx6_cpu_regulator_init(void); extern int mx6q_sabreauto_init_pfuze100(u32 int_gpio); extern int mx6q_sabresd_init_pfuze100(u32 int_gpio); +extern void imx_print_silicon_rev(const char *cpu, int srev); #endif diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 6fce8c4b8255..eaddb7e3a4f6 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -34,6 +34,7 @@ struct platform_device *__init imx_add_dma(const struct imx_dma_data *data); struct imx_fec_data { resource_size_t iobase; resource_size_t irq; + const char *devid; }; struct platform_device *__init imx_add_fec( const struct imx_fec_data *data, @@ -104,6 +105,20 @@ struct imx_snvs_rtc_data { struct platform_device *__init imx_add_snvs_rtc( const struct imx_snvs_rtc_data *data); +struct imx_caam_jr_data { + resource_size_t offset_jr; + resource_size_t irq_jr; +}; + +struct imx_caam_data { + resource_size_t iobase_caam; + resource_size_t irq_sec_vio; + resource_size_t irq_snvs; + struct imx_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */ +}; + +struct platform_device *__init imx_add_caam( + const struct imx_caam_data *data); #include <mach/imxfb.h> struct imx_imx_fb_data { @@ -453,6 +468,17 @@ struct platform_device *__init imx_add_imx_pxp( const struct imx_pxp_data *data); struct platform_device *__init imx_add_imx_pxp_client(void); +#include <linux/fsl_devices.h> +struct imx_elcdif_data { + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; + +struct platform_device *__init imx_add_imx_elcdif( + const struct imx_elcdif_data *data, + const struct mxc_fb_platform_data *pdata); + #include <mach/epdc.h> struct imx_epdc_data { resource_size_t iobase; @@ -463,6 +489,10 @@ struct platform_device *__init imx_add_imx_epdc( const struct imx_epdc_data *data, const struct imx_epdc_fb_platform_data *pdata); +struct platform_device *__init imx_add_imx_spdc( + const struct imx_epdc_data *data, + const struct imx_spdc_fb_platform_data *pdata); + struct imx_spdif_data { resource_size_t iobase; resource_size_t irq; diff --git a/arch/arm/plat-mxc/include/mach/epdc.h b/arch/arm/plat-mxc/include/mach/epdc.h index 89abcc670dd2..36aac88230c8 100644 --- a/arch/arm/plat-mxc/include/mach/epdc.h +++ b/arch/arm/plat-mxc/include/mach/epdc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -38,4 +38,31 @@ struct imx_epdc_fb_platform_data { void (*disable_pins) (void); }; +struct imx_spdc_panel_init_set { + bool yoe_pol; + bool dual_gate; + u8 resolution; + bool ud; + bool rl; + bool data_filter_n; + bool power_ready; + bool rgbw_mode_enable; + bool hburst_len_en; +}; + +struct imx_spdc_fb_mode { + struct fb_videomode *vmode; + struct imx_spdc_panel_init_set *init_set; + const char *wave_timing; +}; + +struct imx_spdc_fb_platform_data { + struct imx_spdc_fb_mode *spdc_mode; + int num_modes; + int (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); +}; + #endif /* __MACH_EPDC_H_ */ diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h index 48b5d9bcdeef..b56f2fe1ff1b 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -24,23 +24,6 @@ #include <mach/iomux-v3.h> -/* - * various IOMUX alternate output functions (1-7) - */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, - IOMUX_CONFIG_ALT1, - IOMUX_CONFIG_ALT2, - IOMUX_CONFIG_ALT3, - IOMUX_CONFIG_ALT4, - IOMUX_CONFIG_ALT5, - IOMUX_CONFIG_ALT6, - IOMUX_CONFIG_ALT7, - IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */ - } iomux_pin_cfg_t; - -#define NON_MUX_I 0x3FF -#define NON_PAD_I 0x7FF #define MX6Q_CCM_CLK0_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h new file mode 100755 index 000000000000..529ee99c2fa1 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6sl.h @@ -0,0 +1,2968 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Auto Generate file, please don't edit it + * + */ + +#ifndef __MACH_IOMUX_MX6SL_H__ +#define __MACH_IOMUX_MX6SL_H__ + +#include <mach/iomux-v3.h> + +#define MX6SL_HIGH_DRV PAD_CTL_DSE_120ohm +#define MX6SL_DISP_PAD_CLT MX6SL_HIGH_DRV + +#define MX6SL_CCM_CLKO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_USDHC_PAD_CTRL_200MHZ (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6SL_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS | PAD_CTL_ODE) + +#define MX6SL_ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_USB_HSIC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define MX6SL_HP_DET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define MX6SL_LCDIF_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PUE | PAD_CTL_PKE | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define MX6SL_PAD_AUD_MCLK__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x02A4, 0x004C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__PWM4_PWMO \ + IOMUX_PAD(0x02A4, 0x004C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY \ + IOMUX_PAD(0x02A4, 0x004C, 2, 0x06B4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__FEC_MDC \ + IOMUX_PAD(0x02A4, 0x004C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x02A4, 0x004C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__GPIO_1_6 \ + IOMUX_PAD(0x02A4, 0x004C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x02A4, 0x004C, 6, 0x07F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_MCLK__TPSMP_HDATA_27 \ + IOMUX_PAD(0x02A4, 0x004C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXC__AUDMUX_AUD3_RXC \ + IOMUX_PAD(0x02A8, 0x0050, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__I2C1_SDA \ + IOMUX_PAD(0x02A8, 0x0050, 1 | IOMUX_CONFIG_SION, 0x0720, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__UART3_TXD \ + IOMUX_PAD(0x02A8, 0x0050, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__UART3_RXD \ + IOMUX_PAD(0x02A8, 0x0050, 2, 0x080C, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__FEC_TX_CLK \ + IOMUX_PAD(0x02A8, 0x0050, 3, 0x070C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__I2C3_SDA \ + IOMUX_PAD(0x02A8, 0x0050, 4 | IOMUX_CONFIG_SION, 0x0730, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__GPIO_1_1 \ + IOMUX_PAD(0x02A8, 0x0050, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__ECSPI3_SS1 \ + IOMUX_PAD(0x02A8, 0x0050, 6, 0x06C4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXC__PL301_SIM_MX6SL_PER1_HREADYOUT \ + IOMUX_PAD(0x02A8, 0x0050, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXD__AUDMUX_AUD3_RXD \ + IOMUX_PAD(0x02AC, 0x0054, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__ECSPI3_MOSI \ + IOMUX_PAD(0x02AC, 0x0054, 1, 0x06BC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__UART4_TXD \ + IOMUX_PAD(0x02AC, 0x0054, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__UART4_RXD \ + IOMUX_PAD(0x02AC, 0x0054, 2, 0x0814, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__FEC_RX_ER \ + IOMUX_PAD(0x02AC, 0x0054, 3, 0x0708, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__USDHC1_LCTL \ + IOMUX_PAD(0x02AC, 0x0054, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__GPIO_1_2 \ + IOMUX_PAD(0x02AC, 0x0054, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__SRC_INT_BOOT \ + IOMUX_PAD(0x02AC, 0x0054, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXD__PL301_SIM_MX6SL_PER1_HRESP \ + IOMUX_PAD(0x02AC, 0x0054, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_RXFS__AUDMUX_AUD3_RXFS \ + IOMUX_PAD(0x02B0, 0x0058, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__I2C1_SCL \ + IOMUX_PAD(0x02B0, 0x0058, 1 | IOMUX_CONFIG_SION, 0x071C, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__UART3_TXD \ + IOMUX_PAD(0x02B0, 0x0058, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__UART3_RXD \ + IOMUX_PAD(0x02B0, 0x0058, 2, 0x080C, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__FEC_MDIO \ + IOMUX_PAD(0x02B0, 0x0058, 3, 0x06F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__I2C3_SCL \ + IOMUX_PAD(0x02B0, 0x0058, 4 | IOMUX_CONFIG_SION, 0x072C, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__GPIO_1_0 \ + IOMUX_PAD(0x02B0, 0x0058, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__ECSPI3_SS0 \ + IOMUX_PAD(0x02B0, 0x0058, 6, 0x06C0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_RXFS__PL301_SIM_MX6SL_PER1_HPROT_1 \ + IOMUX_PAD(0x02B0, 0x0058, 7, 0x07EC, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXC__AUDMUX_AUD3_TXC \ + IOMUX_PAD(0x02B4, 0x005C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__ECSPI3_MISO \ + IOMUX_PAD(0x02B4, 0x005C, 1, 0x06B8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__UART4_TXD \ + IOMUX_PAD(0x02B4, 0x005C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__UART4_RXD \ + IOMUX_PAD(0x02B4, 0x005C, 2, 0x0814, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__FEC_RX_DV \ + IOMUX_PAD(0x02B4, 0x005C, 3, 0x0704, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__USDHC2_LCTL \ + IOMUX_PAD(0x02B4, 0x005C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__GPIO_1_3 \ + IOMUX_PAD(0x02B4, 0x005C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__SRC_SYSTEM_RST \ + IOMUX_PAD(0x02B4, 0x005C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXC__TPSMP_HDATA_24 \ + IOMUX_PAD(0x02B4, 0x005C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXD__AUDMUX_AUD3_TXD \ + IOMUX_PAD(0x02B8, 0x0060, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__ECSPI3_SCLK \ + IOMUX_PAD(0x02B8, 0x0060, 1, 0x06B0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__UART4_CTS \ + IOMUX_PAD(0x02B8, 0x0060, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__UART4_RTS \ + IOMUX_PAD(0x02B8, 0x0060, 2, 0x0810, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__FEC_TDATA_0 \ + IOMUX_PAD(0x02B8, 0x0060, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__USDHC4_LCTL \ + IOMUX_PAD(0x02B8, 0x0060, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__GPIO_1_5 \ + IOMUX_PAD(0x02B8, 0x0060, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__ANATOP_ANATOP_TESTI_1 \ + IOMUX_PAD(0x02B8, 0x0060, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXD__TPSMP_HDATA_26 \ + IOMUX_PAD(0x02B8, 0x0060, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_AUD_TXFS__AUDMUX_AUD3_TXFS \ + IOMUX_PAD(0x02BC, 0x0064, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__PWM3_PWMO \ + IOMUX_PAD(0x02BC, 0x0064, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__UART4_CTS \ + IOMUX_PAD(0x02BC, 0x0064, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__UART4_RTS \ + IOMUX_PAD(0x02BC, 0x0064, 2, 0x0810, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__FEC_RDATA_1 \ + IOMUX_PAD(0x02BC, 0x0064, 3, 0x06FC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__USDHC3_LCTL \ + IOMUX_PAD(0x02BC, 0x0064, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__GPIO_1_4 \ + IOMUX_PAD(0x02BC, 0x0064, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__ANATOP_ANATOP_TESTI_0 \ + IOMUX_PAD(0x02BC, 0x0064, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_AUD_TXFS__TPSMP_HDATA_25 \ + IOMUX_PAD(0x02BC, 0x0064, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_BOOT_MODE0__SRC_BOOT_MODE_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_BOOT_MODE1__SRC_BOOT_MODE_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A0__MMDC_DRAM_A_0 \ + IOMUX_PAD(0x02C0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A1__MMDC_DRAM_A_1 \ + IOMUX_PAD(0x02C4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A10__MMDC_DRAM_A_10 \ + IOMUX_PAD(0x02C8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A11__MMDC_DRAM_A_11 \ + IOMUX_PAD(0x02CC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A12__MMDC_DRAM_A_12 \ + IOMUX_PAD(0x02D0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A13__MMDC_DRAM_A_13 \ + IOMUX_PAD(0x02D4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A14__MMDC_DRAM_A_14 \ + IOMUX_PAD(0x02D8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A15__MMDC_DRAM_A_15 \ + IOMUX_PAD(0x02DC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A2__MMDC_DRAM_A_2 \ + IOMUX_PAD(0x02E0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A3__MMDC_DRAM_A_3 \ + IOMUX_PAD(0x02E4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A4__MMDC_DRAM_A_4 \ + IOMUX_PAD(0x02E8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A5__MMDC_DRAM_A_5 \ + IOMUX_PAD(0x02EC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A6__MMDC_DRAM_A_6 \ + IOMUX_PAD(0x02F0, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A7__MMDC_DRAM_A_7 \ + IOMUX_PAD(0x02F4, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A8__MMDC_DRAM_A_8 \ + IOMUX_PAD(0x02F8, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_A9__MMDC_DRAM_A_9 \ + IOMUX_PAD(0x02FC, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CAS__MMDC_DRAM_CAS \ + IOMUX_PAD(0x0300, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CS0__MMDC_DRAM_CS_0 \ + IOMUX_PAD(0x0304, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_CS1__MMDC_DRAM_CS_1 \ + IOMUX_PAD(0x0308, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D0__MMDC_DRAM_D_0 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D1__MMDC_DRAM_D_1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D10__MMDC_DRAM_D_10 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D11__MMDC_DRAM_D_11 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D12__MMDC_DRAM_D_12 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D13__MMDC_DRAM_D_13 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D14__MMDC_DRAM_D_14 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D15__MMDC_DRAM_D_15 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D16__MMDC_DRAM_D_16 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D17__MMDC_DRAM_D_17 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D18__MMDC_DRAM_D_18 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D19__MMDC_DRAM_D_19 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D2__MMDC_DRAM_D_2 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D20__MMDC_DRAM_D_20 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D21__MMDC_DRAM_D_21 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D22__MMDC_DRAM_D_22 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D23__MMDC_DRAM_D_23 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D24__MMDC_DRAM_D_24 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D25__MMDC_DRAM_D_25 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D26__MMDC_DRAM_D_26 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D27__MMDC_DRAM_D_27 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D28__MMDC_DRAM_D_28 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D29__MMDC_DRAM_D_29 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D3__MMDC_DRAM_D_3 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D30__MMDC_DRAM_D_30 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D31__MMDC_DRAM_D_31 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D4__MMDC_DRAM_D_4 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D5__MMDC_DRAM_D_5 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D6__MMDC_DRAM_D_6 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D7__MMDC_DRAM_D_7 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D8__MMDC_DRAM_D_8 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_D9__MMDC_DRAM_D_9 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM0__MMDC_DRAM_DQM_0 \ + IOMUX_PAD(0x030C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM1__MMDC_DRAM_DQM_1 \ + IOMUX_PAD(0x0310, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM2__MMDC_DRAM_DQM_2 \ + IOMUX_PAD(0x0314, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_DQM3__MMDC_DRAM_DQM_3 \ + IOMUX_PAD(0x0318, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_RAS__MMDC_DRAM_RAS \ + IOMUX_PAD(0x031C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_RESET__MMDC_DRAM_RESET \ + IOMUX_PAD(0x0320, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA0__MMDC_DRAM_SDBA_0 \ + IOMUX_PAD(0x0324, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA1__MMDC_DRAM_SDBA_1 \ + IOMUX_PAD(0x0328, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDBA2__MMDC_DRAM_SDBA_2 \ + IOMUX_PAD(0x032C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCKE0__MMDC_DRAM_SDCKE_0 \ + IOMUX_PAD(0x0330, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCKE1__MMDC_DRAM_SDCKE_1 \ + IOMUX_PAD(0x0334, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDCLK_0__MMDC_DRAM_SDCLK0 \ + IOMUX_PAD(0x0338, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDODT0__MMDC_DRAM_ODT_0 \ + IOMUX_PAD(0x033C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDODT1__MMDC_DRAM_ODT_1 \ + IOMUX_PAD(0x0340, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS0__MMDC_DRAM_SDQS_0 \ + IOMUX_PAD(0x0344, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS1__MMDC_DRAM_SDQS_1 \ + IOMUX_PAD(0x0348, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS2__MMDC_DRAM_SDQS_2 \ + IOMUX_PAD(0x034C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDQS3__MMDC_DRAM_SDQS_3 \ + IOMUX_PAD(0x0350, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_DRAM_SDWE__MMDC_DRAM_SDWE \ + IOMUX_PAD(0x0354, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO \ + IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0358, 0x0068, 1, 0x05F8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__UART5_CTS \ + IOMUX_PAD(0x0358, 0x0068, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__UART5_RTS \ + IOMUX_PAD(0x0358, 0x0068, 2, 0x0818, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__EPDC_BDR_0 \ + IOMUX_PAD(0x0358, 0x0068, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__USDHC2_WP \ + IOMUX_PAD(0x0358, 0x0068, 4, 0x0834, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__GPIO_4_10 \ + IOMUX_PAD(0x0358, 0x0068, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__CCM_PLL3_BYP \ + IOMUX_PAD(0x0358, 0x0068, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MISO__MMDC_MMDC_DEBUG_40 \ + IOMUX_PAD(0x0358, 0x0068, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI \ + IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x035C, 0x006C, 1, 0x05F4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__UART5_TXD \ + IOMUX_PAD(0x035C, 0x006C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__UART5_RXD \ + IOMUX_PAD(0x035C, 0x006C, 2, 0x081C, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__EPDC_VCOM_1 \ + IOMUX_PAD(0x035C, 0x006C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__USDHC2_VSELECT \ + IOMUX_PAD(0x035C, 0x006C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__GPIO_4_9 \ + IOMUX_PAD(0x035C, 0x006C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__CCM_PLL2_BYP \ + IOMUX_PAD(0x035C, 0x006C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_MOSI__MMDC_MMDC_DEBUG_49 \ + IOMUX_PAD(0x035C, 0x006C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK \ + IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0360, 0x0070, 1, 0x05E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__UART5_TXD \ + IOMUX_PAD(0x0360, 0x0070, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__UART5_RXD \ + IOMUX_PAD(0x0360, 0x0070, 2, 0x081C, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__EPDC_VCOM_0 \ + IOMUX_PAD(0x0360, 0x0070, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__USDHC2_RST \ + IOMUX_PAD(0x0360, 0x0070, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__GPIO_4_8 \ + IOMUX_PAD(0x0360, 0x0070, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__USB_USBOTG2_OC \ + IOMUX_PAD(0x0360, 0x0070, 6, 0x0820, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SCLK__TPSMP_HDATA_18 \ + IOMUX_PAD(0x0360, 0x0070, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI1_SS0__ECSPI1_SS0 \ + IOMUX_PAD(0x0364, 0x0074, 0, 0x068C, 0, MX6SL_ECSPI_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0364, 0x0074, 1, 0x05E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__UART5_CTS \ + IOMUX_PAD(0x0364, 0x0074, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__UART5_RTS \ + IOMUX_PAD(0x0364, 0x0074, 2, 0x0818, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__EPDC_BDR_1 \ + IOMUX_PAD(0x0364, 0x0074, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__USDHC2_CD \ + IOMUX_PAD(0x0364, 0x0074, 4, 0x0830, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__GPIO_4_11 \ + IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__USB_USBOTG2_PWR \ + IOMUX_PAD(0x0364, 0x0074, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI1_SS0__PL301_SIM_MX6SL_PER1_HADDR_23 \ + IOMUX_PAD(0x0364, 0x0074, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_MISO__GPIO_4_14 \ + IOMUX_PAD(0x0368, 0x0078, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__USB_USBOTG1_OC \ + IOMUX_PAD(0x0368, 0x0078, 6, 0x0824, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__TPSMP_HDATA_23 \ + IOMUX_PAD(0x0368, 0x0078, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__ECSPI2_MISO \ + IOMUX_PAD(0x0368, 0x0078, 0, 0x06A0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__SDMA_SDMA_EXT_EVENT_0 \ + IOMUX_PAD(0x0368, 0x0078, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__UART3_CTS \ + IOMUX_PAD(0x0368, 0x0078, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__UART3_RTS \ + IOMUX_PAD(0x0368, 0x0078, 2, 0x0808, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__CSI_MCLK \ + IOMUX_PAD(0x0368, 0x0078, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MISO__USDHC1_WP \ + IOMUX_PAD(0x0368, 0x0078, 4, 0x082C, 0, MX6SL_USDHC_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_MOSI__ECSPI2_MOSI \ + IOMUX_PAD(0x036C, 0x007C, 0, 0x06A4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__SDMA_SDMA_EXT_EVENT_1 \ + IOMUX_PAD(0x036C, 0x007C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__UART3_TXD \ + IOMUX_PAD(0x036C, 0x007C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__UART3_RXD \ + IOMUX_PAD(0x036C, 0x007C, 2, 0x080C, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__CSI_HSYNC \ + IOMUX_PAD(0x036C, 0x007C, 3, 0x0670, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__USDHC1_VSELECT \ + IOMUX_PAD(0x036C, 0x007C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__GPIO_4_13 \ + IOMUX_PAD(0x036C, 0x007C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__ANATOP_ANATOP_TESTO_1 \ + IOMUX_PAD(0x036C, 0x007C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_MOSI__TPSMP_HDATA_22 \ + IOMUX_PAD(0x036C, 0x007C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_SCLK__ECSPI2_SCLK \ + IOMUX_PAD(0x0370, 0x0080, 0, 0x069C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x0370, 0x0080, 1, 0x07F4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__UART3_TXD \ + IOMUX_PAD(0x0370, 0x0080, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__UART3_RXD \ + IOMUX_PAD(0x0370, 0x0080, 2, 0x080C, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__CSI_PIXCLK \ + IOMUX_PAD(0x0370, 0x0080, 3, 0x0674, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__USDHC1_RST \ + IOMUX_PAD(0x0370, 0x0080, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__GPIO_4_12 \ + IOMUX_PAD(0x0370, 0x0080, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__USB_USBOTG2_OC \ + IOMUX_PAD(0x0370, 0x0080, 6, 0x0820, 1, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SCLK__TPSMP_HDATA_21 \ + IOMUX_PAD(0x0370, 0x0080, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_ECSPI2_SS0__ECSPI2_SS0 \ + IOMUX_PAD(0x0374, 0x0084, 0, 0x06A8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__ECSPI1_SS3 \ + IOMUX_PAD(0x0374, 0x0084, 1, 0x0698, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__UART3_CTS \ + IOMUX_PAD(0x0374, 0x0084, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__UART3_RTS \ + IOMUX_PAD(0x0374, 0x0084, 2, 0x0808, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__CSI_VSYNC \ + IOMUX_PAD(0x0374, 0x0084, 3, 0x0678, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__USDHC1_CD \ + IOMUX_PAD(0x0374, 0x0084, 4, 0x0828, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__GPIO_4_15 \ + IOMUX_PAD(0x0374, 0x0084, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0374, 0x0084, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_ECSPI2_SS0__PL301_SIM_MX6SL_PER1_HADDR_24 \ + IOMUX_PAD(0x0374, 0x0084, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_BDR0__EPDC_BDR_0 \ + IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__USDHC4_CLK \ + IOMUX_PAD(0x0378, 0x0088, 1, 0x0850, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__UART3_CTS \ + IOMUX_PAD(0x0378, 0x0088, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__UART3_RTS \ + IOMUX_PAD(0x0378, 0x0088, 2, 0x0808, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__WEIM_WEIM_A_26 \ + IOMUX_PAD(0x0378, 0x0088, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__TCON_RL \ + IOMUX_PAD(0x0378, 0x0088, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__GPIO_2_5 \ + IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__EPDC_SDCE_7 \ + IOMUX_PAD(0x0378, 0x0088, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR0__MMDC_MMDC_DEBUG_9 \ + IOMUX_PAD(0x0378, 0x0088, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_BDR1__EPDC_BDR_1 \ + IOMUX_PAD(0x037C, 0x008C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__USDHC4_CMD \ + IOMUX_PAD(0x037C, 0x008C, 1, 0x0858, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__UART3_CTS \ + IOMUX_PAD(0x037C, 0x008C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__UART3_RTS \ + IOMUX_PAD(0x037C, 0x008C, 2, 0x0808, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__WEIM_WEIM_CRE \ + IOMUX_PAD(0x037C, 0x008C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__TCON_UD \ + IOMUX_PAD(0x037C, 0x008C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__GPIO_2_6 \ + IOMUX_PAD(0x037C, 0x008C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__EPDC_SDCE_8 \ + IOMUX_PAD(0x037C, 0x008C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_BDR1__MMDC_MMDC_DEBUG_8 \ + IOMUX_PAD(0x037C, 0x008C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D0__EPDC_SDDO_0 \ + IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__ECSPI4_MOSI \ + IOMUX_PAD(0x0380, 0x0090, 1, 0x06D8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__LCDIF_DAT_24 \ + IOMUX_PAD(0x0380, 0x0090, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__CSI_D_0 \ + IOMUX_PAD(0x0380, 0x0090, 3, 0x0630, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__TCON_E_DATA_0 \ + IOMUX_PAD(0x0380, 0x0090, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__GPIO_1_7 \ + IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__ANATOP_USBPHY1_TSTI_TX_HS_MODE \ + IOMUX_PAD(0x0380, 0x0090, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D0__OBSERVE_MUX_OUT_0 \ + IOMUX_PAD(0x0380, 0x0090, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D1__EPDC_SDDO_1 \ + IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__ECSPI4_MISO \ + IOMUX_PAD(0x0384, 0x0094, 1, 0x06D4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__LCDIF_DAT_25 \ + IOMUX_PAD(0x0384, 0x0094, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__CSI_D_1 \ + IOMUX_PAD(0x0384, 0x0094, 3, 0x0634, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__TCON_E_DATA_1 \ + IOMUX_PAD(0x0384, 0x0094, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__GPIO_1_8 \ + IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__ANATOP_USBPHY1_TSTI_TX_LS_MODE \ + IOMUX_PAD(0x0384, 0x0094, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D1__OBSERVE_MUX_OUT_1 \ + IOMUX_PAD(0x0384, 0x0094, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D10__EPDC_SDDO_10 \ + IOMUX_PAD(0x0388, 0x0098, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__ECSPI3_SS0 \ + IOMUX_PAD(0x0388, 0x0098, 1, 0x06C0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__EPDC_PWRCTRL_2 \ + IOMUX_PAD(0x0388, 0x0098, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__WEIM_WEIM_A_18 \ + IOMUX_PAD(0x0388, 0x0098, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__TCON_E_DATA_10 \ + IOMUX_PAD(0x0388, 0x0098, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__GPIO_1_17 \ + IOMUX_PAD(0x0388, 0x0098, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__USDHC4_WP \ + IOMUX_PAD(0x0388, 0x0098, 6, 0x087C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D10__MMDC_MMDC_DEBUG_29 \ + IOMUX_PAD(0x0388, 0x0098, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D11__EPDC_SDDO_11 \ + IOMUX_PAD(0x038C, 0x009C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__ECSPI3_SCLK \ + IOMUX_PAD(0x038C, 0x009C, 1, 0x06B0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__EPDC_PWRCTRL_3 \ + IOMUX_PAD(0x038C, 0x009C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__WEIM_WEIM_A_19 \ + IOMUX_PAD(0x038C, 0x009C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__TCON_E_DATA_11 \ + IOMUX_PAD(0x038C, 0x009C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__GPIO_1_18 \ + IOMUX_PAD(0x038C, 0x009C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__USDHC4_CD \ + IOMUX_PAD(0x038C, 0x009C, 6, 0x0854, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D11__MMDC_MMDC_DEBUG_28 \ + IOMUX_PAD(0x038C, 0x009C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D12__EPDC_SDDO_12 \ + IOMUX_PAD(0x0390, 0x00A0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__UART2_TXD \ + IOMUX_PAD(0x0390, 0x00A0, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__UART2_RXD \ + IOMUX_PAD(0x0390, 0x00A0, 1, 0x0804, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__EPDC_PWRCOM \ + IOMUX_PAD(0x0390, 0x00A0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__WEIM_WEIM_A_20 \ + IOMUX_PAD(0x0390, 0x00A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__TCON_E_DATA_12 \ + IOMUX_PAD(0x0390, 0x00A0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__GPIO_1_19 \ + IOMUX_PAD(0x0390, 0x00A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__ECSPI3_SS1 \ + IOMUX_PAD(0x0390, 0x00A0, 6, 0x06C4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D12__MMDC_MMDC_DEBUG_27 \ + IOMUX_PAD(0x0390, 0x00A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D13__EPDC_SDDO_13 \ + IOMUX_PAD(0x0394, 0x00A4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__UART2_TXD \ + IOMUX_PAD(0x0394, 0x00A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__UART2_RXD \ + IOMUX_PAD(0x0394, 0x00A4, 1, 0x0804, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__EPDC_PWRIRQ \ + IOMUX_PAD(0x0394, 0x00A4, 2, 0x06E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__WEIM_WEIM_A_21 \ + IOMUX_PAD(0x0394, 0x00A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__TCON_E_DATA_13 \ + IOMUX_PAD(0x0394, 0x00A4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__GPIO_1_20 \ + IOMUX_PAD(0x0394, 0x00A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__ECSPI3_SS2 \ + IOMUX_PAD(0x0394, 0x00A4, 6, 0x06C8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D13__MMDC_MMDC_DEBUG_26 \ + IOMUX_PAD(0x0394, 0x00A4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D14__EPDC_SDDO_14 \ + IOMUX_PAD(0x0398, 0x00A8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__UART2_CTS \ + IOMUX_PAD(0x0398, 0x00A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__UART2_RTS \ + IOMUX_PAD(0x0398, 0x00A8, 1, 0x0800, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__EPDC_PWRSTAT \ + IOMUX_PAD(0x0398, 0x00A8, 2, 0x06EC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__WEIM_WEIM_A_22 \ + IOMUX_PAD(0x0398, 0x00A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__TCON_E_DATA_14 \ + IOMUX_PAD(0x0398, 0x00A8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__GPIO_1_21 \ + IOMUX_PAD(0x0398, 0x00A8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__ECSPI3_SS3 \ + IOMUX_PAD(0x0398, 0x00A8, 6, 0x06CC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D14__MMDC_MMDC_DEBUG_25 \ + IOMUX_PAD(0x0398, 0x00A8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D15__EPDC_SDDO_15 \ + IOMUX_PAD(0x039C, 0x00AC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__UART2_CTS \ + IOMUX_PAD(0x039C, 0x00AC, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__UART2_RTS \ + IOMUX_PAD(0x039C, 0x00AC, 1, 0x0800, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__EPDC_PWRWAKE \ + IOMUX_PAD(0x039C, 0x00AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__WEIM_WEIM_A_23 \ + IOMUX_PAD(0x039C, 0x00AC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__TCON_E_DATA_15 \ + IOMUX_PAD(0x039C, 0x00AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__GPIO_1_22 \ + IOMUX_PAD(0x039C, 0x00AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__ECSPI3_RDY \ + IOMUX_PAD(0x039C, 0x00AC, 6, 0x06B4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D15__MMDC_MMDC_DEBUG_24 \ + IOMUX_PAD(0x039C, 0x00AC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D2__EPDC_SDDO_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__ECSPI4_SS0 \ + IOMUX_PAD(0x03A0, 0x00B0, 1, 0x06DC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__LCDIF_DAT_26 \ + IOMUX_PAD(0x03A0, 0x00B0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__CSI_D_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 3, 0x0638, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__TCON_E_DATA_2 \ + IOMUX_PAD(0x03A0, 0x00B0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__GPIO_1_9 \ + IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__ANATOP_USBPHY1_TSTI_TX_DN \ + IOMUX_PAD(0x03A0, 0x00B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D2__TPSMP_HDATA_28 \ + IOMUX_PAD(0x03A0, 0x00B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D3__EPDC_SDDO_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__ECSPI4_SCLK \ + IOMUX_PAD(0x03A4, 0x00B4, 1, 0x06D0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__LCDIF_DAT_27 \ + IOMUX_PAD(0x03A4, 0x00B4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__CSI_D_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 3, 0x063C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__TCON_E_DATA_3 \ + IOMUX_PAD(0x03A4, 0x00B4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__GPIO_1_10 \ + IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__ANATOP_USBPHY1_TSTI_TX_DP \ + IOMUX_PAD(0x03A4, 0x00B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D3__TPSMP_HDATA_29 \ + IOMUX_PAD(0x03A4, 0x00B4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D4__EPDC_SDDO_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__ECSPI4_SS1 \ + IOMUX_PAD(0x03A8, 0x00B8, 1, 0x06E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__LCDIF_DAT_28 \ + IOMUX_PAD(0x03A8, 0x00B8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__CSI_D_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 3, 0x0640, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__TCON_E_DATA_4 \ + IOMUX_PAD(0x03A8, 0x00B8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__GPIO_1_11 \ + IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__ANATOP_USBPHY1_TSTI_TX_EN \ + IOMUX_PAD(0x03A8, 0x00B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D4__TPSMP_HDATA_30 \ + IOMUX_PAD(0x03A8, 0x00B8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D5__EPDC_SDDO_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__ECSPI4_SS2 \ + IOMUX_PAD(0x03AC, 0x00BC, 1, 0x06E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__LCDIF_DAT_29 \ + IOMUX_PAD(0x03AC, 0x00BC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__CSI_D_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 3, 0x0644, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__TCON_E_DATA_5 \ + IOMUX_PAD(0x03AC, 0x00BC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__GPIO_1_12 \ + IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__ANATOP_USBPHY1_TSTI_TX_HIZ \ + IOMUX_PAD(0x03AC, 0x00BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D5__TPSMP_HDATA_31 \ + IOMUX_PAD(0x03AC, 0x00BC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D6__EPDC_SDDO_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__ECSPI4_SS3 \ + IOMUX_PAD(0x03B0, 0x00C0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__LCDIF_DAT_30 \ + IOMUX_PAD(0x03B0, 0x00C0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__CSI_D_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 3, 0x0648, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__TCON_E_DATA_6 \ + IOMUX_PAD(0x03B0, 0x00C0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__GPIO_1_13 \ + IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__ANATOP_USBPHY2_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x03B0, 0x00C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D6__TPSMP_HDATA_20 \ + IOMUX_PAD(0x03B0, 0x00C0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D7__EPDC_SDDO_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__ECSPI4_RDY \ + IOMUX_PAD(0x03B4, 0x00C4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__LCDIF_DAT_31 \ + IOMUX_PAD(0x03B4, 0x00C4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__CSI_D_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 3, 0x064C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__TCON_E_DATA_7 \ + IOMUX_PAD(0x03B4, 0x00C4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__GPIO_1_14 \ + IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__ANATOP_USBPHY2_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x03B4, 0x00C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D7__MMDC_MMDC_DEBUG_32 \ + IOMUX_PAD(0x03B4, 0x00C4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D8__EPDC_SDDO_8 \ + IOMUX_PAD(0x03B8, 0x00C8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__ECSPI3_MOSI \ + IOMUX_PAD(0x03B8, 0x00C8, 1, 0x06BC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__EPDC_PWRCTRL_0 \ + IOMUX_PAD(0x03B8, 0x00C8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__WEIM_WEIM_A_16 \ + IOMUX_PAD(0x03B8, 0x00C8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__TCON_E_DATA_8 \ + IOMUX_PAD(0x03B8, 0x00C8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__GPIO_1_15 \ + IOMUX_PAD(0x03B8, 0x00C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__USDHC4_RST \ + IOMUX_PAD(0x03B8, 0x00C8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D8__MMDC_MMDC_DEBUG_31 \ + IOMUX_PAD(0x03B8, 0x00C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_D9__EPDC_SDDO_9 \ + IOMUX_PAD(0x03BC, 0x00CC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__ECSPI3_MISO \ + IOMUX_PAD(0x03BC, 0x00CC, 1, 0x06B8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__EPDC_PWRCTRL_1 \ + IOMUX_PAD(0x03BC, 0x00CC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__WEIM_WEIM_A_17 \ + IOMUX_PAD(0x03BC, 0x00CC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__TCON_E_DATA_9 \ + IOMUX_PAD(0x03BC, 0x00CC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__GPIO_1_16 \ + IOMUX_PAD(0x03BC, 0x00CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__USDHC4_VSELECT \ + IOMUX_PAD(0x03BC, 0x00CC, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_D9__MMDC_MMDC_DEBUG_30 \ + IOMUX_PAD(0x03BC, 0x00CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK \ + IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__ECSPI2_SS2 \ + IOMUX_PAD(0x03C0, 0x00D0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKR \ + IOMUX_PAD(0x03C0, 0x00D0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK \ + IOMUX_PAD(0x03C0, 0x00D0, 3, 0x0674, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__TCON_YCKL \ + IOMUX_PAD(0x03C0, 0x00D0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__GPIO_1_31 \ + IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__USDHC2_RST \ + IOMUX_PAD(0x03C0, 0x00D0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDCLK__MMDC_MMDC_DEBUG_15 \ + IOMUX_PAD(0x03C0, 0x00D0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDOE__EPDC_GDOE \ + IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__ECSPI2_SS3 \ + IOMUX_PAD(0x03C4, 0x00D4, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__TCON_YOER \ + IOMUX_PAD(0x03C4, 0x00D4, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__CSI_HSYNC \ + IOMUX_PAD(0x03C4, 0x00D4, 3, 0x0670, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__TCON_YOEL \ + IOMUX_PAD(0x03C4, 0x00D4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__GPIO_2_0 \ + IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__USDHC2_VSELECT \ + IOMUX_PAD(0x03C4, 0x00D4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDOE__MMDC_MMDC_DEBUG_14 \ + IOMUX_PAD(0x03C4, 0x00D4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDRL__EPDC_GDRL \ + IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__ECSPI2_RDY \ + IOMUX_PAD(0x03C8, 0x00D8, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUR \ + IOMUX_PAD(0x03C8, 0x00D8, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__CSI_MCLK \ + IOMUX_PAD(0x03C8, 0x00D8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__TCON_YDIOUL \ + IOMUX_PAD(0x03C8, 0x00D8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__GPIO_2_1 \ + IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__USDHC2_WP \ + IOMUX_PAD(0x03C8, 0x00D8, 6, 0x0834, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDRL__MMDC_MMDC_DEBUG_13 \ + IOMUX_PAD(0x03C8, 0x00D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_GDSP__EPDC_GDSP \ + IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__PWM4_PWMO \ + IOMUX_PAD(0x03CC, 0x00DC, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODR \ + IOMUX_PAD(0x03CC, 0x00DC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__CSI_VSYNC \ + IOMUX_PAD(0x03CC, 0x00DC, 3, 0x0678, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__TCON_YDIODL \ + IOMUX_PAD(0x03CC, 0x00DC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__GPIO_2_2 \ + IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__USDHC2_CD \ + IOMUX_PAD(0x03CC, 0x00DC, 6, 0x0830, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_GDSP__MMDC_MMDC_DEBUG_12 \ + IOMUX_PAD(0x03CC, 0x00DC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCOM__EPDC_PWRCOM \ + IOMUX_PAD(0x03D0, 0x00E0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__USDHC4_DAT0 \ + IOMUX_PAD(0x03D0, 0x00E0, 1, 0x085C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__LCDIF_DAT_20 \ + IOMUX_PAD(0x03D0, 0x00E0, 2, 0x07C8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__WEIM_WEIM_BCLK \ + IOMUX_PAD(0x03D0, 0x00E0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__GPIO_2_11 \ + IOMUX_PAD(0x03D0, 0x00E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__USDHC3_RST \ + IOMUX_PAD(0x03D0, 0x00E0, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCOM__MMDC_MMDC_DEBUG_3 \ + IOMUX_PAD(0x03D0, 0x00E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL_0 \ + IOMUX_PAD(0x03D4, 0x00E4, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x03D4, 0x00E4, 1, 0x0604, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__LCDIF_DAT_16 \ + IOMUX_PAD(0x03D4, 0x00E4, 2, 0x07B8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__WEIM_WEIM_RW \ + IOMUX_PAD(0x03D4, 0x00E4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__TCON_YCKL \ + IOMUX_PAD(0x03D4, 0x00E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7 \ + IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__USDHC4_RST \ + IOMUX_PAD(0x03D4, 0x00E4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL0__MMDC_MMDC_DEBUG_7 \ + IOMUX_PAD(0x03D4, 0x00E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL_1 \ + IOMUX_PAD(0x03D8, 0x00E8, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x03D8, 0x00E8, 1, 0x0610, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__LCDIF_DAT_17 \ + IOMUX_PAD(0x03D8, 0x00E8, 2, 0x07BC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__WEIM_WEIM_OE \ + IOMUX_PAD(0x03D8, 0x00E8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__TCON_YOEL \ + IOMUX_PAD(0x03D8, 0x00E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__GPIO_2_8 \ + IOMUX_PAD(0x03D8, 0x00E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__USDHC4_VSELECT \ + IOMUX_PAD(0x03D8, 0x00E8, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL1__MMDC_MMDC_DEBUG_6 \ + IOMUX_PAD(0x03D8, 0x00E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL_2 \ + IOMUX_PAD(0x03DC, 0x00EC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x03DC, 0x00EC, 1, 0x0600, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__LCDIF_DAT_18 \ + IOMUX_PAD(0x03DC, 0x00EC, 2, 0x07C0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x03DC, 0x00EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__TCON_YDIOUL \ + IOMUX_PAD(0x03DC, 0x00EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__GPIO_2_9 \ + IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__USDHC4_WP \ + IOMUX_PAD(0x03DC, 0x00EC, 6, 0x087C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL2__MMDC_MMDC_DEBUG_5 \ + IOMUX_PAD(0x03DC, 0x00EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRCTRL3__EPDC_PWRCTRL_3 \ + IOMUX_PAD(0x03E0, 0x00F0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x03E0, 0x00F0, 1, 0x060C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__LCDIF_DAT_19 \ + IOMUX_PAD(0x03E0, 0x00F0, 2, 0x07C4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x03E0, 0x00F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__TCON_YDIODL \ + IOMUX_PAD(0x03E0, 0x00F0, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__GPIO_2_10 \ + IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__USDHC4_CD \ + IOMUX_PAD(0x03E0, 0x00F0, 6, 0x0854, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRCTRL3__MMDC_MMDC_DEBUG_4 \ + IOMUX_PAD(0x03E0, 0x00F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRINT__EPDC_PWRIRQ \ + IOMUX_PAD(0x03E4, 0x00F4, 0, 0x06E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__USDHC4_DAT1 \ + IOMUX_PAD(0x03E4, 0x00F4, 1, 0x0860, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__LCDIF_DAT_21 \ + IOMUX_PAD(0x03E4, 0x00F4, 2, 0x07CC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__WEIM_ACLK_FREERUN \ + IOMUX_PAD(0x03E4, 0x00F4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x03E4, 0x00F4, 4, 0x05E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__GPIO_2_12 \ + IOMUX_PAD(0x03E4, 0x00F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__USDHC3_VSELECT \ + IOMUX_PAD(0x03E4, 0x00F4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRINT__MMDC_MMDC_DEBUG_2 \ + IOMUX_PAD(0x03E4, 0x00F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT \ + IOMUX_PAD(0x03E8, 0x00F8, 0, 0x06EC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__USDHC4_DAT2 \ + IOMUX_PAD(0x03E8, 0x00F8, 1, 0x0864, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__LCDIF_DAT_22 \ + IOMUX_PAD(0x03E8, 0x00F8, 2, 0x07D0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x03E8, 0x00F8, 3, 0x0884, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__KITTEN_EVENTI \ + IOMUX_PAD(0x03E8, 0x00F8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13 \ + IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__USDHC3_WP \ + IOMUX_PAD(0x03E8, 0x00F8, 6, 0x084C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRSTAT__MMDC_MMDC_DEBUG_1 \ + IOMUX_PAD(0x03E8, 0x00F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_PWRWAKEUP__EPDC_PWRWAKE \ + IOMUX_PAD(0x03EC, 0x00FC, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC4_DAT3 \ + IOMUX_PAD(0x03EC, 0x00FC, 1, 0x0868, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__LCDIF_DAT_23 \ + IOMUX_PAD(0x03EC, 0x00FC, 2, 0x07D4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x03EC, 0x00FC, 3, 0x0880, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__KITTEN_EVENTO \ + IOMUX_PAD(0x03EC, 0x00FC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14 \ + IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__USDHC3_CD \ + IOMUX_PAD(0x03EC, 0x00FC, 6, 0x0838, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_EPDC_PWRWAKEUP__MMDC_MMDC_DEBUG_0 \ + IOMUX_PAD(0x03EC, 0x00FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0 \ + IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__ECSPI2_SS1 \ + IOMUX_PAD(0x03F0, 0x0100, 1, 0x06AC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__PWM3_PWMO \ + IOMUX_PAD(0x03F0, 0x0100, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__WEIM_WEIM_CS_2 \ + IOMUX_PAD(0x03F0, 0x0100, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__TCON_YCKR \ + IOMUX_PAD(0x03F0, 0x0100, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__GPIO_1_27 \ + IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x03F0, 0x0100, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE0__MMDC_MMDC_DEBUG_19 \ + IOMUX_PAD(0x03F0, 0x0100, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1 \ + IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__WDOG2_WDOG_B \ + IOMUX_PAD(0x03F4, 0x0104, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__PWM4_PWMO \ + IOMUX_PAD(0x03F4, 0x0104, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__WEIM_WEIM_LBA \ + IOMUX_PAD(0x03F4, 0x0104, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__TCON_YOER \ + IOMUX_PAD(0x03F4, 0x0104, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__GPIO_1_28 \ + IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__ANATOP_USBPHY1_TSTO_RX_FS_RXD \ + IOMUX_PAD(0x03F4, 0x0104, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE1__MMDC_MMDC_DEBUG_18 \ + IOMUX_PAD(0x03F4, 0x0104, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2 \ + IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__I2C3_SCL \ + IOMUX_PAD(0x03F8, 0x0108, 1 | IOMUX_CONFIG_SION, 0x072C, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__PWM1_PWMO \ + IOMUX_PAD(0x03F8, 0x0108, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__WEIM_WEIM_EB_0 \ + IOMUX_PAD(0x03F8, 0x0108, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__TCON_YDIOUR \ + IOMUX_PAD(0x03F8, 0x0108, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__GPIO_1_29 \ + IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__ANATOP_USBPHY1_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x03F8, 0x0108, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE2__MMDC_MMDC_DEBUG_17 \ + IOMUX_PAD(0x03F8, 0x0108, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCE3__EPDC_SDCE_3 \ + IOMUX_PAD(0x03FC, 0x010C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__I2C3_SDA \ + IOMUX_PAD(0x03FC, 0x010C, 1 | IOMUX_CONFIG_SION, 0x0730, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__PWM2_PWMO \ + IOMUX_PAD(0x03FC, 0x010C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__WEIM_WEIM_EB_1 \ + IOMUX_PAD(0x03FC, 0x010C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__TCON_YDIODR \ + IOMUX_PAD(0x03FC, 0x010C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__GPIO_1_30 \ + IOMUX_PAD(0x03FC, 0x010C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__ANATOP_USBPHY1_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x03FC, 0x010C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCE3__MMDC_MMDC_DEBUG_16 \ + IOMUX_PAD(0x03FC, 0x010C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK \ + IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__ECSPI2_MOSI \ + IOMUX_PAD(0x0400, 0x0110, 1, 0x06A4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__I2C2_SCL \ + IOMUX_PAD(0x0400, 0x0110, 2 | IOMUX_CONFIG_SION, 0x0724, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__CSI_D_8 \ + IOMUX_PAD(0x0400, 0x0110, 3, 0x0650, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__TCON_CL \ + IOMUX_PAD(0x0400, 0x0110, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__GPIO_1_23 \ + IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__ANATOP_USBPHY2_TSTO_RX_HS_RXD \ + IOMUX_PAD(0x0400, 0x0110, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDCLK__MMDC_MMDC_DEBUG_23 \ + IOMUX_PAD(0x0400, 0x0110, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDLE__EPDC_SDLE \ + IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__ECSPI2_MISO \ + IOMUX_PAD(0x0404, 0x0114, 1, 0x06A0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__I2C2_SDA \ + IOMUX_PAD(0x0404, 0x0114, 2 | IOMUX_CONFIG_SION, 0x0728, 0, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__CSI_D_9 \ + IOMUX_PAD(0x0404, 0x0114, 3, 0x0654, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__TCON_LD \ + IOMUX_PAD(0x0404, 0x0114, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__GPIO_1_24 \ + IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__ANATOP_USBPHY2_TSTO_RX_SQUELCH \ + IOMUX_PAD(0x0404, 0x0114, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDLE__MMDC_MMDC_DEBUG_22 \ + IOMUX_PAD(0x0404, 0x0114, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDOE__EPDC_SDOE \ + IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__ECSPI2_SS0 \ + IOMUX_PAD(0x0408, 0x0118, 1, 0x06A8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOR \ + IOMUX_PAD(0x0408, 0x0118, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__CSI_D_10 \ + IOMUX_PAD(0x0408, 0x0118, 3, 0x0658, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__TCON_XDIOL \ + IOMUX_PAD(0x0408, 0x0118, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__GPIO_1_25 \ + IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV \ + IOMUX_PAD(0x0408, 0x0118, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDOE__MMDC_MMDC_DEBUG_21 \ + IOMUX_PAD(0x0408, 0x0118, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR \ + IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__ECSPI2_SCLK \ + IOMUX_PAD(0x040C, 0x011C, 1, 0x069C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__EPDC_SDCE_4 \ + IOMUX_PAD(0x040C, 0x011C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__CSI_D_11 \ + IOMUX_PAD(0x040C, 0x011C, 3, 0x065C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__TCON_XDIOR \ + IOMUX_PAD(0x040C, 0x011C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__GPIO_1_26 \ + IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__ANATOP_USBPHY1_TSTO_RX_DISCON_DET \ + IOMUX_PAD(0x040C, 0x011C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_SDSHR__MMDC_MMDC_DEBUG_20 \ + IOMUX_PAD(0x040C, 0x011C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_VCOM0__EPDC_VCOM_0 \ + IOMUX_PAD(0x0410, 0x0120, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x0410, 0x0120, 1, 0x0608, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__UART3_TXD \ + IOMUX_PAD(0x0410, 0x0120, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__UART3_RXD \ + IOMUX_PAD(0x0410, 0x0120, 2, 0x080C, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__WEIM_WEIM_A_24 \ + IOMUX_PAD(0x0410, 0x0120, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__TCON_VCOM_0 \ + IOMUX_PAD(0x0410, 0x0120, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__GPIO_2_3 \ + IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__EPDC_SDCE_5 \ + IOMUX_PAD(0x0410, 0x0120, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM0__MMDC_MMDC_DEBUG_11 \ + IOMUX_PAD(0x0410, 0x0120, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_EPDC_VCOM1__EPDC_VCOM_1 \ + IOMUX_PAD(0x0414, 0x0124, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x0414, 0x0124, 1, 0x05FC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__UART3_TXD \ + IOMUX_PAD(0x0414, 0x0124, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__UART3_RXD \ + IOMUX_PAD(0x0414, 0x0124, 2, 0x080C, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__WEIM_WEIM_A_25 \ + IOMUX_PAD(0x0414, 0x0124, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__TCON_VCOM_1 \ + IOMUX_PAD(0x0414, 0x0124, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__GPIO_2_4 \ + IOMUX_PAD(0x0414, 0x0124, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__EPDC_SDCE_6 \ + IOMUX_PAD(0x0414, 0x0124, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_EPDC_VCOM1__MMDC_MMDC_DEBUG_10 \ + IOMUX_PAD(0x0414, 0x0124, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV \ + IOMUX_PAD(0x0418, 0x0128, 0, 0x0704, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__USDHC4_DAT1 \ + IOMUX_PAD(0x0418, 0x0128, 1, 0x0860, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x0418, 0x0128, 2, 0x0624, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO \ + IOMUX_PAD(0x0418, 0x0128, 3, 0x06D4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__GPT_CMPOUT2 \ + IOMUX_PAD(0x0418, 0x0128, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__GPIO_4_25 \ + IOMUX_PAD(0x0418, 0x0128, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__KITTEN_TRACE_31 \ + IOMUX_PAD(0x0418, 0x0128, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_CRS_DV__PL301_SIM_MX6SL_PER1_HADDR_3 \ + IOMUX_PAD(0x0418, 0x0128, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_MDC__FEC_MDC \ + IOMUX_PAD(0x041C, 0x012C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC4_DAT4 \ + IOMUX_PAD(0x041C, 0x012C, 1, 0x086C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x041C, 0x012C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC1_RST \ + IOMUX_PAD(0x041C, 0x012C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__USDHC3_RST \ + IOMUX_PAD(0x041C, 0x012C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__GPIO_4_23 \ + IOMUX_PAD(0x041C, 0x012C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__KITTEN_TRACE_29 \ + IOMUX_PAD(0x041C, 0x012C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDC__PL301_SIM_MX6SL_PER1_HADDR_8 \ + IOMUX_PAD(0x041C, 0x012C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_MDIO__FEC_MDIO \ + IOMUX_PAD(0x0420, 0x0130, 0, 0x06F4, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__USDHC4_CLK \ + IOMUX_PAD(0x0420, 0x0130, 1, 0x0850, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0420, 0x0130, 2, 0x0620, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__ECSPI4_SS0 \ + IOMUX_PAD(0x0420, 0x0130, 3, 0x06DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__GPT_CAPIN1 \ + IOMUX_PAD(0x0420, 0x0130, 4, 0x0710, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__GPIO_4_20 \ + IOMUX_PAD(0x0420, 0x0130, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__KITTEN_TRACE_26 \ + IOMUX_PAD(0x0420, 0x0130, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_MDIO__PL301_SIM_MX6SL_PER1_HADDR_15 \ + IOMUX_PAD(0x0420, 0x0130, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT \ + IOMUX_PAD(0x0424, 0x0134, 0x10, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__USDHC4_RST \ + IOMUX_PAD(0x0424, 0x0134, 1, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__WDOG1_WDOG_B \ + IOMUX_PAD(0x0424, 0x0134, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__PWM4_PWMO \ + IOMUX_PAD(0x0424, 0x0134, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__CCM_PMIC_RDY \ + IOMUX_PAD(0x0424, 0x0134, 4, 0x062C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__GPIO_4_26 \ + IOMUX_PAD(0x0424, 0x0134, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__SPDIF_SPDIF_EXT_CLK \ + IOMUX_PAD(0x0424, 0x0134, 6, 0x07F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_REF_CLK__PL301_SIM_MX6SL_PER1_HADDR_0 \ + IOMUX_PAD(0x0424, 0x0134, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RX_ER__GPIO_4_19 \ + IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, MX6SL_HP_DET_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__KITTEN_TRACE_25 \ + IOMUX_PAD(0x0428, 0x0138, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__PL301_SIM_MX6SL_PER1_HADDR_5 \ + IOMUX_PAD(0x0428, 0x0138, 7, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__FEC_RX_ER \ + IOMUX_PAD(0x0428, 0x0138, 0, 0x0708, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__USDHC4_DAT0 \ + IOMUX_PAD(0x0428, 0x0138, 1, 0x085C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x0428, 0x0138, 2, 0x0614, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__ECSPI4_MOSI \ + IOMUX_PAD(0x0428, 0x0138, 3, 0x06D8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RX_ER__GPT_CMPOUT1 \ + IOMUX_PAD(0x0428, 0x0138, 4, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RXD0__FEC_RDATA_0 \ + IOMUX_PAD(0x042C, 0x013C, 0, 0x06F8, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC4_DAT5 \ + IOMUX_PAD(0x042C, 0x013C, 1, 0x0870, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x042C, 0x013C, 2, 0x05DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC1_VSELECT \ + IOMUX_PAD(0x042C, 0x013C, 3, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__USDHC3_VSELECT \ + IOMUX_PAD(0x042C, 0x013C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__GPIO_4_17 \ + IOMUX_PAD(0x042C, 0x013C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__KITTEN_TRACE_24 \ + IOMUX_PAD(0x042C, 0x013C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD0__PL301_SIM_MX6SL_PER1_HADDR_7 \ + IOMUX_PAD(0x042C, 0x013C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_RXD1__FEC_RDATA_1 \ + IOMUX_PAD(0x0430, 0x0140, 0, 0x06FC, 1, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__USDHC4_DAT2 \ + IOMUX_PAD(0x0430, 0x0140, 1, 0x0864, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x0430, 0x0140, 2, 0x0628, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__ECSPI4_SS1 \ + IOMUX_PAD(0x0430, 0x0140, 3, 0x06E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__GPT_CMPOUT3 \ + IOMUX_PAD(0x0430, 0x0140, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__GPIO_4_18 \ + IOMUX_PAD(0x0430, 0x0140, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__FEC_COL \ + IOMUX_PAD(0x0430, 0x0140, 6, 0x06F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_RXD1__PL301_SIM_MX6SL_PER1_HADDR_9 \ + IOMUX_PAD(0x0430, 0x0140, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TX_CLK__FEC_TX_CLK \ + IOMUX_PAD(0x0434, 0x0144, 0, 0x070C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__USDHC4_CMD \ + IOMUX_PAD(0x0434, 0x0144, 1, 0x0858, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x0434, 0x0144, 2, 0x061C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__ECSPI4_SCLK \ + IOMUX_PAD(0x0434, 0x0144, 3, 0x06D0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__GPT_CAPIN2 \ + IOMUX_PAD(0x0434, 0x0144, 4, 0x0714, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__GPIO_4_21 \ + IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__KITTEN_TRACE_27 \ + IOMUX_PAD(0x0434, 0x0144, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_CLK__PL301_SIM_MX6SL_PER1_HADDR_4 \ + IOMUX_PAD(0x0434, 0x0144, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TX_EN__FEC_TX_EN \ + IOMUX_PAD(0x0438, 0x0148, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC4_DAT6 \ + IOMUX_PAD(0x0438, 0x0148, 1, 0x0874, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__SPDIF_IN1 \ + IOMUX_PAD(0x0438, 0x0148, 2, 0x07F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC1_WP \ + IOMUX_PAD(0x0438, 0x0148, 3, 0x082C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__USDHC3_WP \ + IOMUX_PAD(0x0438, 0x0148, 4, 0x084C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__GPIO_4_22 \ + IOMUX_PAD(0x0438, 0x0148, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__KITTEN_TRACE_28 \ + IOMUX_PAD(0x0438, 0x0148, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TX_EN__PL301_SIM_MX6SL_PER1_HADDR_1 \ + IOMUX_PAD(0x0438, 0x0148, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TXD0__FEC_TDATA_0 \ + IOMUX_PAD(0x043C, 0x014C, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__USDHC4_DAT3 \ + IOMUX_PAD(0x043C, 0x014C, 1, 0x0868, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x043C, 0x014C, 2, 0x0618, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__ECSPI4_SS2 \ + IOMUX_PAD(0x043C, 0x014C, 3, 0x06E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__GPT_CLKIN \ + IOMUX_PAD(0x043C, 0x014C, 4, 0x0718, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__GPIO_4_24 \ + IOMUX_PAD(0x043C, 0x014C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__KITTEN_TRACE_30 \ + IOMUX_PAD(0x043C, 0x014C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD0__PL301_SIM_MX6SL_PER1_HADDR_2 \ + IOMUX_PAD(0x043C, 0x014C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_FEC_TXD1__FEC_TDATA_1 \ + IOMUX_PAD(0x0440, 0x0150, 0, 0x0000, 0, MX6SL_ENET_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC4_DAT7 \ + IOMUX_PAD(0x0440, 0x0150, 1, 0x0878, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__SPDIF_OUT1 \ + IOMUX_PAD(0x0440, 0x0150, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC1_CD \ + IOMUX_PAD(0x0440, 0x0150, 3, 0x0828, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__USDHC3_CD \ + IOMUX_PAD(0x0440, 0x0150, 4, 0x0838, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__GPIO_4_16 \ + IOMUX_PAD(0x0440, 0x0150, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__FEC_RX_CLK \ + IOMUX_PAD(0x0440, 0x0150, 6, 0x0700, 0, NO_PAD_CTRL) +#define MX6SL_PAD_FEC_TXD1__PL301_SIM_MX6SL_PER1_HADDR_6 \ + IOMUX_PAD(0x0440, 0x0150, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_HSIC_DAT__USB_H_DATA \ + IOMUX_PAD(0x0444, 0x0154, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__I2C1_SCL \ + IOMUX_PAD(0x0444, 0x0154, 1 | IOMUX_CONFIG_SION, 0x071C, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__PWM1_PWMO \ + IOMUX_PAD(0x0444, 0x0154, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x0444, 0x0154, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__OSC32K_32K_OUT \ + IOMUX_PAD(0x0444, 0x0154, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_DAT__GPIO_3_19 \ + IOMUX_PAD(0x0444, 0x0154, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE \ + IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__USB_H_STROBE_START \ + IOMUX_PAD(0x0448, 0x0158, 0, 0x0000, 0, MX6SL_USB_HSIC_PAD_CTRL | PAD_CTL_PUS_47K_UP) +#define MX6SL_PAD_HSIC_STROBE__I2C1_SDA \ + IOMUX_PAD(0x0448, 0x0158, 1 | IOMUX_CONFIG_SION, 0x0720, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__PWM2_PWMO \ + IOMUX_PAD(0x0448, 0x0158, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x0448, 0x0158, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_HSIC_STROBE__GPIO_3_20 \ + IOMUX_PAD(0x0448, 0x0158, 5, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C1_SCL__I2C1_SCL \ + IOMUX_PAD(0x044C, 0x015C, 0 | IOMUX_CONFIG_SION, 0x071C, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__UART1_CTS \ + IOMUX_PAD(0x044C, 0x015C, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__UART1_RTS \ + IOMUX_PAD(0x044C, 0x015C, 1, 0x07F8, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__ECSPI3_SS2 \ + IOMUX_PAD(0x044C, 0x015C, 2, 0x06C8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__FEC_RDATA_0 \ + IOMUX_PAD(0x044C, 0x015C, 3, 0x06F8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__USDHC3_RST \ + IOMUX_PAD(0x044C, 0x015C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__GPIO_3_12 \ + IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__ECSPI1_SS1 \ + IOMUX_PAD(0x044C, 0x015C, 6, 0x0690, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SCL__PL301_SIM_MX6SL_PER1_HSIZE_0 \ + IOMUX_PAD(0x044C, 0x015C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C1_SDA__I2C1_SDA \ + IOMUX_PAD(0x0450, 0x0160, 0 | IOMUX_CONFIG_SION, 0x0720, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__UART1_CTS \ + IOMUX_PAD(0x0450, 0x0160, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__UART1_RTS \ + IOMUX_PAD(0x0450, 0x0160, 1, 0x07F8, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__ECSPI3_SS3 \ + IOMUX_PAD(0x0450, 0x0160, 2, 0x06CC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__FEC_TX_EN \ + IOMUX_PAD(0x0450, 0x0160, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__USDHC3_VSELECT \ + IOMUX_PAD(0x0450, 0x0160, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__GPIO_3_13 \ + IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__ECSPI1_SS2 \ + IOMUX_PAD(0x0450, 0x0160, 6, 0x0694, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C1_SDA__PL301_SIM_MX6SL_PER1_HSIZE_1 \ + IOMUX_PAD(0x0450, 0x0160, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C2_SCL__I2C2_SCL \ + IOMUX_PAD(0x0454, 0x0164, 0 | IOMUX_CONFIG_SION, 0x0724, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x0454, 0x0164, 1, 0x05F0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__SPDIF_IN1 \ + IOMUX_PAD(0x0454, 0x0164, 2, 0x07F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__FEC_TDATA_1 \ + IOMUX_PAD(0x0454, 0x0164, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__USDHC3_WP \ + IOMUX_PAD(0x0454, 0x0164, 4, 0x084C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__GPIO_3_14 \ + IOMUX_PAD(0x0454, 0x0164, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__ECSPI1_RDY \ + IOMUX_PAD(0x0454, 0x0164, 6, 0x0680, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SCL__PL301_SIM_MX6SL_PER1_HSIZE_2 \ + IOMUX_PAD(0x0454, 0x0164, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_I2C2_SDA__I2C2_SDA \ + IOMUX_PAD(0x0458, 0x0168, 0 | IOMUX_CONFIG_SION, 0x0728, 1, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x0458, 0x0168, 1, 0x05EC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__SPDIF_OUT1 \ + IOMUX_PAD(0x0458, 0x0168, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__FEC_REF_OUT \ + IOMUX_PAD(0x0458, 0x0168, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__USDHC3_CD \ + IOMUX_PAD(0x0458, 0x0168, 4, 0x0838, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__GPIO_3_15 \ + IOMUX_PAD(0x0458, 0x0168, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__ANATOP_ANATOP_TESTO_0 \ + IOMUX_PAD(0x0458, 0x0168, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_I2C2_SDA__PL301_SIM_MX6SL_PER1_HWRITE \ + IOMUX_PAD(0x0458, 0x0168, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_MOD__SJC_MOD \ + IOMUX_PAD(0x045C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TCK__SJC_TCK \ + IOMUX_PAD(0x0460, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TDI__SJC_TDI \ + IOMUX_PAD(0x0464, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TDO__SJC_TDO \ + IOMUX_PAD(0x0468, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TMS__SJC_TMS \ + IOMUX_PAD(0x046C, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_JTAG_TRSTB__SJC_TRSTB \ + IOMUX_PAD(0x0470, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL0__KPP_COL_0 \ + IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__I2C2_SCL \ + IOMUX_PAD(0x0474, 0x016C, 1 | IOMUX_CONFIG_SION, 0x0724, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__LCDIF_DAT_0 \ + IOMUX_PAD(0x0474, 0x016C, 2, 0x0778, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__WEIM_WEIM_DA_A_0 \ + IOMUX_PAD(0x0474, 0x016C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__USDHC1_CD \ + IOMUX_PAD(0x0474, 0x016C, 4, 0x0828, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__GPIO_3_24 \ + IOMUX_PAD(0x0474, 0x016C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__MSHC_SCLK \ + IOMUX_PAD(0x0474, 0x016C, 6, 0x07E8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL0__TPSMP_HDATA_0 \ + IOMUX_PAD(0x0474, 0x016C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL1__KPP_COL_1 \ + IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__ECSPI4_MOSI \ + IOMUX_PAD(0x0478, 0x0170, 1, 0x06D8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__LCDIF_DAT_2 \ + IOMUX_PAD(0x0478, 0x0170, 2, 0x0780, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__WEIM_WEIM_DA_A_2 \ + IOMUX_PAD(0x0478, 0x0170, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__USDHC3_DAT4 \ + IOMUX_PAD(0x0478, 0x0170, 4, 0x083C, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__GPIO_3_26 \ + IOMUX_PAD(0x0478, 0x0170, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__MSHC_DATA_0 \ + IOMUX_PAD(0x0478, 0x0170, 6, 0x07D8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL1__TPSMP_HDATA_2 \ + IOMUX_PAD(0x0478, 0x0170, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL2__KPP_COL_2 \ + IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__ECSPI4_SS0 \ + IOMUX_PAD(0x047C, 0x0174, 1, 0x06DC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__LCDIF_DAT_4 \ + IOMUX_PAD(0x047C, 0x0174, 2, 0x0788, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__WEIM_WEIM_DA_A_4 \ + IOMUX_PAD(0x047C, 0x0174, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__USDHC3_DAT6 \ + IOMUX_PAD(0x047C, 0x0174, 4, 0x0844, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__GPIO_3_28 \ + IOMUX_PAD(0x047C, 0x0174, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__MSHC_DATA_2 \ + IOMUX_PAD(0x047C, 0x0174, 6, 0x07E0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL2__TPSMP_HDATA_4 \ + IOMUX_PAD(0x047C, 0x0174, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL3__KPP_COL_3 \ + IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__AUDMUX_AUD6_RXFS \ + IOMUX_PAD(0x0480, 0x0178, 1, 0x0620, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__LCDIF_DAT_6 \ + IOMUX_PAD(0x0480, 0x0178, 2, 0x0790, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__WEIM_WEIM_DA_A_6 \ + IOMUX_PAD(0x0480, 0x0178, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__USDHC4_DAT6 \ + IOMUX_PAD(0x0480, 0x0178, 4, 0x0874, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__GPIO_3_30 \ + IOMUX_PAD(0x0480, 0x0178, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__USDHC1_RST \ + IOMUX_PAD(0x0480, 0x0178, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL3__TPSMP_HDATA_6 \ + IOMUX_PAD(0x0480, 0x0178, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL4__KPP_COL_4 \ + IOMUX_PAD(0x0484, 0x017C, 0, 0x0744, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__AUDMUX_AUD6_RXD \ + IOMUX_PAD(0x0484, 0x017C, 1, 0x0614, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__LCDIF_DAT_8 \ + IOMUX_PAD(0x0484, 0x017C, 2, 0x0798, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__WEIM_WEIM_DA_A_8 \ + IOMUX_PAD(0x0484, 0x017C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__USDHC4_CLK \ + IOMUX_PAD(0x0484, 0x017C, 4, 0x0850, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__GPIO_4_0 \ + IOMUX_PAD(0x0484, 0x017C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL4__TPSMP_HDATA_8 \ + IOMUX_PAD(0x0484, 0x017C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL5__KPP_COL_5 \ + IOMUX_PAD(0x0488, 0x0180, 0, 0x0748, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__AUDMUX_AUD6_TXFS \ + IOMUX_PAD(0x0488, 0x0180, 1, 0x0628, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__LCDIF_DAT_10 \ + IOMUX_PAD(0x0488, 0x0180, 2, 0x07A0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__WEIM_WEIM_DA_A_10 \ + IOMUX_PAD(0x0488, 0x0180, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__USDHC4_DAT0 \ + IOMUX_PAD(0x0488, 0x0180, 4, 0x085C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__GPIO_4_2 \ + IOMUX_PAD(0x0488, 0x0180, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__USB_USBOTG2_PWR \ + IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL5__TPSMP_HDATA_10 \ + IOMUX_PAD(0x0488, 0x0180, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL6__KPP_COL_6 \ + IOMUX_PAD(0x048C, 0x0184, 0, 0x074C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__UART4_TXD \ + IOMUX_PAD(0x048C, 0x0184, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__UART4_RXD \ + IOMUX_PAD(0x048C, 0x0184, 1, 0x0814, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__LCDIF_DAT_12 \ + IOMUX_PAD(0x048C, 0x0184, 2, 0x07A8, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__WEIM_WEIM_DA_A_12 \ + IOMUX_PAD(0x048C, 0x0184, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__USDHC4_DAT2 \ + IOMUX_PAD(0x048C, 0x0184, 4, 0x0864, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__GPIO_4_4 \ + IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__USDHC3_RST \ + IOMUX_PAD(0x048C, 0x0184, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL6__TPSMP_HDATA_12 \ + IOMUX_PAD(0x048C, 0x0184, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_COL7__KPP_COL_7 \ + IOMUX_PAD(0x0490, 0x0188, 0, 0x0750, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__UART4_CTS \ + IOMUX_PAD(0x0490, 0x0188, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__UART4_RTS \ + IOMUX_PAD(0x0490, 0x0188, 1, 0x0810, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__LCDIF_DAT_14 \ + IOMUX_PAD(0x0490, 0x0188, 2, 0x07B0, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__WEIM_WEIM_DA_A_14 \ + IOMUX_PAD(0x0490, 0x0188, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__USDHC4_DAT4 \ + IOMUX_PAD(0x0490, 0x0188, 4, 0x086C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__GPIO_4_6 \ + IOMUX_PAD(0x0490, 0x0188, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__USDHC1_WP \ + IOMUX_PAD(0x0490, 0x0188, 6, 0x082C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_COL7__TPSMP_HDATA_14 \ + IOMUX_PAD(0x0490, 0x0188, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW0__KPP_ROW_0 \ + IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__I2C2_SDA \ + IOMUX_PAD(0x0494, 0x018C, 1 | IOMUX_CONFIG_SION, 0x0728, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__LCDIF_DAT_1 \ + IOMUX_PAD(0x0494, 0x018C, 2, 0x077C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__WEIM_WEIM_DA_A_1 \ + IOMUX_PAD(0x0494, 0x018C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__USDHC1_WP \ + IOMUX_PAD(0x0494, 0x018C, 4, 0x082C, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__GPIO_3_25 \ + IOMUX_PAD(0x0494, 0x018C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__MSHC_BS \ + IOMUX_PAD(0x0494, 0x018C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW0__TPSMP_HDATA_1 \ + IOMUX_PAD(0x0494, 0x018C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW1__KPP_ROW_1 \ + IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__ECSPI4_MISO \ + IOMUX_PAD(0x0498, 0x0190, 1, 0x06D4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__LCDIF_DAT_3 \ + IOMUX_PAD(0x0498, 0x0190, 2, 0x0784, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__WEIM_WEIM_DA_A_3 \ + IOMUX_PAD(0x0498, 0x0190, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__USDHC3_DAT5 \ + IOMUX_PAD(0x0498, 0x0190, 4, 0x0840, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__GPIO_3_27 \ + IOMUX_PAD(0x0498, 0x0190, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__MSHC_DATA_1 \ + IOMUX_PAD(0x0498, 0x0190, 6, 0x07DC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW1__TPSMP_HDATA_3 \ + IOMUX_PAD(0x0498, 0x0190, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW2__KPP_ROW_2 \ + IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__ECSPI4_SCLK \ + IOMUX_PAD(0x049C, 0x0194, 1, 0x06D0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__LCDIF_DAT_5 \ + IOMUX_PAD(0x049C, 0x0194, 2, 0x078C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__WEIM_WEIM_DA_A_5 \ + IOMUX_PAD(0x049C, 0x0194, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__USDHC3_DAT7 \ + IOMUX_PAD(0x049C, 0x0194, 4, 0x0848, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__GPIO_3_29 \ + IOMUX_PAD(0x049C, 0x0194, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__MSHC_DATA_3 \ + IOMUX_PAD(0x049C, 0x0194, 6, 0x07E4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW2__TPSMP_HDATA_5 \ + IOMUX_PAD(0x049C, 0x0194, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW3__KPP_ROW_3 \ + IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__AUDMUX_AUD6_RXC \ + IOMUX_PAD(0x04A0, 0x0198, 1, 0x061C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__LCDIF_DAT_7 \ + IOMUX_PAD(0x04A0, 0x0198, 2, 0x0794, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__WEIM_WEIM_DA_A_7 \ + IOMUX_PAD(0x04A0, 0x0198, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__USDHC4_DAT7 \ + IOMUX_PAD(0x04A0, 0x0198, 4, 0x0878, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__GPIO_3_31 \ + IOMUX_PAD(0x04A0, 0x0198, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__USDHC1_VSELECT \ + IOMUX_PAD(0x04A0, 0x0198, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW3__TPSMP_HDATA_7 \ + IOMUX_PAD(0x04A0, 0x0198, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW4__KPP_ROW_4 \ + IOMUX_PAD(0x04A4, 0x019C, 0, 0x0764, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__AUDMUX_AUD6_TXC \ + IOMUX_PAD(0x04A4, 0x019C, 1, 0x0624, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__LCDIF_DAT_9 \ + IOMUX_PAD(0x04A4, 0x019C, 2, 0x079C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__WEIM_WEIM_DA_A_9 \ + IOMUX_PAD(0x04A4, 0x019C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__USDHC4_CMD \ + IOMUX_PAD(0x04A4, 0x019C, 4, 0x0858, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__GPIO_4_1 \ + IOMUX_PAD(0x04A4, 0x019C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__USB_USBOTG1_OC \ + IOMUX_PAD(0x04A4, 0x019C, 6, 0x0824, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW4__TPSMP_HDATA_9 \ + IOMUX_PAD(0x04A4, 0x019C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW5__KPP_ROW_5 \ + IOMUX_PAD(0x04A8, 0x01A0, 0, 0x0768, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__AUDMUX_AUD6_TXD \ + IOMUX_PAD(0x04A8, 0x01A0, 1, 0x0618, 1, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__LCDIF_DAT_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 2, 0x07A4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__WEIM_WEIM_DA_A_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__USDHC4_DAT1 \ + IOMUX_PAD(0x04A8, 0x01A0, 4, 0x0860, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__GPIO_4_3 \ + IOMUX_PAD(0x04A8, 0x01A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__USB_USBOTG2_OC \ + IOMUX_PAD(0x04A8, 0x01A0, 6, 0x0820, 2, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW5__TPSMP_HDATA_11 \ + IOMUX_PAD(0x04A8, 0x01A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW6__KPP_ROW_6 \ + IOMUX_PAD(0x04AC, 0x01A4, 0, 0x076C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__UART4_TXD \ + IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__UART4_RXD \ + IOMUX_PAD(0x04AC, 0x01A4, 1, 0x0814, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__LCDIF_DAT_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 2, 0x07AC, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__WEIM_WEIM_DA_A_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__USDHC4_DAT3 \ + IOMUX_PAD(0x04AC, 0x01A4, 4, 0x0868, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__GPIO_4_5 \ + IOMUX_PAD(0x04AC, 0x01A4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__USDHC3_VSELECT \ + IOMUX_PAD(0x04AC, 0x01A4, 6, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW6__TPSMP_HDATA_13 \ + IOMUX_PAD(0x04AC, 0x01A4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_KEY_ROW7__KPP_ROW_7 \ + IOMUX_PAD(0x04B0, 0x01A8, 0, 0x0770, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__UART4_CTS \ + IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__UART4_RTS \ + IOMUX_PAD(0x04B0, 0x01A8, 1, 0x0810, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__LCDIF_DAT_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 2, 0x07B4, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__WEIM_WEIM_DA_A_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__USDHC4_DAT5 \ + IOMUX_PAD(0x04B0, 0x01A8, 4, 0x0870, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__GPIO_4_7 \ + IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__USDHC1_CD \ + IOMUX_PAD(0x04B0, 0x01A8, 6, 0x0828, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_KEY_ROW7__TPSMP_HDATA_15 \ + IOMUX_PAD(0x04B0, 0x01A8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_CLK__LCDIF_CLK \ + IOMUX_PAD(0x04B4, 0x01AC, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__USDHC4_DAT4 \ + IOMUX_PAD(0x04B4, 0x01AC, 1, 0x086C, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__LCDIF_WR_RWN \ + IOMUX_PAD(0x04B4, 0x01AC, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__WEIM_WEIM_RW \ + IOMUX_PAD(0x04B4, 0x01AC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__PWM4_PWMO \ + IOMUX_PAD(0x04B4, 0x01AC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__GPIO_2_15 \ + IOMUX_PAD(0x04B4, 0x01AC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__SRC_EARLY_RST \ + IOMUX_PAD(0x04B4, 0x01AC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_CLK__TPSMP_HTRANS_0 \ + IOMUX_PAD(0x04B4, 0x01AC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT0__LCDIF_DAT_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 0, 0x0778, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__ECSPI1_MOSI \ + IOMUX_PAD(0x04B8, 0x01B0, 1, 0x0688, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x04B8, 0x01B0, 2, 0x05E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__PWM1_PWMO \ + IOMUX_PAD(0x04B8, 0x01B0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__UART5_DTR \ + IOMUX_PAD(0x04B8, 0x01B0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__GPIO_2_20 \ + IOMUX_PAD(0x04B8, 0x01B0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__KITTEN_TRACE_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT0__SRC_BT_CFG_0 \ + IOMUX_PAD(0x04B8, 0x01B0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT1__LCDIF_DAT_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 0, 0x077C, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__ECSPI1_MISO \ + IOMUX_PAD(0x04BC, 0x01B4, 1, 0x0684, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x04BC, 0x01B4, 2, 0x05DC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__PWM2_PWMO \ + IOMUX_PAD(0x04BC, 0x01B4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x04BC, 0x01B4, 4, 0x05F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__GPIO_2_21 \ + IOMUX_PAD(0x04BC, 0x01B4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__KITTEN_TRACE_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT1__SRC_BT_CFG_1 \ + IOMUX_PAD(0x04BC, 0x01B4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT10__LCDIF_DAT_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 0, 0x07A0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__KPP_COL_1 \ + IOMUX_PAD(0x04C0, 0x01B8, 1, 0x0738, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__CSI_D_7 \ + IOMUX_PAD(0x04C0, 0x01B8, 2, 0x064C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__WEIM_WEIM_D_4 \ + IOMUX_PAD(0x04C0, 0x01B8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__ECSPI2_MISO \ + IOMUX_PAD(0x04C0, 0x01B8, 4, 0x06A0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__GPIO_2_30 \ + IOMUX_PAD(0x04C0, 0x01B8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__KITTEN_TRACE_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT10__SRC_BT_CFG_10 \ + IOMUX_PAD(0x04C0, 0x01B8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT11__LCDIF_DAT_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 0, 0x07A4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__KPP_ROW_1 \ + IOMUX_PAD(0x04C4, 0x01BC, 1, 0x0758, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__CSI_D_6 \ + IOMUX_PAD(0x04C4, 0x01BC, 2, 0x0648, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__WEIM_WEIM_D_5 \ + IOMUX_PAD(0x04C4, 0x01BC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__ECSPI2_SS1 \ + IOMUX_PAD(0x04C4, 0x01BC, 4, 0x06AC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__GPIO_2_31 \ + IOMUX_PAD(0x04C4, 0x01BC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__KITTEN_TRACE_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT11__SRC_BT_CFG_11 \ + IOMUX_PAD(0x04C4, 0x01BC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT12__LCDIF_DAT_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 0, 0x07A8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__KPP_COL_2 \ + IOMUX_PAD(0x04C8, 0x01C0, 1, 0x073C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__CSI_D_5 \ + IOMUX_PAD(0x04C8, 0x01C0, 2, 0x0644, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__WEIM_WEIM_D_6 \ + IOMUX_PAD(0x04C8, 0x01C0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__UART5_CTS \ + IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__UART5_RTS \ + IOMUX_PAD(0x04C8, 0x01C0, 4, 0x0818, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__GPIO_3_0 \ + IOMUX_PAD(0x04C8, 0x01C0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__KITTEN_TRACE_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT12__SRC_BT_CFG_12 \ + IOMUX_PAD(0x04C8, 0x01C0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT13__LCDIF_DAT_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 0, 0x07AC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__KPP_ROW_2 \ + IOMUX_PAD(0x04CC, 0x01C4, 1, 0x075C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__CSI_D_4 \ + IOMUX_PAD(0x04CC, 0x01C4, 2, 0x0640, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__WEIM_WEIM_D_7 \ + IOMUX_PAD(0x04CC, 0x01C4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__UART5_CTS \ + IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__UART5_RTS \ + IOMUX_PAD(0x04CC, 0x01C4, 4, 0x0818, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__GPIO_3_1 \ + IOMUX_PAD(0x04CC, 0x01C4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__KITTEN_TRACE_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT13__SRC_BT_CFG_13 \ + IOMUX_PAD(0x04CC, 0x01C4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT14__LCDIF_DAT_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 0, 0x07B0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__KPP_COL_3 \ + IOMUX_PAD(0x04D0, 0x01C8, 1, 0x0740, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__CSI_D_3 \ + IOMUX_PAD(0x04D0, 0x01C8, 2, 0x063C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__WEIM_WEIM_D_8 \ + IOMUX_PAD(0x04D0, 0x01C8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__UART5_TXD \ + IOMUX_PAD(0x04D0, 0x01C8, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__UART5_RXD \ + IOMUX_PAD(0x04D0, 0x01C8, 4, 0x081C, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__GPIO_3_2 \ + IOMUX_PAD(0x04D0, 0x01C8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__KITTEN_TRACE_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT14__SRC_BT_CFG_14 \ + IOMUX_PAD(0x04D0, 0x01C8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT15__LCDIF_DAT_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 0, 0x07B4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__KPP_ROW_3 \ + IOMUX_PAD(0x04D4, 0x01CC, 1, 0x0760, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__CSI_D_2 \ + IOMUX_PAD(0x04D4, 0x01CC, 2, 0x0638, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__WEIM_WEIM_D_9 \ + IOMUX_PAD(0x04D4, 0x01CC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__UART5_TXD \ + IOMUX_PAD(0x04D4, 0x01CC, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__UART5_RXD \ + IOMUX_PAD(0x04D4, 0x01CC, 4, 0x081C, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__GPIO_3_3 \ + IOMUX_PAD(0x04D4, 0x01CC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__KITTEN_TRACE_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT15__SRC_BT_CFG_15 \ + IOMUX_PAD(0x04D4, 0x01CC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT16__LCDIF_DAT_16 \ + IOMUX_PAD(0x04D8, 0x01D0, 0, 0x07B8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__KPP_COL_4 \ + IOMUX_PAD(0x04D8, 0x01D0, 1, 0x0744, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__CSI_D_1 \ + IOMUX_PAD(0x04D8, 0x01D0, 2, 0x0634, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__WEIM_WEIM_D_10 \ + IOMUX_PAD(0x04D8, 0x01D0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__I2C2_SCL \ + IOMUX_PAD(0x04D8, 0x01D0, 4 | IOMUX_CONFIG_SION, 0x0724, 3, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__GPIO_3_4 \ + IOMUX_PAD(0x04D8, 0x01D0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__KITTEN_TRACE_16 \ + IOMUX_PAD(0x04D8, 0x01D0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT16__SRC_BT_CFG_24 \ + IOMUX_PAD(0x04D8, 0x01D0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT17__LCDIF_DAT_17 \ + IOMUX_PAD(0x04DC, 0x01D4, 0, 0x07BC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__KPP_ROW_4 \ + IOMUX_PAD(0x04DC, 0x01D4, 1, 0x0764, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__CSI_D_0 \ + IOMUX_PAD(0x04DC, 0x01D4, 2, 0x0630, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__WEIM_WEIM_D_11 \ + IOMUX_PAD(0x04DC, 0x01D4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__I2C2_SDA \ + IOMUX_PAD(0x04DC, 0x01D4, 4 | IOMUX_CONFIG_SION, 0x0728, 3, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__GPIO_3_5 \ + IOMUX_PAD(0x04DC, 0x01D4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__KITTEN_TRACE_17 \ + IOMUX_PAD(0x04DC, 0x01D4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT17__SRC_BT_CFG_25 \ + IOMUX_PAD(0x04DC, 0x01D4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT18__LCDIF_DAT_18 \ + IOMUX_PAD(0x04E0, 0x01D8, 0, 0x07C0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__KPP_COL_5 \ + IOMUX_PAD(0x04E0, 0x01D8, 1, 0x0748, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__CSI_D_15 \ + IOMUX_PAD(0x04E0, 0x01D8, 2, 0x066C, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__WEIM_WEIM_D_12 \ + IOMUX_PAD(0x04E0, 0x01D8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__GPT_CAPIN1 \ + IOMUX_PAD(0x04E0, 0x01D8, 4, 0x0710, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__GPIO_3_6 \ + IOMUX_PAD(0x04E0, 0x01D8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__KITTEN_TRACE_18 \ + IOMUX_PAD(0x04E0, 0x01D8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT18__SRC_BT_CFG_26 \ + IOMUX_PAD(0x04E0, 0x01D8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT19__LCDIF_DAT_19 \ + IOMUX_PAD(0x04E4, 0x01DC, 0, 0x07C4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__KPP_ROW_5 \ + IOMUX_PAD(0x04E4, 0x01DC, 1, 0x0768, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__CSI_D_14 \ + IOMUX_PAD(0x04E4, 0x01DC, 2, 0x0668, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__WEIM_WEIM_D_13 \ + IOMUX_PAD(0x04E4, 0x01DC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__GPT_CAPIN2 \ + IOMUX_PAD(0x04E4, 0x01DC, 4, 0x0714, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__GPIO_3_7 \ + IOMUX_PAD(0x04E4, 0x01DC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__KITTEN_TRACE_19 \ + IOMUX_PAD(0x04E4, 0x01DC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT19__SRC_BT_CFG_27 \ + IOMUX_PAD(0x04E4, 0x01DC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT2__LCDIF_DAT_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 0, 0x0780, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__ECSPI1_SS0 \ + IOMUX_PAD(0x04E8, 0x01E0, 1, 0x068C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__EPIT2_EPITO \ + IOMUX_PAD(0x04E8, 0x01E0, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__PWM3_PWMO \ + IOMUX_PAD(0x04E8, 0x01E0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x04E8, 0x01E0, 4, 0x05EC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__GPIO_2_22 \ + IOMUX_PAD(0x04E8, 0x01E0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__KITTEN_TRACE_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT2__SRC_BT_CFG_2 \ + IOMUX_PAD(0x04E8, 0x01E0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT20__LCDIF_DAT_20 \ + IOMUX_PAD(0x04EC, 0x01E4, 0, 0x07C8, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__KPP_COL_6 \ + IOMUX_PAD(0x04EC, 0x01E4, 1, 0x074C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__CSI_D_13 \ + IOMUX_PAD(0x04EC, 0x01E4, 2, 0x0664, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__WEIM_WEIM_D_14 \ + IOMUX_PAD(0x04EC, 0x01E4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__GPT_CMPOUT1 \ + IOMUX_PAD(0x04EC, 0x01E4, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__GPIO_3_8 \ + IOMUX_PAD(0x04EC, 0x01E4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__KITTEN_TRACE_20 \ + IOMUX_PAD(0x04EC, 0x01E4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT20__SRC_BT_CFG_28 \ + IOMUX_PAD(0x04EC, 0x01E4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT21__LCDIF_DAT_21 \ + IOMUX_PAD(0x04F0, 0x01E8, 0, 0x07CC, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__KPP_ROW_6 \ + IOMUX_PAD(0x04F0, 0x01E8, 1, 0x076C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__CSI_D_12 \ + IOMUX_PAD(0x04F0, 0x01E8, 2, 0x0660, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__WEIM_WEIM_D_15 \ + IOMUX_PAD(0x04F0, 0x01E8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__GPT_CMPOUT2 \ + IOMUX_PAD(0x04F0, 0x01E8, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__GPIO_3_9 \ + IOMUX_PAD(0x04F0, 0x01E8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__KITTEN_TRACE_21 \ + IOMUX_PAD(0x04F0, 0x01E8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT21__SRC_BT_CFG_29 \ + IOMUX_PAD(0x04F0, 0x01E8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT22__LCDIF_DAT_22 \ + IOMUX_PAD(0x04F4, 0x01EC, 0, 0x07D0, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__KPP_COL_7 \ + IOMUX_PAD(0x04F4, 0x01EC, 1, 0x0750, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__CSI_D_11 \ + IOMUX_PAD(0x04F4, 0x01EC, 2, 0x065C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__WEIM_WEIM_EB_3 \ + IOMUX_PAD(0x04F4, 0x01EC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__GPT_CMPOUT3 \ + IOMUX_PAD(0x04F4, 0x01EC, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__GPIO_3_10 \ + IOMUX_PAD(0x04F4, 0x01EC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__KITTEN_TRACE_22 \ + IOMUX_PAD(0x04F4, 0x01EC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT22__SRC_BT_CFG_30 \ + IOMUX_PAD(0x04F4, 0x01EC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT23__LCDIF_DAT_23 \ + IOMUX_PAD(0x04F8, 0x01F0, 0, 0x07D4, 1, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__KPP_ROW_7 \ + IOMUX_PAD(0x04F8, 0x01F0, 1, 0x0770, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__CSI_D_10 \ + IOMUX_PAD(0x04F8, 0x01F0, 2, 0x0658, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__WEIM_WEIM_EB_2 \ + IOMUX_PAD(0x04F8, 0x01F0, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__GPT_CLKIN \ + IOMUX_PAD(0x04F8, 0x01F0, 4, 0x0718, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__GPIO_3_11 \ + IOMUX_PAD(0x04F8, 0x01F0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__KITTEN_TRACE_23 \ + IOMUX_PAD(0x04F8, 0x01F0, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT23__SRC_BT_CFG_31 \ + IOMUX_PAD(0x04F8, 0x01F0, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT3__LCDIF_DAT_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 0, 0x0784, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__ECSPI1_SCLK \ + IOMUX_PAD(0x04FC, 0x01F4, 1, 0x067C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__UART5_DSR \ + IOMUX_PAD(0x04FC, 0x01F4, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__PWM4_PWMO \ + IOMUX_PAD(0x04FC, 0x01F4, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x04FC, 0x01F4, 4, 0x05E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__GPIO_2_23 \ + IOMUX_PAD(0x04FC, 0x01F4, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__KITTEN_TRACE_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT3__SRC_BT_CFG_3 \ + IOMUX_PAD(0x04FC, 0x01F4, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT4__LCDIF_DAT_4 \ + IOMUX_PAD(0x0500, 0x01F8, 0, 0x0788, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__ECSPI1_SS1 \ + IOMUX_PAD(0x0500, 0x01F8, 1, 0x0690, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__CSI_VSYNC \ + IOMUX_PAD(0x0500, 0x01F8, 2, 0x0678, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__WDOG2_WDOG_RST_B_DEB \ + IOMUX_PAD(0x0500, 0x01F8, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x0500, 0x01F8, 4, 0x05F4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__GPIO_2_24 \ + IOMUX_PAD(0x0500, 0x01F8, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__KITTEN_TRACE_4 \ + IOMUX_PAD(0x0500, 0x01F8, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT4__SRC_BT_CFG_4 \ + IOMUX_PAD(0x0500, 0x01F8, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT5__LCDIF_DAT_5 \ + IOMUX_PAD(0x0504, 0x01FC, 0, 0x078C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__ECSPI1_SS2 \ + IOMUX_PAD(0x0504, 0x01FC, 1, 0x0694, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__CSI_HSYNC \ + IOMUX_PAD(0x0504, 0x01FC, 2, 0x0670, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__WEIM_WEIM_CS_3 \ + IOMUX_PAD(0x0504, 0x01FC, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x0504, 0x01FC, 4, 0x05F8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__GPIO_2_25 \ + IOMUX_PAD(0x0504, 0x01FC, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__KITTEN_TRACE_5 \ + IOMUX_PAD(0x0504, 0x01FC, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT5__SRC_BT_CFG_5 \ + IOMUX_PAD(0x0504, 0x01FC, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT6__LCDIF_DAT_6 \ + IOMUX_PAD(0x0508, 0x0200, 0, 0x0790, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__ECSPI1_SS3 \ + IOMUX_PAD(0x0508, 0x0200, 1, 0x0698, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__CSI_PIXCLK \ + IOMUX_PAD(0x0508, 0x0200, 2, 0x0674, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__WEIM_WEIM_D_0 \ + IOMUX_PAD(0x0508, 0x0200, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0508, 0x0200, 4, 0x05E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__GPIO_2_26 \ + IOMUX_PAD(0x0508, 0x0200, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__KITTEN_TRACE_6 \ + IOMUX_PAD(0x0508, 0x0200, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT6__SRC_BT_CFG_6 \ + IOMUX_PAD(0x0508, 0x0200, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT7__LCDIF_DAT_7 \ + IOMUX_PAD(0x050C, 0x0204, 0, 0x0794, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__ECSPI1_RDY \ + IOMUX_PAD(0x050C, 0x0204, 1, 0x0680, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__CSI_MCLK \ + IOMUX_PAD(0x050C, 0x0204, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__WEIM_WEIM_D_1 \ + IOMUX_PAD(0x050C, 0x0204, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x050C, 0x0204, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__GPIO_2_27 \ + IOMUX_PAD(0x050C, 0x0204, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__KITTEN_TRACE_7 \ + IOMUX_PAD(0x050C, 0x0204, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT7__SRC_BT_CFG_7 \ + IOMUX_PAD(0x050C, 0x0204, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT8__LCDIF_DAT_8 \ + IOMUX_PAD(0x0510, 0x0208, 0, 0x0798, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__KPP_COL_0 \ + IOMUX_PAD(0x0510, 0x0208, 1, 0x0734, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__CSI_D_9 \ + IOMUX_PAD(0x0510, 0x0208, 2, 0x0654, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__WEIM_WEIM_D_2 \ + IOMUX_PAD(0x0510, 0x0208, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__ECSPI2_SCLK \ + IOMUX_PAD(0x0510, 0x0208, 4, 0x069C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__GPIO_2_28 \ + IOMUX_PAD(0x0510, 0x0208, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__KITTEN_TRACE_8 \ + IOMUX_PAD(0x0510, 0x0208, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT8__SRC_BT_CFG_8 \ + IOMUX_PAD(0x0510, 0x0208, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_DAT9__LCDIF_DAT_9 \ + IOMUX_PAD(0x0514, 0x020C, 0, 0x079C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__KPP_ROW_0 \ + IOMUX_PAD(0x0514, 0x020C, 1, 0x0754, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__CSI_D_8 \ + IOMUX_PAD(0x0514, 0x020C, 2, 0x0650, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__WEIM_WEIM_D_3 \ + IOMUX_PAD(0x0514, 0x020C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__ECSPI2_MOSI \ + IOMUX_PAD(0x0514, 0x020C, 4, 0x06A4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__GPIO_2_29 \ + IOMUX_PAD(0x0514, 0x020C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__KITTEN_TRACE_9 \ + IOMUX_PAD(0x0514, 0x020C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_DAT9__SRC_BT_CFG_9 \ + IOMUX_PAD(0x0514, 0x020C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_ENABLE__LCDIF_ENABLE \ + IOMUX_PAD(0x0518, 0x0210, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__USDHC4_DAT5 \ + IOMUX_PAD(0x0518, 0x0210, 1, 0x0870, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__LCDIF_RD_E \ + IOMUX_PAD(0x0518, 0x0210, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__WEIM_WEIM_OE \ + IOMUX_PAD(0x0518, 0x0210, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__UART2_TXD \ + IOMUX_PAD(0x0518, 0x0210, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__UART2_RXD \ + IOMUX_PAD(0x0518, 0x0210, 4, 0x0804, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__GPIO_2_16 \ + IOMUX_PAD(0x0518, 0x0210, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__OCOTP_CTRL_WRAPPER_FUSE_LATCHED \ + IOMUX_PAD(0x0518, 0x0210, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_ENABLE__TPSMP_HTRANS_1 \ + IOMUX_PAD(0x0518, 0x0210, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_HSYNC__LCDIF_HSYNC \ + IOMUX_PAD(0x051C, 0x0214, 0, 0x0774, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__USDHC4_DAT6 \ + IOMUX_PAD(0x051C, 0x0214, 1, 0x0874, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__LCDIF_CS \ + IOMUX_PAD(0x051C, 0x0214, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__WEIM_WEIM_CS_0 \ + IOMUX_PAD(0x051C, 0x0214, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__UART2_TXD \ + IOMUX_PAD(0x051C, 0x0214, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__UART2_RXD \ + IOMUX_PAD(0x051C, 0x0214, 4, 0x0804, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__GPIO_2_17 \ + IOMUX_PAD(0x051C, 0x0214, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__KITTEN_TRCLK \ + IOMUX_PAD(0x051C, 0x0214, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_HSYNC__TPSMP_HDATA_16 \ + IOMUX_PAD(0x051C, 0x0214, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_RESET__LCDIF_RESET \ + IOMUX_PAD(0x0520, 0x0218, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_DTACK_B \ + IOMUX_PAD(0x0520, 0x0218, 1, 0x0880, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__LCDIF_BUSY \ + IOMUX_PAD(0x0520, 0x0218, 2, 0x0774, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__WEIM_WEIM_WAIT \ + IOMUX_PAD(0x0520, 0x0218, 3, 0x0884, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__UART2_CTS \ + IOMUX_PAD(0x0520, 0x0218, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__UART2_RTS \ + IOMUX_PAD(0x0520, 0x0218, 4, 0x0800, 2, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__GPIO_2_19 \ + IOMUX_PAD(0x0520, 0x0218, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__CCM_PMIC_RDY \ + IOMUX_PAD(0x0520, 0x0218, 6, 0x062C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_RESET__TPSMP_HDATA_DIR \ + IOMUX_PAD(0x0520, 0x0218, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_LCD_VSYNC__LCDIF_VSYNC \ + IOMUX_PAD(0x0524, 0x021C, 0, 0x0000, 0, MX6SL_LCDIF_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__USDHC4_DAT7 \ + IOMUX_PAD(0x0524, 0x021C, 1, 0x0878, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__LCDIF_RS \ + IOMUX_PAD(0x0524, 0x021C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__WEIM_WEIM_CS_1 \ + IOMUX_PAD(0x0524, 0x021C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__UART2_CTS \ + IOMUX_PAD(0x0524, 0x021C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__UART2_RTS \ + IOMUX_PAD(0x0524, 0x021C, 4, 0x0800, 3, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__GPIO_2_18 \ + IOMUX_PAD(0x0524, 0x021C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__KITTEN_TRCTL \ + IOMUX_PAD(0x0524, 0x021C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_LCD_VSYNC__TPSMP_HDATA_17 \ + IOMUX_PAD(0x0524, 0x021C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PMIC_ON_REQ__SNVS_LP_WRAPPER_SNVS_WAKEUP_ALARM \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PMIC_STBY_REQ__CCM_PMIC_VSTBY_REQ \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_POR_B__SRC_POR_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_PWM1__PWM1_PWMO \ + IOMUX_PAD(0x0528, 0x0220, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__CCM_CLKO \ + IOMUX_PAD(0x0528, 0x0220, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__AUDMUX_AUDIO_CLK_OUT \ + IOMUX_PAD(0x0528, 0x0220, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__FEC_REF_OUT \ + IOMUX_PAD(0x0528, 0x0220, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__CSI_MCLK \ + IOMUX_PAD(0x0528, 0x0220, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__GPIO_3_23 \ + IOMUX_PAD(0x0528, 0x0220, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__EPIT1_EPITO \ + IOMUX_PAD(0x0528, 0x0220, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_PWM1__OBSERVE_MUX_OUT_4 \ + IOMUX_PAD(0x0528, 0x0220, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_REF_CLK_24M__ANATOP_ANATOP_24M_OUT \ + IOMUX_PAD(0x052C, 0x0224, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__I2C3_SCL \ + IOMUX_PAD(0x052C, 0x0224, 1 | IOMUX_CONFIG_SION, 0x072C, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__PWM3_PWMO \ + IOMUX_PAD(0x052C, 0x0224, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x052C, 0x0224, 3, 0x05E0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__CCM_PMIC_RDY \ + IOMUX_PAD(0x052C, 0x0224, 4, 0x062C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__GPIO_3_21 \ + IOMUX_PAD(0x052C, 0x0224, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__USDHC3_WP \ + IOMUX_PAD(0x052C, 0x0224, 6, 0x084C, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_24M__TPSMP_HDATA_19 \ + IOMUX_PAD(0x052C, 0x0224, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_REF_CLK_32K__ANATOP_ANATOP_32K_OUT \ + IOMUX_PAD(0x0530, 0x0228, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__I2C3_SDA \ + IOMUX_PAD(0x0530, 0x0228, 1 | IOMUX_CONFIG_SION, 0x0730, 2, MX6SL_I2C_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__PWM4_PWMO \ + IOMUX_PAD(0x0530, 0x0228, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x0530, 0x0228, 3, 0x05DC, 3, NO_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__USDHC1_LCTL \ + IOMUX_PAD(0x0530, 0x0228, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__GPIO_3_22 \ + IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__USDHC3_CD \ + IOMUX_PAD(0x0530, 0x0228, 6, 0x0838, 3, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_REF_CLK_32K__OBSERVE_MUX_OUT_3 \ + IOMUX_PAD(0x0530, 0x0228, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_RESET_IN_B__SRC_RESET_B \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_CLK__USDHC1_CLK \ + IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__FEC_MDIO \ + IOMUX_PAD(0x0534, 0x022C, 1, 0x06F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__KPP_COL_0 \ + IOMUX_PAD(0x0534, 0x022C, 2, 0x0734, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__EPDC_SDCE_4 \ + IOMUX_PAD(0x0534, 0x022C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__MSHC_SCLK \ + IOMUX_PAD(0x0534, 0x022C, 4, 0x07E8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__GPIO_5_15 \ + IOMUX_PAD(0x0534, 0x022C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__ANATOP_ANATOP_TESTO_2 \ + IOMUX_PAD(0x0534, 0x022C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CLK__PL301_SIM_MX6SL_PER1_HADDR_25 \ + IOMUX_PAD(0x0534, 0x022C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_CMD__USDHC1_CMD \ + IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__FEC_TX_CLK \ + IOMUX_PAD(0x0538, 0x0230, 1, 0x070C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__KPP_ROW_0 \ + IOMUX_PAD(0x0538, 0x0230, 2, 0x0754, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__EPDC_SDCE_5 \ + IOMUX_PAD(0x0538, 0x0230, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__MSHC_BS \ + IOMUX_PAD(0x0538, 0x0230, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__GPIO_5_14 \ + IOMUX_PAD(0x0538, 0x0230, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__ANATOP_ANATOP_TESTO_3 \ + IOMUX_PAD(0x0538, 0x0230, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_CMD__PL301_SIM_MX6SL_PER1_HADDR_26 \ + IOMUX_PAD(0x0538, 0x0230, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT0__USDHC1_DAT0 \ + IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__FEC_RX_ER \ + IOMUX_PAD(0x053C, 0x0234, 1, 0x0708, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__KPP_COL_1 \ + IOMUX_PAD(0x053C, 0x0234, 2, 0x0738, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__EPDC_SDCE_6 \ + IOMUX_PAD(0x053C, 0x0234, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__MSHC_DATA_0 \ + IOMUX_PAD(0x053C, 0x0234, 4, 0x07D8, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__GPIO_5_11 \ + IOMUX_PAD(0x053C, 0x0234, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__ANATOP_ANATOP_TESTO_4 \ + IOMUX_PAD(0x053C, 0x0234, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT0__PL301_SIM_MX6SL_PER1_HADDR_27 \ + IOMUX_PAD(0x053C, 0x0234, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT1__USDHC1_DAT1 \ + IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__FEC_RX_DV \ + IOMUX_PAD(0x0540, 0x0238, 1, 0x0704, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__KPP_ROW_1 \ + IOMUX_PAD(0x0540, 0x0238, 2, 0x0758, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__EPDC_SDCE_7 \ + IOMUX_PAD(0x0540, 0x0238, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__MSHC_DATA_1 \ + IOMUX_PAD(0x0540, 0x0238, 4, 0x07DC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__GPIO_5_8 \ + IOMUX_PAD(0x0540, 0x0238, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__ANATOP_ANATOP_TESTO_5 \ + IOMUX_PAD(0x0540, 0x0238, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT1__PL301_SIM_MX6SL_PER1_HADDR_28 \ + IOMUX_PAD(0x0540, 0x0238, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT2__USDHC1_DAT2 \ + IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__FEC_RDATA_1 \ + IOMUX_PAD(0x0544, 0x023C, 1, 0x06FC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__KPP_COL_2 \ + IOMUX_PAD(0x0544, 0x023C, 2, 0x073C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__EPDC_SDCE_8 \ + IOMUX_PAD(0x0544, 0x023C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__MSHC_DATA_2 \ + IOMUX_PAD(0x0544, 0x023C, 4, 0x07E0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__GPIO_5_13 \ + IOMUX_PAD(0x0544, 0x023C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__ANATOP_ANATOP_TESTO_6 \ + IOMUX_PAD(0x0544, 0x023C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT2__PL301_SIM_MX6SL_PER1_HADDR_29 \ + IOMUX_PAD(0x0544, 0x023C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT3__USDHC1_DAT3 \ + IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__FEC_TDATA_0 \ + IOMUX_PAD(0x0548, 0x0240, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__KPP_ROW_2 \ + IOMUX_PAD(0x0548, 0x0240, 2, 0x075C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__EPDC_SDCE_9 \ + IOMUX_PAD(0x0548, 0x0240, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__MSHC_DATA_3 \ + IOMUX_PAD(0x0548, 0x0240, 4, 0x07E4, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__GPIO_5_6 \ + IOMUX_PAD(0x0548, 0x0240, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__ANATOP_ANATOP_TESTO_7 \ + IOMUX_PAD(0x0548, 0x0240, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT3__PL301_SIM_MX6SL_PER1_HADDR_30 \ + IOMUX_PAD(0x0548, 0x0240, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT4__USDHC1_DAT4 \ + IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__FEC_MDC \ + IOMUX_PAD(0x054C, 0x0244, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__KPP_COL_3 \ + IOMUX_PAD(0x054C, 0x0244, 2, 0x0740, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__EPDC_SDCLKN \ + IOMUX_PAD(0x054C, 0x0244, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__UART4_TXD \ + IOMUX_PAD(0x054C, 0x0244, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__UART4_RXD \ + IOMUX_PAD(0x054C, 0x0244, 4, 0x0814, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__GPIO_5_12 \ + IOMUX_PAD(0x054C, 0x0244, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__ANATOP_ANATOP_TESTO_8 \ + IOMUX_PAD(0x054C, 0x0244, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT4__PL301_SIM_MX6SL_PER1_HADDR_31 \ + IOMUX_PAD(0x054C, 0x0244, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT5__USDHC1_DAT5 \ + IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__FEC_RDATA_0 \ + IOMUX_PAD(0x0550, 0x0248, 1, 0x06F8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__KPP_ROW_3 \ + IOMUX_PAD(0x0550, 0x0248, 2, 0x0760, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__EPDC_SDOED \ + IOMUX_PAD(0x0550, 0x0248, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__UART4_TXD \ + IOMUX_PAD(0x0550, 0x0248, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__UART4_RXD \ + IOMUX_PAD(0x0550, 0x0248, 4, 0x0814, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__GPIO_5_9 \ + IOMUX_PAD(0x0550, 0x0248, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__ANATOP_ANATOP_TESTO_9 \ + IOMUX_PAD(0x0550, 0x0248, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT5__PL301_SIM_MX6SL_PER1_HPROT_3 \ + IOMUX_PAD(0x0550, 0x0248, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT6__USDHC1_DAT6 \ + IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__FEC_TX_EN \ + IOMUX_PAD(0x0554, 0x024C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__KPP_COL_4 \ + IOMUX_PAD(0x0554, 0x024C, 2, 0x0744, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__EPDC_SDOEZ \ + IOMUX_PAD(0x0554, 0x024C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__UART4_CTS \ + IOMUX_PAD(0x0554, 0x024C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__UART4_RTS \ + IOMUX_PAD(0x0554, 0x024C, 4, 0x0810, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__GPIO_5_7 \ + IOMUX_PAD(0x0554, 0x024C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__ANATOP_ANATOP_TESTO_10 \ + IOMUX_PAD(0x0554, 0x024C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT6__PL301_SIM_MX6SL_PER1_HPROT_2 \ + IOMUX_PAD(0x0554, 0x024C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD1_DAT7__USDHC1_DAT7 \ + IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__FEC_TDATA_1 \ + IOMUX_PAD(0x0558, 0x0250, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__KPP_ROW_4 \ + IOMUX_PAD(0x0558, 0x0250, 2, 0x0764, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__CCM_PMIC_RDY \ + IOMUX_PAD(0x0558, 0x0250, 3, 0x062C, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__UART4_CTS \ + IOMUX_PAD(0x0558, 0x0250, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__UART4_RTS \ + IOMUX_PAD(0x0558, 0x0250, 4, 0x0810, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__GPIO_5_10 \ + IOMUX_PAD(0x0558, 0x0250, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__ANATOP_ANATOP_TESTO_11 \ + IOMUX_PAD(0x0558, 0x0250, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD1_DAT7__PL301_SIM_MX6SL_PER1_HMASTLOCK \ + IOMUX_PAD(0x0558, 0x0250, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_CLK__USDHC2_CLK \ + IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__AUDMUX_AUD4_RXFS \ + IOMUX_PAD(0x055C, 0x0254, 1, 0x05F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__ECSPI3_SCLK \ + IOMUX_PAD(0x055C, 0x0254, 2, 0x06B0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__CSI_D_0 \ + IOMUX_PAD(0x055C, 0x0254, 3, 0x0630, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__OSC32K_32K_OUT \ + IOMUX_PAD(0x055C, 0x0254, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__GPIO_5_5 \ + IOMUX_PAD(0x055C, 0x0254, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__ANATOP_ANATOP_TESTO_13 \ + IOMUX_PAD(0x055C, 0x0254, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CLK__PL301_SIM_MX6SL_PER1_HPROT_1 \ + IOMUX_PAD(0x055C, 0x0254, 7, 0x07EC, 1, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_CMD__USDHC2_CMD \ + IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__AUDMUX_AUD4_RXC \ + IOMUX_PAD(0x0560, 0x0258, 1, 0x05EC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__ECSPI3_SS0 \ + IOMUX_PAD(0x0560, 0x0258, 2, 0x06C0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__CSI_D_1 \ + IOMUX_PAD(0x0560, 0x0258, 3, 0x0634, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__EPIT1_EPITO \ + IOMUX_PAD(0x0560, 0x0258, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__GPIO_5_4 \ + IOMUX_PAD(0x0560, 0x0258, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__ANATOP_ANATOP_TESTO_14 \ + IOMUX_PAD(0x0560, 0x0258, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_CMD__PL301_SIM_MX6SL_PER1_HADDR_21 \ + IOMUX_PAD(0x0560, 0x0258, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT0__USDHC2_DAT0 \ + IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD \ + IOMUX_PAD(0x0564, 0x025C, 1, 0x05E4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__ECSPI3_MOSI \ + IOMUX_PAD(0x0564, 0x025C, 2, 0x06BC, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__CSI_D_2 \ + IOMUX_PAD(0x0564, 0x025C, 3, 0x0638, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__UART5_CTS \ + IOMUX_PAD(0x0564, 0x025C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__UART5_RTS \ + IOMUX_PAD(0x0564, 0x025C, 4, 0x0818, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__GPIO_5_1 \ + IOMUX_PAD(0x0564, 0x025C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__ANATOP_ANATOP_TESTO_15 \ + IOMUX_PAD(0x0564, 0x025C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT0__PL301_SIM_MX6SL_PER1_HPROT_0 \ + IOMUX_PAD(0x0564, 0x025C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT1__USDHC2_DAT1 \ + IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__AUDMUX_AUD4_TXC \ + IOMUX_PAD(0x0568, 0x0260, 1, 0x05F4, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__ECSPI3_MISO \ + IOMUX_PAD(0x0568, 0x0260, 2, 0x06B8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__CSI_D_3 \ + IOMUX_PAD(0x0568, 0x0260, 3, 0x063C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__UART5_CTS \ + IOMUX_PAD(0x0568, 0x0260, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__UART5_RTS \ + IOMUX_PAD(0x0568, 0x0260, 4, 0x0818, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__GPIO_4_30 \ + IOMUX_PAD(0x0568, 0x0260, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__MMDC_MMDC_DEBUG_39 \ + IOMUX_PAD(0x0568, 0x0260, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT1__PL301_SIM_MX6SL_PER1_HBURST_1 \ + IOMUX_PAD(0x0568, 0x0260, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT2__USDHC2_DAT2 \ + IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__AUDMUX_AUD4_TXFS \ + IOMUX_PAD(0x056C, 0x0264, 1, 0x05F8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__FEC_COL \ + IOMUX_PAD(0x056C, 0x0264, 2, 0x06F0, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__CSI_D_4 \ + IOMUX_PAD(0x056C, 0x0264, 3, 0x0640, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__UART5_TXD \ + IOMUX_PAD(0x056C, 0x0264, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__UART5_RXD \ + IOMUX_PAD(0x056C, 0x0264, 4, 0x081C, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__GPIO_5_3 \ + IOMUX_PAD(0x056C, 0x0264, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__MMDC_MMDC_DEBUG_38 \ + IOMUX_PAD(0x056C, 0x0264, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT2__PL301_SIM_MX6SL_PER1_HADDR_22 \ + IOMUX_PAD(0x056C, 0x0264, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT3__USDHC2_DAT3 \ + IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__AUDMUX_AUD4_TXD \ + IOMUX_PAD(0x0570, 0x0268, 1, 0x05E8, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__FEC_RX_CLK \ + IOMUX_PAD(0x0570, 0x0268, 2, 0x0700, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__CSI_D_5 \ + IOMUX_PAD(0x0570, 0x0268, 3, 0x0644, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__UART5_TXD \ + IOMUX_PAD(0x0570, 0x0268, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__UART5_RXD \ + IOMUX_PAD(0x0570, 0x0268, 4, 0x081C, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__GPIO_4_28 \ + IOMUX_PAD(0x0570, 0x0268, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__MMDC_MMDC_DEBUG_37 \ + IOMUX_PAD(0x0570, 0x0268, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT3__PL301_SIM_MX6SL_PER1_HBURST_0 \ + IOMUX_PAD(0x0570, 0x0268, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT4__USDHC2_DAT4 \ + IOMUX_PAD(0x0574, 0x026C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__USDHC3_DAT4 \ + IOMUX_PAD(0x0574, 0x026C, 1, 0x083C, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__UART2_TXD \ + IOMUX_PAD(0x0574, 0x026C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__UART2_RXD \ + IOMUX_PAD(0x0574, 0x026C, 2, 0x0804, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__CSI_D_6 \ + IOMUX_PAD(0x0574, 0x026C, 3, 0x0648, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__SPDIF_OUT1 \ + IOMUX_PAD(0x0574, 0x026C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__GPIO_5_2 \ + IOMUX_PAD(0x0574, 0x026C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__MMDC_MMDC_DEBUG_36 \ + IOMUX_PAD(0x0574, 0x026C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT4__PL301_SIM_MX6SL_PER1_HADDR_10 \ + IOMUX_PAD(0x0574, 0x026C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT5__USDHC2_DAT5 \ + IOMUX_PAD(0x0578, 0x0270, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__USDHC3_DAT5 \ + IOMUX_PAD(0x0578, 0x0270, 1, 0x0840, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__UART2_TXD \ + IOMUX_PAD(0x0578, 0x0270, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__UART2_RXD \ + IOMUX_PAD(0x0578, 0x0270, 2, 0x0804, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__CSI_D_7 \ + IOMUX_PAD(0x0578, 0x0270, 3, 0x064C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__SPDIF_IN1 \ + IOMUX_PAD(0x0578, 0x0270, 4, 0x07F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__GPIO_4_31 \ + IOMUX_PAD(0x0578, 0x0270, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__MMDC_MMDC_DEBUG_35 \ + IOMUX_PAD(0x0578, 0x0270, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT5__PL301_SIM_MX6SL_PER1_HADDR_20 \ + IOMUX_PAD(0x0578, 0x0270, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT6__USDHC2_DAT6 \ + IOMUX_PAD(0x057C, 0x0274, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__USDHC3_DAT6 \ + IOMUX_PAD(0x057C, 0x0274, 1, 0x0844, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__UART2_CTS \ + IOMUX_PAD(0x057C, 0x0274, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__UART2_RTS \ + IOMUX_PAD(0x057C, 0x0274, 2, 0x0800, 4, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__CSI_D_8 \ + IOMUX_PAD(0x057C, 0x0274, 3, 0x0650, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__USDHC2_WP \ + IOMUX_PAD(0x057C, 0x0274, 4, 0x0834, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__GPIO_4_29 \ + IOMUX_PAD(0x057C, 0x0274, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__MMDC_MMDC_DEBUG_34 \ + IOMUX_PAD(0x057C, 0x0274, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT6__PL301_SIM_MX6SL_PER1_HADDR_19 \ + IOMUX_PAD(0x057C, 0x0274, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_DAT7__USDHC2_DAT7 \ + IOMUX_PAD(0x0580, 0x0278, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__USDHC3_DAT7 \ + IOMUX_PAD(0x0580, 0x0278, 1, 0x0848, 1, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__UART2_CTS \ + IOMUX_PAD(0x0580, 0x0278, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__UART2_RTS \ + IOMUX_PAD(0x0580, 0x0278, 2, 0x0800, 5, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__CSI_D_9 \ + IOMUX_PAD(0x0580, 0x0278, 3, 0x0654, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__USDHC2_CD \ + IOMUX_PAD(0x0580, 0x0278, 4, 0x0830, 2, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__GPIO_5_0 \ + IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__MMDC_MMDC_DEBUG_33 \ + IOMUX_PAD(0x0580, 0x0278, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_DAT7__PL301_SIM_MX6SL_PER1_HADDR_16 \ + IOMUX_PAD(0x0580, 0x0278, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD2_RST__USDHC2_RST \ + IOMUX_PAD(0x0584, 0x027C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__FEC_REF_OUT \ + IOMUX_PAD(0x0584, 0x027C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__WDOG2_WDOG_B \ + IOMUX_PAD(0x0584, 0x027C, 2, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__SPDIF_OUT1 \ + IOMUX_PAD(0x0584, 0x027C, 3, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__CSI_MCLK \ + IOMUX_PAD(0x0584, 0x027C, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__GPIO_4_27 \ + IOMUX_PAD(0x0584, 0x027C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__ANATOP_ANATOP_TESTO_12 \ + IOMUX_PAD(0x0584, 0x027C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD2_RST__PL301_SIM_MX6SL_PER1_HBURST_2 \ + IOMUX_PAD(0x0584, 0x027C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_CLK__USDHC3_CLK \ + IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__AUDMUX_AUD5_RXFS \ + IOMUX_PAD(0x0588, 0x0280, 1, 0x0608, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__KPP_COL_5 \ + IOMUX_PAD(0x0588, 0x0280, 2, 0x0748, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__CSI_D_10 \ + IOMUX_PAD(0x0588, 0x0280, 3, 0x0658, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x0588, 0x0280, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__GPIO_5_18 \ + IOMUX_PAD(0x0588, 0x0280, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__USB_USBOTG1_PWR \ + IOMUX_PAD(0x0588, 0x0280, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CLK__PL301_SIM_MX6SL_PER1_HADDR_13 \ + IOMUX_PAD(0x0588, 0x0280, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_CMD__USDHC3_CMD \ + IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__AUDMUX_AUD5_RXC \ + IOMUX_PAD(0x058C, 0x0284, 1, 0x0604, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__KPP_ROW_5 \ + IOMUX_PAD(0x058C, 0x0284, 2, 0x0768, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__CSI_D_11 \ + IOMUX_PAD(0x058C, 0x0284, 3, 0x065C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__ANATOP_USBOTG2_ID \ + IOMUX_PAD(0x058C, 0x0284, 4, 0x05E0, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__GPIO_5_21 \ + IOMUX_PAD(0x058C, 0x0284, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__USB_USBOTG2_PWR \ + IOMUX_PAD(0x058C, 0x0284, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_CMD__PL301_SIM_MX6SL_PER1_HADDR_18 \ + IOMUX_PAD(0x058C, 0x0284, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT0__USDHC3_DAT0 \ + IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__AUDMUX_AUD5_RXD \ + IOMUX_PAD(0x0590, 0x0288, 1, 0x05FC, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__KPP_COL_6 \ + IOMUX_PAD(0x0590, 0x0288, 2, 0x074C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__CSI_D_12 \ + IOMUX_PAD(0x0590, 0x0288, 3, 0x0660, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__ANATOP_USBOTG1_ID \ + IOMUX_PAD(0x0590, 0x0288, 4, 0x05DC, 4, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__GPIO_5_19 \ + IOMUX_PAD(0x0590, 0x0288, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__SJC_JTAG_ACT \ + IOMUX_PAD(0x0590, 0x0288, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT0__PL301_SIM_MX6SL_PER1_HADDR_11 \ + IOMUX_PAD(0x0590, 0x0288, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT1__USDHC3_DAT1 \ + IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__AUDMUX_AUD5_TXC \ + IOMUX_PAD(0x0594, 0x028C, 1, 0x060C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__KPP_ROW_6 \ + IOMUX_PAD(0x0594, 0x028C, 2, 0x076C, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__CSI_D_13 \ + IOMUX_PAD(0x0594, 0x028C, 3, 0x0664, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__USDHC1_VSELECT \ + IOMUX_PAD(0x0594, 0x028C, 4, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__GPIO_5_20 \ + IOMUX_PAD(0x0594, 0x028C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__SJC_DE_B \ + IOMUX_PAD(0x0594, 0x028C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT1__PL301_SIM_MX6SL_PER1_HADDR_17 \ + IOMUX_PAD(0x0594, 0x028C, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT2__USDHC3_DAT2 \ + IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__AUDMUX_AUD5_TXFS \ + IOMUX_PAD(0x0598, 0x0290, 1, 0x0610, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__KPP_COL_7 \ + IOMUX_PAD(0x0598, 0x0290, 2, 0x0750, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__CSI_D_14 \ + IOMUX_PAD(0x0598, 0x0290, 3, 0x0668, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__EPIT1_EPITO \ + IOMUX_PAD(0x0598, 0x0290, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__GPIO_5_16 \ + IOMUX_PAD(0x0598, 0x0290, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__USB_USBOTG2_OC \ + IOMUX_PAD(0x0598, 0x0290, 6, 0x0820, 3, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT2__PL301_SIM_MX6SL_PER1_HADDR_14 \ + IOMUX_PAD(0x0598, 0x0290, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_SD3_DAT3__USDHC3_DAT3 \ + IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, MX6SL_USDHC_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__AUDMUX_AUD5_TXD \ + IOMUX_PAD(0x059C, 0x0294, 1, 0x0600, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__KPP_ROW_7 \ + IOMUX_PAD(0x059C, 0x0294, 2, 0x0770, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__CSI_D_15 \ + IOMUX_PAD(0x059C, 0x0294, 3, 0x066C, 1, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__EPIT2_EPITO \ + IOMUX_PAD(0x059C, 0x0294, 4, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__GPIO_5_17 \ + IOMUX_PAD(0x059C, 0x0294, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__USB_USBOTG1_OC \ + IOMUX_PAD(0x059C, 0x0294, 6, 0x0824, 2, NO_PAD_CTRL) +#define MX6SL_PAD_SD3_DAT3__PL301_SIM_MX6SL_PER1_HADDR_12 \ + IOMUX_PAD(0x059C, 0x0294, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_TAMPER__SNVS_LP_WRAPPER_SNVS_TD1 \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_TEST_MODE__TCU_TEST_MODE \ + IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_UART1_RXD__UART1_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART1_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__PWM1_PWMO \ + IOMUX_PAD(0x05A0, 0x0298, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART4_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART4_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 2, 0x0814, 6, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__FEC_COL \ + IOMUX_PAD(0x05A0, 0x0298, 3, 0x06F0, 2, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART5_TXD \ + IOMUX_PAD(0x05A0, 0x0298, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__UART5_RXD \ + IOMUX_PAD(0x05A0, 0x0298, 4, 0x081C, 6, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__GPIO_3_16 \ + IOMUX_PAD(0x05A0, 0x0298, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__ANATOP_ANATOP_TESTI_2 \ + IOMUX_PAD(0x05A0, 0x0298, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_RXD__TPSMP_CLK \ + IOMUX_PAD(0x05A0, 0x0298, 7, 0x0000, 0, NO_PAD_CTRL) + +#define MX6SL_PAD_UART1_TXD__UART1_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART1_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 0, 0x07FC, 1, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__PWM2_PWMO \ + IOMUX_PAD(0x05A4, 0x029C, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART4_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART4_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 2, 0x0814, 7, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__FEC_RX_CLK \ + IOMUX_PAD(0x05A4, 0x029C, 3, 0x0700, 2, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_TXD \ + IOMUX_PAD(0x05A4, 0x029C, 4, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_RXD \ + IOMUX_PAD(0x05A4, 0x029C, 4, 0x081C, 7, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__GPIO_3_17 \ + IOMUX_PAD(0x05A4, 0x029C, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__ANATOP_ANATOP_TESTI_3 \ + IOMUX_PAD(0x05A4, 0x029C, 6, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_UART1_TXD__UART5_DCD \ + IOMUX_PAD(0x05A4, 0x029C, 7, 0x0000, 0, MX6SL_UART_PAD_CTRL) + +#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_B \ + IOMUX_PAD(0x05A8, 0x02A0, 0, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__WDOG1_WDOG_RST_B_DEB \ + IOMUX_PAD(0x05A8, 0x02A0, 1, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__UART5_RI \ + IOMUX_PAD(0x05A8, 0x02A0, 2, 0x0000, 0, MX6SL_UART_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__GPIO_3_18 \ + IOMUX_PAD(0x05A8, 0x02A0, 5, 0x0000, 0, NO_PAD_CTRL) +#define MX6SL_PAD_WDOG_B__OBSERVE_MUX_OUT_2 \ + IOMUX_PAD(0x05A8, 0x02A0, 7, 0x0000, 0, NO_PAD_CTRL) + +#endif /* __MACH_IOMUX_MX6SL_H__*/ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 60fb82ecbc1b..1ff80f9fff55 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -86,6 +86,8 @@ typedef u64 iomux_v3_cfg_t; * Use to set PAD control */ #define NO_PAD_CTRL (1 << 17) +#define NO_PAD_I 0 +#define NO_MUX_I 0 #ifdef CONFIG_SOC_IMX6Q #define PAD_CTL_HYS (1 << 16) diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 8f22b7010bab..350ae0f9fce5 100755 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -23,6 +23,7 @@ #define MX51_PHYS_OFFSET UL(0x90000000) #define MX53_PHYS_OFFSET UL(0x70000000) #define MX6_PHYS_OFFSET UL(0x10000000) +#define MX6SL_PHYS_OFFSET UL(0x80000000) #if !defined(CONFIG_RUNTIME_PHYS_OFFSET) # if defined CONFIG_ARCH_MX1 diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index b28b5ee2ca2e..51c047acf8bc 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -64,6 +64,8 @@ #define MMDC0_ARB_END_ADDR 0x7FFFFFFF #define MMDC1_ARB_BASE_ADDR 0x80000000 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define MX6SL_MMDC0_ARB_BASE_ADDR 0x80000000 /* only MX6SL */ +#define MX6SL_MMDC0_ARB_END_ADDR 0xFFFFFFFF #define OCRAM_ARB_BASE_ADDR 0x00900000 #define OCRAM_ARB_END_ADDR 0x009FFFFF #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR @@ -91,6 +93,8 @@ #define GPU_3D_ARB_END_ADDR 0x00133FFF #define GPU_2D_ARB_BASE_ADDR 0x00134000 #define GPU_2D_ARB_END_ADDR 0x00137FFF +#define MX6SL_GPU_2D_ARB_BASE_ADDR 0x02200000 /* MX6SL */ +#define MX6SL_GPU_2D_ARB_END_ADDR 0x02203FFF /* MX6SL */ #define DTCP_ARB_BASE_ADDR 0x00138000 #define DTCP_ARB_END_ADDR 0x0013BFFF @@ -98,6 +102,7 @@ #define GPV0_BASE_ADDR 0x00B00000 #define GPV1_BASE_ADDR 0x00C00000 #define GPV2_BASE_ADDR 0x00200000 +#define MX6SL_GPV2_BASE_ADDR 0x00D00000 /* GPV0-2 for MX6SL */ #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 @@ -137,12 +142,16 @@ #define MX6Q_ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) /* slot 4 */ #define MX6Q_ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) /* slot 5 */ #define MX6Q_ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) /* slot 6 */ +#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) /* MX6SL */ #define UART1_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) /* slot 8 */ #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) /* slot 9 */ +#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) /* MX6SL */ #define MX6Q_SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */ #define MX6Q_SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */ #define MX6Q_SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */ #define MX6Q_ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) /* slot 13 */ +#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) /* MX6SL */ +#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) /* MX6SL */ #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) /* slot 15 */ #define MX6Q_VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) /* slot 33, global en[1], til 0x7BFFF */ @@ -158,7 +167,9 @@ #define MX6Q_PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) #define MX6Q_PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) #define MX6Q_CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) +#define MX6SL_DBGMON_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) #define MX6Q_CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define MX6SL_QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) #define GPT_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) @@ -181,11 +192,14 @@ #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) #define MX6Q_IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define MX6SL_CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define MX6SL_SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define MX6Q_SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #define MX6DL_EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) #define MX6DL_EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define MX6DL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define MX6DL_ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define MX6SL_DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #define MX6Q_DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) /* ATZ#2- On Platform */ @@ -206,8 +220,14 @@ #define MX6Q_USB_HS1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4200) #define MX6Q_USB_HS2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4400) #define MX6Q_USB_HS3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4600) +#define MX6SL_USB_HS1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4200) +#define MX6SL_USB_HS2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4400) +#define MX6SL_USB_HS3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4600) #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x8000) #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000) +#define MX6SL_MSHC_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC000) + +#define MXC_CAAM_BASE_ADDR (AIPS2_ARB_BASE_ADDR + 0x00000) #define MX6Q_USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) #define MX6Q_USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) @@ -216,9 +236,11 @@ #define MX6Q_I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) #define MX6Q_I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) #define MX6Q_I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) +#define MX6SL_I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#define MX6SL_RNGB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) @@ -253,6 +275,7 @@ #define MX6Q_UART3_BASE_ADDR UART3_BASE_ADDR #define MX6Q_UART4_BASE_ADDR UART4_BASE_ADDR #define MX6Q_FEC_BASE_ADDR ENET_BASE_ADDR +#define MX6DL_FEC_BASE_ADDR ENET_BASE_ADDR #define MX6Q_MIPI_DSI_BASE_ADDR MIPI_DSI_BASE_ADDR #define MX6Q_MIPI_CSI2_BASE_ADDR MIPI_CSI2_BASE_ADDR @@ -296,10 +319,14 @@ #define MXC_INT_CHEETAH_CSYSPWRUPREQ 33 #define MX6Q_INT_SDMA 34 #define MX6Q_INT_VPU_JPG 35 +#define MX6DL_INT_MSHC 35 #define MXC_INT_INTERRUPT_36_NUM 36 #define MX6Q_INT_IPU1_ERR 37 +#define MX6DL_INT_RNGB 37 #define MX6Q_INT_IPU1_SYN 38 +#define MX6SL_INT_SPDC 38 #define MX6Q_INT_IPU2_ERR 39 +#define MX6DL_INT_CSI 39 #define MX6Q_INT_IPU2_SYN 40 #define MXC_INT_GPU3D_IRQ 41 #define MXC_INT_GPU2D_IRQ 42 @@ -333,19 +360,26 @@ #define MX6Q_INT_I2C2 69 #define MX6Q_INT_I2C3 70 #define MX6Q_INT_SATA 71 -#define MX6DL_INT_LCDIF 71 +#define MX6DL_INT_ELCDIF 71 #define MX6Q_INT_USB_HS1 72 +#define MX6SL_INT_USB_HS1 74 #define MX6Q_INT_USB_HS2 73 +#define MX6SL_INT_USB_HS2 72 #define MX6Q_INT_USB_HS3 74 +#define MX6SL_INT_USB_HS3 73 #define MX6Q_INT_USB_OTG 75 #define MX6Q_INT_USB_PHY0 76 #define MX6Q_INT_USB_PHY1 77 +#define MX6SL_INT_USB_PHY0 76 +#define MX6SL_INT_USB_PHY1 77 /* * MX6Q_INT_USB_PHY2, MX6Q_INT_USB_PHY3 are dummy interrupts * In order to compile pass for platform device's definition */ #define MX6Q_INT_USB_PHY2 73 #define MX6Q_INT_USB_PHY3 74 +#define MX6SL_INT_USB_PHY2 72 +#define MX6SL_INT_USB_PHY3 73 #define MX6Q_INT_SSI1 78 #define MX6Q_INT_SSI2 79 #define MX6Q_INT_SSI3 80 @@ -355,6 +389,7 @@ #define MX6Q_INT_SPDIF 84 #define MXC_INT_MLB 85 #define MXC_INT_ANATOP_ANA1 86 +#define MXDL_INT_PMU 86 #define MXC_INT_GPT 87 #define MXC_INT_EPIT1 88 #define MXC_INT_EPIT2 89 @@ -400,6 +435,9 @@ #define MX6DL_INT_EPDC 129 #define MX6DL_INT_EPXP 130 #define MXC_INT_INTERRUPT_131_NUM 131 +#define MX6DL_INT_DCP_GEN 131 +#define MX6DL_INT_DCP_CH0 132 +#define MX6DL_INT_DCP_SEC 133 #define MXC_INT_CSI_INTR1 132 #define MXC_INT_CSI_INTR2 133 #define MXC_INT_DSI 134 @@ -415,6 +453,7 @@ #define MX6Q_INT_PERFMON1 144 #define MX6Q_INT_PERFMON2 145 #define MX6Q_INT_PERFMON3 146 +#define MX6DL_INT_FEC 146 #define MX6Q_INT_HDMI_TX 147 #define MX6Q_INT_HDMI_TX_WAKEUP 148 #define MXC_INT_MLB_AHB0 149 @@ -509,4 +548,10 @@ #define MX6Q_DMA_REQ_SSI3_TX0 46 #define MX6Q_DMA_REQ_DTCP 47 +#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) +extern int mx6q_revision(void); +extern int mx6dl_revision(void); +extern int mx6sl_revision(void); +#endif + #endif /* __ASM_ARCH_MXC_MX6_H__ */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index 6e7dfcc6e3b3..2f23c725a971 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -38,6 +38,7 @@ #define MXC_CPU_MX53 53 #define MXC_CPU_MX6Q 63 #define MXC_CPU_MX6DL 61 +#define MXC_CPU_MX6SL 60 #define IMX_CHIP_REVISION_1_0 0x10 #define IMX_CHIP_REVISION_1_1 0x11 @@ -234,17 +235,14 @@ extern unsigned int __mxc_cpu_type; # define mxc_cpu_type __mxc_cpu_type # define cpu_is_mx6q() (mxc_cpu_type == MXC_CPU_MX6Q) # define cpu_is_mx6dl() (mxc_cpu_type == MXC_CPU_MX6DL) +# define cpu_is_mx6sl() (mxc_cpu_type == MXC_CPU_MX6SL) #else # define cpu_is_mx6q() (0) # define cpu_is_mx6dl() (0) +# define cpu_is_mx6sl() (0) #endif #ifndef __ASSEMBLY__ -#ifdef CONFIG_SOC_IMX6Q -extern int mx6q_revision(void); -#else -#define mx6q_revision(void) (0) -#endif struct cpu_op { u32 pll_reg; @@ -284,7 +282,7 @@ extern int tzic_enable_wake(int is_idle); #define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) -#define cpu_is_mx6() (cpu_is_mx6q() || cpu_is_mx6dl()) +#define cpu_is_mx6() (cpu_is_mx6q() || cpu_is_mx6dl() || cpu_is_mx6sl()) #define MXC_PGCR_PCR 1 #define MXC_SRPGCR_PCR 1 diff --git a/arch/arm/plat-mxc/include/mach/mxc_edid.h b/arch/arm/plat-mxc/include/mach/mxc_edid.h index 10baa01bf9b1..7385c2710db8 100755 --- a/arch/arm/plat-mxc/include/mach/mxc_edid.h +++ b/arch/arm/plat-mxc/include/mach/mxc_edid.h @@ -68,6 +68,7 @@ struct mxc_edid_cfg { u8 max_channels; u8 sample_sizes; u8 sample_rates; + u8 speaker_alloc; }; int mxc_edid_var_to_vic(struct fb_var_screeninfo *var); diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 7021c85d1b59..c1dfe258a477 100755 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -25,4 +25,21 @@ extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); void arch_idle(void); void arch_reset(char mode, const char *cmd); + +#ifdef CONFIG_MXC_REBOOT_MFGMODE +void do_switch_mfgmode(void); +void mxc_clear_mfgmode(void); +#else +#define do_switch_mfgmode() do {} while (0) +#define mxc_clear_mfgmode() do {} while (0) +#endif + +#ifdef CONFIG_MXC_REBOOT_ANDROID_CMD +void do_switch_recovery(void); +void do_switch_fastboot(void); +#else +#define do_switch_recovery() do {} while (0) +#define do_switch_fastboot() do {} while (0) +#endif + #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 99449b48f0fd..5a022321802f 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -21,8 +21,10 @@ #include <linux/io.h> #include <linux/err.h> #include <linux/delay.h> +#include <linux/string.h> #include <mach/hardware.h> #include <mach/common.h> +#include <mach/system.h> #include <asm/proc-fns.h> #include <asm/system.h> #ifdef CONFIG_SMP @@ -32,22 +34,6 @@ static void __iomem *wdog_base; -#ifdef CONFIG_MXC_REBOOT_MFGMODE -void do_switch_mfgmode(void); -void mxc_clear_mfgmode(void); -#else -void do_switch_mfgmode() {} -void mxc_clear_mfgmode() {} -#endif - -#ifdef CONFIG_MXC_REBOOT_ANDROID_CMD -void do_switch_recovery(void); -void do_switch_fastboot(void); -#else -void do_switch_recovery() {} -void do_switch_fastboot() {} -#endif - static void arch_reset_special_mode(char mode, const char *cmd) { if (strcmp(cmd, "download") == 0) @@ -69,7 +55,11 @@ void arch_reset(char mode, const char *cmd) #ifdef CONFIG_ARCH_MX6 /* wait for reset to assert... */ + #ifdef CONFIG_MX6_INTER_LDO_BYPASS + wcr_enable = 0x14; /*reset system by extern pmic*/ + #else wcr_enable = (1 << 2); + #endif __raw_writew(wcr_enable, wdog_base); /* errata TKT039676, SRS bit may be missed when SRC sample it, need to write the wdog controller diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 2cb78f6b9d5e..3f99628a410e 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c @@ -79,10 +79,6 @@ static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; static void __iomem *timer_base; -#ifdef CONFIG_ARCH_MX6 -extern int mx6q_revision(void); -#endif - static inline void gpt_irq_disable(void) { unsigned int tmp; @@ -343,7 +339,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { - if (cpu_is_mx5() || + if (cpu_is_mx5() || cpu_is_mx6sl() || mx6q_revision() == IMX_CHIP_REVISION_1_0) tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c index a4a3721246f8..b18f5239c8b9 100755 --- a/arch/arm/plat-mxc/usb_common.c +++ b/arch/arm/plat-mxc/usb_common.c @@ -55,6 +55,14 @@ void __iomem *imx_otg_base; #define MXC_NUMBER_USB_TRANSCEIVER 6 struct fsl_xcvr_ops *g_xc_ops[MXC_NUMBER_USB_TRANSCEIVER] = { NULL }; +bool usb_icbug_swfix_need(void) +{ + if (cpu_is_mx6sl()) + return false; + else + return true; +} + enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata) { enum fsl_usb2_modes mode; @@ -88,7 +96,7 @@ static int fsl_check_usbclk(void) usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); if (clk_enable(usb_ahb_clk)) { - if (cpu_is_mx6q() || cpu_is_mx6dl()) + if (cpu_is_mx6()) return 0; /* there is no ahb clock at mx6 */ printk(KERN_ERR "clk_enable(usb_ahb_clk) failed\n"); return -EINVAL; @@ -97,7 +105,7 @@ static int fsl_check_usbclk(void) usb_clk = clk_get(NULL, "usb_clk"); if (clk_enable(usb_clk)) { - if (cpu_is_mx6q() || cpu_is_mx6dl()) + if (cpu_is_mx6()) return 0; /* there is usb_clk at mx6 */ printk(KERN_ERR "clk_enable(usb_clk) failed\n"); return -EINVAL; @@ -502,7 +510,7 @@ int fsl_usb_host_init(struct platform_device *pdev) if (usb_register_remote_wakeup(pdev)) pr_debug("%s port is not a wakeup source.\n", pdata->name); - if (!(cpu_is_mx6q() || cpu_is_mx6dl())) { + if (!(cpu_is_mx6())) { if (xops->xcvr_type == PORTSC_PTS_SERIAL) { if (cpu_is_mx35()) { usbh2_set_serial_xcvr(); @@ -814,7 +822,7 @@ int usbotg_init(struct platform_device *pdev) return -EINVAL; if (xops->init) xops->init(xops); - if (!((cpu_is_mx6q() || cpu_is_mx6dl()))) { + if (!(cpu_is_mx6())) { UOG_PORTSC1 = UOG_PORTSC1 & ~PORTSC_PHCD; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 4a344c289602..5b48a6bdc8f6 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1117,4 +1117,5 @@ mx6q_sabreauto MACH_MX6Q_SABREAUTO MX6Q_SABREAUTO 3529 mx6q_sabrelite MACH_MX6Q_SABRELITE MX6Q_SABRELITE 3769 mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980 mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837 +mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091 diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c index 123c86409ec1..2fc2f5f49e54 100644 --- a/drivers/cpufreq/cpufreq_interactive.c +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -827,7 +827,7 @@ int cpufreq_gov_irq_tuner_register(struct irq_tuner dbs_irq_tuner) } EXPORT_SYMBOL_GPL(cpufreq_gov_irq_tuner_register); #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE -fs_initcall(cpufreq_interactive_init); +late_initcall(cpufreq_interactive_init); #else module_init(cpufreq_interactive_init); #endif diff --git a/drivers/crypto/caam/Kconfig b/drivers/crypto/caam/Kconfig index 2d876bb98ff4..82a1011978d8 100644 --- a/drivers/crypto/caam/Kconfig +++ b/drivers/crypto/caam/Kconfig @@ -1,6 +1,6 @@ config CRYPTO_DEV_FSL_CAAM tristate "Freescale CAAM-Multicore driver backend" - depends on FSL_SOC + depends on FSL_SOC || ARCH_MXC help Enables the driver module for Freescale's Cryptographic Accelerator and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c index 676d957c22b0..3c3e76b6ee1f 100644 --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c @@ -1,7 +1,7 @@ /* * caam - Freescale FSL CAAM support for crypto API * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. * * Based on talitos crypto API driver. * @@ -62,10 +62,22 @@ #define CAAM_MAX_IV_LENGTH 16 /* length of descriptors text */ -#define DESC_AEAD_SHARED_TEXT_LEN 4 -#define DESC_AEAD_ENCRYPT_TEXT_LEN 21 -#define DESC_AEAD_DECRYPT_TEXT_LEN 24 -#define DESC_AEAD_GIVENCRYPT_TEXT_LEN 27 +#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 3 + CAAM_PTR_SZ * 3) + +#define DESC_AEAD_BASE (4 * CAAM_CMD_SZ) +#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ) +#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ) +#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ) + +#define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ) +#define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \ + 20 * CAAM_CMD_SZ) +#define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \ + 15 * CAAM_CMD_SZ) + +#define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \ + CAAM_MAX_KEY_SIZE) +#define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ) #ifdef DEBUG /* for print_hex_dumps with line references */ @@ -76,30 +88,372 @@ #define debug(format, arg...) #endif +/* Set DK bit in class 1 operation if shared */ +static inline void append_dec_op1(u32 *desc, u32 type) +{ + u32 *jump_cmd, *uncond_jump_cmd; + + jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD); + append_operation(desc, type | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT); + uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL); + set_jump_tgt_here(desc, jump_cmd); + append_operation(desc, type | OP_ALG_AS_INITFINAL | + OP_ALG_DECRYPT | OP_ALG_AAI_DK); + set_jump_tgt_here(desc, uncond_jump_cmd); +} + +/* + * Wait for completion of class 1 key loading before allowing + * error propagation + */ +static inline void append_dec_shr_done(u32 *desc) +{ + u32 *jump_cmd; + + jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL); + set_jump_tgt_here(desc, jump_cmd); + append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD); +} + +/* + * For aead functions, read payload and write payload, + * both of which are specified in req->src and req->dst + */ +static inline void aead_append_src_dst(u32 *desc, u32 msg_type) +{ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | + KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH); + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); +} + +/* + * For aead encrypt and decrypt, read iv for both classes + */ +static inline void aead_append_ld_iv(u32 *desc, int ivsize) +{ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | + LDST_CLASS_1_CCB | ivsize); + append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize); +} + +/* + * For ablkcipher encrypt and decrypt, read from req->src and + * write to req->dst + */ +static inline void ablkcipher_append_src_dst(u32 *desc) +{ + append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ); \ + append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); \ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | \ + KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1); \ + append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); \ +} + +/* + * If all data, including src (with assoc and iv) or dst (with iv only) are + * contiguous + */ +#define GIV_SRC_CONTIG 1 +#define GIV_DST_CONTIG (1 << 1) + /* * per-session context */ struct caam_ctx { struct device *jrdev; - u32 *sh_desc; - dma_addr_t shared_desc_phys; + u32 sh_desc_enc[DESC_MAX_USED_LEN]; + u32 sh_desc_dec[DESC_MAX_USED_LEN]; + u32 sh_desc_givenc[DESC_MAX_USED_LEN]; + dma_addr_t sh_desc_enc_dma; + dma_addr_t sh_desc_dec_dma; + dma_addr_t sh_desc_givenc_dma; u32 class1_alg_type; u32 class2_alg_type; u32 alg_op; - u8 *key; - dma_addr_t key_phys; + u8 key[CAAM_MAX_KEY_SIZE]; + dma_addr_t key_dma; unsigned int enckeylen; unsigned int split_key_len; unsigned int split_key_pad_len; unsigned int authsize; }; -static int aead_authenc_setauthsize(struct crypto_aead *authenc, +static void append_key_aead(u32 *desc, struct caam_ctx *ctx, + int keys_fit_inline) +{ + if (keys_fit_inline) { + append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len, + ctx->split_key_len, CLASS_2 | + KEY_DEST_MDHA_SPLIT | KEY_ENC); + append_key_as_imm(desc, (void *)ctx->key + + ctx->split_key_pad_len, ctx->enckeylen, + ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); + } else { + append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 | + KEY_DEST_MDHA_SPLIT | KEY_ENC); + append_key(desc, ctx->key_dma + ctx->split_key_pad_len, + ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); + } +} + +static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx, + int keys_fit_inline) +{ + u32 *key_jump_cmd; + + init_sh_desc(desc, HDR_SHARE_WAIT); + + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + append_key_aead(desc, ctx, keys_fit_inline); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* Propagate errors from shared to job descriptor */ + append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD); +} + +static int aead_set_sh_desc(struct crypto_aead *aead) +{ + struct aead_tfm *tfm = &aead->base.crt_aead; + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *jrdev = ctx->jrdev; + bool keys_fit_inline = 0; + u32 *key_jump_cmd, *jump_cmd; + u32 geniv, moveiv; + u32 *desc; + + if (!ctx->enckeylen || !ctx->authsize) + return 0; + + /* + * Job Descriptor and Shared Descriptors + * must all fit into the 64-word Descriptor h/w Buffer + */ + if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN + + ctx->split_key_pad_len + ctx->enckeylen <= + CAAM_DESC_BYTES_MAX) + keys_fit_inline = 1; + + /* aead_encrypt shared descriptor */ + desc = ctx->sh_desc_enc; + + init_sh_desc_key_aead(desc, ctx, keys_fit_inline); + + /* Class 2 operation */ + append_operation(desc, ctx->class2_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); + + /* cryptlen = seqoutlen - authsize */ + append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); + + /* assoclen + cryptlen = seqinlen - ivsize */ + append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize); + + /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */ + append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ); + + /* read assoc before reading payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | + KEY_VLF); + aead_append_ld_iv(desc, tfm->ivsize); + + /* Class 1 operation */ + append_operation(desc, ctx->class1_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); + + /* Read and write cryptlen bytes */ + append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); + append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); + aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2); + + /* Write ICV */ + append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_CONTEXT); + + ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead enc shdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + + dma_sync_single_for_cpu(jrdev, ctx->sh_desc_enc_dma, desc_bytes(desc), + DMA_TO_DEVICE); + /* + * Job Descriptor and Shared Descriptors + * must all fit into the 64-word Descriptor h/w Buffer + */ + if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN + + ctx->split_key_pad_len + ctx->enckeylen <= + CAAM_DESC_BYTES_MAX) + keys_fit_inline = 1; + + desc = ctx->sh_desc_dec; + + /* aead_decrypt shared descriptor */ + init_sh_desc(desc, HDR_SHARE_WAIT); + + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + append_key_aead(desc, ctx, keys_fit_inline); + + /* Only propagate error immediately if shared */ + jump_cmd = append_jump(desc, JUMP_TEST_ALL); + set_jump_tgt_here(desc, key_jump_cmd); + append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD); + set_jump_tgt_here(desc, jump_cmd); + + /* Class 2 operation */ + append_operation(desc, ctx->class2_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); + + /* assoclen + cryptlen = seqinlen - ivsize */ + append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, + ctx->authsize + tfm->ivsize) + /* assoclen = (assoclen + cryptlen) - cryptlen */ + append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); + append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ); + + /* read assoc before reading payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | + KEY_VLF); + + aead_append_ld_iv(desc, tfm->ivsize); + + append_dec_op1(desc, ctx->class1_alg_type); + + /* Read and write cryptlen bytes */ + append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); + append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ); + aead_append_src_dst(desc, FIFOLD_TYPE_MSG); + + /* Load ICV */ + append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 | + FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV); + append_dec_shr_done(desc); + + ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead dec shdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_cpu(jrdev, ctx->sh_desc_dec_dma, desc_bytes(desc), + DMA_TO_DEVICE); + + /* + * Job Descriptor and Shared Descriptors + * must all fit into the 64-word Descriptor h/w Buffer + */ + if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN + + ctx->split_key_pad_len + ctx->enckeylen <= + CAAM_DESC_BYTES_MAX) + keys_fit_inline = 1; + + /* aead_givencrypt shared descriptor */ + desc = ctx->sh_desc_givenc; + + init_sh_desc_key_aead(desc, ctx, keys_fit_inline); + + /* Generate IV */ + geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | + NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | + NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT); + append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); + append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); + append_move(desc, MOVE_SRC_INFIFO | + MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT)); + append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); + + /* Copy IV to class 1 context */ + append_move(desc, MOVE_SRC_CLASS1CTX | + MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT)); + + /* Return to encryption */ + append_operation(desc, ctx->class2_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); + + /* ivsize + cryptlen = seqoutlen - authsize */ + append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); + + /* assoclen = seqinlen - (ivsize + cryptlen) */ + append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ); + + /* read assoc before reading payload */ + append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | + KEY_VLF); + + /* Copy iv from class 1 ctx to class 2 fifo*/ + moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 | + NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT); + append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB | + LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); + append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB | + LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); + + /* Class 1 operation */ + append_operation(desc, ctx->class1_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); + + /* Will write ivsize + cryptlen */ + append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ); + + /* Not need to reload iv */ + append_seq_fifo_load(desc, tfm->ivsize, + FIFOLD_CLASS_SKIP); + + /* Will read cryptlen */ + append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); + aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2); + + /* Write ICV */ + append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_CONTEXT); + + ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead givenc shdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_cpu(jrdev, ctx->sh_desc_givenc_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + return 0; +} + +static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize) { struct caam_ctx *ctx = crypto_aead_ctx(authenc); ctx->authsize = authsize; + aead_set_sh_desc(authenc); return 0; } @@ -117,6 +471,7 @@ static void split_key_done(struct device *dev, u32 *desc, u32 err, #ifdef DEBUG dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif + if (err) { char tmp[CAAM_ERROR_STR_MAX]; @@ -161,6 +516,9 @@ static u32 gen_split_key(struct caam_ctx *ctx, const u8 *key_in, u32 authkeylen) kfree(desc); return -ENOMEM; } + dma_sync_single_for_device(jrdev, dma_addr_in, authkeylen, + DMA_TO_DEVICE); + append_key(desc, dma_addr_in, authkeylen, CLASS_2 | KEY_DEST_CLASS_REG); @@ -211,6 +569,8 @@ static u32 gen_split_key(struct caam_ctx *ctx, const u8 *key_in, u32 authkeylen) #endif } + dma_sync_single_for_cpu(jrdev, dma_addr_out, ctx->split_key_pad_len, + DMA_FROM_DEVICE); dma_unmap_single(jrdev, dma_addr_out, ctx->split_key_pad_len, DMA_FROM_DEVICE); dma_unmap_single(jrdev, dma_addr_in, authkeylen, DMA_TO_DEVICE); @@ -220,73 +580,7 @@ static u32 gen_split_key(struct caam_ctx *ctx, const u8 *key_in, u32 authkeylen) return ret; } -static int build_sh_desc_ipsec(struct caam_ctx *ctx) -{ - struct device *jrdev = ctx->jrdev; - u32 *sh_desc; - u32 *jump_cmd; - bool keys_fit_inline = 0; - - /* - * largest Job Descriptor and its Shared Descriptor - * must both fit into the 64-word Descriptor h/w Buffer - */ - if ((DESC_AEAD_GIVENCRYPT_TEXT_LEN + - DESC_AEAD_SHARED_TEXT_LEN) * CAAM_CMD_SZ + - ctx->split_key_pad_len + ctx->enckeylen <= CAAM_DESC_BYTES_MAX) - keys_fit_inline = 1; - - /* build shared descriptor for this session */ - sh_desc = kmalloc(CAAM_CMD_SZ * DESC_AEAD_SHARED_TEXT_LEN + - (keys_fit_inline ? - ctx->split_key_pad_len + ctx->enckeylen : - CAAM_PTR_SZ * 2), GFP_DMA | GFP_KERNEL); - if (!sh_desc) { - dev_err(jrdev, "could not allocate shared descriptor\n"); - return -ENOMEM; - } - - init_sh_desc(sh_desc, HDR_SAVECTX | HDR_SHARE_SERIAL); - - jump_cmd = append_jump(sh_desc, CLASS_BOTH | JUMP_TEST_ALL | - JUMP_COND_SHRD | JUMP_COND_SELF); - - /* - * process keys, starting with class 2/authentication. - */ - if (keys_fit_inline) { - append_key_as_imm(sh_desc, ctx->key, ctx->split_key_pad_len, - ctx->split_key_len, - CLASS_2 | KEY_DEST_MDHA_SPLIT | KEY_ENC); - - append_key_as_imm(sh_desc, (void *)ctx->key + - ctx->split_key_pad_len, ctx->enckeylen, - ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); - } else { - append_key(sh_desc, ctx->key_phys, ctx->split_key_len, CLASS_2 | - KEY_DEST_MDHA_SPLIT | KEY_ENC); - append_key(sh_desc, ctx->key_phys + ctx->split_key_pad_len, - ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); - } - - /* update jump cmd now that we are at the jump target */ - set_jump_tgt_here(sh_desc, jump_cmd); - - ctx->shared_desc_phys = dma_map_single(jrdev, sh_desc, - desc_bytes(sh_desc), - DMA_TO_DEVICE); - if (dma_mapping_error(jrdev, ctx->shared_desc_phys)) { - dev_err(jrdev, "unable to map shared descriptor\n"); - kfree(sh_desc); - return -ENOMEM; - } - - ctx->sh_desc = sh_desc; - - return 0; -} - -static int aead_authenc_setkey(struct crypto_aead *aead, +static int aead_setkey(struct crypto_aead *aead, const u8 *key, unsigned int keylen) { /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */ @@ -326,27 +620,19 @@ static int aead_authenc_setkey(struct crypto_aead *aead, print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); #endif - ctx->key = kmalloc(ctx->split_key_pad_len + enckeylen, - GFP_KERNEL | GFP_DMA); - if (!ctx->key) { - dev_err(jrdev, "could not allocate key output memory\n"); - return -ENOMEM; - } ret = gen_split_key(ctx, key, authkeylen); if (ret) { - kfree(ctx->key); goto badkey; } /* postpend encryption key to auth split key */ memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen); - ctx->key_phys = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len + + ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len + enckeylen, DMA_TO_DEVICE); - if (dma_mapping_error(jrdev, ctx->key_phys)) { + if (dma_mapping_error(jrdev, ctx->key_dma)) { dev_err(jrdev, "unable to map key i/o memory\n"); - kfree(ctx->key); return -ENOMEM; } #ifdef DEBUG @@ -354,14 +640,16 @@ static int aead_authenc_setkey(struct crypto_aead *aead, DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, ctx->split_key_pad_len + enckeylen, 1); #endif + dma_sync_single_for_device(jrdev, ctx->key_dma, + ctx->split_key_pad_len + enckeylen, + DMA_TO_DEVICE); ctx->enckeylen = enckeylen; - ret = build_sh_desc_ipsec(ctx); + ret = aead_set_sh_desc(aead); if (ret) { - dma_unmap_single(jrdev, ctx->key_phys, ctx->split_key_pad_len + + dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len + enckeylen, DMA_TO_DEVICE); - kfree(ctx->key); } return ret; @@ -370,73 +658,257 @@ badkey: return -EINVAL; } +static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, + const u8 *key, unsigned int keylen) +{ + struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); + struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher; + struct device *jrdev = ctx->jrdev; + int ret = 0; + u32 *key_jump_cmd, *jump_cmd; + u32 *desc; + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); +#endif + + memcpy(ctx->key, key, keylen); + ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen, + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->key_dma)) { + dev_err(jrdev, "unable to map key i/o memory\n"); + return -ENOMEM; + } + ctx->enckeylen = keylen; + dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE); + + /* ablkcipher_encrypt shared descriptor */ + desc = ctx->sh_desc_enc; + init_sh_desc(desc, HDR_SHARE_WAIT); + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + /* Load class1 key only */ + append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, + ctx->enckeylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + set_jump_tgt_here(desc, key_jump_cmd); + + /* Propagate errors from shared to job descriptor */ + append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD); + + /* Load iv */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | + LDST_CLASS_1_CCB | tfm->ivsize); + + /* Load operation */ + append_operation(desc, ctx->class1_alg_type | + OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); + + /* Perform operation */ + ablkcipher_append_src_dst(desc); + + ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ablkcipher enc shdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + /* ablkcipher_decrypt shared descriptor */ + desc = ctx->sh_desc_dec; + + init_sh_desc(desc, HDR_SHARE_WAIT); + /* Skip if already shared */ + key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | + JUMP_COND_SHRD); + + /* Load class1 key only */ + append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, + ctx->enckeylen, CLASS_1 | + KEY_DEST_CLASS_REG); + + /* For aead, only propagate error immediately if shared */ + jump_cmd = append_jump(desc, JUMP_TEST_ALL); + set_jump_tgt_here(desc, key_jump_cmd); + append_cmd(desc, SET_OK_PROP_ERRORS | CMD_LOAD); + set_jump_tgt_here(desc, jump_cmd); + + /* load IV */ + append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | + LDST_CLASS_1_CCB | tfm->ivsize); + + /* Choose operation */ + append_dec_op1(desc, ctx->class1_alg_type); + + /* Perform operation */ + ablkcipher_append_src_dst(desc); + + /* Wait for key to load before allowing propagating error */ + append_dec_shr_done(desc); + + ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, + desc_bytes(desc), + DMA_TO_DEVICE); + if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { + dev_err(jrdev, "unable to map shared descriptor\n"); + return -ENOMEM; + } + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ablkcipher dec shdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, desc, + desc_bytes(desc), 1); +#endif + dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma, + desc_bytes(desc), DMA_TO_DEVICE); + + return ret; +} + +/* + * 16-byte hardware scatter/gather table + * An 8-byte table exists in the hardware spec, but has never been + * implemented to date. The 8/16 option is selected at RTL-compile-time. + * and this selection is visible in the Compile Time Parameters Register + */ + +#define LINKTBL_EXT 0x80000000 /* Entry points to table */ +#define LINKTBL_FINAL 0x40000000 /* Last ent in table */ +#define LINKTBL_BPID_MASK 0x000000ff +#define LINKTBL_BPID_SHIFT 16 +#define LINKTBL_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */ +#define LINKTBL_OFFS_MASK 0x00001fff + struct link_tbl_entry { +#ifdef CONFIG_64BIT u64 ptr; +#else + u32 reserved; + u32 ptr; +#endif u32 len; - u8 reserved; - u8 buf_pool_id; - u16 offset; + u32 bpid_offset; /* BPID in high, offset in lowest bits */ }; /* - * ipsec_esp_edesc - s/w-extended ipsec_esp descriptor + * aead_edesc - s/w-extended aead descriptor + * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist * @src_nents: number of segments in input scatterlist * @dst_nents: number of segments in output scatterlist - * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist + * @iv_dma: dma address of iv for checking continuity and link table * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE) * @link_tbl_bytes: length of dma mapped link_tbl space * @link_tbl_dma: bus physical mapped address of h/w link table * @hw_desc: the h/w job descriptor followed by any referenced link tables */ -struct ipsec_esp_edesc { +struct aead_edesc { int assoc_nents; int src_nents; int dst_nents; + dma_addr_t iv_dma; int link_tbl_bytes; dma_addr_t link_tbl_dma; struct link_tbl_entry *link_tbl; u32 hw_desc[0]; }; -static void ipsec_esp_unmap(struct device *dev, - struct ipsec_esp_edesc *edesc, - struct aead_request *areq) -{ - dma_unmap_sg(dev, areq->assoc, edesc->assoc_nents, DMA_TO_DEVICE); +/* + * ablkcipher_edesc - s/w-extended ablkcipher descriptor + * @src_nents: number of segments in input scatterlist + * @dst_nents: number of segments in output scatterlist + * @iv_dma: dma address of iv for checking continuity and link table + * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE) + * @link_tbl_bytes: length of dma mapped link_tbl space + * @link_tbl_dma: bus physical mapped address of h/w link table + * @hw_desc: the h/w job descriptor followed by any referenced link tables + */ +struct ablkcipher_edesc { + int src_nents; + int dst_nents; + dma_addr_t iv_dma; + int link_tbl_bytes; + dma_addr_t link_tbl_dma; + struct link_tbl_entry *link_tbl; + u32 hw_desc[0]; +}; - if (unlikely(areq->dst != areq->src)) { - dma_unmap_sg(dev, areq->src, edesc->src_nents, - DMA_TO_DEVICE); - dma_unmap_sg(dev, areq->dst, edesc->dst_nents, - DMA_FROM_DEVICE); +static void caam_unmap(struct device *dev, struct scatterlist *src, + struct scatterlist *dst, int src_nents, int dst_nents, + dma_addr_t iv_dma, int ivsize, dma_addr_t link_tbl_dma, + int link_tbl_bytes) +{ + if (unlikely(dst != src)) { + dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE); + dma_sync_sg_for_cpu(dev, dst, dst_nents, DMA_FROM_DEVICE); + dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE); } else { - dma_unmap_sg(dev, areq->src, edesc->src_nents, - DMA_BIDIRECTIONAL); + dma_sync_sg_for_cpu(dev, src, src_nents, DMA_BIDIRECTIONAL); + dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL); } - if (edesc->link_tbl_bytes) - dma_unmap_single(dev, edesc->link_tbl_dma, - edesc->link_tbl_bytes, + if (iv_dma) + dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE); + + if (link_tbl_bytes) + dma_unmap_single(dev, link_tbl_dma, link_tbl_bytes, DMA_TO_DEVICE); } -/* - * ipsec_esp descriptor callbacks - */ -static void ipsec_esp_encrypt_done(struct device *jrdev, u32 *desc, u32 err, +static void aead_unmap(struct device *dev, + struct aead_edesc *edesc, + struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + int ivsize = crypto_aead_ivsize(aead); + + dma_unmap_sg(dev, req->assoc, edesc->assoc_nents, DMA_TO_DEVICE); + + caam_unmap(dev, req->src, req->dst, + edesc->src_nents, edesc->dst_nents, + edesc->iv_dma, ivsize, edesc->link_tbl_dma, + edesc->link_tbl_bytes); +} + +static void ablkcipher_unmap(struct device *dev, + struct ablkcipher_edesc *edesc, + struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + + caam_unmap(dev, req->src, req->dst, + edesc->src_nents, edesc->dst_nents, + edesc->iv_dma, ivsize, edesc->link_tbl_dma, + edesc->link_tbl_bytes); +} + +static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err, void *context) { - struct aead_request *areq = context; - struct ipsec_esp_edesc *edesc; + struct aead_request *req = context; + struct aead_edesc *edesc; #ifdef DEBUG - struct crypto_aead *aead = crypto_aead_reqtfm(areq); - int ivsize = crypto_aead_ivsize(aead); + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); + int ivsize = crypto_aead_ivsize(aead); dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif - edesc = (struct ipsec_esp_edesc *)((char *)desc - - offsetof(struct ipsec_esp_edesc, hw_desc)); + + edesc = (struct aead_edesc *)((char *)desc - + offsetof(struct aead_edesc, hw_desc)); if (err) { char tmp[CAAM_ERROR_STR_MAX]; @@ -444,39 +916,50 @@ static void ipsec_esp_encrypt_done(struct device *jrdev, u32 *desc, u32 err, dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); } - ipsec_esp_unmap(jrdev, edesc, areq); + aead_unmap(jrdev, edesc, req); #ifdef DEBUG print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc), - areq->assoclen , 1); + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), + req->assoclen , 1); print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize, + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize, edesc->src_nents ? 100 : ivsize, 1); print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src), - edesc->src_nents ? 100 : areq->cryptlen + + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->src_nents ? 100 : req->cryptlen + ctx->authsize + 4, 1); #endif kfree(edesc); - aead_request_complete(areq, err); + aead_request_complete(req, err); } -static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err, +static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err, void *context) { - struct aead_request *areq = context; - struct ipsec_esp_edesc *edesc; + struct aead_request *req = context; + struct aead_edesc *edesc; #ifdef DEBUG - struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); + int ivsize = crypto_aead_ivsize(aead); dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); #endif - edesc = (struct ipsec_esp_edesc *)((char *)desc - - offsetof(struct ipsec_esp_edesc, hw_desc)); + + edesc = (struct aead_edesc *)((char *)desc - + offsetof(struct aead_edesc, hw_desc)); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, req->iv, + ivsize, 1); + print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst), + req->cryptlen, 1); +#endif if (err) { char tmp[CAAM_ERROR_STR_MAX]; @@ -484,7 +967,7 @@ static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err, dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); } - ipsec_esp_unmap(jrdev, edesc, areq); + aead_unmap(jrdev, edesc, req); /* * verify hw auth check passed else return -EBADMSG @@ -495,255 +978,423 @@ static void ipsec_esp_decrypt_done(struct device *jrdev, u32 *desc, u32 err, #ifdef DEBUG print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, - ((char *)sg_virt(areq->assoc) - sizeof(struct iphdr)), - sizeof(struct iphdr) + areq->assoclen + - ((areq->cryptlen > 1500) ? 1500 : areq->cryptlen) + + ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)), + sizeof(struct iphdr) + req->assoclen + + ((req->cryptlen > 1500) ? 1500 : req->cryptlen) + ctx->authsize + 36, 1); if (!err && edesc->link_tbl_bytes) { - struct scatterlist *sg = sg_last(areq->src, edesc->src_nents); + struct scatterlist *sg = sg_last(req->src, edesc->src_nents); print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg), sg->length + ctx->authsize + 16, 1); } #endif + kfree(edesc); - aead_request_complete(areq, err); + aead_request_complete(req, err); +} + +static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + struct ablkcipher_request *req = context; + struct ablkcipher_edesc *edesc; +#ifdef DEBUG + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + + dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); +#endif + + edesc = (struct ablkcipher_edesc *)((char *)desc - + offsetof(struct ablkcipher_edesc, hw_desc)); + + if (err) { + char tmp[CAAM_ERROR_STR_MAX]; + + dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); + } + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, req->info, + edesc->src_nents > 1 ? 100 : ivsize, 1); + print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->dst_nents > 1 ? 100 : req->nbytes, 1); +#endif + + ablkcipher_unmap(jrdev, edesc, req); + kfree(edesc); + + ablkcipher_request_complete(req, err); +} + +static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + struct ablkcipher_request *req = context; + struct ablkcipher_edesc *edesc; +#ifdef DEBUG + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + + dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err); +#endif + + edesc = (struct ablkcipher_edesc *)((char *)desc - + offsetof(struct ablkcipher_edesc, hw_desc)); + if (err) { + char tmp[CAAM_ERROR_STR_MAX]; + + dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); + } + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, req->info, + ivsize, 1); + print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->dst_nents > 1 ? 100 : req->nbytes, 1); +#endif + + ablkcipher_unmap(jrdev, edesc, req); + kfree(edesc); + + ablkcipher_request_complete(req, err); +} + +static void sg_to_link_tbl_one(struct link_tbl_entry *link_tbl_ptr, + dma_addr_t dma, u32 len, u32 offset) +{ +#ifndef CONFIG_64BIT + link_tbl_ptr->reserved = 0; /* ensure high half is zero */ +#endif + link_tbl_ptr->ptr = dma; + link_tbl_ptr->len = (len & LINKTBL_LEN_MASK); + /* Does not add in buffer pool ID's at this time */ + link_tbl_ptr->bpid_offset = (offset & LINKTBL_OFFS_MASK); + +#ifdef DEBUG + print_hex_dump(KERN_ERR, "link_tbl_ptr@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, link_tbl_ptr, + sizeof(struct link_tbl_entry), 1); +#endif } /* * convert scatterlist to h/w link table format - * scatterlist must have been previously dma mapped + * but does not have final bit; instead, returns last entry */ -static void sg_to_link_tbl(struct scatterlist *sg, int sg_count, - struct link_tbl_entry *link_tbl_ptr, u32 offset) +static struct link_tbl_entry *sg_to_link_tbl(struct scatterlist *sg, + int sg_count, struct link_tbl_entry + *link_tbl_ptr, u32 offset) { while (sg_count) { - link_tbl_ptr->ptr = sg_dma_address(sg); - link_tbl_ptr->len = sg_dma_len(sg); - link_tbl_ptr->reserved = 0; - link_tbl_ptr->buf_pool_id = 0; - link_tbl_ptr->offset = offset; + sg_to_link_tbl_one(link_tbl_ptr, sg_dma_address(sg), + sg_dma_len(sg), offset); link_tbl_ptr++; sg = sg_next(sg); sg_count--; } + return link_tbl_ptr - 1; +} - /* set Final bit (marks end of link table) */ - link_tbl_ptr--; - link_tbl_ptr->len |= 0x40000000; +/* + * convert scatterlist to h/w link table format + * scatterlist must have been previously dma mapped + */ +static void sg_to_link_tbl_last(struct scatterlist *sg, int sg_count, + struct link_tbl_entry *link_tbl_ptr, u32 offset) +{ + link_tbl_ptr = sg_to_link_tbl(sg, sg_count, link_tbl_ptr, offset); + link_tbl_ptr->len |= LINKTBL_FINAL; } /* - * fill in and submit ipsec_esp job descriptor + * Fill in aead job descriptor */ -static int ipsec_esp(struct ipsec_esp_edesc *edesc, struct aead_request *areq, - u32 encrypt, - void (*callback) (struct device *dev, u32 *desc, - u32 err, void *context)) +static void init_aead_job(u32 *sh_desc, dma_addr_t ptr, + struct aead_edesc *edesc, + struct aead_request *req, + bool all_contig, bool encrypt) { - struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - u32 *desc = edesc->hw_desc, options; - int ret, sg_count, assoc_sg_count; int ivsize = crypto_aead_ivsize(aead); int authsize = ctx->authsize; - dma_addr_t ptr, dst_dma, src_dma; -#ifdef DEBUG - u32 *sh_desc = ctx->sh_desc; + u32 *desc = edesc->hw_desc; + u32 out_options = 0, in_options; + dma_addr_t dst_dma, src_dma; + int len, link_tbl_index = 0; +#ifdef DEBUG debug("assoclen %d cryptlen %d authsize %d\n", - areq->assoclen, areq->cryptlen, authsize); + req->assoclen, req->cryptlen, authsize); print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->assoc), - areq->assoclen , 1); + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), + req->assoclen , 1); print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src) - ivsize, + DUMP_PREFIX_ADDRESS, 16, 4, req->iv, edesc->src_nents ? 100 : ivsize, 1); print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(areq->src), - edesc->src_nents ? 100 : areq->cryptlen + authsize, 1); + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->src_nents ? 100 : req->cryptlen, 1); print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ", DUMP_PREFIX_ADDRESS, 16, 4, sh_desc, desc_bytes(sh_desc), 1); #endif - assoc_sg_count = dma_map_sg(jrdev, areq->assoc, edesc->assoc_nents ?: 1, - DMA_TO_DEVICE); - if (areq->src == areq->dst) - sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1, - DMA_BIDIRECTIONAL); - else - sg_count = dma_map_sg(jrdev, areq->src, edesc->src_nents ? : 1, - DMA_TO_DEVICE); - /* start auth operation */ - append_operation(desc, ctx->class2_alg_type | OP_ALG_AS_INITFINAL | - (encrypt ? : OP_ALG_ICV_ON)); + len = desc_len(sh_desc); + init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); - /* Load FIFO with data for Class 2 CHA */ - options = FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG; - if (!edesc->assoc_nents) { - ptr = sg_dma_address(areq->assoc); + if (all_contig) { + src_dma = sg_dma_address(req->assoc); + in_options = 0; } else { - sg_to_link_tbl(areq->assoc, edesc->assoc_nents, - edesc->link_tbl, 0); - ptr = edesc->link_tbl_dma; - options |= LDST_SGF; + src_dma = edesc->link_tbl_dma; + link_tbl_index += (edesc->assoc_nents ? : 1) + 1 + + (edesc->src_nents ? : 1); + in_options = LDST_SGF; } - append_fifo_load(desc, ptr, areq->assoclen, options); - - /* copy iv from cipher/class1 input context to class2 infifo */ - append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize); - - if (!encrypt) { - u32 *jump_cmd, *uncond_jump_cmd; - - /* JUMP if shared */ - jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD); + if (encrypt) + append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + + req->cryptlen - authsize, in_options); + else + append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + + req->cryptlen, in_options); - /* start class 1 (cipher) operation, non-shared version */ - append_operation(desc, ctx->class1_alg_type | - OP_ALG_AS_INITFINAL); + if (likely(req->src == req->dst)) { + if (all_contig) { + dst_dma = sg_dma_address(req->src); + } else { + dst_dma = src_dma + sizeof(struct link_tbl_entry) * + ((edesc->assoc_nents ? : 1) + 1); + out_options = LDST_SGF; + } + } else { + if (!edesc->dst_nents) { + dst_dma = sg_dma_address(req->dst); + } else { + dst_dma = edesc->link_tbl_dma + + link_tbl_index * + sizeof(struct link_tbl_entry); + out_options = LDST_SGF; + } + } + if (encrypt) + append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options); + else + append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize, + out_options); +} - uncond_jump_cmd = append_jump(desc, 0); +/* + * Fill in aead givencrypt job descriptor + */ +static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr, + struct aead_edesc *edesc, + struct aead_request *req, + int contig) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + int ivsize = crypto_aead_ivsize(aead); + int authsize = ctx->authsize; + u32 *desc = edesc->hw_desc; + u32 out_options = 0, in_options; + dma_addr_t dst_dma, src_dma; + int len, link_tbl_index = 0; - set_jump_tgt_here(desc, jump_cmd); +#ifdef DEBUG + debug("assoclen %d cryptlen %d authsize %d\n", + req->assoclen, req->cryptlen, authsize); + print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), + req->assoclen , 1); + print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1); + print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->src_nents > 1 ? 100 : req->cryptlen, 1); + print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sh_desc, + desc_bytes(sh_desc), 1); +#endif - /* start class 1 (cipher) operation, shared version */ - append_operation(desc, ctx->class1_alg_type | - OP_ALG_AS_INITFINAL | OP_ALG_AAI_DK); - set_jump_tgt_here(desc, uncond_jump_cmd); - } else - append_operation(desc, ctx->class1_alg_type | - OP_ALG_AS_INITFINAL | encrypt); + len = desc_len(sh_desc); + init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); - /* load payload & instruct to class2 to snoop class 1 if encrypting */ - options = 0; - if (!edesc->src_nents) { - src_dma = sg_dma_address(areq->src); + if (contig & GIV_SRC_CONTIG) { + src_dma = sg_dma_address(req->assoc); + in_options = 0; } else { - sg_to_link_tbl(areq->src, edesc->src_nents, edesc->link_tbl + - edesc->assoc_nents, 0); - src_dma = edesc->link_tbl_dma + edesc->assoc_nents * - sizeof(struct link_tbl_entry); - options |= LDST_SGF; + src_dma = edesc->link_tbl_dma; + link_tbl_index += edesc->assoc_nents + 1 + edesc->src_nents; + in_options = LDST_SGF; } - append_seq_in_ptr(desc, src_dma, areq->cryptlen + authsize, options); - append_seq_fifo_load(desc, areq->cryptlen, FIFOLD_CLASS_BOTH | - FIFOLD_TYPE_LASTBOTH | - (encrypt ? FIFOLD_TYPE_MSG1OUT2 - : FIFOLD_TYPE_MSG)); - - /* specify destination */ - if (areq->src == areq->dst) { - dst_dma = src_dma; + append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + + req->cryptlen - authsize, in_options); + + if (contig & GIV_DST_CONTIG) { + dst_dma = edesc->iv_dma; } else { - sg_count = dma_map_sg(jrdev, areq->dst, edesc->dst_nents ? : 1, - DMA_FROM_DEVICE); - if (!edesc->dst_nents) { - dst_dma = sg_dma_address(areq->dst); - options = 0; + if (likely(req->src == req->dst)) { + dst_dma = src_dma + sizeof(struct link_tbl_entry) * + edesc->assoc_nents; + out_options = LDST_SGF; } else { - sg_to_link_tbl(areq->dst, edesc->dst_nents, - edesc->link_tbl + edesc->assoc_nents + - edesc->src_nents, 0); - dst_dma = edesc->link_tbl_dma + (edesc->assoc_nents + - edesc->src_nents) * + dst_dma = edesc->link_tbl_dma + + link_tbl_index * sizeof(struct link_tbl_entry); - options = LDST_SGF; + out_options = LDST_SGF; } } - append_seq_out_ptr(desc, dst_dma, areq->cryptlen + authsize, options); - append_seq_fifo_store(desc, areq->cryptlen, FIFOST_TYPE_MESSAGE_DATA); - /* ICV */ - if (encrypt) - append_seq_store(desc, authsize, LDST_CLASS_2_CCB | - LDST_SRCDST_BYTE_CONTEXT); - else - append_seq_fifo_load(desc, authsize, FIFOLD_CLASS_CLASS2 | - FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV); + append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options); +} + +/* + * Fill in ablkcipher job descriptor + */ +static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr, + struct ablkcipher_edesc *edesc, + struct ablkcipher_request *req, + bool iv_contig) +{ + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + u32 *desc = edesc->hw_desc; + u32 out_options = 0, in_options; + dma_addr_t dst_dma, src_dma; + int len, link_tbl_index = 0; #ifdef DEBUG - debug("job_desc_len %d\n", desc_len(desc)); - print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc) , 1); - print_hex_dump(KERN_ERR, "jdlinkt@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->link_tbl, - edesc->link_tbl_bytes, 1); + print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, req->info, + ivsize, 1); + print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + edesc->src_nents ? 100 : req->nbytes, 1); #endif - ret = caam_jr_enqueue(jrdev, desc, callback, areq); - if (!ret) - ret = -EINPROGRESS; - else { - ipsec_esp_unmap(jrdev, edesc, areq); - kfree(edesc); + len = desc_len(sh_desc); + init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); + + if (iv_contig) { + src_dma = edesc->iv_dma; + in_options = 0; + } else { + src_dma = edesc->link_tbl_dma; + link_tbl_index += (iv_contig ? 0 : 1) + edesc->src_nents; + in_options = LDST_SGF; } + append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options); - return ret; + if (likely(req->src == req->dst)) { + if (!edesc->src_nents && iv_contig) { + dst_dma = sg_dma_address(req->src); + } else { + dst_dma = edesc->link_tbl_dma + + sizeof(struct link_tbl_entry); + out_options = LDST_SGF; + } + } else { + if (!edesc->dst_nents) { + dst_dma = sg_dma_address(req->dst); + } else { + dst_dma = edesc->link_tbl_dma + + link_tbl_index * sizeof(struct link_tbl_entry); + out_options = LDST_SGF; + } + } + append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options); } /* * derive number of elements in scatterlist */ -static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained) +static int sg_count(struct scatterlist *sg_list, int nbytes) { struct scatterlist *sg = sg_list; int sg_nents = 0; - *chained = 0; while (nbytes > 0) { sg_nents++; nbytes -= sg->length; if (!sg_is_last(sg) && (sg + 1)->length == 0) - *chained = 1; + BUG(); /* Not support chaining */ sg = scatterwalk_sg_next(sg); } + if (likely(sg_nents == 1)) + return 0; + return sg_nents; } /* - * allocate and map the ipsec_esp extended descriptor + * allocate and map the aead extended descriptor */ -static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq, - int desc_bytes) +static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, + int desc_bytes, bool *all_contig_ptr) { - struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; - gfp_t flags = areq->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : - GFP_ATOMIC; - int assoc_nents, src_nents, dst_nents = 0, chained, link_tbl_bytes; - struct ipsec_esp_edesc *edesc; - - assoc_nents = sg_count(areq->assoc, areq->assoclen, &chained); - BUG_ON(chained); - if (likely(assoc_nents == 1)) - assoc_nents = 0; - - src_nents = sg_count(areq->src, areq->cryptlen + ctx->authsize, - &chained); - BUG_ON(chained); - if (src_nents == 1) - src_nents = 0; - - if (unlikely(areq->dst != areq->src)) { - dst_nents = sg_count(areq->dst, areq->cryptlen + ctx->authsize, - &chained); - BUG_ON(chained); - if (dst_nents == 1) - dst_nents = 0; + gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC; + int assoc_nents, src_nents, dst_nents = 0; + struct aead_edesc *edesc; + dma_addr_t iv_dma = 0; + int sgc; + bool all_contig = true; + int ivsize = crypto_aead_ivsize(aead); + int link_tbl_index, link_tbl_len = 0, link_tbl_bytes; + + assoc_nents = sg_count(req->assoc, req->assoclen); + src_nents = sg_count(req->src, req->cryptlen); + + if (unlikely(req->dst != req->src)) + dst_nents = sg_count(req->dst, req->cryptlen); + + sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1, + DMA_BIDIRECTIONAL); + dma_sync_sg_for_device(jrdev, req->assoc, sgc, + DMA_BIDIRECTIONAL); + if (likely(req->src == req->dst)) { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_BIDIRECTIONAL); + dma_sync_sg_for_device(jrdev, req->src, sgc, + DMA_BIDIRECTIONAL); + } else { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_TO_DEVICE); + dma_sync_sg_for_device(jrdev, req->src, sgc, + DMA_TO_DEVICE); + sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1, + DMA_FROM_DEVICE); } - link_tbl_bytes = (assoc_nents + src_nents + dst_nents) * - sizeof(struct link_tbl_entry); - debug("link_tbl_bytes %d\n", link_tbl_bytes); + /* Check if data are contiguous */ + iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE); + if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen != + iv_dma || src_nents || iv_dma + ivsize != + sg_dma_address(req->src)) { + all_contig = false; + assoc_nents = assoc_nents ? : 1; + src_nents = src_nents ? : 1; + link_tbl_len = assoc_nents + 1 + src_nents; + } + link_tbl_len += dst_nents; + + link_tbl_bytes = link_tbl_len * sizeof(struct link_tbl_entry); + dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); /* allocate space for base edesc and hw desc commands, link tables */ - edesc = kmalloc(sizeof(struct ipsec_esp_edesc) + desc_bytes + + edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes + link_tbl_bytes, GFP_DMA | flags); if (!edesc) { dev_err(jrdev, "could not allocate extended descriptor\n"); @@ -753,142 +1404,470 @@ static struct ipsec_esp_edesc *ipsec_esp_edesc_alloc(struct aead_request *areq, edesc->assoc_nents = assoc_nents; edesc->src_nents = src_nents; edesc->dst_nents = dst_nents; - edesc->link_tbl = (void *)edesc + sizeof(struct ipsec_esp_edesc) + + edesc->iv_dma = iv_dma; + edesc->link_tbl_bytes = link_tbl_bytes; + edesc->link_tbl = (void *)edesc + sizeof(struct aead_edesc) + desc_bytes; edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl, link_tbl_bytes, DMA_TO_DEVICE); - edesc->link_tbl_bytes = link_tbl_bytes; + *all_contig_ptr = all_contig; + + link_tbl_index = 0; + if (!all_contig) { + sg_to_link_tbl(req->assoc, + (assoc_nents ? : 1), + edesc->link_tbl + + link_tbl_index, 0); + link_tbl_index += assoc_nents ? : 1; + sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index, + iv_dma, ivsize, 0); + link_tbl_index += 1; + sg_to_link_tbl_last(req->src, + (src_nents ? : 1), + edesc->link_tbl + + link_tbl_index, 0); + link_tbl_index += src_nents ? : 1; + } + if (dst_nents) { + sg_to_link_tbl_last(req->dst, dst_nents, + edesc->link_tbl + link_tbl_index, 0); + } + dma_sync_single_for_device(jrdev, edesc->link_tbl_dma, link_tbl_bytes, + DMA_TO_DEVICE); return edesc; } -static int aead_authenc_encrypt(struct aead_request *areq) +static int aead_encrypt(struct aead_request *req) { - struct ipsec_esp_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct aead_edesc *edesc; + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; - int ivsize = crypto_aead_ivsize(aead); + bool all_contig; u32 *desc; - dma_addr_t iv_dma; + int ret = 0; + + req->cryptlen += ctx->authsize; /* allocate extended descriptor */ - edesc = ipsec_esp_edesc_alloc(areq, DESC_AEAD_ENCRYPT_TEXT_LEN * - CAAM_CMD_SZ); + edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * + CAAM_CMD_SZ, &all_contig); if (IS_ERR(edesc)) return PTR_ERR(edesc); - desc = edesc->hw_desc; - - /* insert shared descriptor pointer */ - init_job_desc_shared(desc, ctx->shared_desc_phys, - desc_len(ctx->sh_desc), HDR_SHARE_DEFER); - - iv_dma = dma_map_single(jrdev, areq->iv, ivsize, DMA_TO_DEVICE); - /* check dma error */ + /* Create and submit job descriptor */ + init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req, + all_contig, true); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, + desc_bytes(edesc->hw_desc), 1); +#endif - append_load(desc, iv_dma, ivsize, - LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT); + desc = edesc->hw_desc; + ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); + if (!ret) { + ret = -EINPROGRESS; + } else { + aead_unmap(jrdev, edesc, req); + kfree(edesc); + } - return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done); + return ret; } -static int aead_authenc_decrypt(struct aead_request *req) +static int aead_decrypt(struct aead_request *req) { + struct aead_edesc *edesc; struct crypto_aead *aead = crypto_aead_reqtfm(req); - int ivsize = crypto_aead_ivsize(aead); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; - struct ipsec_esp_edesc *edesc; + bool all_contig; u32 *desc; - dma_addr_t iv_dma; - - req->cryptlen -= ctx->authsize; + int ret = 0; /* allocate extended descriptor */ - edesc = ipsec_esp_edesc_alloc(req, DESC_AEAD_DECRYPT_TEXT_LEN * - CAAM_CMD_SZ); + edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * + CAAM_CMD_SZ, &all_contig); if (IS_ERR(edesc)) return PTR_ERR(edesc); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "dec src@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + req->cryptlen, 1); +#endif + + /* Create and submit job descriptor*/ + init_aead_job(ctx->sh_desc_dec, + ctx->sh_desc_dec_dma, edesc, req, all_contig, false); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, + desc_bytes(edesc->hw_desc), 1); +#endif + desc = edesc->hw_desc; + ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); + if (!ret) { + ret = -EINPROGRESS; + } else { + aead_unmap(jrdev, edesc, req); + kfree(edesc); + } - /* insert shared descriptor pointer */ - init_job_desc_shared(desc, ctx->shared_desc_phys, - desc_len(ctx->sh_desc), HDR_SHARE_DEFER); + return ret; +} - iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE); - /* check dma error */ +/* + * allocate and map the aead extended descriptor for aead givencrypt + */ +static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request + *greq, int desc_bytes, + u32 *contig_ptr) +{ + struct aead_request *req = &greq->areq; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct caam_ctx *ctx = crypto_aead_ctx(aead); + struct device *jrdev = ctx->jrdev; + gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC; + int assoc_nents, src_nents, dst_nents = 0; + struct aead_edesc *edesc; + dma_addr_t iv_dma = 0; + int sgc; + u32 contig = GIV_SRC_CONTIG | GIV_DST_CONTIG; + int ivsize = crypto_aead_ivsize(aead); + int link_tbl_index, link_tbl_len = 0, link_tbl_bytes; + + assoc_nents = sg_count(req->assoc, req->assoclen); + src_nents = sg_count(req->src, req->cryptlen); + + if (unlikely(req->dst != req->src)) + dst_nents = sg_count(req->dst, req->cryptlen); + + sgc = dma_map_sg(jrdev, req->assoc, assoc_nents ? : 1, + DMA_BIDIRECTIONAL); + dma_sync_sg_for_device(jrdev, req->assoc, assoc_nents ? : 1, + DMA_BIDIRECTIONAL); + if (likely(req->src == req->dst)) { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_BIDIRECTIONAL); + dma_sync_sg_for_device(jrdev, req->src, src_nents ? : 1, + DMA_BIDIRECTIONAL); + } else { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_TO_DEVICE); + dma_sync_sg_for_device(jrdev, req->src, src_nents ? : 1, + DMA_TO_DEVICE); + sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1, + DMA_FROM_DEVICE); + } - append_load(desc, iv_dma, ivsize, - LDST_CLASS_1_CCB | LDST_SRCDST_BYTE_CONTEXT); + /* Check if data are contiguous */ + iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE); + if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen != + iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src)) + contig &= ~GIV_SRC_CONTIG; + if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst)) + contig &= ~GIV_DST_CONTIG; + if (unlikely(req->src != req->dst)) { + dst_nents = dst_nents ? : 1; + link_tbl_len += 1; + } + if (!(contig & GIV_SRC_CONTIG)) { + assoc_nents = assoc_nents ? : 1; + src_nents = src_nents ? : 1; + link_tbl_len += assoc_nents + 1 + src_nents; + if (likely(req->src == req->dst)) + contig &= ~GIV_DST_CONTIG; + } + link_tbl_len += dst_nents; + + link_tbl_bytes = link_tbl_len * sizeof(struct link_tbl_entry); + + dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); + + /* allocate space for base edesc and hw desc commands, link tables */ + edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes + + link_tbl_bytes, GFP_DMA | flags); + if (!edesc) { + dev_err(jrdev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } + + edesc->assoc_nents = assoc_nents; + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->iv_dma = iv_dma; + edesc->link_tbl_bytes = link_tbl_bytes; + edesc->link_tbl = (void *)edesc + sizeof(struct aead_edesc) + + desc_bytes; + edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl, + link_tbl_bytes, DMA_TO_DEVICE); + *contig_ptr = contig; + + link_tbl_index = 0; + if (!(contig & GIV_SRC_CONTIG)) { + sg_to_link_tbl(req->assoc, assoc_nents, + edesc->link_tbl + + link_tbl_index, 0); + link_tbl_index += assoc_nents; + sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index, + iv_dma, ivsize, 0); + link_tbl_index += 1; + sg_to_link_tbl_last(req->src, src_nents, + edesc->link_tbl + + link_tbl_index, 0); + link_tbl_index += src_nents; + } + if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) { + sg_to_link_tbl_one(edesc->link_tbl + link_tbl_index, + iv_dma, ivsize, 0); + link_tbl_index += 1; + sg_to_link_tbl_last(req->dst, dst_nents, + edesc->link_tbl + link_tbl_index, 0); + } + dma_sync_single_for_device(jrdev, edesc->link_tbl_dma, link_tbl_bytes, + DMA_TO_DEVICE); - return ipsec_esp(edesc, req, !OP_ALG_ENCRYPT, ipsec_esp_decrypt_done); + return edesc; } -static int aead_authenc_givencrypt(struct aead_givcrypt_request *req) +static int aead_givencrypt(struct aead_givcrypt_request *areq) { - struct aead_request *areq = &req->areq; - struct ipsec_esp_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(areq); + struct aead_request *req = &areq->areq; + struct aead_edesc *edesc; + struct crypto_aead *aead = crypto_aead_reqtfm(req); struct caam_ctx *ctx = crypto_aead_ctx(aead); struct device *jrdev = ctx->jrdev; - int ivsize = crypto_aead_ivsize(aead); - dma_addr_t iv_dma; + u32 contig; u32 *desc; + int ret = 0; - iv_dma = dma_map_single(jrdev, req->giv, ivsize, DMA_FROM_DEVICE); - - debug("%s: giv %p\n", __func__, req->giv); + req->cryptlen += ctx->authsize; /* allocate extended descriptor */ - edesc = ipsec_esp_edesc_alloc(areq, DESC_AEAD_GIVENCRYPT_TEXT_LEN * - CAAM_CMD_SZ); + edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN * + CAAM_CMD_SZ, &contig); + if (IS_ERR(edesc)) return PTR_ERR(edesc); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "giv src@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), + req->cryptlen, 1); +#endif + + /* Create and submit job descriptor*/ + init_aead_giv_job(ctx->sh_desc_givenc, + ctx->sh_desc_givenc_dma, edesc, req, contig); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, + desc_bytes(edesc->hw_desc), 1); +#endif + desc = edesc->hw_desc; + ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); + if (!ret) { + ret = -EINPROGRESS; + } else { + aead_unmap(jrdev, edesc, req); + kfree(edesc); + } - /* insert shared descriptor pointer */ - init_job_desc_shared(desc, ctx->shared_desc_phys, - desc_len(ctx->sh_desc), HDR_SHARE_DEFER); + return ret; +} - /* - * LOAD IMM Info FIFO - * to DECO, Last, Padding, Random, Message, 16 bytes - */ - append_load_imm_u32(desc, NFIFOENTRY_DEST_DECO | NFIFOENTRY_LC1 | - NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DTYPE_MSG | - NFIFOENTRY_PTYPE_RND | ivsize, - LDST_SRCDST_WORD_INFO_FIFO); +/* + * allocate and map the ablkcipher extended descriptor for ablkcipher + */ +static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request + *req, int desc_bytes, + bool *iv_contig_out) +{ + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); + struct device *jrdev = ctx->jrdev; + gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | + CRYPTO_TFM_REQ_MAY_SLEEP)) ? + GFP_KERNEL : GFP_ATOMIC; + int src_nents, dst_nents = 0, link_tbl_bytes; + struct ablkcipher_edesc *edesc; + dma_addr_t iv_dma = 0; + bool iv_contig = false; + int sgc; + int ivsize = crypto_ablkcipher_ivsize(ablkcipher); + int link_tbl_index; + + src_nents = sg_count(req->src, req->nbytes); + + if (unlikely(req->dst != req->src)) + dst_nents = sg_count(req->dst, req->nbytes); + + if (likely(req->src == req->dst)) { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_BIDIRECTIONAL); + dma_sync_sg_for_device(jrdev, req->src, sgc, + DMA_BIDIRECTIONAL); + } else { + sgc = dma_map_sg(jrdev, req->src, src_nents ? : 1, + DMA_TO_DEVICE); + dma_sync_sg_for_device(jrdev, req->src, sgc, DMA_TO_DEVICE); + sgc = dma_map_sg(jrdev, req->dst, dst_nents ? : 1, + DMA_FROM_DEVICE); + } + /* FIXME: no test for sgc values returned above... */ /* - * disable info fifo entries since the above serves as the entry - * this way, the MOVE command won't generate an entry. - * Note that this isn't required in more recent versions of - * SEC as a MOVE that doesn't do info FIFO entries is available. + * Check if iv can be contiguous with source and destination. + * If so, include it. If not, create scatterlist. */ - append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); + iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE); + dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); + if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src)) + iv_contig = true; + else + src_nents = src_nents ? : 1; + link_tbl_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) * + sizeof(struct link_tbl_entry); - /* MOVE DECO Alignment -> C1 Context 16 bytes */ - append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX | ivsize); + /* allocate space for base edesc and hw desc commands, link tables */ + edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes + + link_tbl_bytes, GFP_DMA | flags); + if (!edesc) { + dev_err(jrdev, "could not allocate extended descriptor\n"); + return ERR_PTR(-ENOMEM); + } - /* re-enable info fifo entries */ - append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); + edesc->src_nents = src_nents; + edesc->dst_nents = dst_nents; + edesc->link_tbl_bytes = link_tbl_bytes; + edesc->link_tbl = (void *)edesc + sizeof(struct ablkcipher_edesc) + + desc_bytes; + + link_tbl_index = 0; + if (!iv_contig) { + sg_to_link_tbl_one(edesc->link_tbl, iv_dma, ivsize, 0); + sg_to_link_tbl_last(req->src, src_nents, + edesc->link_tbl + 1, 0); + link_tbl_index += 1 + src_nents; + } + + if (unlikely(dst_nents)) { + sg_to_link_tbl_last(req->dst, dst_nents, + edesc->link_tbl + link_tbl_index, 0); + } + + edesc->link_tbl_dma = dma_map_single(jrdev, edesc->link_tbl, + link_tbl_bytes, DMA_TO_DEVICE); + edesc->iv_dma = iv_dma; - /* MOVE C1 Context -> OFIFO 16 bytes */ - append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO | ivsize); + dma_sync_single_for_device(jrdev, edesc->link_tbl_dma, link_tbl_bytes, + DMA_TO_DEVICE); - append_fifo_store(desc, iv_dma, ivsize, FIFOST_TYPE_MESSAGE_DATA); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ablkcipher link_tbl@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->link_tbl, + link_tbl_bytes, 1); +#endif - return ipsec_esp(edesc, areq, OP_ALG_ENCRYPT, ipsec_esp_encrypt_done); + *iv_contig_out = iv_contig; + return edesc; } +static int ablkcipher_encrypt(struct ablkcipher_request *req) +{ + struct ablkcipher_edesc *edesc; + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); + struct device *jrdev = ctx->jrdev; + bool iv_contig; + u32 *desc; + int ret = 0; + + /* allocate extended descriptor */ + edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN * + CAAM_CMD_SZ, &iv_contig); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + /* Create and submit job descriptor*/ + init_ablkcipher_job(ctx->sh_desc_enc, + ctx->sh_desc_enc_dma, edesc, req, iv_contig); +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, + desc_bytes(edesc->hw_desc), 1); +#endif + desc = edesc->hw_desc; + ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req); + + if (!ret) { + ret = -EINPROGRESS; + } else { + ablkcipher_unmap(jrdev, edesc, req); + kfree(edesc); + } + + return ret; +} + +static int ablkcipher_decrypt(struct ablkcipher_request *req) +{ + struct ablkcipher_edesc *edesc; + struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); + struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); + struct device *jrdev = ctx->jrdev; + bool iv_contig; + u32 *desc; + int ret = 0; + + /* allocate extended descriptor */ + edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN * + CAAM_CMD_SZ, &iv_contig); + if (IS_ERR(edesc)) + return PTR_ERR(edesc); + + /* Create and submit job descriptor*/ + init_ablkcipher_job(ctx->sh_desc_dec, + ctx->sh_desc_dec_dma, edesc, req, iv_contig); + desc = edesc->hw_desc; +#ifdef DEBUG + print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ", + DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, + desc_bytes(edesc->hw_desc), 1); +#endif + + ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req); + if (!ret) { + ret = -EINPROGRESS; + } else { + ablkcipher_unmap(jrdev, edesc, req); + kfree(edesc); + } + + return ret; +} + +#define template_aead template_u.aead +#define template_ablkcipher template_u.ablkcipher struct caam_alg_template { char name[CRYPTO_MAX_ALG_NAME]; char driver_name[CRYPTO_MAX_ALG_NAME]; unsigned int blocksize; - struct aead_alg aead; + u32 type; + union { + struct ablkcipher_alg ablkcipher; + struct aead_alg aead; + struct blkcipher_alg blkcipher; + struct cipher_alg cipher; + struct compress_alg compress; + struct rng_alg rng; + } template_u; u32 class1_alg_type; u32 class2_alg_type; u32 alg_op; @@ -900,12 +1879,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha1),cbc(aes))", .driver_name = "authenc-hmac-sha1-cbc-aes-caam", .blocksize = AES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = AES_BLOCK_SIZE, .maxauthsize = SHA1_DIGEST_SIZE, @@ -918,12 +1898,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha256),cbc(aes))", .driver_name = "authenc-hmac-sha256-cbc-aes-caam", .blocksize = AES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = AES_BLOCK_SIZE, .maxauthsize = SHA256_DIGEST_SIZE, @@ -937,12 +1918,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha512),cbc(aes))", .driver_name = "authenc-hmac-sha512-cbc-aes-caam", .blocksize = AES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = AES_BLOCK_SIZE, .maxauthsize = SHA512_DIGEST_SIZE, @@ -956,12 +1938,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha1),cbc(des3_ede))", .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam", .blocksize = DES3_EDE_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES3_EDE_BLOCK_SIZE, .maxauthsize = SHA1_DIGEST_SIZE, @@ -974,12 +1957,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha256),cbc(des3_ede))", .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam", .blocksize = DES3_EDE_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES3_EDE_BLOCK_SIZE, .maxauthsize = SHA256_DIGEST_SIZE, @@ -993,12 +1977,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha512),cbc(des3_ede))", .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam", .blocksize = DES3_EDE_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES3_EDE_BLOCK_SIZE, .maxauthsize = SHA512_DIGEST_SIZE, @@ -1012,12 +1997,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha1),cbc(des))", .driver_name = "authenc-hmac-sha1-cbc-des-caam", .blocksize = DES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES_BLOCK_SIZE, .maxauthsize = SHA1_DIGEST_SIZE, @@ -1030,12 +2016,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha256),cbc(des))", .driver_name = "authenc-hmac-sha256-cbc-des-caam", .blocksize = DES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES_BLOCK_SIZE, .maxauthsize = SHA256_DIGEST_SIZE, @@ -1049,12 +2036,13 @@ static struct caam_alg_template driver_algs[] = { .name = "authenc(hmac(sha512),cbc(des))", .driver_name = "authenc-hmac-sha512-cbc-des-caam", .blocksize = DES_BLOCK_SIZE, - .aead = { - .setkey = aead_authenc_setkey, - .setauthsize = aead_authenc_setauthsize, - .encrypt = aead_authenc_encrypt, - .decrypt = aead_authenc_decrypt, - .givencrypt = aead_authenc_givencrypt, + .type = CRYPTO_ALG_TYPE_AEAD, + .template_aead = { + .setkey = aead_setkey, + .setauthsize = aead_setauthsize, + .encrypt = aead_encrypt, + .decrypt = aead_decrypt, + .givencrypt = aead_givencrypt, .geniv = "<built-in>", .ivsize = DES_BLOCK_SIZE, .maxauthsize = SHA512_DIGEST_SIZE, @@ -1064,6 +2052,55 @@ static struct caam_alg_template driver_algs[] = { OP_ALG_AAI_HMAC_PRECOMP, .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC, }, + /* ablkcipher descriptor */ + { + .name = "cbc(aes)", + .driver_name = "cbc-aes-caam", + .blocksize = AES_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, + }, + { + .name = "cbc(des3_ede)", + .driver_name = "cbc-3des-caam", + .blocksize = DES3_EDE_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC, + }, + { + .name = "cbc(des)", + .driver_name = "cbc-des-caam", + .blocksize = DES_BLOCK_SIZE, + .type = CRYPTO_ALG_TYPE_ABLKCIPHER, + .template_ablkcipher = { + .setkey = ablkcipher_setkey, + .encrypt = ablkcipher_encrypt, + .decrypt = ablkcipher_decrypt, + .geniv = "eseqiv", + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + }, + .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, + } }; struct caam_crypto_alg { @@ -1102,38 +2139,29 @@ static void caam_cra_exit(struct crypto_tfm *tfm) { struct caam_ctx *ctx = crypto_tfm_ctx(tfm); - if (!dma_mapping_error(ctx->jrdev, ctx->shared_desc_phys)) - dma_unmap_single(ctx->jrdev, ctx->shared_desc_phys, - desc_bytes(ctx->sh_desc), DMA_TO_DEVICE); - kfree(ctx->sh_desc); - - if (!dma_mapping_error(ctx->jrdev, ctx->key_phys)) - dma_unmap_single(ctx->jrdev, ctx->key_phys, - ctx->split_key_pad_len + ctx->enckeylen, + if (ctx->sh_desc_enc_dma && + !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma)) + dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma, + desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE); + if (ctx->sh_desc_dec_dma && + !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma)) + dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma, + desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE); + if (ctx->sh_desc_givenc_dma && + !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma)) + dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma, + desc_bytes(ctx->sh_desc_givenc), DMA_TO_DEVICE); - kfree(ctx->key); } -static void __exit caam_algapi_exit(void) +void caam_algapi_shutdown(struct platform_device *pdev) { - - struct device_node *dev_node; - struct platform_device *pdev; struct device *ctrldev; struct caam_drv_private *priv; struct caam_crypto_alg *t_alg, *n; int i, err; - dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - if (!dev_node) - return; - - pdev = of_find_device_by_node(dev_node); - if (!pdev) - return; - ctrldev = &pdev->dev; - of_node_put(dev_node); priv = dev_get_drvdata(ctrldev); if (!priv->alg_list.next) @@ -1175,12 +2203,20 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev, alg->cra_init = caam_cra_init; alg->cra_exit = caam_cra_exit; alg->cra_priority = CAAM_CRA_PRIORITY; - alg->cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC; alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; - alg->cra_type = &crypto_aead_type; alg->cra_ctxsize = sizeof(struct caam_ctx); - alg->cra_u.aead = template->aead; + alg->cra_flags = CRYPTO_ALG_ASYNC | template->type; + switch (template->type) { + case CRYPTO_ALG_TYPE_ABLKCIPHER: + alg->cra_type = &crypto_ablkcipher_type; + alg->cra_ablkcipher = template->template_ablkcipher; + break; + case CRYPTO_ALG_TYPE_AEAD: + alg->cra_type = &crypto_aead_type; + alg->cra_aead = template->template_aead; + break; + } t_alg->class1_alg_type = template->class1_alg_type; t_alg->class2_alg_type = template->class2_alg_type; @@ -1190,26 +2226,14 @@ static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev, return t_alg; } -static int __init caam_algapi_init(void) +int caam_algapi_startup(struct platform_device *pdev) { - struct device_node *dev_node; - struct platform_device *pdev; struct device *ctrldev, **jrdev; struct caam_drv_private *priv; int i = 0, err = 0; - dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - if (!dev_node) - return -ENODEV; - - pdev = of_find_device_by_node(dev_node); - if (!pdev) - return -ENODEV; - ctrldev = &pdev->dev; priv = dev_get_drvdata(ctrldev); - of_node_put(dev_node); - INIT_LIST_HEAD(&priv->alg_list); jrdev = kmalloc(sizeof(*jrdev) * priv->total_jobrs, GFP_KERNEL); @@ -1260,9 +2284,51 @@ static int __init caam_algapi_init(void) return err; } +#ifdef CONFIG_OF +static void __exit caam_algapi_exit(void) +{ + + struct device_node *dev_node; + struct platform_device *pdev; + + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) + return; + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return; + + caam_algapi_shutdown(pdev); + + of_node_put(dev_node); +} + +static int __init caam_algapi_init(void) +{ + struct device_node *dev_node; + struct platform_device *pdev; + int stat; + + dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); + if (!dev_node) + return -ENODEV; + + pdev = of_find_device_by_node(dev_node); + if (!pdev) + return -ENODEV; + + stat = caam_algapi_startup(pdev); + + of_node_put(dev_node); + + return stat; +} + module_init(caam_algapi_init); module_exit(caam_algapi_exit); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("FSL CAAM support for crypto API"); MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); +#endif diff --git a/drivers/crypto/caam/compat.h b/drivers/crypto/caam/compat.h index 950450346f70..9ad93d4156c2 100644 --- a/drivers/crypto/caam/compat.h +++ b/drivers/crypto/caam/compat.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. */ #ifndef CAAM_COMPAT_H @@ -12,7 +12,6 @@ #include <linux/interrupt.h> #include <linux/crypto.h> #include <linux/hw_random.h> -#include <linux/of_platform.h> #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/spinlock.h> @@ -22,6 +21,18 @@ #include <linux/types.h> #include <linux/debugfs.h> #include <linux/circ_buf.h> + +#ifdef CONFIG_OF +#include <linux/of_platform.h> +#else +#include <linux/platform_device.h> +#endif + +#ifdef CONFIG_ARM /* needs the clock control subsystem */ +#include <linux/clk.h> +#include <asm/cacheflush.h> +#endif + #include <net/xfrm.h> #include <crypto/algapi.h> @@ -31,5 +42,6 @@ #include <crypto/aead.h> #include <crypto/authenc.h> #include <crypto/scatterwalk.h> +#include <crypto/internal/skcipher.h> #endif /* !defined(CAAM_COMPAT_H) */ diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 9009713a3c2e..7c1132097c0f 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -2,7 +2,7 @@ * CAAM control-plane driver backend * Controller-level driver, kernel property detection, initialization * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. */ #include "compat.h" @@ -22,6 +22,9 @@ static int caam_remove(struct platform_device *pdev) ctrlpriv = dev_get_drvdata(ctrldev); topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; +#ifndef CONFIG_OF + caam_algapi_shutdown(pdev); +#endif /* shut down JobRs */ for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]); @@ -37,6 +40,9 @@ static int caam_remove(struct platform_device *pdev) /* Unmap controller region */ iounmap(&topregs->ctrl); + /* shut clocks off before finalizing shutdown */ + clk_disable(ctrlpriv->caam_clk); + kfree(ctrlpriv->jrdev); kfree(ctrlpriv); @@ -48,13 +54,24 @@ static int caam_probe(struct platform_device *pdev) { int d, ring, rspec; struct device *dev; - struct device_node *nprop, *np; + struct device_node *np; struct caam_ctrl __iomem *ctrl; struct caam_full __iomem *topregs; struct caam_drv_private *ctrlpriv; - struct caam_perfmon *perfmon; struct caam_deco **deco; u32 deconum; +#ifdef CONFIG_DEBUG_FS + struct caam_perfmon *perfmon; +#endif +#ifdef CONFIG_OF + struct device_node *nprop; +#else + struct resource *res; + char *rname, inst; +#endif +#ifdef CONFIG_ARM + int ret = 0; +#endif ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL); if (!ctrlpriv) @@ -63,22 +80,71 @@ static int caam_probe(struct platform_device *pdev) dev = &pdev->dev; dev_set_drvdata(dev, ctrlpriv); ctrlpriv->pdev = pdev; - nprop = pdev->dev.of_node; /* Get configuration properties from device tree */ /* First, get register page */ +#ifdef CONFIG_OF + nprop = pdev->dev.of_node; ctrl = of_iomap(nprop, 0); if (ctrl == NULL) { dev_err(dev, "caam: of_iomap() failed\n"); return -ENOMEM; } +#else + /* Get the named resource for the controller base address */ + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "iobase_caam"); + if (!res) { + dev_err(dev, "caam: invalid address resource type\n"); + return -ENODEV; + } + ctrl = ioremap(res->start, SZ_64K); + if (ctrl == NULL) { + dev_err(dev, "caam: ioremap() failed\n"); + return -ENOMEM; + } +#endif + ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; /* topregs used to derive pointers to CAAM sub-blocks only */ topregs = (struct caam_full __iomem *)ctrl; /* Get the IRQ of the controller (for security violations only) */ +#ifdef CONFIG_OF ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL); +#else + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, "irq_sec_vio"); + if (!res) { + dev_err(dev, "caam: invalid IRQ resource type\n"); + return -ENODEV; + } + ctrlpriv->secvio_irq = res->start; +#endif + +/* + * ARM targets tend to have clock control subsystems that can + * enable/disable clocking to our device. Turn clocking on to proceed + */ +#ifdef CONFIG_ARM + ctrlpriv->caam_clk = clk_get(&ctrlpriv->pdev->dev, "caam_clk"); + if (IS_ERR(ctrlpriv->caam_clk)) { + ret = PTR_ERR(ctrlpriv->caam_clk); + dev_err(&ctrlpriv->pdev->dev, + "can't identify CAAM bus clk: %d\n", ret); + return -ENODEV; + } + + ret = clk_enable(ctrlpriv->caam_clk); + if (ret < 0) { + dev_err(&pdev->dev, "can't enable CAAM bus clock: %d\n", ret); + return -ENODEV; + } + + pr_debug("%s caam_clk:%d\n", __func__, + (int)clk_get_rate(ctrlpriv->caam_clk)); +#endif /* * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, @@ -87,8 +153,11 @@ static int caam_probe(struct platform_device *pdev) setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + /* Set DMA masks according to platform ranging */ if (sizeof(dma_addr_t) == sizeof(u64)) dma_set_mask(dev, DMA_BIT_MASK(36)); + else + dma_set_mask(dev, DMA_BIT_MASK(32)); /* Find out how many DECOs are present */ deconum = (rd_reg64(&topregs->ctrl.perfmon.cha_num) & @@ -100,15 +169,41 @@ static int caam_probe(struct platform_device *pdev) deco = (struct caam_deco __force **)&topregs->deco; for (d = 0; d < deconum; d++) ctrlpriv->deco[d] = deco[d]; - /* * Detect and enable JobRs * First, find out how many ring spec'ed, allocate references * for all, then go probe each one. */ rspec = 0; +#ifdef CONFIG_OF for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") rspec++; +#else + np = NULL; + + /* Build the name of the IRQ platform resources to identify */ + rname = kzalloc(strlen(JR_IRQRES_NAME_ROOT) + 1, 0); + if (rname == NULL) { + iounmap(&topregs->ctrl); + return -ENOMEM; + } + + /* + * Emulate behavor of for_each_compatible_node() for non OF targets + * Identify all IRQ platform resources present + */ + for (d = 0; d < 4; d++) { + rname[0] = 0; + inst = '0' + d; + strcat(rname, JR_IRQRES_NAME_ROOT); + strncat(rname, &inst, 1); + res = platform_get_resource_byname(pdev, + IORESOURCE_IRQ, rname); + if (res) + rspec++; + } + kfree(rname); +#endif ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL); if (ctrlpriv->jrdev == NULL) { iounmap(&topregs->ctrl); @@ -117,7 +212,11 @@ static int caam_probe(struct platform_device *pdev) ring = 0; ctrlpriv->total_jobrs = 0; +#ifdef CONFIG_OF for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") { +#else + for (d = 0; d < rspec; d++) { +#endif caam_jr_probe(pdev, np, ring); ctrlpriv->total_jobrs++; ring++; @@ -164,52 +263,52 @@ static int caam_probe(struct platform_device *pdev) /* Controller-level - performance monitor counters */ ctrlpriv->ctl_rq_dequeued = debugfs_create_u64("rq_dequeued", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->req_dequeued); ctrlpriv->ctl_ob_enc_req = debugfs_create_u64("ob_rq_encrypted", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ob_enc_req); ctrlpriv->ctl_ib_dec_req = debugfs_create_u64("ib_rq_decrypted", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ib_dec_req); ctrlpriv->ctl_ob_enc_bytes = debugfs_create_u64("ob_bytes_encrypted", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ob_enc_bytes); ctrlpriv->ctl_ob_prot_bytes = debugfs_create_u64("ob_bytes_protected", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ob_prot_bytes); ctrlpriv->ctl_ib_dec_bytes = debugfs_create_u64("ib_bytes_decrypted", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ib_dec_bytes); ctrlpriv->ctl_ib_valid_bytes = debugfs_create_u64("ib_bytes_validated", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->ib_valid_bytes); /* Controller level - global status values */ ctrlpriv->ctl_faultaddr = debugfs_create_u64("fault_addr", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->faultaddr); ctrlpriv->ctl_faultdetail = debugfs_create_u32("fault_detail", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->faultdetail); ctrlpriv->ctl_faultstatus = debugfs_create_u32("fault_status", - S_IFCHR | S_IRUSR | S_IRGRP | S_IROTH, + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &perfmon->status); /* Internal covering keys (useful in non-secure mode only) */ ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0]; ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_kek = debugfs_create_blob("kek", - S_IFCHR | S_IRUSR | + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &ctrlpriv->ctl_kek_wrap); @@ -217,7 +316,7 @@ static int caam_probe(struct platform_device *pdev) ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0]; ctrlpriv->ctl_tkek_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_tkek = debugfs_create_blob("tkek", - S_IFCHR | S_IRUSR | + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &ctrlpriv->ctl_tkek_wrap); @@ -225,14 +324,27 @@ static int caam_probe(struct platform_device *pdev) ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0]; ctrlpriv->ctl_tdsk_wrap.size = KEK_KEY_SIZE * sizeof(u32); ctrlpriv->ctl_tdsk = debugfs_create_blob("tdsk", - S_IFCHR | S_IRUSR | + S_IRUSR | S_IRGRP | S_IROTH, ctrlpriv->ctl, &ctrlpriv->ctl_tdsk_wrap); #endif + +/* + * Non OF configurations use plaform_device, and therefore cannot simply + * go and get a device node by name, which the algapi module startup code + * assumes is possible. Therefore, non OF configurations will have to + * start up the API code explicitly, and forego modularization + */ +#ifndef CONFIG_OF + /* FIXME: check status */ + caam_algapi_startup(pdev); +#endif + return 0; } +#ifdef CONFIG_OF static struct of_device_id caam_match[] = { { .compatible = "fsl,sec-v4.0", @@ -240,12 +352,17 @@ static struct of_device_id caam_match[] = { {}, }; MODULE_DEVICE_TABLE(of, caam_match); +#endif /* CONFIG_OF */ static struct platform_driver caam_driver = { .driver = { .name = "caam", .owner = THIS_MODULE, +#ifdef CONFIG_OF .of_match_table = caam_match, +#else + +#endif }, .probe = caam_probe, .remove = __devexit_p(caam_remove), @@ -253,12 +370,20 @@ static struct platform_driver caam_driver = { static int __init caam_base_init(void) { +#ifdef CONFIG_OF + return of_register_platform_driver(&caam_driver); +#else return platform_driver_register(&caam_driver); +#endif } static void __exit caam_base_exit(void) { +#ifdef CONFIG_OF + return of_unregister_platform_driver(&caam_driver); +#else return platform_driver_unregister(&caam_driver); +#endif } module_init(caam_base_init); diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h index 46915800c26f..1e5d54c72aa8 100644 --- a/drivers/crypto/caam/desc_constr.h +++ b/drivers/crypto/caam/desc_constr.h @@ -1,7 +1,7 @@ /* * caam descriptor construction helper functions * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. */ #include "desc.h" @@ -9,7 +9,7 @@ #define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) #define CAAM_PTR_SZ sizeof(dma_addr_t) -#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * 64) +#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #ifdef DEBUG #define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\ @@ -18,6 +18,9 @@ #define PRINT_POS #endif +#define SET_OK_PROP_ERRORS (IMMEDIATE | LDST_CLASS_DECO | \ + LDST_SRCDST_WORD_DECOCTRL | \ + (LDOFF_CHG_SHARE_OK_PROP << LDST_OFFSET_SHIFT)) #define DISABLE_AUTO_INFO_FIFO (IMMEDIATE | LDST_CLASS_DECO | \ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_DISABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) @@ -203,3 +206,56 @@ static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \ append_cmd(desc, immediate); \ } APPEND_CMD_RAW_IMM(load, LOAD, u32); + +/* + * Append math command. Only the last part of destination and source need to + * be specified + */ +#define APPEND_MATH(op, desc, dest, src_0, src_1, len) \ +append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \ + MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32) (len & MATH_LEN_MASK)); + +#define append_math_add(desc, dest, src0, src1, len) \ + APPEND_MATH(ADD, desc, dest, src0, src1, len) +#define append_math_sub(desc, dest, src0, src1, len) \ + APPEND_MATH(SUB, desc, dest, src0, src1, len) +#define append_math_add_c(desc, dest, src0, src1, len) \ + APPEND_MATH(ADDC, desc, dest, src0, src1, len) +#define append_math_sub_b(desc, dest, src0, src1, len) \ + APPEND_MATH(SUBB, desc, dest, src0, src1, len) +#define append_math_and(desc, dest, src0, src1, len) \ + APPEND_MATH(AND, desc, dest, src0, src1, len) +#define append_math_or(desc, dest, src0, src1, len) \ + APPEND_MATH(OR, desc, dest, src0, src1, len) +#define append_math_xor(desc, dest, src0, src1, len) \ + APPEND_MATH(XOR, desc, dest, src0, src1, len) +#define append_math_lshift(desc, dest, src0, src1, len) \ + APPEND_MATH(LSHIFT, desc, dest, src0, src1, len) +#define append_math_rshift(desc, dest, src0, src1, len) \ + APPEND_MATH(RSHIFT, desc, dest, src0, src1, len) + +/* Exactly one source is IMM. Data is passed in as u32 value */ +#define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \ +do { \ + APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \ + append_cmd(desc, data); \ +} while (0); + +#define append_math_add_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data) +#define append_math_sub_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUB, desc, dest, src0, src1, data) +#define append_math_add_c_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(ADDC, desc, dest, src0, src1, data) +#define append_math_sub_b_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(SUBB, desc, dest, src0, src1, data) +#define append_math_and_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(AND, desc, dest, src0, src1, data) +#define append_math_or_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(OR, desc, dest, src0, src1, data) +#define append_math_xor_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(XOR, desc, dest, src0, src1, data) +#define append_math_lshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data) +#define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \ + APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data) diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h index a34be01b0b29..19e4f25c25a8 100644 --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h @@ -2,7 +2,7 @@ * CAAM/SEC 4.x driver backend * Private/internal definitions between modules * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. * */ @@ -26,6 +26,23 @@ #define JOBR_INTC_COUNT_THLD 0 #endif +#ifndef CONFIG_OF +#define JR_IRQRES_NAME_ROOT "irq_jr" +#define JR_MEMRES_NAME_ROOT "offset_jr" +#endif + +#ifdef CONFIG_ARM +/* + * FIXME: ARM tree doesn't seem to provide this, ergo it seems to be + * in "platform limbo". Find a better place, perhaps. + */ +static inline void irq_dispose_mapping(unsigned int virq) +{ + return; +} +#endif + + /* * Storage for tracking each in-process entry moving across a ring * Each entry on an output ring needs one of these @@ -91,6 +108,10 @@ struct caam_drv_private { /* list of registered crypto algorithms (mk generic context handle?) */ struct list_head alg_list; +#ifdef CONFIG_ARM + struct clk *caam_clk; +#endif + /* * debugfs entries for developer view into driver/device * variables at runtime. @@ -108,6 +129,7 @@ struct caam_drv_private { #endif }; -void caam_jr_algapi_init(struct device *dev); -void caam_jr_algapi_remove(struct device *dev); +void caam_algapi_shutdown(struct platform_device *pdev); +int caam_algapi_startup(struct platform_device *pdev); + #endif /* INTERN_H */ diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c index 340fa322c0f0..280aaaa3d4d4 100644 --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c @@ -2,7 +2,7 @@ * CAAM/SEC 4.x transport/backend driver * JobR backend functionality * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright 2008-2012 Freescale Semiconductor, Inc. */ #include "compat.h" @@ -57,9 +57,15 @@ static void caam_jr_dequeue(unsigned long devarg) struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); u32 *userdesc, userstatus; + dma_addr_t outbusaddr; void *userarg; unsigned long flags; + outbusaddr = rd_reg64(&jrp->rregs->outring_base); + dma_sync_single_for_cpu(dev, outbusaddr, + sizeof(struct jr_outentry) * JOBR_DEPTH, + DMA_FROM_DEVICE); + spin_lock_irqsave(&jrp->outlock, flags); head = ACCESS_ONCE(jrp->head); @@ -73,7 +79,6 @@ static void caam_jr_dequeue(unsigned long devarg) sw_idx = (tail + i) & (JOBR_DEPTH - 1); smp_read_barrier_depends(); - if (jrp->outring[hw_idx].desc == jrp->entinfo[sw_idx].desc_addr_dma) break; /* found */ @@ -240,7 +245,7 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, struct caam_jrentry_info *head_entry; unsigned long flags; int head, tail, desc_size; - dma_addr_t desc_dma; + dma_addr_t desc_dma, inpbusaddr; desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32); desc_dma = dma_map_single(dev, desc, desc_size, DMA_TO_DEVICE); @@ -249,6 +254,12 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, return -EIO; } + dma_sync_single_for_device(dev, desc_dma, desc_size, DMA_TO_DEVICE); + + inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); + dma_sync_single_for_device(dev, inpbusaddr, + sizeof(dma_addr_t) * JOBR_DEPTH, + DMA_TO_DEVICE); spin_lock_irqsave(&jrp->inplock, flags); head = jrp->head; @@ -270,6 +281,10 @@ int caam_jr_enqueue(struct device *dev, u32 *desc, jrp->inpring[jrp->inp_ring_write_index] = desc_dma; + dma_sync_single_for_device(dev, inpbusaddr, + sizeof(dma_addr_t) * JOBR_DEPTH, + DMA_TO_DEVICE); + smp_wmb(); jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) & @@ -343,7 +358,7 @@ static int caam_jr_init(struct device *dev) (unsigned long)dev); error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED, - "caam-jobr", dev); + "caam-jr", dev); if (error) { dev_err(dev, "can't connect JobR %d interrupt (%d)\n", jrp->ridx, jrp->irq); @@ -377,7 +392,7 @@ static int caam_jr_init(struct device *dev) /* Setup rings */ inpbusaddr = dma_map_single(dev, jrp->inpring, sizeof(u32 *) * JOBR_DEPTH, - DMA_BIDIRECTIONAL); + DMA_TO_DEVICE); if (dma_mapping_error(dev, inpbusaddr)) { dev_err(dev, "caam_jr_init(): can't map input ring\n"); kfree(jrp->inpring); @@ -388,12 +403,12 @@ static int caam_jr_init(struct device *dev) outbusaddr = dma_map_single(dev, jrp->outring, sizeof(struct jr_outentry) * JOBR_DEPTH, - DMA_BIDIRECTIONAL); + DMA_FROM_DEVICE); if (dma_mapping_error(dev, outbusaddr)) { dev_err(dev, "caam_jr_init(): can't map output ring\n"); dma_unmap_single(dev, inpbusaddr, sizeof(u32 *) * JOBR_DEPTH, - DMA_BIDIRECTIONAL); + DMA_TO_DEVICE); kfree(jrp->inpring); kfree(jrp->outring); kfree(jrp->entinfo); @@ -446,11 +461,9 @@ int caam_jr_shutdown(struct device *dev) outbusaddr = rd_reg64(&jrp->rregs->outring_base); dma_unmap_single(dev, outbusaddr, sizeof(struct jr_outentry) * JOBR_DEPTH, - DMA_BIDIRECTIONAL); + DMA_FROM_DEVICE); dma_unmap_single(dev, inpbusaddr, sizeof(u32 *) * JOBR_DEPTH, - DMA_BIDIRECTIONAL); - kfree(jrp->outring); - kfree(jrp->inpring); + DMA_TO_DEVICE); kfree(jrp->entinfo); return ret; @@ -467,8 +480,12 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np, struct platform_device *jr_pdev; struct caam_drv_private *ctrlpriv; struct caam_drv_private_jr *jrpriv; - u32 *jroffset; int error; + /* FIXME: perhaps "struct resource *" for OF and non? */ + u32 *jroffset, *irqres; +#ifndef CONFIG_OF + char *rname, rinst; +#endif ctrldev = &pdev->dev; ctrlpriv = dev_get_drvdata(ctrldev); @@ -489,12 +506,35 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np, * need to add in the offset to this JobR. Don't know if I * like this long-term, but it'll run */ +#ifdef CONFIG_OF jroffset = (u32 *)of_get_property(np, "reg", NULL); +#else + rname = kmalloc(strlen(JR_MEMRES_NAME_ROOT) + 1, 0); + if (rname == NULL) { + dev_err(ctrldev, "can't alloc resource detection buffer %d\n", + ring); + kfree(jrpriv); + return -ENOMEM; + } + rname[0] = 0; + rinst = '0' + ring; + strcat(rname, JR_MEMRES_NAME_ROOT); + strncat(rname, &rinst, 1); + jroffset = (u32 *)platform_get_resource_byname(pdev, IORESOURCE_MEM, + rname); + kfree(rname); +#endif jrpriv->rregs = (struct caam_job_ring __iomem *)((void *)ctrlpriv->ctrl + *jroffset); /* Build a local dev for each detected queue */ +#ifdef CONFIG_OF jr_pdev = of_platform_device_create(np, NULL, ctrldev); +#else + jr_pdev = platform_device_register_data(ctrldev, "caam_jr", ring, + jrpriv, + sizeof(struct caam_drv_private_jr)); +#endif if (jr_pdev == NULL) { kfree(jrpriv); return -EINVAL; @@ -504,7 +544,24 @@ int caam_jr_probe(struct platform_device *pdev, struct device_node *np, ctrlpriv->jrdev[ring] = jrdev; /* Identify the interrupt */ +#ifdef CONFIG_OF jrpriv->irq = of_irq_to_resource(np, 0, NULL); +#else + rname = kmalloc(strlen(JR_IRQRES_NAME_ROOT) + 1, 0); + if (rname == NULL) { + dev_err(ctrldev, "can't alloc resource detection buffer %d\n", + ring); + kfree(jrpriv); + return -ENOMEM; + } + rname[0] = 0; + strcat(rname, JR_IRQRES_NAME_ROOT); + strncat(rname, &rinst, 1); + irqres = (u32 *)platform_get_resource_byname(pdev, IORESOURCE_IRQ, + rname); + jrpriv->irq = *irqres; + kfree(rname); +#endif /* Now do the platform independent part */ error = caam_jr_init(jrdev); /* now turn on hardware */ diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h index aee394e39056..888706d2801c 100644 --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h @@ -1,7 +1,7 @@ /* * CAAM hardware register-level view * - * Copyright 2008-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. */ #ifndef REGS_H @@ -74,15 +74,21 @@ #endif #else #ifdef __LITTLE_ENDIAN -#define wr_reg32(reg, data) __raw_writel(reg, data) -#define rd_reg32(reg) __raw_readl(reg) +#define wr_reg32(reg, data) writel(data, reg) +#define rd_reg32(reg) readl(reg) #ifdef CONFIG_64BIT -#define wr_reg64(reg, data) __raw_writeq(reg, data) -#define rd_reg64(reg) __raw_readq(reg) +#define wr_reg64(reg, data) writeq(data, reg) +#define rd_reg64(reg) readq(reg) #endif #endif #endif +#ifdef CONFIG_ARM +/* These are common macros for Power, put here for ARMs */ +#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) +#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) +#endif + #ifndef CONFIG_64BIT static inline void wr_reg64(u64 __iomem *reg, u64 data) { diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c index 306dcdd0dc38..a4ed05342168 100644 --- a/drivers/dma/imx-sdma.c +++ b/drivers/dma/imx-sdma.c @@ -340,9 +340,9 @@ static int sdma_config_ownership(struct sdma_channel *sdmac, if (event_override && mcu_override && dsp_override) return -EINVAL; - evt = __raw_readl(sdma->regs + SDMA_H_EVTOVR); - mcu = __raw_readl(sdma->regs + SDMA_H_HOSTOVR); - dsp = __raw_readl(sdma->regs + SDMA_H_DSPOVR); + evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); + mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); + dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); if (dsp_override) dsp &= ~(1 << channel); @@ -359,9 +359,9 @@ static int sdma_config_ownership(struct sdma_channel *sdmac, else mcu |= (1 << channel); - __raw_writel(evt, sdma->regs + SDMA_H_EVTOVR); - __raw_writel(mcu, sdma->regs + SDMA_H_HOSTOVR); - __raw_writel(dsp, sdma->regs + SDMA_H_DSPOVR); + writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); + writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); + writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); return 0; } @@ -378,7 +378,7 @@ static int sdma_run_channel(struct sdma_channel *sdmac) init_completion(&sdmac->done); wmb(); - __raw_writel(1 << channel, sdma->regs + SDMA_H_START); + writel_relaxed(1 << channel, sdma->regs + SDMA_H_START); ret = wait_for_completion_timeout(&sdmac->done, HZ); @@ -421,9 +421,9 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event) u32 val; u32 chnenbl = chnenbl_ofs(sdma, event); - val = __raw_readl(sdma->regs + chnenbl); + val = readl_relaxed(sdma->regs + chnenbl); val |= (1 << channel); - __raw_writel(val, sdma->regs + chnenbl); + writel_relaxed(val, sdma->regs + chnenbl); } static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) @@ -433,9 +433,9 @@ static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event) u32 chnenbl = chnenbl_ofs(sdma, event); u32 val; - val = __raw_readl(sdma->regs + chnenbl); + val = readl_relaxed(sdma->regs + chnenbl); val &= ~(1 << channel); - __raw_writel(val, sdma->regs + chnenbl); + writel_relaxed(val, sdma->regs + chnenbl); } static void sdma_handle_channel_loop(struct sdma_channel *sdmac) @@ -512,8 +512,8 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id) struct sdma_engine *sdma = dev_id; u32 stat; - stat = __raw_readl(sdma->regs + SDMA_H_INTR); - __raw_writel(stat, sdma->regs + SDMA_H_INTR); + stat = readl_relaxed(sdma->regs + SDMA_H_INTR); + writel_relaxed(stat, sdma->regs + SDMA_H_INTR); while (stat) { int channel = fls(stat) - 1; @@ -673,7 +673,7 @@ static void sdma_disable_channel(struct sdma_channel *sdmac) struct sdma_engine *sdma = sdmac->sdma; int channel = sdmac->channel; - __raw_writel(1 << channel, sdma->regs + SDMA_H_STATSTOP); + writel_relaxed(1 << channel, sdma->regs + SDMA_H_STATSTOP); sdmac->status = DMA_ERROR; } @@ -778,7 +778,7 @@ static int sdma_set_channel_priority(struct sdma_channel *sdmac, return -EINVAL; } - __raw_writel(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); + writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); return 0; } @@ -817,7 +817,7 @@ out: static void sdma_enable_channel(struct sdma_engine *sdma, int channel) { wmb(); - __raw_writel(1 << channel, sdma->regs + SDMA_H_START); + writel(1 << channel, sdma->regs + SDMA_H_START); } static dma_cookie_t sdma_assign_cookie(struct sdma_channel *sdmac) @@ -1246,7 +1246,7 @@ static int __init sdma_init(struct sdma_engine *sdma) clk_enable(sdma->clk); /* Be sure SDMA has not started yet */ - __raw_writel(0, sdma->regs + SDMA_H_C0PTR); + writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); sdma->channel_control = dma_alloc_coherent(NULL, MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + @@ -1269,11 +1269,11 @@ static int __init sdma_init(struct sdma_engine *sdma) /* disable all channels */ for (i = 0; i < sdma->num_events; i++) - __raw_writel(0, sdma->regs + chnenbl_ofs(sdma, i)); + writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); /* All channels have priority 0 */ for (i = 0; i < MAX_DMA_CHANNELS; i++) - __raw_writel(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); + writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); ret = sdma_request_channel(&sdma->channel[0]); if (ret) @@ -1282,16 +1282,16 @@ static int __init sdma_init(struct sdma_engine *sdma) sdma_config_ownership(&sdma->channel[0], false, true, false); /* Set Command Channel (Channel Zero) */ - __raw_writel(0x4050, sdma->regs + SDMA_CHN0ADDR); + writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); /* Set bits of CONFIG register but with static context switching */ /* FIXME: Check whether to set ACR bit depending on clock ratios */ - __raw_writel(0, sdma->regs + SDMA_H_CONFIG); + writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); - __raw_writel(ccb_phys, sdma->regs + SDMA_H_C0PTR); + writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); /* Set bits of CONFIG register with given context switching mode */ - __raw_writel(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); + writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG); /* Initializes channel's priorities */ sdma_set_channel_priority(&sdma->channel[0], 7); diff --git a/drivers/dma/pxp/pxp_dma.c b/drivers/dma/pxp/pxp_dma.c index eb5b4fb60306..ddd1c0cd192d 100644 --- a/drivers/dma/pxp/pxp_dma.c +++ b/drivers/dma/pxp/pxp_dma.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -180,6 +180,7 @@ static bool is_yuv(u32 pix_fmt) (pix_fmt == PXP_PIX_FMT_YUV444) | (pix_fmt == PXP_PIX_FMT_NV12) | (pix_fmt == PXP_PIX_FMT_GREY) | + (pix_fmt == PXP_PIX_FMT_GY04) | (pix_fmt == PXP_PIX_FMT_YVU410P) | (pix_fmt == PXP_PIX_FMT_YUV410P) | (pix_fmt == PXP_PIX_FMT_YVU420P) | @@ -215,6 +216,9 @@ static void pxp_set_ctrl(struct pxps *pxp) case PXP_PIX_FMT_GREY: fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420; break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV420; + break; case PXP_PIX_FMT_YUV422P: fmt_ctrl = BV_PXP_CTRL_S0_FORMAT__YUV422; break; @@ -243,6 +247,9 @@ static void pxp_set_ctrl(struct pxps *pxp) case PXP_PIX_FMT_GREY: fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC8; break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_CTRL_OUTBUF_FORMAT__MONOC4; + break; default: fmt_ctrl = 0; } @@ -620,6 +627,14 @@ static void pxp_set_s0buf(struct pxps *pxp) __raw_writel(U, pxp->base + HW_PXP_S0UBUF); __raw_writel(V, pxp->base + HW_PXP_S0VBUF); } + + /* TODO: only support RGB565, Y8 , Y4 */ + if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) + __raw_writel(s0_params->width, pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(s0_params->width >> 1, pxp->base + HW_PXP_PS_PITCH); + else + __raw_writel(s0_params->width * 2, pxp->base + HW_PXP_PS_PITCH); } /** diff --git a/drivers/dma/pxp/pxp_dma_v2.c b/drivers/dma/pxp/pxp_dma_v2.c index 3fadd9a5f762..ceb72edbd39e 100644 --- a/drivers/dma/pxp/pxp_dma_v2.c +++ b/drivers/dma/pxp/pxp_dma_v2.c @@ -220,6 +220,7 @@ static bool is_yuv(u32 pix_fmt) (pix_fmt == PXP_PIX_FMT_YUV444) | (pix_fmt == PXP_PIX_FMT_NV12) | (pix_fmt == PXP_PIX_FMT_GREY) | + (pix_fmt == PXP_PIX_FMT_GY04) | (pix_fmt == PXP_PIX_FMT_YVU410P) | (pix_fmt == PXP_PIX_FMT_YUV410P) | (pix_fmt == PXP_PIX_FMT_YVU420P) | @@ -257,6 +258,9 @@ static void pxp_set_ctrl(struct pxps *pxp) case PXP_PIX_FMT_GREY: fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y8; break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__Y4; + break; case PXP_PIX_FMT_YUV422P: fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV422; break; @@ -287,6 +291,9 @@ static void pxp_set_ctrl(struct pxps *pxp) case PXP_PIX_FMT_GREY: fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y8; break; + case PXP_PIX_FMT_GY04: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__Y4; + break; default: fmt_ctrl = 0; } @@ -697,9 +704,11 @@ static void pxp_set_s0buf(struct pxps *pxp) __raw_writel(V, pxp->base + HW_PXP_PS_VBUF); } - /* TODO: only support RGB565, Y8 */ + /* TODO: only support RGB565, Y8, Y4 */ if (s0_params->pixel_fmt == PXP_PIX_FMT_GREY) __raw_writel(s0_params->width, pxp->base + HW_PXP_PS_PITCH); + else if (s0_params->pixel_fmt == PXP_PIX_FMT_GY04) + __raw_writel(s0_params->width >> 1, pxp->base + HW_PXP_PS_PITCH); else __raw_writel(s0_params->width * 2, pxp->base + HW_PXP_PS_PITCH); } diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index bf8d1797589c..bf002d471b1f 100755 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -187,6 +187,18 @@ config TOUCHSCREEN_EGALAX To compile this driver as a module, choose M here: the module will be called egalax_ts. +config TOUCHSCREEN_ELAN + tristate "ELAN touchscreen input driver" + depends on I2C + help + Say Y here if you have an I2C ELAN touchscreen + attached. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called elan-touch. + config TOUCHSCREEN_FUJITSU tristate "Fujitsu serial touchscreen" select SERIO diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index f61dfe88bc62..28ac2d2c81bd 100755 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -66,3 +66,4 @@ obj-$(CONFIG_TOUCHSCREEN_P1003) += p1003_ts.o obj-$(CONFIG_TOUCHSCREEN_TPS6507X) += tps6507x-ts.o obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o +obj-$(CONFIG_TOUCHSCREEN_ELAN) += elan_ts.o diff --git a/drivers/input/touchscreen/elan_ts.c b/drivers/input/touchscreen/elan_ts.c new file mode 100644 index 000000000000..7edd87d6cd1b --- /dev/null +++ b/drivers/input/touchscreen/elan_ts.c @@ -0,0 +1,387 @@ +/* + * Copyright (C) 2007-2008 HTC Corporation. + * + * This driver is adapted from elan8232_i2c.c written by Shan-Fu Chiou + * <sfchiou@gmail.com> and Jay Tu <jay_tu@htc.com>. + * This driver is also adapted from the ELAN Touch Screen driver + * written by Stanley Zeng <stanley.zeng@emc.com.tw> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/input.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/init.h> +#include <linux/jiffies.h> +#include <linux/interrupt.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <linux/hrtimer.h> +#include <linux/gpio.h> + +static const char ELAN_TS_NAME[] = "elan-touch"; + +#define ELAN_TS_X_MAX 1088 +#define ELAN_TS_Y_MAX 768 +#define ELAN_USER_X_MAX 800 +#define ELAN_USER_Y_MAX 600 +#define IDX_PACKET_SIZE 8 + +enum { + hello_packet = 0x55, + idx_coordinate_packet = 0x5a, +}; + +enum { + idx_finger_state = 7, +}; + +static struct workqueue_struct *elan_wq; + +static struct elan_data { + int intr_gpio; + int use_irq; + struct hrtimer timer; + struct work_struct work; + struct i2c_client *client; + struct input_dev *input; + wait_queue_head_t wait; +} elan_touch_data; + +/*--------------------------------------------------------------*/ +static int elan_touch_detect_int_level(void) +{ + unsigned v; + v = gpio_get_value(elan_touch_data.intr_gpio); + + return v; +} + +static int __elan_touch_poll(struct i2c_client *client) +{ + int status = 0, retry = 20; + + do { + status = elan_touch_detect_int_level(); + retry--; + mdelay(20); + } while (status == 1 && retry > 0); + + return (status == 0 ? 0 : -ETIMEDOUT); +} + +static int elan_touch_poll(struct i2c_client *client) +{ + return __elan_touch_poll(client); +} + +static int __hello_packet_handler(struct i2c_client *client) +{ + int rc; + uint8_t buf_recv[4] = { 0 }; + + rc = elan_touch_poll(client); + + if (rc < 0) { + return -EINVAL; + } + + rc = i2c_master_recv(client, buf_recv, 4); + + if (rc != 4) { + return rc; + } else { + int i; + printk("hello packet: [0x%02x 0x%02x 0x%02x 0x%02x]\n", + buf_recv[0], buf_recv[1], buf_recv[2], buf_recv[3]); + + for (i = 0; i < 4; i++) + if (buf_recv[i] != hello_packet) + return -EINVAL; + } + + return 0; +} + +static inline int elan_touch_parse_xy(uint8_t *data, uint16_t *x, + uint16_t *y) +{ + *x = (data[0] & 0xf0); + *x <<= 4; + *x |= data[1]; + if (*x >= ELAN_TS_X_MAX) + *x = ELAN_TS_X_MAX; + *x = ((((ELAN_TS_X_MAX - + *x) * 1000) / ELAN_TS_X_MAX) * ELAN_USER_X_MAX) / 1000; + + *y = (data[0] & 0x0f); + *y <<= 8; + *y |= data[2]; + if (*y >= ELAN_TS_Y_MAX) + *y = ELAN_TS_Y_MAX; + *y = ((((ELAN_TS_Y_MAX - + *y) * 1000) / ELAN_TS_Y_MAX) * ELAN_USER_Y_MAX) / 1000; + + return 0; +} + +/* __elan_touch_init -- hand shaking with touch panel + * + * 1.recv hello packet + */ +static int __elan_touch_init(struct i2c_client *client) +{ + int rc; + rc = __hello_packet_handler(client); + if (rc < 0) + goto hand_shake_failed; + +hand_shake_failed: + return rc; +} + +static int elan_touch_recv_data(struct i2c_client *client, uint8_t * buf) +{ + int rc, bytes_to_recv = IDX_PACKET_SIZE; + + if (buf == NULL) + return -EINVAL; + + memset(buf, 0, bytes_to_recv); + rc = i2c_master_recv(client, buf, bytes_to_recv); + if (rc != bytes_to_recv) { + return -EINVAL; + } + + return rc; +} + +static void elan_touch_report_data(struct i2c_client *client, uint8_t * buf) +{ + switch (buf[0]) { + case idx_coordinate_packet: + { + uint16_t x1, x2, y1, y2; + uint8_t finger_stat; + + finger_stat = (buf[idx_finger_state] & 0x06) >> 1; + + if (finger_stat == 0) { + input_report_key(elan_touch_data.input, BTN_TOUCH, 0); + input_report_key(elan_touch_data.input, BTN_2, 0); + } else if (finger_stat == 1) { + elan_touch_parse_xy(&buf[1], &x1, &y1); + input_report_abs(elan_touch_data.input, ABS_X, x1); + input_report_abs(elan_touch_data.input, ABS_Y, y1); + input_report_key(elan_touch_data.input, BTN_TOUCH, 1); + input_report_key(elan_touch_data.input, BTN_2, 0); + } else if (finger_stat == 2) { + elan_touch_parse_xy(&buf[1], &x1, &y1); + input_report_abs(elan_touch_data.input, ABS_X, x1); + input_report_abs(elan_touch_data.input, ABS_Y, y1); + input_report_key(elan_touch_data.input, BTN_TOUCH, 1); + elan_touch_parse_xy(&buf[4], &x2, &y2); + input_report_abs(elan_touch_data.input, ABS_HAT0X, x2); + input_report_abs(elan_touch_data.input, ABS_HAT0Y, y2); + input_report_key(elan_touch_data.input, BTN_2, 1); + } + input_sync(elan_touch_data.input); + break; + } + + default: + break; + } +} + +static void elan_touch_work_func(struct work_struct *work) +{ + int rc; + uint8_t buf[IDX_PACKET_SIZE] = { 0 }; + struct i2c_client *client = elan_touch_data.client; + + if (elan_touch_detect_int_level()) + return; + + rc = elan_touch_recv_data(client, buf); + if (rc < 0) + return; + + elan_touch_report_data(client, buf); +} + +static irqreturn_t elan_touch_ts_interrupt(int irq, void *dev_id) +{ + queue_work(elan_wq, &elan_touch_data.work); + + return IRQ_HANDLED; +} + +static enum hrtimer_restart elan_touch_timer_func(struct hrtimer *timer) +{ + queue_work(elan_wq, &elan_touch_data.work); + hrtimer_start(&elan_touch_data.timer, ktime_set(0, 12500000), + HRTIMER_MODE_REL); + + return HRTIMER_NORESTART; +} + +static int elan_touch_register_interrupt(struct i2c_client *client) +{ + int err = 0; + + if (client->irq) { + elan_touch_data.use_irq = 1; + err = + request_irq(client->irq, elan_touch_ts_interrupt, + IRQF_TRIGGER_FALLING, ELAN_TS_NAME, + &elan_touch_data); + + if (err < 0) { + printk("%s(%s): Can't allocate irq %d\n", __FILE__, + __func__, client->irq); + elan_touch_data.use_irq = 0; + } + } + + if (!elan_touch_data.use_irq) { + hrtimer_init(&elan_touch_data.timer, CLOCK_MONOTONIC, + HRTIMER_MODE_REL); + elan_touch_data.timer.function = elan_touch_timer_func; + hrtimer_start(&elan_touch_data.timer, ktime_set(1, 0), + HRTIMER_MODE_REL); + } + + printk("elan ts starts in %s mode.\n", + elan_touch_data.use_irq == 1 ? "interrupt" : "polling"); + + return 0; +} + +static int elan_touch_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err = 0; + + elan_wq = create_singlethread_workqueue("elan_wq"); + if (!elan_wq) { + err = -ENOMEM; + goto fail; + } + + elan_touch_data.client = client; + strlcpy(client->name, ELAN_TS_NAME, I2C_NAME_SIZE); + + INIT_WORK(&elan_touch_data.work, elan_touch_work_func); + + elan_touch_data.intr_gpio = irq_to_gpio(client->irq); + pr_debug("irq_to_gpio irq %d, gpio %d\n", client->irq, + elan_touch_data.intr_gpio); + + elan_touch_data.input = input_allocate_device(); + if (elan_touch_data.input == NULL) { + err = -ENOMEM; + goto fail; + } + + err = __elan_touch_init(client); + if (err < 0) { + printk("elan - Read Hello Packet Failed\n"); + goto fail; + } + + elan_touch_data.input->name = ELAN_TS_NAME; + elan_touch_data.input->id.bustype = BUS_I2C; + + set_bit(EV_SYN, elan_touch_data.input->evbit); + + set_bit(EV_KEY, elan_touch_data.input->evbit); + set_bit(BTN_TOUCH, elan_touch_data.input->keybit); + set_bit(BTN_2, elan_touch_data.input->keybit); + + set_bit(EV_ABS, elan_touch_data.input->evbit); + set_bit(ABS_X, elan_touch_data.input->absbit); + set_bit(ABS_Y, elan_touch_data.input->absbit); + set_bit(ABS_HAT0X, elan_touch_data.input->absbit); + set_bit(ABS_HAT0Y, elan_touch_data.input->absbit); + + input_set_abs_params(elan_touch_data.input, ABS_X, 0, ELAN_USER_X_MAX, + 0, 0); + input_set_abs_params(elan_touch_data.input, ABS_Y, 0, ELAN_USER_Y_MAX, + 0, 0); + input_set_abs_params(elan_touch_data.input, ABS_HAT0X, 0, + ELAN_USER_X_MAX, 0, 0); + input_set_abs_params(elan_touch_data.input, ABS_HAT0Y, 0, + ELAN_USER_Y_MAX, 0, 0); + + err = input_register_device(elan_touch_data.input); + if (err < 0) { + goto fail; + } + + elan_touch_register_interrupt(elan_touch_data.client); + + return 0; + +fail: + input_free_device(elan_touch_data.input); + if (elan_wq) + destroy_workqueue(elan_wq); + return err; +} + +static int elan_touch_remove(struct i2c_client *client) +{ + if (elan_wq) + destroy_workqueue(elan_wq); + + input_unregister_device(elan_touch_data.input); + + if (elan_touch_data.use_irq) + free_irq(client->irq, client); + else + hrtimer_cancel(&elan_touch_data.timer); + return 0; +} + +/* -------------------------------------------------------------------- */ +static const struct i2c_device_id elan_touch_id[] = { + {"elan-touch", 0}, + {} +}; + +static struct i2c_driver elan_touch_driver = { + .probe = elan_touch_probe, + .remove = elan_touch_remove, + .id_table = elan_touch_id, + .driver = { + .name = "elan-touch", + .owner = THIS_MODULE, + }, +}; + +static int __init elan_touch_init(void) +{ + return i2c_add_driver(&elan_touch_driver); +} + +static void __exit elan_touch_exit(void) +{ + i2c_del_driver(&elan_touch_driver); +} + +module_init(elan_touch_init); +module_exit(elan_touch_exit); + +MODULE_AUTHOR("Stanley Zeng <stanley.zeng@emc.com.tw>"); +MODULE_DESCRIPTION("ELAN Touch Screen driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/input/touchscreen/max11801_ts.c b/drivers/input/touchscreen/max11801_ts.c index ca88d6823a98..48ee3600a03b 100755 --- a/drivers/input/touchscreen/max11801_ts.c +++ b/drivers/input/touchscreen/max11801_ts.c @@ -2,7 +2,7 @@ * Driver for MAXI MAX11801 - A Resistive touch screen controller with * i2c interface * - * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. * Author: Zhang Jiejing <jiejing.zhang@freescale.com> * * Based on mcs5000_ts.c @@ -38,6 +38,8 @@ #include <linux/input.h> #include <linux/slab.h> #include <linux/bitops.h> +#include <linux/delay.h> + /* Register Address define */ #define GENERNAL_STATUS_REG 0x00 @@ -53,13 +55,32 @@ #define AUX_MESURE_CONF_REG 0x0a #define OP_MODE_CONF_REG 0x0b +#define Panel_Setup_X (0x69 << 1) +#define Panel_Setup_Y (0x6b << 1) + +#define XY_combined_measurement (0x70 << 1) +#define X_measurement (0x78 << 1) +#define Y_measurement (0x7a << 1) +#define AUX_measurement (0x76 << 1) + /* FIFO is found only in max11800 and max11801 */ #define FIFO_RD_CMD (0x50 << 1) #define MAX11801_FIFO_INT (1 << 2) #define MAX11801_FIFO_OVERFLOW (1 << 3) +#define MAX11801_EDGE_INT (1 << 1) + +#define FIFO_RD_X_MSB (0x52 << 1) +#define FIFO_RD_X_LSB (0x53 << 1) +#define FIFO_RD_Y_MSB (0x54 << 1) +#define FIFO_RD_Y_LSB (0x55 << 1) +#define FIFO_RD_AUX_MSB (0x5a << 1) +#define FIFO_RD_AUX_LSB (0x5b << 1) #define XY_BUFSIZE 4 #define XY_BUF_OFFSET 4 +#define X_BUFSIZE 2 +#define Y_BUFSIZE 2 +#define AUX_BUFSIZE 2 #define MAX11801_MAX_X 0xfff #define MAX11801_MAX_Y 0xfff @@ -83,6 +104,54 @@ struct max11801_data { struct i2c_client *client; struct input_dev *input_dev; }; +struct i2c_client *max11801_client; +unsigned int max11801_workmode; + +static int max11801_dcm_write_command(struct i2c_client *client, int command) +{ + return i2c_smbus_write_byte(client, command); +} + +static u32 max11801_dcm_sample_aux(struct i2c_client *client) +{ + u8 temp_buf; + u8 aux_buf[AUX_BUFSIZE]; + int ret; + int aux = 0; + u32 sample_data = 0; + /* AUX_measurement*/ + max11801_dcm_write_command(client, AUX_measurement); + mdelay(5); + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_MSB, + 1, &temp_buf); + aux_buf[0] = temp_buf; + if (ret < 1) + printk(KERN_DEBUG "FIFO_RD_AUX_MSB read fails\n"); + mdelay(5); + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_AUX_LSB, + 1, &temp_buf); + aux_buf[1] = temp_buf; + if (ret < 1) + printk(KERN_DEBUG "FIFO_RD_AUX_LSB read fails\n"); + aux = (aux_buf[0] << 4) + + (aux_buf[1] >> 4); + /* + voltage = (9170*aux)/7371; + voltage is (26.2*3150*aux)/(16.2*0xFFF) + V(aux)=3150*sample/0xFFF,V(battery)=212*V(aux)/81 + sample_data = (14840*aux)/7371-1541; + */ + sample_data = (14840*aux)/7371; + return sample_data; +} + +u32 max11801_read_adc(void) +{ + u32 adc_data; + adc_data = max11801_dcm_sample_aux(max11801_client); + return adc_data; +} +EXPORT_SYMBOL_GPL(max11801_read_adc); static u8 read_register(struct i2c_client *client, int addr) { @@ -109,76 +178,166 @@ static irqreturn_t max11801_ts_interrupt(int irq, void *dev_id) struct i2c_client *client = data->client; int status, i, ret; u8 buf[XY_BUFSIZE]; + u8 x_buf[X_BUFSIZE]; + u8 y_buf[Y_BUFSIZE]; + u8 temp_buf[1]; int x = -1; int y = -1; status = read_register(data->client, GENERNAL_STATUS_REG); - - if (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) { - status = read_register(data->client, GENERNAL_STATUS_REG); - - ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD, - XY_BUFSIZE, buf); - - /* - * We should get 4 bytes buffer that contains X,Y - * and event tag - */ - if (ret < XY_BUFSIZE) - goto out; - - for (i = 0; i < XY_BUFSIZE; i += XY_BUFSIZE / 2) { - if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_X_TAG) - x = (buf[i] << XY_BUF_OFFSET) + - (buf[i + 1] >> XY_BUF_OFFSET); - else if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG) - y = (buf[i] << XY_BUF_OFFSET) + - (buf[i + 1] >> XY_BUF_OFFSET); - } - - if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK)) - goto out; - - switch (buf[1] & EVENT_TAG_MASK) { - case EVENT_INIT: - /* fall through */ - case EVENT_MIDDLE: - calibration_pointer(&x, &y); - input_report_abs(data->input_dev, ABS_X, x); - input_report_abs(data->input_dev, ABS_Y, y); - input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1); - input_sync(data->input_dev); - break; - - case EVENT_RELEASE: - input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0); - input_sync(data->input_dev); - break; - - case EVENT_FIFO_END: - break; - } - } + if (max11801_workmode == 0) { + if (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) { + status = read_register(data->client, GENERNAL_STATUS_REG); + + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD, + XY_BUFSIZE, buf); + + /* + * We should get 4 bytes buffer that contains X,Y + * and event tag + */ + if (ret < XY_BUFSIZE) + goto out; + + for (i = 0; i < XY_BUFSIZE; i += XY_BUFSIZE / 2) { + if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_X_TAG) + x = (buf[i] << XY_BUF_OFFSET) + + (buf[i + 1] >> XY_BUF_OFFSET); + else if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG) + y = (buf[i] << XY_BUF_OFFSET) + + (buf[i + 1] >> XY_BUF_OFFSET); + } + + if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK)) + goto out; + + switch (buf[1] & EVENT_TAG_MASK) { + case EVENT_INIT: + /* fall through */ + case EVENT_MIDDLE: + calibration_pointer(&x, &y); + input_report_abs(data->input_dev, ABS_X, x); + input_report_abs(data->input_dev, ABS_Y, y); + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1); + input_sync(data->input_dev); + break; + + case EVENT_RELEASE: + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0); + input_sync(data->input_dev); + break; + + case EVENT_FIFO_END: + break; + } + } out: - return IRQ_HANDLED; +return IRQ_HANDLED; + } + else if (max11801_workmode == 1) { + if (status & (MAX11801_EDGE_INT)) { + status = read_register(data->client, GENERNAL_STATUS_REG); + + /* X = panel setup*/ + max11801_dcm_write_command(client, Panel_Setup_X); + /* X_measurement*/ + max11801_dcm_write_command(client, X_measurement); + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_X_MSB, + 1, temp_buf); + x_buf[0] = temp_buf[0]; + if (ret < 1) + goto out2; + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_X_LSB, + 1, temp_buf); + x_buf[1] = temp_buf[0]; + if (ret < 1) + goto out2; + /* Y = panel setup*/ + max11801_dcm_write_command(client, Panel_Setup_Y); + /* Y_measurement*/ + max11801_dcm_write_command(client, Y_measurement); + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_Y_MSB, + 1, temp_buf); + y_buf[0] = temp_buf[0]; + if (ret < 1) + goto out2; + ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_Y_LSB, + 1, temp_buf); + y_buf[1] = temp_buf[0]; + if (ret < 1) + goto out2; + + if ((x_buf[1] & MEASURE_TAG_MASK) == MEASURE_X_TAG) + x = (x_buf[0] << XY_BUF_OFFSET) + + (x_buf[1] >> XY_BUF_OFFSET); + if ((y_buf[1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG) + y = (y_buf[0] << XY_BUF_OFFSET) + + (y_buf[1] >> XY_BUF_OFFSET); + + if ((x_buf[1] & EVENT_TAG_MASK) != (y_buf[1] & EVENT_TAG_MASK)) + goto out2; + + switch (x_buf[1] & EVENT_TAG_MASK) { + case EVENT_INIT: + /* fall through */ + case EVENT_MIDDLE: + calibration_pointer(&x, &y); + input_report_abs(data->input_dev, ABS_X, x); + input_report_abs(data->input_dev, ABS_Y, y); + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1); + input_sync(data->input_dev); + break; + + case EVENT_RELEASE: + input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0); + input_sync(data->input_dev); + break; + + case EVENT_FIFO_END: + break; + } + } + } +out2: +return IRQ_HANDLED; } static void __devinit max11801_ts_phy_init(struct max11801_data *data) { struct i2c_client *client = data->client; - - /* Average X,Y, take 16 samples, average eight media sample */ - max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff); - /* X,Y panel setup time set to 20us */ - max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11); - /* Rough pullup time (2uS), Fine pullup time (10us) */ - max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10); - /* Auto mode init period = 5ms , scan period = 5ms*/ - max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa); - /* Aperture X,Y set to +- 4LSB */ - max11801_write_reg(client, APERTURE_CONF_REG, 0x33); - /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */ - max11801_write_reg(client, OP_MODE_CONF_REG, 0x36); + max11801_client = client; + if (max11801_workmode == 0) { + /* Average X,Y, take 16 samples, average eight media sample */ + max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff); + /* X,Y panel setup time set to 20us */ + max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11); + /* Rough pullup time (2uS), Fine pullup time (10us) */ + max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10); + /* Auto mode init period = 5ms , scan period = 5ms*/ + max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa); + /* Aperture X,Y set to +- 4LSB */ + max11801_write_reg(client, APERTURE_CONF_REG, 0x33); + /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */ + max11801_write_reg(client, OP_MODE_CONF_REG, 0x36); + } + if (max11801_workmode == 1) { + /* Average X,Y, take 16 samples, average eight media sample */ + max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff); + /* X,Y panel setup time set to 20us */ + max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11); + /* Rough pullup time (2uS), Fine pullup time (10us) */ + max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10); + /* Auto mode init period = 5ms , scan period = 5ms*/ + max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa); + /* Aperture X,Y set to +- 4LSB */ + max11801_write_reg(client, APERTURE_CONF_REG, 0x33); + /* Enable Power, enable Direct conversion mode , enable Aperture, enable Average X,Y */ + max11801_write_reg(client, OP_MODE_CONF_REG, 0x16); + /* Delay initial=1ms, Sampling time 2us ,Averaging sample depth 2 samples, Resolution 12bit */ + max11801_write_reg(client, AUX_MESURE_CONF_REG, 0x76); + /* Use edge interrupt with direct conversion mode */ + max11801_write_reg(client, GENERNAL_CONF_REG, 0xf3); + } } static int __devinit max11801_ts_probe(struct i2c_client *client, @@ -195,7 +354,7 @@ static int __devinit max11801_ts_probe(struct i2c_client *client, error = -ENOMEM; goto err_free_mem; } - + max11801_workmode = *(int *)(client->dev).platform_data; data->client = client; data->input_dev = input_dev; diff --git a/drivers/media/video/mxc/capture/ipu_prp_enc.c b/drivers/media/video/mxc/capture/ipu_prp_enc.c index 6710cba5d817..02515b35ba03 100644 --- a/drivers/media/video/mxc/capture/ipu_prp_enc.c +++ b/drivers/media/video/mxc/capture/ipu_prp_enc.c @@ -1,5 +1,5 @@ /* - * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -170,7 +170,8 @@ static int prp_enc_setup(cam_data *cam) return err; } - ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_ENC, cam->csi, true, true); + ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_ENC, + cam->mclk_source, true, true); grotation = cam->rotation; if (cam->rotation >= IPU_ROTATE_90_RIGHT) { diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c index 7713b3d80846..c2bda758a362 100644 --- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.c +++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.c @@ -32,19 +32,19 @@ #include <linux/types.h> #include <linux/fb.h> #include <linux/dma-mapping.h> +#include <linux/delay.h> #include <linux/mxcfb.h> #include <media/v4l2-chip-ident.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-int-device.h> +#include <linux/fsl_devices.h> #include "mxc_v4l2_capture.h" #include "ipu_prp_sw.h" #define init_MUTEX(sem) sema_init(sem, 1) #define MXC_SENSOR_NUM 2 -static int sensor_index; -static int video_nr = -1, local_buf_num; -static cam_data *g_cam; +static int video_nr = -1; /*! This data is used for the output to the display. */ #define MXC_V4L2_CAPTURE_NUM_OUTPUTS 3 @@ -404,7 +404,7 @@ static int mxc_streamon(cam_data *cam) } cam->ping_pong_csi = 0; - local_buf_num = 0; + cam->local_buf_num = 0; if (cam->enc_update_eba) { frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); @@ -1229,7 +1229,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) case V4L2_CID_MXC_SWITCH_CAM: if (cam->sensor != cam->all_sensors[c->value]) { /* power down other cameraes before enable new one */ - for (i = 0; i < sensor_index; i++) { + for (i = 0; i < cam->sensor_index; i++) { if (i != c->value) { vidioc_int_dev_exit(cam->all_sensors[i]); vidioc_int_s_power(cam->all_sensors[i], 0); @@ -1684,12 +1684,13 @@ static int mxc_v4l_open(struct file *file) cam_fmt.fmt.pix.pixelformat, csi_param); - ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, cam->csi, + ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, cam->mclk_source, true, true); vidioc_int_s_power(cam->sensor, 1); + msleep(1); vidioc_int_init(cam->sensor); vidioc_int_dev_init(cam->sensor); -} + } file->private_data = dev; @@ -2519,7 +2520,7 @@ static void camera_callback(u32 mask, void *dev) struct mxc_v4l_frame, queue); - if (done_frame->ipu_buf_num != local_buf_num) + if (done_frame->ipu_buf_num != cam->local_buf_num) goto next; /* @@ -2556,7 +2557,7 @@ next: list_del(cam->ready_q.next); list_add_tail(&ready_frame->queue, &cam->working_q); - ready_frame->ipu_buf_num = local_buf_num; + ready_frame->ipu_buf_num = cam->local_buf_num; } } else { if (cam->enc_update_eba) @@ -2565,7 +2566,7 @@ next: &cam->ping_pong_csi); } - local_buf_num = (local_buf_num == 0) ? 1 : 0; + cam->local_buf_num = (cam->local_buf_num == 0) ? 1 : 0; return; } @@ -2579,11 +2580,13 @@ next: */ static void init_camera_struct(cam_data *cam, struct platform_device *pdev) { + struct fsl_mxc_capture_platform_data *pdata = pdev->dev.platform_data; + pr_debug("In MVC: init_camera_struct\n"); /* Default everything to 0 */ memset(cam, 0, sizeof(cam_data)); - cam->ipu = ipu_get_soc(0); + cam->ipu = ipu_get_soc(pdata->ipu); if (cam->ipu == NULL) pr_err("ERROR: v4l2 capture: failed to get ipu\n"); else if (cam->ipu == ERR_PTR(-ENODEV)) @@ -2640,8 +2643,8 @@ static void init_camera_struct(cam_data *cam, struct platform_device *pdev) cam->win.w.left = 0; cam->win.w.top = 0; - cam->csi = 0; /* Need to determine how to set this correctly with - * multiple video input devices. */ + cam->csi = pdata->csi; + cam->mclk_source = pdata->mclk_source; cam->enc_callback = camera_callback; init_waitqueue_head(&cam->power_queue); @@ -2655,6 +2658,12 @@ static void init_camera_struct(cam_data *cam, struct platform_device *pdev) pr_err("ERROR: v4l2 capture: Allocate dummy frame " "failed.\n"); cam->dummy_frame.buffer.length = SZ_8M; + + cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL); + cam->self->module = THIS_MODULE; + sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi); + cam->self->type = v4l2_int_type_master; + cam->self->u.master = &mxc_v4l2_master; } static ssize_t show_streaming(struct device *dev, @@ -2662,9 +2671,9 @@ static ssize_t show_streaming(struct device *dev, { struct video_device *video_dev = container_of(dev, struct video_device, dev); - cam_data *g_cam = video_get_drvdata(video_dev); + cam_data *cam = video_get_drvdata(video_dev); - if (g_cam->capture_on) + if (cam->capture_on) return sprintf(buf, "stream on\n"); else return sprintf(buf, "stream off\n"); @@ -2676,9 +2685,9 @@ static ssize_t show_overlay(struct device *dev, { struct video_device *video_dev = container_of(dev, struct video_device, dev); - cam_data *g_cam = video_get_drvdata(video_dev); + cam_data *cam = video_get_drvdata(video_dev); - if (g_cam->overlay_on) + if (cam->overlay_on) return sprintf(buf, "overlay on\n"); else return sprintf(buf, "overlay off\n"); @@ -2695,38 +2704,38 @@ static DEVICE_ATTR(fsl_v4l2_overlay_property, S_IRUGO, show_overlay, NULL); */ static int mxc_v4l2_probe(struct platform_device *pdev) { - /* Create g_cam and initialize it. */ - g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL); - if (g_cam == NULL) { + /* Create cam and initialize it. */ + cam_data *cam = kmalloc(sizeof(cam_data), GFP_KERNEL); + if (cam == NULL) { pr_err("ERROR: v4l2 capture: failed to register camera\n"); return -1; } - init_camera_struct(g_cam, pdev); + init_camera_struct(cam, pdev); pdev->dev.release = camera_platform_release; /* Set up the v4l2 device and register it*/ - mxc_v4l2_int_device.priv = g_cam; + cam->self->priv = cam; /* This function contains a bug that won't let this be rmmod'd. */ - v4l2_int_device_register(&mxc_v4l2_int_device); + v4l2_int_device_register(cam->self); /* register v4l video device */ - if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr) + if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr) == -1) { - kfree(g_cam); - g_cam = NULL; + kfree(cam); + cam = NULL; pr_err("ERROR: v4l2 capture: video_register_device failed\n"); return -1; } pr_debug(" Video device registered: %s #%d\n", - g_cam->video_dev->name, g_cam->video_dev->minor); + cam->video_dev->name, cam->video_dev->minor); - if (device_create_file(&g_cam->video_dev->dev, + if (device_create_file(&cam->video_dev->dev, &dev_attr_fsl_v4l2_capture_property)) dev_err(&pdev->dev, "Error on creating sysfs file" " for capture\n"); - if (device_create_file(&g_cam->video_dev->dev, + if (device_create_file(&cam->video_dev->dev, &dev_attr_fsl_v4l2_overlay_property)) dev_err(&pdev->dev, "Error on creating sysfs file" " for overlay\n"); @@ -2744,31 +2753,31 @@ static int mxc_v4l2_probe(struct platform_device *pdev) */ static int mxc_v4l2_remove(struct platform_device *pdev) { + cam_data *cam = (cam_data *)platform_get_drvdata(pdev); - if (g_cam->dummy_frame.vaddress != 0) { - dma_free_coherent(0, g_cam->dummy_frame.buffer.length, - g_cam->dummy_frame.vaddress, - g_cam->dummy_frame.paddress); - g_cam->dummy_frame.vaddress = 0; + if (cam->dummy_frame.vaddress != 0) { + dma_free_coherent(0, cam->dummy_frame.buffer.length, + cam->dummy_frame.vaddress, + cam->dummy_frame.paddress); + cam->dummy_frame.vaddress = 0; } - if (g_cam->open_count) { + if (cam->open_count) { pr_err("ERROR: v4l2 capture:camera open " "-- setting ops to NULL\n"); return -EBUSY; } else { - device_remove_file(&g_cam->video_dev->dev, + device_remove_file(&cam->video_dev->dev, &dev_attr_fsl_v4l2_capture_property); - device_remove_file(&g_cam->video_dev->dev, + device_remove_file(&cam->video_dev->dev, &dev_attr_fsl_v4l2_overlay_property); pr_info("V4L2 freeing image input device\n"); v4l2_int_device_unregister(&mxc_v4l2_int_device); - video_unregister_device(g_cam->video_dev); + video_unregister_device(cam->video_dev); - mxc_free_frame_buf(g_cam); - kfree(g_cam); - g_cam = NULL; + mxc_free_frame_buf(cam); + kfree(cam); } pr_info("V4L2 unregistering video\n"); @@ -2865,6 +2874,7 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) cam_data *cam = slave->u.slave->master->priv; struct v4l2_format cam_fmt; int i; + struct sensor_data *sdata = slave->priv; pr_debug("In MVC: mxc_v4l2_master_attach\n"); pr_debug(" slave.name = %s\n", slave->name); @@ -2875,17 +2885,22 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) return -1; } + if (sdata->csi != cam->csi) { + pr_debug("%s: csi doesn't match\n", __func__); + return -1; + } + cam->sensor = slave; - if (sensor_index < MXC_SENSOR_NUM) { - cam->all_sensors[sensor_index] = slave; - sensor_index++; + if (cam->sensor_index < MXC_SENSOR_NUM) { + cam->all_sensors[cam->sensor_index] = slave; + cam->sensor_index++; } else { pr_err("ERROR: v4l2 capture: slave number exceeds the maximum.\n"); return -1; } - for (i = 0; i < sensor_index; i++) { + for (i = 0; i < cam->sensor_index; i++) { vidioc_int_dev_exit(cam->all_sensors[i]); vidioc_int_s_power(cam->all_sensors[i], 0); } @@ -2937,23 +2952,23 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) pr_debug("In MVC:mxc_v4l2_master_detach\n"); - if (sensor_index > 1) { - for (i = 0; i < sensor_index; i++) { + if (cam->sensor_index > 1) { + for (i = 0; i < cam->sensor_index; i++) { if (cam->all_sensors[i] != slave) continue; /* Move all the sensors behind this * sensor one step forward */ - for (; i < sensor_index - 1; i++) + for (; i < cam->sensor_index - 1; i++) cam->all_sensors[i] = cam->all_sensors[i+1]; break; } /* Point current sensor to the last one */ - cam->sensor = cam->all_sensors[sensor_index - 2]; + cam->sensor = cam->all_sensors[cam->sensor_index - 2]; } else cam->sensor = NULL; - sensor_index--; + cam->sensor_index--; vidioc_int_dev_exit(slave); } diff --git a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h index 5b7b0bfe7706..dcb90a9f4ce5 100644 --- a/drivers/media/video/mxc/capture/mxc_v4l2_capture.h +++ b/drivers/media/video/mxc/capture/mxc_v4l2_capture.h @@ -34,6 +34,8 @@ #include <mach/ipu-v3.h> #include <media/v4l2-dev.h> +#include <media/v4l2-int-device.h> + #define FRAME_NUM 10 @@ -190,12 +192,17 @@ typedef struct _cam_data { bool low_power; wait_queue_head_t power_queue; unsigned int csi; + u8 mclk_source; int current_input; + int local_buf_num; + /* camera sensor interface */ struct camera_sensor *cam_sensor; /* old version */ struct v4l2_int_device *all_sensors[2]; struct v4l2_int_device *sensor; + struct v4l2_int_device *self; + int sensor_index; void *ipu; } cam_data; @@ -218,6 +225,7 @@ struct sensor_data { int ae_mode; u32 mclk; + u8 mclk_source; int csi; void (*io_init)(void); diff --git a/drivers/media/video/mxc/capture/ov3640.c b/drivers/media/video/mxc/capture/ov3640.c index b1d1abb884d9..69a3ad43b22c 100644 --- a/drivers/media/video/mxc/capture/ov3640.c +++ b/drivers/media/video/mxc/capture/ov3640.c @@ -1354,7 +1354,7 @@ static int ioctl_dev_init(struct v4l2_int_device *s) ov3640_data.mclk = tgt_xclk; pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); - set_mclk_rate(&ov3640_data.mclk, ov3640_data.csi); + set_mclk_rate(&ov3640_data.mclk, ov3640_data.mclk_source); /* Default camera frame rate is set in probe */ tgt_fps = sensor->streamcap.timeperframe.denominator / @@ -1442,6 +1442,7 @@ static int ov3640_probe(struct i2c_client *client, memset(&ov3640_data, 0, sizeof(ov3640_data)); ov3640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ ov3640_data.mclk = plat_data->mclk; + ov3640_data.mclk_source = plat_data->mclk_source; ov3640_data.csi = plat_data->csi; ov3640_data.io_init = plat_data->io_init; diff --git a/drivers/media/video/mxc/capture/ov5640.c b/drivers/media/video/mxc/capture/ov5640.c index f9087499b5f1..c2dfe314c65d 100644 --- a/drivers/media/video/mxc/capture/ov5640.c +++ b/drivers/media/video/mxc/capture/ov5640.c @@ -1309,7 +1309,7 @@ static int ioctl_dev_init(struct v4l2_int_device *s) ov5640_data.mclk = tgt_xclk; pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); - set_mclk_rate(&ov5640_data.mclk, ov5640_data.csi); + set_mclk_rate(&ov5640_data.mclk, ov5640_data.mclk_source); /* Default camera frame rate is set in probe */ tgt_fps = sensor->streamcap.timeperframe.denominator / @@ -1397,6 +1397,7 @@ static int ov5640_probe(struct i2c_client *client, memset(&ov5640_data, 0, sizeof(ov5640_data)); ov5640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ ov5640_data.mclk = plat_data->mclk; + ov5640_data.mclk_source = plat_data->mclk_source; ov5640_data.csi = plat_data->csi; ov5640_data.io_init = plat_data->io_init; diff --git a/drivers/media/video/mxc/capture/ov5640_mipi.c b/drivers/media/video/mxc/capture/ov5640_mipi.c index 2d9d83b7b139..9ffca952cc29 100644 --- a/drivers/media/video/mxc/capture/ov5640_mipi.c +++ b/drivers/media/video/mxc/capture/ov5640_mipi.c @@ -195,7 +195,7 @@ static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { }; static struct reg_value ov5640_setting_15fps_VGA_640_480[] = { - {0x3035, 0x24, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, + {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -237,7 +237,7 @@ static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { }; static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { - {0x3035, 0x24, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, + {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, @@ -909,6 +909,15 @@ bool binning_on(void) return false; } +static void ov5640_set_virtual_channel(int channel) +{ + u8 channel_id; + + ov5640_read_reg(0x4814, &channel_id); + channel_id &= ~(3 << 6); + ov5640_write_reg(0x4814, channel_id | (channel << 6)); +} + static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, enum ov5640_mode mode) { @@ -1164,6 +1173,7 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, OV5640_set_AE_target(AE_Target); OV5640_get_light_frequency(); OV5640_set_bandingfilter(); + ov5640_set_virtual_channel(ov5640_data.csi); if (mipi_csi2_info) { unsigned int i; @@ -1604,7 +1614,7 @@ static int ioctl_dev_init(struct v4l2_int_device *s) ov5640_data.mclk = tgt_xclk; pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); - set_mclk_rate(&ov5640_data.mclk, ov5640_data.csi); + set_mclk_rate(&ov5640_data.mclk, ov5640_data.mclk_source); /* Default camera frame rate is set in probe */ tgt_fps = sensor->streamcap.timeperframe.denominator / @@ -1712,6 +1722,7 @@ static int ov5640_probe(struct i2c_client *client, memset(&ov5640_data, 0, sizeof(ov5640_data)); ov5640_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ ov5640_data.mclk = plat_data->mclk; + ov5640_data.mclk_source = plat_data->mclk_source; ov5640_data.csi = plat_data->csi; ov5640_data.io_init = plat_data->io_init; diff --git a/drivers/media/video/mxc/capture/ov5642.c b/drivers/media/video/mxc/capture/ov5642.c index f8f8a6c12ab4..58ee92eef678 100644 --- a/drivers/media/video/mxc/capture/ov5642.c +++ b/drivers/media/video/mxc/capture/ov5642.c @@ -279,7 +279,7 @@ static struct reg_value ov5642_initial_setting[] = { {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, - {0x302b, 0x00, 0, 0}, + {0x302b, 0x00, 0, 300}, }; static struct reg_value ov5642_setting_15fps_QCIF_176_144[] = { @@ -3255,7 +3255,7 @@ static int ioctl_dev_init(struct v4l2_int_device *s) ov5642_data.mclk = tgt_xclk; pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); - set_mclk_rate(&ov5642_data.mclk, ov5642_data.csi); + set_mclk_rate(&ov5642_data.mclk, ov5642_data.mclk_source); /* Default camera frame rate is set in probe */ tgt_fps = sensor->streamcap.timeperframe.denominator / @@ -3368,6 +3368,7 @@ static int ov5642_probe(struct i2c_client *client, memset(&ov5642_data, 0, sizeof(ov5642_data)); ov5642_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ ov5642_data.mclk = plat_data->mclk; + ov5642_data.mclk_source = plat_data->mclk_source; ov5642_data.csi = plat_data->csi; ov5642_data.io_init = plat_data->io_init; diff --git a/drivers/media/video/mxc/capture/ov8820_mipi.c b/drivers/media/video/mxc/capture/ov8820_mipi.c index 4c2a49d8bef5..6fddbb03fc0b 100644 --- a/drivers/media/video/mxc/capture/ov8820_mipi.c +++ b/drivers/media/video/mxc/capture/ov8820_mipi.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -92,6 +92,7 @@ struct sensor { int ae_mode; u32 mclk; + u8 mclk_source; int csi; } ov8820_data; @@ -762,7 +763,7 @@ static int ioctl_dev_init(struct v4l2_int_device *s) ov8820_data.mclk = tgt_xclk; pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); - set_mclk_rate(&ov8820_data.mclk, ov8820_data.csi); + set_mclk_rate(&ov8820_data.mclk, ov8820_data.mclk_source); /* Default camera frame rate is set in probe */ tgt_fps = sensor->streamcap.timeperframe.denominator / @@ -871,6 +872,7 @@ static int ov8820_probe(struct i2c_client *client, memset(&ov8820_data, 0, sizeof(ov8820_data)); ov8820_data.mclk = 24000000; /* 6 - 54 MHz, typical 24MHz */ ov8820_data.mclk = plat_data->mclk; + ov8820_data.mclk_source = plat_data->mclk_source; ov8820_data.csi = plat_data->csi; ov8820_data.i2c_client = client; diff --git a/drivers/media/video/mxc/output/mxc_vout.c b/drivers/media/video/mxc/output/mxc_vout.c index aebe57fda0c5..e3e9483ac70c 100644 --- a/drivers/media/video/mxc/output/mxc_vout.c +++ b/drivers/media/video/mxc/output/mxc_vout.c @@ -1675,16 +1675,18 @@ static void release_disp_output(struct mxc_vout_output *vout) set_window_position(vout, &pos); if (get_ipu_channel(fbi) == MEM_BG_SYNC) { - console_lock(); - fbi->fix.smem_start = vout->fb_smem_start; - fbi->fix.smem_len = vout->fb_smem_len; - vout->fb_var.activate |= FB_ACTIVATE_FORCE; - fbi->flags |= FBINFO_MISC_USEREVENT; - ret = fb_set_var(fbi, &vout->fb_var); - fbi->flags &= ~FBINFO_MISC_USEREVENT; - console_unlock(); - if (ret < 0) - v4l2_err(vout->vfd->v4l2_dev, "ERR: fb_set_var.\n"); + if ((vout->fb_smem_len != 0) && (vout->fb_smem_start != 0)) { + console_lock(); + fbi->fix.smem_start = vout->fb_smem_start; + fbi->fix.smem_len = vout->fb_smem_len; + vout->fb_var.activate |= FB_ACTIVATE_FORCE; + fbi->flags |= FBINFO_MISC_USEREVENT; + ret = fb_set_var(fbi, &vout->fb_var); + fbi->flags &= ~FBINFO_MISC_USEREVENT; + console_unlock(); + if (ret < 0) + v4l2_err(vout->vfd->v4l2_dev, "ERR: fb_set_var.\n"); + } console_lock(); fbi->flags |= FBINFO_MISC_USEREVENT; fb_blank(fbi, FB_BLANK_UNBLANK); diff --git a/drivers/mfd/pfuze-core.c b/drivers/mfd/pfuze-core.c index 96b62924adec..9c7a988cf89b 100644 --- a/drivers/mfd/pfuze-core.c +++ b/drivers/mfd/pfuze-core.c @@ -501,9 +501,10 @@ static int pfuze_probe(struct i2c_client *client, if (ret) goto err_mask; } - ret = request_threaded_irq(client->irq, NULL, pfuze_irq_thread, - IRQF_ONESHOT | IRQF_TRIGGER_LOW, "pfuze", - mc_pfuze); + if (client->irq) + ret = request_threaded_irq(client->irq, NULL, pfuze_irq_thread, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, "pfuze", + mc_pfuze); if (ret) { err_mask: err_revision: diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 17773740d014..d20fc54eebf0 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -108,6 +108,8 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = pltfm_host->priv; + struct esdhc_platform_data *boarddata + = host->mmc->parent->platform_data; /* fake CARD_PRESENT flag on mx25/35 */ u32 val = readl(host->ioaddr + reg); @@ -127,18 +129,18 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) val |= (fsl_prss & 0x00800000) << 1; } - if (unlikely((reg == SDHCI_PRESENT_STATE) - && (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP))) { - struct esdhc_platform_data *boarddata = - host->mmc->parent->platform_data; - - if (boarddata && gpio_is_valid(boarddata->cd_gpio) - && gpio_get_value(boarddata->cd_gpio)) - /* no card, if a valid gpio says so... */ - val &= ~SDHCI_CARD_PRESENT; - else - /* ... in all other cases assume card is present */ + if (unlikely(reg == SDHCI_PRESENT_STATE)) { + if (boarddata && boarddata->always_present) val |= SDHCI_CARD_PRESENT; + else if (imx_data->flags & ESDHC_FLAG_GPIO_FOR_CD_WP) { + if (boarddata && gpio_is_valid(boarddata->cd_gpio) + && gpio_get_value(boarddata->cd_gpio)) + /* no card, if a valid gpio says so */ + val &= ~SDHCI_CARD_PRESENT; + else + /* in all other cases assume card is present */ + val |= SDHCI_CARD_PRESENT; + } } if (reg == SDHCI_INT_STATUS && cpu_is_mx6() @@ -756,7 +758,7 @@ static int esdhc_pltfm_init(struct sdhci_host *host, struct sdhci_pltfm_data *pd if (boarddata) { /* Device is always present, e.x, populated emmc device */ if (boarddata->always_present) { - imx_data->flags |= ESDHC_FLAG_GPIO_FOR_CD_WP; + /* remove BROKEN_CD to disable card polling */ host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; if (host->clk_mgr_en) clk_disable(pltfm_host->clk); diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1aedbe436c25..2f200b8aa49b 100755 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -35,6 +35,11 @@ #define DBG(f, x...) \ pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) +#if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ + defined(CONFIG_MMC_SDHCI_MODULE)) +/* FIXME: temp workaround for calling clk_enable in an interrupt context */ +#define SDHCI_USE_LEDS_CLASS_BROKEN +#endif #define MAX_TUNING_LOOP 40 diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 1c273e4eb2b4..75c2e618b28a 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -152,7 +152,7 @@ static int enable_ddr_onfi(struct gpmi_nand_data *this) struct mtd_info *mtd = &this->mtd; int saved_chip_number = 0; uint8_t device_feature[FEATURE_SIZE]; - int mode = 0;/* there is 5 mode available, default is 0 */ + int mode = 5;/* there is 5 mode available, default is 0 */ saved_chip_number = this->current_chip; nand->select_chip(mtd, 0); @@ -178,14 +178,16 @@ static int enable_ddr_onfi(struct gpmi_nand_data *this) /* [3] about the clock, pay attention! */ nand->select_chip(mtd, saved_chip_number); { - struct clk *pll1; - pll1 = clk_get(NULL, "pll1_main_clk"); - if (IS_ERR(pll1)) { - printk(KERN_INFO "No PLL1 clock\n"); + struct clk *enfc_clk; + enfc_clk = clk_get(NULL, "enfc_clk"); + if (IS_ERR(enfc_clk)) { + printk(KERN_INFO "No enfc_clk clock\n"); return -EINVAL; } - clk_set_parent(resources->clock, pll1); - clk_set_rate(resources->clock, 20000000); + clk_set_parent(resources->clock, enfc_clk); + clk_set_rate(enfc_clk, \ + enfc_clk->round_rate(enfc_clk, 100000000)); + clk_set_rate(resources->clock, 100000000); } nand->select_chip(mtd, 0); @@ -258,18 +260,20 @@ static int enable_ddr_toggle(struct gpmi_nand_data *this) /* [3] about the clock, pay attention! */ nand->select_chip(mtd, saved_chip_number); { - struct clk *pll1; + struct clk *enfc_clk; unsigned long rate; - pll1 = clk_get(NULL, "pll1_main_clk"); - if (IS_ERR(pll1)) { - printk(KERN_INFO "No PLL1 clock\n"); + enfc_clk = clk_get(NULL, "enfc_clk"); + if (IS_ERR(enfc_clk)) { + printk(KERN_INFO "No enfc_clk clock\n"); return -EINVAL; } /* toggle nand : 133/66 MHz */ rate = 33000000; - clk_set_parent(resources->clock, pll1); + clk_set_parent(resources->clock, enfc_clk); + clk_set_rate(enfc_clk, \ + enfc_clk->round_rate(enfc_clk, rate)); clk_set_rate(resources->clock, rate); } nand->select_chip(mtd, 0); diff --git a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c index 25a893cd614c..c24439d1af1e 100644 --- a/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c +++ b/drivers/mxc/gpu-viv/arch/GC350/hal/kernel/gc_hal_kernel_hardware_vg.c @@ -1476,7 +1476,7 @@ static gceSTATUS _CommandStall( gcmkERR_BREAK(gckOS_WaitSignal( command->os, command->powerStallSignal, - gcvINFINITE)); + gcdGPU_TIMEOUT)); } @@ -1750,7 +1750,7 @@ gckVGHARDWARE_SetPowerManagementState( if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON)) { /* Turn on the power. */ - gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG , gcvTRUE, gcvTRUE)); + gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE)); /* Mark clock and power as enabled. */ Hardware->clockState = gcvTRUE; diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c index 6ddbcee2bda4..a186bbe3386e 100644 --- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c +++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_context.c @@ -545,7 +545,8 @@ _InitializeContextBuffer( index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); - index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); + index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); + index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); /* Setup states. */ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); diff --git a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c index 99b699d3a6c8..1578ff2b09c5 100644 --- a/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c +++ b/drivers/mxc/gpu-viv/arch/XAQ2/hal/kernel/gc_hal_kernel_hardware.c @@ -217,16 +217,23 @@ _IdentifyHardware( } } + /* If new HZ is available, disable other early z modes. */ + if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) + || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))))) + { + /* Disable EZ. */ + Identity->chipFeatures + = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))); + } + /* Disable HZ when EZ is present for older chips. */ - if (!((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) - && - !((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) - ) + else if (!((((gctUINT32) (Identity->chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))))) { /* Disable HIERARCHICAL_Z. */ Identity->chipMinorFeatures = ((((gctUINT32) (Identity->chipMinorFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) << (0 ? 27:27))); } + /* Disable rectangle primitive when chip is gc880_5_1_0_rc6*/ if ((Identity->chipModel == gcv880) && (Identity->chipRevision == 0x5106)) { @@ -234,6 +241,7 @@ _IdentifyHardware( Identity->chipMinorFeatures2 = ((((gctUINT32) (Identity->chipMinorFeatures2)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); } + gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Identity: chipFeatures=0x%08X", Identity->chipFeatures); @@ -494,7 +502,10 @@ gckHARDWARE_Construct( /* Enable the GPU. */ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE)); - gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00000, 0)); + gcmkONERROR(gckOS_WriteRegisterEx(Os, + Core, + 0x00000, + 0x00000900)); /* Allocate the gckHARDWARE object. */ gcmkONERROR(gckOS_Allocate(Os, @@ -609,7 +620,7 @@ OnError: if (hardware != gcvNULL) { /* Turn off the power. */ - gcmkVERIFY_OK(gckOS_SetGPUPower(Os, hardware->core, gcvFALSE, gcvFALSE)); + gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE)); if (hardware->globalSemaphore != gcvNULL) { diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c index 187b9cc6d810..773a262562c4 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.c @@ -289,7 +289,10 @@ OnError: if (kernel->hardware != gcvNULL) { /* Turn off the power. */ - gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os, kernel->hardware->core, gcvFALSE, gcvFALSE)); + gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os, + kernel->hardware->core, + gcvFALSE, + gcvFALSE)); gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware)); } } @@ -1037,7 +1040,7 @@ gckKERNEL_Dispatch( break; case gcvHAL_UNMAP_USER_MEMORY: - address = Interface->u.MapUserMemory.address; + address = Interface->u.UnmapUserMemory.address; /* Unmap user memory. */ gcmkONERROR( @@ -1169,9 +1172,10 @@ gckKERNEL_Dispatch( #if gcdREGISTER_ACCESS_FROM_USER { gceCHIPPOWERSTATE power; + + gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE); gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware, &power)); - if (power == gcvPOWER_ON) { /* Read a register. */ @@ -1187,6 +1191,7 @@ gckKERNEL_Dispatch( Interface->u.ReadRegisterData.data = 0; status = gcvSTATUS_CHIP_NOT_READY; } + gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex)); } #else /* No access from user land to read registers. */ @@ -1197,12 +1202,29 @@ gckKERNEL_Dispatch( case gcvHAL_WRITE_REGISTER: #if gcdREGISTER_ACCESS_FROM_USER - /* Write a register. */ - gcmkONERROR( - gckOS_WriteRegisterEx(Kernel->os, - Kernel->core, - Interface->u.WriteRegisterData.address, - Interface->u.WriteRegisterData.data)); + { + gceCHIPPOWERSTATE power; + + gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE); + gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware, + &power)); + if (power == gcvPOWER_ON) + { + /* Write a register. */ + gcmkONERROR( + gckOS_WriteRegisterEx(Kernel->os, + Kernel->core, + Interface->u.WriteRegisterData.address, + Interface->u.WriteRegisterData.data)); + } + else + { + /* Chip is in power-state. */ + Interface->u.WriteRegisterData.data = 0; + status = gcvSTATUS_CHIP_NOT_READY; + } + gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex)); + } #else /* No access from user land to write registers. */ status = gcvSTATUS_NOT_SUPPORTED; diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h index bdc94bc088b3..a9697a12c2e2 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel.h @@ -613,24 +613,24 @@ typedef union _gcuVIDMEM_NODE gctSIZE_T pageCount; /* Used only when node is not contiguous */ - gctPOINTER pageTables[gcdCORE_COUNT]; + gctPOINTER pageTables[gcdGPU_COUNT]; /* Pointer to gckKERNEL object who lock this. */ - gckKERNEL lockKernels[gcdCORE_COUNT]; + gckKERNEL lockKernels[gcdGPU_COUNT]; /* Actual physical address */ - gctUINT32 addresses[gcdCORE_COUNT]; + gctUINT32 addresses[gcdGPU_COUNT]; /* Mutex. */ gctPOINTER mutex; /* Locked counter. */ - gctINT32 lockeds[gcdCORE_COUNT]; + gctINT32 lockeds[gcdGPU_COUNT]; #ifdef __QNXNTO__ /* Single linked list of nodes. */ gcuVIDMEM_NODE_PTR next; /* Unlock pending flag. */ - gctBOOL unlockPendings[gcdCORE_COUNT]; + gctBOOL unlockPendings[gcdGPU_COUNT]; /* Free pending flag. */ gctBOOL freePending; diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c index 14ac175a1b2d..7a5e82eef3b4 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command.c @@ -2480,8 +2480,6 @@ gckCOMMAND_Stall( gcmkONERROR(gckOS_Broadcast( os, hardware, gcvBROADCAST_GPU_STUCK )); - - gcmkONERROR(gcvSTATUS_GPU_NOT_RESPONDING); } /* Delete the signal. */ diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c index 3a29f023ff80..227ab683778e 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_command_vg.c @@ -1236,12 +1236,6 @@ _TaskUnmapUserMemory( gcsBLOCK_TASK_ENTRY_PTR TaskHeader ); -static gceSTATUS -_TaskUnmapMemory( - gckVGCOMMAND Command, - gcsBLOCK_TASK_ENTRY_PTR TaskHeader - ); - static gctTASKROUTINE _taskRoutine[] = { _TaskLink, /* gcvTASK_LINK */ @@ -1254,7 +1248,6 @@ static gctTASKROUTINE _taskRoutine[] = _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */ - _TaskUnmapMemory, /* gcvTASK_UNMAP_MEMORY */ }; static gceSTATUS @@ -1676,38 +1669,6 @@ _TaskUnmapUserMemory( return status; } -static gceSTATUS -_TaskUnmapMemory( - gckVGCOMMAND Command, - gcsBLOCK_TASK_ENTRY_PTR TaskHeader - ) -{ - gceSTATUS status; - - do - { - /* Cast the task pointer. */ - gcsTASK_UNMAP_MEMORY_PTR task - = (gcsTASK_UNMAP_MEMORY_PTR) TaskHeader->task; - - /* Unmap memory. */ - gcmkERR_BREAK(gckKERNEL_UnmapMemory( - Command->kernel->kernel, task->physical, task->bytes, task->logical - )); - - /* Update the reference counter. */ - TaskHeader->container->referenceCount -= 1; - - /* Update the task pointer. */ - TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); - } - while (gcvFALSE); - - /* Return status. */ - return status; -} - - /******************************************************************************\ ************ Hardware Block Interrupt Handlers For Scheduled Events ************ \******************************************************************************/ diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c index 77ea27a6c31e..00decd9fb09d 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_debug.c @@ -1596,7 +1596,7 @@ _GetOutputBuffer( #if gcdTHREAD_BUFFERS > 1 /* Get the current thread ID. */ - gctUINT32 threadID = gcmkGETTHREADID(); + gctUINT32 ThreadID = gcmkGETTHREADID(); /* Locate the output buffer for the thread. */ outputBuffer = _outputBufferHead; @@ -1629,10 +1629,14 @@ _GetOutputBuffer( /* Reset the buffer. */ outputBuffer->threadID = ThreadID; +#if gcdBUFFERED_OUTPUT outputBuffer->start = 0; outputBuffer->index = 0; outputBuffer->count = 0; +#endif +#if gcdSHOW_LINE_NUMBER outputBuffer->lineNumber = 0; +#endif } #else outputBuffer = _outputBufferHead; diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c index 4f8628c19946..43363b9e685b 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_event.c @@ -203,20 +203,54 @@ _TryToIdleGPU( { gceSTATUS status; gctBOOL empty = gcvFALSE, idle = gcvFALSE; + gctUINT32 process, thread; + gctBOOL powerLocked = gcvFALSE; + gckHARDWARE hardware; + gcmkHEADER_ARG("Event=0x%x", Event); /* Verify the arguments. */ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); + /* Grab gckHARDWARE object. */ + hardware = Event->kernel->hardware; + gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); + + /* Check whether the event queue is empty. */ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty)); if (empty) { + status = gckOS_AcquireMutex(hardware->os, hardware->powerMutex, 0); + if (status == gcvSTATUS_TIMEOUT) + { + gcmkONERROR(gckOS_GetProcessID(&process)); + gcmkONERROR(gckOS_GetThreadID(&thread)); + + /* Just return to prevent deadlock. */ + if ((hardware->powerProcess != process) + || (hardware->powerThread != thread)) + { + gcmkFOOTER_NO(); + return gcvSTATUS_OK; + } + } + else + { + powerLocked = gcvTRUE; + } + /* Query whether the hardware is idle. */ gcmkONERROR(gckHARDWARE_QueryIdle(Event->kernel->hardware, &idle)); + if (powerLocked) + { + gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex)); + powerLocked = gcvFALSE; + } + if (idle) { /* Inform the system of idle GPU. */ @@ -230,6 +264,13 @@ _TryToIdleGPU( return gcvSTATUS_OK; OnError: + + if (powerLocked) + { + gcmkONERROR(gckOS_ReleaseMutex(hardware->os, hardware->powerMutex)); + powerLocked = gcvFALSE; + } + gcmkFOOTER(); return status; } diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c index deb658d98568..7062dd9a1b27 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_mmu.c @@ -68,7 +68,7 @@ typedef struct _gcsSharedPageTable gckMMU mmu; /* Hardwares which use this shared pagetable. */ - gckHARDWARE hardwares[gcdCORE_COUNT]; + gckHARDWARE hardwares[gcdGPU_COUNT]; /* Number of cores use this shared pagetable. */ gctUINT32 reference; @@ -1201,7 +1201,7 @@ gckMMU_Enable( gcmkONERROR(_SetupDynamicSpace(Mmu)); #if gcdSHARED_PAGETABLE - for(i = 0; i < gcdCORE_COUNT; i++) + for(i = 0; i < gcdGPU_COUNT; i++) { hardware = sharedPageTable->hardwares[i]; if (hardware != gcvNULL) @@ -1402,7 +1402,7 @@ gckMMU_Flush( gckHARDWARE hardware; #if gcdSHARED_PAGETABLE gctINT i; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { #if gcdENABLE_VG if (i == gcvCORE_VG) diff --git a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c index 88e4d7705bd8..89a86a8486a7 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c +++ b/drivers/mxc/gpu-viv/hal/kernel/gc_hal_kernel_video_memory.c @@ -245,7 +245,7 @@ gckVIDMEM_ConstructVirtual( node->Virtual.contiguous = Contiguous; node->Virtual.logical = gcvNULL; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { node->Virtual.lockeds[i] = 0; node->Virtual.pageTables[i] = gcvNULL; @@ -259,7 +259,7 @@ gckVIDMEM_ConstructVirtual( #ifdef __QNXNTO__ node->Virtual.next = gcvNULL; node->Virtual.freePending = gcvFALSE; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { node->Virtual.unlockPendings[i] = gcvFALSE; } @@ -366,7 +366,7 @@ gckVIDMEM_DestroyVirtual( /* Delete the mutex. */ gcmkVERIFY_OK(gckOS_DeleteMutex(os, Node->Virtual.mutex)); - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (Node->Virtual.pageTables[i] != gcvNULL) { @@ -1392,7 +1392,7 @@ gckVIDMEM_Free( acquired = gcvTRUE; - for (i = 0, totalLocked = 0; i < gcdCORE_COUNT; i++) + for (i = 0, totalLocked = 0; i < gcdGPU_COUNT; i++) { totalLocked += Node->Virtual.lockeds[i]; } @@ -1590,7 +1590,7 @@ _NeedVirtualMapping( gcmkVERIFY_ARGUMENT(Kernel != gcvNULL); gcmkVERIFY_ARGUMENT(Node != gcvNULL); gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL); - gcmkVERIFY_ARGUMENT(Core < gcdCORE_COUNT); + gcmkVERIFY_ARGUMENT(Core < gcdGPU_COUNT); if (Node->Virtual.contiguous) { @@ -2052,7 +2052,7 @@ gckVIDMEM_Unlock( #endif } - for (i = 0, totalLocked = 0; i < gcdCORE_COUNT; i++) + for (i = 0, totalLocked = 0; i < gcdGPU_COUNT; i++) { totalLocked += Node->Virtual.lockeds[i]; } diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h index 87b811d8dfaf..f986e4e4e009 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal.h @@ -137,7 +137,7 @@ typedef enum _gceCORE } gceCORE; -#define gcdCORE_COUNT 3 +#define gcdGPU_COUNT 3 /******************************************************************************* ** @@ -1226,8 +1226,8 @@ gckOS_BroadcastCalibrateSpeed( ** gckOS Os ** Pointer to a gckOS object.ß ** -** gceCORE Core -** Core type. +** gckCORE Core +** GPU whose power is set. ** ** gctBOOL Clock ** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock. diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h index 5fafefbe058e..b1e6b488f0af 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_base.h @@ -129,6 +129,7 @@ typedef struct _gcsTLS gco3D engine3D; #endif gco2D engine2D; + gctBOOL copied; } gcsTLS; @@ -642,6 +643,9 @@ gcoOS_GetTLS( OUT gcsTLS_PTR * TLS ); + /* Copy the TLS from a source thread. */ + gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source); + /* Destroy the objects associated with the current thread. */ void gcoOS_FreeThreadData( @@ -2061,6 +2065,11 @@ gcoDUMP_Delete( IN gctUINT32 Address ); +/* Enable dump or not. */ +gceSTATUS +gcoDUMP_SetDumpFlag( + IN gctBOOL DumpState + ); /******************************************************************************\ ******************************* gcsRECT Structure ****************************** diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h index fe57968ba423..447663f964bd 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_driver_vg.h @@ -109,8 +109,7 @@ typedef enum _gceTASK gcvTASK_UNLOCK_VIDEO_MEMORY, gcvTASK_FREE_VIDEO_MEMORY, gcvTASK_FREE_CONTIGUOUS_MEMORY, - gcvTASK_UNMAP_USER_MEMORY, - gcvTASK_UNMAP_MEMORY + gcvTASK_UNMAP_USER_MEMORY } gceTASK; @@ -268,23 +267,6 @@ typedef struct _gcsTASK_UNMAP_USER_MEMORY } gcsTASK_UNMAP_USER_MEMORY; -typedef struct _gcsTASK_UNMAP_MEMORY * gcsTASK_UNMAP_MEMORY_PTR; -typedef struct _gcsTASK_UNMAP_MEMORY -{ - /* Task ID (gcvTASK_UNMAP_MEMORY). */ - IN gceTASK id; - - /* Physical memory address to unmap. */ - IN gctPHYS_ADDR physical; - - /* Number of bytes in physical memory to unmap. */ - IN gctSIZE_T bytes; - - /* Address of mapped memory to unmap. */ - IN gctPOINTER logical; -} -gcsTASK_UNMAP_MEMORY; - #ifdef __cplusplus } #endif diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h index f4b7d2886e8e..b9bf7c8f916e 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_eglplatform.h @@ -251,11 +251,63 @@ typedef struct __BITFIELDINFO{ } BITFIELDINFO; #elif defined(LINUX) && defined(EGL_API_FB) && !defined(__APPLE__) + +#if defined(EGL_API_WL) +/* Wayland platform. */ + +#include <wayland-egl.h> + +#define WL_EGL_NUM_BACKBUFFERS 2 + +struct wl_egl_buffer_info +{ + gctINT32 width; + gctINT32 height; + gctINT32 stride; + gctUINT32 physical; + gctPOINTER logical; + gceSURF_FORMAT format; + gcoSURF surface; +}; + +struct wl_egl_buffer +{ + struct wl_buffer* wl_buffer; + struct wl_egl_buffer_info info; +}; + +struct wl_egl_window_info +{ + gctUINT width; + gctUINT height; + gceSURF_FORMAT format; + gctUINT bpp; +}; + +struct wl_egl_window +{ +/* struct wl_egl_display *display;*/ + struct wl_surface* surface; + struct wl_egl_window_info info; + struct wl_egl_buffer backbuffers[WL_EGL_NUM_BACKBUFFERS]; + gctUINT current; + /* + int backbuffer; + int dx; + int dy; +*/ +}; + + +typedef void* HALNativeDisplayType; +typedef void* HALNativeWindowType; +typedef void* HALNativePixmapType; +#else /* Linux platform for FBDEV. */ typedef struct _FBDisplay * HALNativeDisplayType; typedef struct _FBWindow * HALNativeWindowType; typedef struct _FBPixmap * HALNativePixmapType; - +#endif #elif defined(__ANDROID__) || defined(ANDROID) struct egl_native_pixmap_t; @@ -370,6 +422,8 @@ typedef struct _halDISPLAY_INFO ** if the address is not known for the specified display. */ gctSIZE_T physical; + gctBOOL isCompositor; /* true if compositor, false otherwise. */ + #ifndef __QNXNTO__ /* 355_FB_MULTI_BUFFER */ gctINT multiBuffer; diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h index f77cf5826a6a..7ad46da0b40e 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_engine.h @@ -1173,6 +1173,27 @@ gco3D_InvokeThreadWalker( IN gcsTHREAD_WALKER_INFO_PTR Info ); +#if gcdUSE_WCLIP_PATCH +/* Set w clip and w plane limit value. */ +gceSTATUS +gco3D_SetWClipEnable( + IN gco3D Engine, + IN gctBOOL Enable + ); + +gceSTATUS +gco3D_SetWPlaneLimitF( + IN gco3D Engine, + IN gctFLOAT Value + ); + +gceSTATUS +gco3D_SetWPlaneLimitX( + IN gco3D Engine, + IN gctFIXED_POINT Value + ); +#endif + /*----------------------------------------------------------------------------*/ /*-------------------------- gco3D Fragment Processor ------------------------*/ @@ -1437,6 +1458,7 @@ gceSTATUS gcoTEXTURE_AddMipMap( IN gcoTEXTURE Texture, IN gctINT Level, + IN gctINT imageFormat, IN gceSURF_FORMAT Format, IN gctUINT Width, IN gctUINT Height, diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h index d10686a259c3..18ddf5bff754 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_enum.h @@ -144,6 +144,7 @@ typedef enum _gceFEATURE gcvFEATURE_RS_YUV_TARGET, gcvFEATURE_2D_FC_SOURCE, gcvFEATURE_PE_DITHER_FIX, + gcvFEATURE_2D_YUV_SEPARATE_STRIDE, } gceFEATURE; @@ -263,6 +264,13 @@ typedef enum _gceSURF_ROTATION } gceSURF_ROTATION; +typedef enum _gceMIPMAP_IMAGE_FORMAT +{ + gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2 +} +gceMIPMAP_IMAGE_FORMAT; + + /* Surface formats. */ typedef enum _gceSURF_FORMAT { diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h index 73b666a37570..35743c62f2a2 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_options.h @@ -258,7 +258,7 @@ virtual data. */ #ifndef gcdMMU_SIZE -# define gcdMMU_SIZE (128 << 10) +# define gcdMMU_SIZE (2048 << 10) #endif /* @@ -778,4 +778,8 @@ # define gcdHIGH_PRECISION_DELAY_ENABLE 1 #endif +#ifndef gcdUSE_WCLIP_PATCH +# define gcdUSE_WCLIP_PATCH 0 +#endif + #endif /* __gc_hal_options_h_ */ diff --git a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h index 132832c9224d..0bc1ffc46943 100644 --- a/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h +++ b/drivers/mxc/gpu-viv/hal/kernel/inc/gc_hal_version.h @@ -28,9 +28,9 @@ #define gcvVERSION_MINOR 6 -#define gcvVERSION_PATCH 7 +#define gcvVERSION_PATCH 8 -#define gcvVERSION_BUILD 1422 +#define gcvVERSION_BUILD 1443 #define gcvVERSION_DATE __DATE__ diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c index df75a8b3c65c..305b1cc9acb6 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.c @@ -404,7 +404,7 @@ gckGALDEVICE_Construct( device->requestedContiguousSize = 0; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { physical = device->requestedRegisterMemBases[i]; @@ -582,19 +582,19 @@ gckGALDEVICE_Construct( device->irqLines[gcvCORE_VG] = IrqLineVG; /* Initialize the kernel thread semaphores. */ - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0); } device->signal = Signal; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (device->kernels[i] != gcvNULL) break; } - if (i == gcdCORE_COUNT) gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); + if (i == gcdGPU_COUNT) gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); #if gcdENABLE_VG if (i == gcvCORE_VG) @@ -854,7 +854,7 @@ gckGALDEVICE_Destroy( if (Device != gcvNULL) { - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (Device->kernels[i] != gcvNULL) { @@ -937,7 +937,7 @@ gckGALDEVICE_Destroy( } } - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (Device->registerBases[i] != gcvNULL) { @@ -1428,7 +1428,7 @@ gckGALDEVICE_Stop_Threads( gcmkVERIFY_ARGUMENT(Device != NULL); - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { /* Stop the kernel threads. */ if (Device->threadInitializeds[i]) diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h index 69c985c90ff3..9e4f5b48e78f 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_device.h @@ -38,7 +38,7 @@ typedef struct _gckGALDEVICE { /* Objects. */ gckOS os; - gckKERNEL kernels[gcdCORE_COUNT]; + gckKERNEL kernels[gcdGPU_COUNT]; /* Attributes. */ gctSIZE_T internalSize; @@ -57,23 +57,23 @@ typedef struct _gckGALDEVICE gctPOINTER contiguousMappedUser; gctSIZE_T systemMemorySize; gctUINT32 systemMemoryBaseAddress; - gctPOINTER registerBases[gcdCORE_COUNT]; - gctSIZE_T registerSizes[gcdCORE_COUNT]; + gctPOINTER registerBases[gcdGPU_COUNT]; + gctSIZE_T registerSizes[gcdGPU_COUNT]; gctUINT32 baseAddress; - gctUINT32 requestedRegisterMemBases[gcdCORE_COUNT]; - gctSIZE_T requestedRegisterMemSizes[gcdCORE_COUNT]; + gctUINT32 requestedRegisterMemBases[gcdGPU_COUNT]; + gctSIZE_T requestedRegisterMemSizes[gcdGPU_COUNT]; gctUINT32 requestedContiguousBase; gctSIZE_T requestedContiguousSize; /* IRQ management. */ - gctINT irqLines[gcdCORE_COUNT]; - gctBOOL isrInitializeds[gcdCORE_COUNT]; - gctBOOL dataReadys[gcdCORE_COUNT]; + gctINT irqLines[gcdGPU_COUNT]; + gctBOOL isrInitializeds[gcdGPU_COUNT]; + gctBOOL dataReadys[gcdGPU_COUNT]; /* Thread management. */ - struct task_struct *threadCtxts[gcdCORE_COUNT]; - struct semaphore semas[gcdCORE_COUNT]; - gctBOOL threadInitializeds[gcdCORE_COUNT]; + struct task_struct *threadCtxts[gcdGPU_COUNT]; + struct semaphore semas[gcdGPU_COUNT]; + gctBOOL threadInitializeds[gcdGPU_COUNT]; gctBOOL killThread; /* Signal management. */ @@ -83,7 +83,7 @@ typedef struct _gckGALDEVICE gceCORE coreMapping[8]; /* States before suspend. */ - gceCHIPPOWERSTATE statesStored[gcdCORE_COUNT]; + gceCHIPPOWERSTATE statesStored[gcdGPU_COUNT]; /* Clock management.*/ struct clk *clk_3d_core; diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c index 0daf9a1cb149..c5ce248e77ba 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_driver.c @@ -85,7 +85,7 @@ module_param(contiguousSize, ulong, 0644); static ulong contiguousBase = 0; module_param(contiguousBase, ulong, 0644); -static ulong bankSize = 32 << 20; +static ulong bankSize = 0; module_param(bankSize, ulong, 0644); static int fastClear = -1; @@ -182,7 +182,7 @@ int drv_open( gcmkONERROR(gckOS_GetProcessID(&data->pidOpen)); /* Attached the process. */ - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (galDevice->kernels[i] != gcvNULL) { @@ -225,7 +225,7 @@ OnError: if (attached) { - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (galDevice->kernels[i] != gcvNULL) { @@ -304,7 +304,7 @@ int drv_release( } /* A process gets detached. */ - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (galDevice->kernels[i] != gcvNULL) { @@ -442,7 +442,7 @@ long drv_ioctl( if (iface.command == gcvHAL_CHIP_INFO) { count = 0; - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (device->kernels[i] != gcvNULL) { @@ -959,7 +959,7 @@ static int __devinit gpu_suspend(struct platform_device *dev, pm_message_t state device = platform_get_drvdata(dev); - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (device->kernels[i] != gcvNULL) { @@ -990,8 +990,6 @@ static int __devinit gpu_suspend(struct platform_device *dev, pm_message_t state { status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF); } - /*gpu clock must be turned on before power down*/ - gckOS_SetGPUPower(device->os, i, gcvTRUE, gcvFALSE); if (gcmIS_ERROR(status)) { return -1; @@ -1012,7 +1010,7 @@ static int __devinit gpu_resume(struct platform_device *dev) device = platform_get_drvdata(dev); - for (i = 0; i < gcdCORE_COUNT; i++) + for (i = 0; i < gcdGPU_COUNT; i++) { if (device->kernels[i] != gcvNULL) { diff --git a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c index cf0ccc2d4e2b..63ac50912833 100644 --- a/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c +++ b/drivers/mxc/gpu-viv/hal/os/linux/kernel/gc_hal_kernel_os.c @@ -197,7 +197,6 @@ typedef struct _gcsSIGNAL /* ID. */ gctUINT32 id; - } gcsSIGNAL; @@ -1150,6 +1149,52 @@ _DestroyIntegerId( return gcvSTATUS_OK; } +static void +_UnmapUserLogical( + IN gctINT Pid, + IN gctPOINTER Logical, + IN gctUINT32 Size +) +{ + struct task_struct *task; + struct mm_struct *mm; + + /* Get the task_struct of the task with stored pid. */ + rcu_read_lock(); + + task = FIND_TASK_BY_PID(Pid); + + if (task == gcvNULL) + { + rcu_read_unlock(); + return; + } + + /* Get the mm_struct. */ + mm = get_task_mm(task); + + rcu_read_unlock(); + + if (mm == gcvNULL) + { + return; + } + + down_write(&mm->mmap_sem); + if (do_munmap(mm, (unsigned long)Logical, Size) < 0) + { + gcmkTRACE_ZONE( + gcvLEVEL_WARNING, gcvZONE_OS, + "%s(%d): do_munmap failed", + __FUNCTION__, __LINE__ + ); + } + up_write(&mm->mmap_sem); + + /* Dereference. */ + mmput(mm); +} + /******************************************************************************* ** ** gckOS_Construct @@ -1329,7 +1374,6 @@ gckOS_Destroy( */ /* Destroy the mutex. */ - gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex)); if (Os->heap != gcvNULL) @@ -1898,7 +1942,6 @@ gckOS_UnmapMemoryEx( { PLINUX_MDL_MAP mdlMap; PLINUX_MDL mdl = (PLINUX_MDL)Physical; - struct task_struct * task; gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d", Os, Physical, Bytes, Logical, PID); @@ -1924,24 +1967,7 @@ gckOS_UnmapMemoryEx( return gcvSTATUS_INVALID_ARGUMENT; } - /* Get the current pointer for the task with stored pid. */ - task = FIND_TASK_BY_PID(mdlMap->pid); - - if (task != gcvNULL && task->mm != gcvNULL) - { - down_write(&task->mm->mmap_sem); - do_munmap(task->mm, (unsigned long)Logical, mdl->numPages*PAGE_SIZE); - up_write(&task->mm->mmap_sem); - } - else - { - gcmkTRACE_ZONE( - gcvLEVEL_INFO, gcvZONE_OS, - "%s(%d): can't find the task with pid->%d. No unmapping", - __FUNCTION__, __LINE__, - mdlMap->pid - ); - } + _UnmapUserLogical(PID, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE); gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap)); } @@ -2287,7 +2313,6 @@ gceSTATUS gckOS_FreeNonPagedMemory( { PLINUX_MDL mdl; PLINUX_MDL_MAP mdlMap; - struct task_struct * task; #ifdef NO_DMA_COHERENT unsigned size; gctPOINTER vaddr; @@ -2350,27 +2375,7 @@ gceSTATUS gckOS_FreeNonPagedMemory( { if (mdlMap->vmaAddr != gcvNULL) { - /* Get the current pointer for the task with stored pid. */ - task = FIND_TASK_BY_PID(mdlMap->pid); - - if (task != gcvNULL && task->mm != gcvNULL) - { - down_write(&task->mm->mmap_sem); - - if (do_munmap(task->mm, - (unsigned long)mdlMap->vmaAddr, - mdl->numPages * PAGE_SIZE) < 0) - { - gcmkTRACE_ZONE( - gcvLEVEL_WARNING, gcvZONE_OS, - "%s(%d): do_munmap failed", - __FUNCTION__, __LINE__ - ); - } - - up_write(&task->mm->mmap_sem); - } - + _UnmapUserLogical(mdlMap->pid, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE); mdlMap->vmaAddr = gcvNULL; } @@ -4687,7 +4692,6 @@ gckOS_UnlockPages( { PLINUX_MDL_MAP mdlMap; PLINUX_MDL mdl = (PLINUX_MDL)Physical; - struct task_struct * task; gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X", Os, Physical, Bytes, Logical); @@ -4709,16 +4713,7 @@ gckOS_UnlockPages( { if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid)) { - /* Get the current pointer for the task with stored pid. */ - task = FIND_TASK_BY_PID(mdlMap->pid); - - if (task != gcvNULL && task->mm != gcvNULL) - { - down_write(&task->mm->mmap_sem); - do_munmap(task->mm, (unsigned long)mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE); - up_write(&task->mm->mmap_sem); - } - + _UnmapUserLogical(mdlMap->pid, mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE); mdlMap->vmaAddr = gcvNULL; } @@ -6914,8 +6909,8 @@ gckOS_GetThreadID( ** gckOS Os ** Pointer to a gckOS object. ** -** gceCORE Core -** Core type. +** gckCORE Core +** GPU whose power is set. ** ** gctBOOL Clock ** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock. @@ -7597,7 +7592,6 @@ gckOS_MapSignal( { gceSTATUS status; gcsSIGNAL_PTR signal; - gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process); gcmkVERIFY_ARGUMENT(Signal != gcvNULL); @@ -7605,7 +7599,7 @@ gckOS_MapSignal( gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)Signal, (gctPOINTER)&signal)); - if (atomic_inc_return(&signal->ref) <= 1) + if(atomic_inc_return(&signal->ref) <= 1) { /* The previous value is 0, it has been deleted. */ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); @@ -7674,6 +7668,7 @@ gckOS_CreateUserSignal( OUT gctINT * SignalID ) { + /* Create a new signal. */ return gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) SignalID); } diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index 61687ad1411c..db22753e8276 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -40,6 +40,7 @@ #include "ipu_regs.h" #include "ipu_param_mem.h" +static DEFINE_MUTEX(ipu_clk_lock); static struct ipu_soc ipu_array[MXC_IPU_MAX_NUM]; int g_ipu_hw_rev; @@ -149,8 +150,8 @@ static int __devinit ipu_clk_setup_enable(struct ipu_soc *ipu, } dev_dbg(ipu->dev, "ipu_clk = %lu\n", clk_get_rate(ipu->ipu_clk)); - ipu->pixel_clk[0] = ipu_pixel_clk[0]; - ipu->pixel_clk[1] = ipu_pixel_clk[1]; + ipu->pixel_clk[0] = ipu_pixel_clk[pdev->id][0]; + ipu->pixel_clk[1] = ipu_pixel_clk[pdev->id][1]; ipu_lookups[pdev->id][0].clk = &ipu->pixel_clk[0]; ipu_lookups[pdev->id][1].clk = &ipu->pixel_clk[1]; @@ -371,14 +372,24 @@ void _ipu_unlock(struct ipu_soc *ipu) void _ipu_get(struct ipu_soc *ipu) { - if (atomic_inc_return(&ipu->ipu_use_count) == 1) - clk_enable(ipu->ipu_clk); + int ret; + + if (in_interrupt()) + return; + mutex_lock(&ipu_clk_lock); + ret = clk_enable(ipu->ipu_clk); + if (ret < 0) + BUG(); + mutex_unlock(&ipu_clk_lock); } void _ipu_put(struct ipu_soc *ipu) { - if (atomic_dec_return(&ipu->ipu_use_count) == 0) - clk_disable(ipu->ipu_clk); + if (in_interrupt()) + return; + mutex_lock(&ipu_clk_lock); + clk_disable(ipu->ipu_clk); + mutex_unlock(&ipu_clk_lock); } /*! @@ -406,7 +417,6 @@ static int __devinit ipu_probe(struct platform_device *pdev) spin_lock_init(&ipu->spin_lock); mutex_init(&ipu->mutex_lock); - atomic_set(&ipu->ipu_use_count, 0); g_ipu_hw_rev = plat_data->rev; @@ -2683,10 +2693,13 @@ EXPORT_SYMBOL(ipu_clear_irq); bool ipu_get_irq_status(struct ipu_soc *ipu, uint32_t irq) { uint32_t reg; + unsigned long lock_flags; _ipu_get(ipu); + spin_lock_irqsave(&ipu->spin_lock, lock_flags); reg = ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq)); + spin_unlock_irqrestore(&ipu->spin_lock, lock_flags); _ipu_put(ipu); @@ -2722,6 +2735,7 @@ int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, irqreturn_t(*handler) (int, void *), uint32_t irq_flags, const char *devname, void *dev_id) { + uint32_t reg; unsigned long lock_flags; BUG_ON(irq >= IPU_IRQ_COUNT); @@ -2744,13 +2758,15 @@ int ipu_request_irq(struct ipu_soc *ipu, uint32_t irq, /* clear irq stat for previous use */ ipu_cm_write(ipu, IPUIRQ_2_MASK(irq), IPUIRQ_2_STATREG(irq)); + /* enable the interrupt */ + reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq)); + reg |= IPUIRQ_2_MASK(irq); + ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq)); spin_unlock_irqrestore(&ipu->spin_lock, lock_flags); _ipu_put(ipu); - ipu_enable_irq(ipu, irq); /* enable the interrupt */ - return 0; } EXPORT_SYMBOL(ipu_request_irq); @@ -2769,14 +2785,23 @@ EXPORT_SYMBOL(ipu_request_irq); */ void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id) { + uint32_t reg; unsigned long lock_flags; - ipu_disable_irq(ipu, irq); /* disable the interrupt */ + _ipu_get(ipu); spin_lock_irqsave(&ipu->spin_lock, lock_flags); + + /* disable the interrupt */ + reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq)); + reg &= ~IPUIRQ_2_MASK(irq); + ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq)); if (ipu->irq_list[irq].dev_id == dev_id) ipu->irq_list[irq].handler = NULL; + spin_unlock_irqrestore(&ipu->spin_lock, lock_flags); + + _ipu_put(ipu); } EXPORT_SYMBOL(ipu_free_irq); @@ -2855,11 +2880,11 @@ uint32_t ipu_channel_status(struct ipu_soc *ipu, ipu_channel_t channel) { uint32_t dma_status; - _ipu_lock(ipu); _ipu_get(ipu); + _ipu_lock(ipu); dma_status = ipu_is_channel_busy(ipu, channel); - _ipu_put(ipu); _ipu_unlock(ipu); + _ipu_put(ipu); dev_dbg(ipu->dev, "%s, dma_status:%d.\n", __func__, dma_status); @@ -2979,13 +3004,16 @@ bool ipu_pixel_format_has_alpha(uint32_t fmt) return false; } -static int ipu_suspend_noirq(struct device *dev) +static int ipu_suspend(struct platform_device *pdev, pm_message_t state) { - struct platform_device *pdev = to_platform_device(dev); struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data; struct ipu_soc *ipu = platform_get_drvdata(pdev); + int i; - if (atomic_read(&ipu->ipu_use_count)) { + mutex_lock(&ipu_clk_lock); + ipu->ipu_use_count = clk_get_usecount(ipu->ipu_clk); + dev_dbg(ipu->dev, "%s, ipu_use_cnt:%d\n", __func__, ipu->ipu_use_count); + if (ipu->ipu_use_count) { /* save and disable enabled channels*/ ipu->idma_enable_reg[0] = ipu_idmac_read(ipu, IDMAC_CHA_EN(0)); ipu->idma_enable_reg[1] = ipu_idmac_read(ipu, IDMAC_CHA_EN(32)); @@ -3009,7 +3037,7 @@ static int ipu_suspend_noirq(struct device *dev) msleep(2); time += 2; if (time >= timeout) - return -1; + goto err; } ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(0)); ipu_idmac_write(ipu, 0, IDMAC_CHA_EN(32)); @@ -3051,26 +3079,34 @@ static int ipu_suspend_noirq(struct device *dev) ipu->buf_ready_reg[8] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(0)); ipu->buf_ready_reg[9] = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(32)); - clk_disable(ipu->ipu_clk); + for (i = 0; i < ipu->ipu_use_count; i++) + clk_disable(ipu->ipu_clk); } + mutex_unlock(&ipu_clk_lock); if (plat_data->pg) plat_data->pg(1); return 0; + +err: + mutex_unlock(&ipu_clk_lock); + return -1; } -static int ipu_resume_noirq(struct device *dev) +static int ipu_resume(struct platform_device *pdev) { - struct platform_device *pdev = to_platform_device(dev); struct imx_ipuv3_platform_data *plat_data = pdev->dev.platform_data; struct ipu_soc *ipu = platform_get_drvdata(pdev); + int i; if (plat_data->pg) plat_data->pg(0); - if (atomic_read(&ipu->ipu_use_count)) { - clk_enable(ipu->ipu_clk); + dev_dbg(ipu->dev, "%s, ipu_use_cnt:%d\n", __func__, ipu->ipu_use_count); + if (ipu->ipu_use_count) { + for (i = 0; i < ipu->ipu_use_count; i++) + _ipu_get(ipu); /* restore buf ready regs */ ipu_cm_write(ipu, ipu->buf_ready_reg[0], IPU_CHA_BUF0_RDY(0)); @@ -3122,20 +3158,16 @@ static int ipu_resume_noirq(struct device *dev) return 0; } -static const struct dev_pm_ops mxcipu_pm_ops = { - .suspend_noirq = ipu_suspend_noirq, - .resume_noirq = ipu_resume_noirq, -}; - /*! * This structure contains pointers to the power management callback functions. */ static struct platform_driver mxcipu_driver = { .driver = { .name = "imx-ipuv3", - .pm = &mxcipu_pm_ops, }, .probe = ipu_probe, + .suspend = ipu_suspend, + .resume = ipu_resume, .remove = ipu_remove, }; diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c index 6810cea8f503..8de791bbd118 100644 --- a/drivers/mxc/ipu3/ipu_device.c +++ b/drivers/mxc/ipu3/ipu_device.c @@ -351,6 +351,7 @@ static DECLARE_WAIT_QUEUE_HEAD(thread_waitq); static DECLARE_WAIT_QUEUE_HEAD(res_waitq); static atomic_t req_cnt; static int major; +static int max_ipu_no; static int thread_id; static atomic_t frame_no; static struct class *ipu_class; @@ -1147,7 +1148,7 @@ static int _get_vdoa_ipu_res(struct ipu_task_entry *t) } } - for (i = 0; i < MXC_IPU_MAX_NUM; i++) { + for (i = 0; i < max_ipu_no; i++) { ipu = ipu_get_soc(i); if (IS_ERR(ipu)) BUG(); @@ -1176,7 +1177,7 @@ static int _get_vdoa_ipu_res(struct ipu_task_entry *t) if (found_ipu) goto next; - for (i = 0; i < MXC_IPU_MAX_NUM; i++) { + for (i = 0; i < max_ipu_no; i++) { ipu = ipu_get_soc(i); if (IS_ERR(ipu)) BUG(); @@ -1704,7 +1705,7 @@ static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t, return -EINVAL; else if (param.band_mode) param.band_lines = (1 << t->set.band_lines); - for (i = 0; i < MXC_IPU_MAX_NUM; i++) { + for (i = 0; i < max_ipu_no; i++) { ipu_idx = ipu_get_soc(i); if (!IS_ERR(ipu_idx) && ipu_idx == ipu) break; @@ -1712,7 +1713,7 @@ static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t, if (t->set.task & VDOA_ONLY) /* dummy, didn't need ipu res */ i = 0; - if (MXC_IPU_MAX_NUM == i) { + if (max_ipu_no == i) { dev_err(t->dev, "ERR:[0x%p] get ipu num\n", t); return -EINVAL; } @@ -1749,7 +1750,9 @@ static int init_tiled_buf(struct ipu_soc *ipu, struct ipu_task_entry *t, return -EINVAL; } } - vdoa_setup(t->vdoa_handle, ¶m); + ret = vdoa_setup(t->vdoa_handle, ¶m); + if (ret) + goto done; vdoa_get_output_buf(t->vdoa_handle, &buf); if (t->set.task & VDOA_ONLY) goto done; @@ -2883,7 +2886,7 @@ static void wait_split_task_complete(struct ipu_task_entry *parent, out: if (ret == -ETIMEDOUT) { /* debug */ - for (k = 0; k < MXC_IPU_MAX_NUM; k++) { + for (k = 0; k < max_ipu_no; k++) { ipu = ipu_get_soc(k); if (IS_ERR(ipu)) { BUG(); @@ -3407,6 +3410,7 @@ int register_ipu_device(struct ipu_soc *ipu, int id) mutex_init(&ipu_ch_tbl.lock); } + max_ipu_no = ++id; ipu->rot_dma[0].size = 0; ipu->rot_dma[1].size = 0; diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index d2fa65dd774e..4a774396ee99 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -174,44 +174,68 @@ static int _ipu_pixel_clk_set_parent(struct clk *clk, struct clk *parent) #else #define __INIT_CLK_DEBUG(n) #endif -struct clk ipu_pixel_clk[] = { +struct clk ipu_pixel_clk[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU] = { { - __INIT_CLK_DEBUG(pixel_clk_0) - .id = 0, - .get_rate = _ipu_pixel_clk_get_rate, - .set_rate = _ipu_pixel_clk_set_rate, - .round_rate = _ipu_pixel_clk_round_rate, - .set_parent = _ipu_pixel_clk_set_parent, - .enable = _ipu_pixel_clk_enable, - .disable = _ipu_pixel_clk_disable, + { + __INIT_CLK_DEBUG(ipu1_pixel_clk_0) + .id = 0, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, + { + __INIT_CLK_DEBUG(ipu1_pixel_clk_1) + .id = 1, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, }, { - __INIT_CLK_DEBUG(pixel_clk_1) - .id = 1, - .get_rate = _ipu_pixel_clk_get_rate, - .set_rate = _ipu_pixel_clk_set_rate, - .round_rate = _ipu_pixel_clk_round_rate, - .set_parent = _ipu_pixel_clk_set_parent, - .enable = _ipu_pixel_clk_enable, - .disable = _ipu_pixel_clk_disable, + { + __INIT_CLK_DEBUG(ipu2_pixel_clk_0) + .id = 0, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, + { + __INIT_CLK_DEBUG(ipu2_pixel_clk_1) + .id = 1, + .get_rate = _ipu_pixel_clk_get_rate, + .set_rate = _ipu_pixel_clk_set_rate, + .round_rate = _ipu_pixel_clk_round_rate, + .set_parent = _ipu_pixel_clk_set_parent, + .enable = _ipu_pixel_clk_enable, + .disable = _ipu_pixel_clk_disable, + }, }, }; -struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2] = { +struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU] = { { { - .con_id = "pixel_clk_0", + .con_id = "ipu1_pixel_clk_0", }, { - .con_id = "pixel_clk_1", + .con_id = "ipu1_pixel_clk_1", }, }, { { - .con_id = "pixel_clk_0", + .con_id = "ipu2_pixel_clk_0", }, { - .con_id = "pixel_clk_1", + .con_id = "ipu2_pixel_clk_1", }, }, }; diff --git a/drivers/mxc/ipu3/ipu_ic.c b/drivers/mxc/ipu3/ipu_ic.c index e21d6134c84a..84dcbb145f6f 100644 --- a/drivers/mxc/ipu3/ipu_ic.c +++ b/drivers/mxc/ipu3/ipu_ic.c @@ -841,7 +841,7 @@ static bool _calc_resize_coeffs(struct ipu_soc *ipu, where M = 2^13, SI - input size, SO - output size */ *resizeCoeff = (8192L * (tempSize - 1)) / (outSize - 1); if (*resizeCoeff >= 16384L) { - dev_err(ipu->dev, "Warning! Overflow on resize coeff.\n"); + dev_dbg(ipu->dev, "Warning! Overflow on resize coeff.\n"); *resizeCoeff = 0x3FFF; } diff --git a/drivers/mxc/ipu3/ipu_prv.h b/drivers/mxc/ipu3/ipu_prv.h index 526a2c0a36f0..7280dbaf00a8 100644 --- a/drivers/mxc/ipu3/ipu_prv.h +++ b/drivers/mxc/ipu3/ipu_prv.h @@ -20,16 +20,13 @@ #include <linux/interrupt.h> #include <linux/fsl_devices.h> -#ifdef CONFIG_MXC_IPU_V3H -#define MXC_IPU_MAX_NUM 2 -#else -#define MXC_IPU_MAX_NUM 1 -#endif +#define MXC_IPU_MAX_NUM 2 +#define MXC_DI_NUM_PER_IPU 2 /* Globals */ extern int dmfc_type_setup; -extern struct clk ipu_pixel_clk[]; -extern struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][2]; +extern struct clk ipu_pixel_clk[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU]; +extern struct clk_lookup ipu_lookups[MXC_IPU_MAX_NUM][MXC_DI_NUM_PER_IPU]; #define IDMA_CHAN_INVALID 0xFF #define HIGH_RESOLUTION_WIDTH 1024 @@ -92,7 +89,7 @@ struct ipu_soc { uint32_t channel_enable_mask; /*use count*/ - atomic_t ipu_use_count; + int ipu_use_count; int dc_use_count; int dp_use_count; int dmfc_use_count; diff --git a/drivers/mxc/ipu3/vdoa.c b/drivers/mxc/ipu3/vdoa.c index 5800fc606f8c..f9cba78e27b4 100644 --- a/drivers/mxc/ipu3/vdoa.c +++ b/drivers/mxc/ipu3/vdoa.c @@ -25,10 +25,10 @@ #include <linux/iram_alloc.h> #include "vdoa.h" -/* FIXME: use cmdline to specify the iram size */ /* 6band(3field* double buffer) * (width*2) * bandline(8) = 6x1024x2x8 = 96k or 72k(1.5byte) */ -#define VDOA_IRAM_SIZE (1024*96) +#define MAX_VDOA_IRAM_SIZE (1024*96) +#define VDOA_IRAM_SIZE (1024*72) #define VDOAC_BAND_HEIGHT_32LINES (32) #define VDOAC_BAND_HEIGHT_16LINES (16) @@ -123,6 +123,7 @@ struct vdoa_info { }; static struct vdoa_info *g_vdoa; +static unsigned long iram_size; static DEFINE_MUTEX(vdoa_lock); static inline void vdoa_read_register(struct vdoa_info *vdoa, @@ -148,15 +149,16 @@ static void dump_registers(struct vdoa_info *vdoa) vdoa_read_register(vdoa, i, &data); } -void vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params) +int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params) { int band_size; + int total_band_size = 0; int ipu_stride; u32 data; struct vdoa_info *vdoa = (struct vdoa_info *)handle; CHECK_NULL_PTR(vdoa); - CHECK_STATE(VDOA_GET | VDOA_GET_OBUF | VDOA_STOP, return); + CHECK_STATE(VDOA_GET | VDOA_GET_OBUF | VDOA_STOP, return -EINVAL); if (VDOA_GET == vdoa->state) { dev_dbg(vdoa->dev, "w:%d, h:%d.\n", params->width, params->height); @@ -193,6 +195,12 @@ void vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params) band_size = ((params->width * 3) >> 1) * params->band_lines; if (params->interlaced) { + total_band_size = 6 * band_size; /* 3 frames*double buffer */ + if (iram_size < total_band_size) { + dev_err(vdoa->dev, "iram_size:0x%lx is smaller than " + "request:0x%x!\n", iram_size, total_band_size); + return -EINVAL; + } if (params->vfield_buf.prev_veba) { if (params->band_mode) { vdoa_write_register(vdoa, VDOAIEBA00, @@ -265,6 +273,7 @@ void vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params) params->width * params->height); } vdoa->state = VDOA_SETUP; + return 0; } void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf) @@ -330,7 +339,7 @@ void vdoa_stop(vdoa_handle_t handle) struct vdoa_info *vdoa = (struct vdoa_info *)handle; CHECK_NULL_PTR(vdoa); - CHECK_STATE(VDOA_START | VDOA_INIRQ, return); + CHECK_STATE(VDOA_GET | VDOA_START | VDOA_INIRQ, return); vdoa->state = VDOA_STOP; disable_irq(vdoa->irq); @@ -394,6 +403,21 @@ static irqreturn_t vdoa_irq_handler(int irq, void *data) return IRQ_HANDLED; } +/* IRAM Size in Kbytes, example:vdoa_iram_size=64, 64KBytes */ +static int __init vdoa_iram_size_setup(char *options) +{ + int ret; + + ret = strict_strtoul(options, 0, &iram_size); + if (ret) + iram_size = 0; + else + iram_size *= SZ_1K; + + return 1; +} +__setup("vdoa_iram_size=", vdoa_iram_size_setup); + static int vdoa_probe(struct platform_device *pdev) { int ret; @@ -451,16 +475,16 @@ static int vdoa_probe(struct platform_device *pdev) ret = PTR_ERR(vdoa->clk); goto err_clk; } - - vdoa->iram_base = iram_alloc(VDOA_IRAM_SIZE, &vdoa->iram_paddr); + if ((iram_size == 0) || (iram_size > MAX_VDOA_IRAM_SIZE)) + iram_size = VDOA_IRAM_SIZE; + vdoa->iram_base = iram_alloc(iram_size, &vdoa->iram_paddr); if (!vdoa->iram_base) { - dev_err(dev, "failed to get iram memory:0x%x\n", - VDOA_IRAM_SIZE); + dev_err(dev, "failed to get iram memory:0x%lx\n", iram_size); ret = -ENOMEM; goto err_iram_alloc; } - dev_dbg(dev, "iram_base:0x%p,iram_paddr:0x%lx,size:0x%x\n", - vdoa->iram_base, vdoa->iram_paddr, VDOA_IRAM_SIZE); + dev_dbg(dev, "iram_base:0x%p,iram_paddr:0x%lx,size:0x%lx\n", + vdoa->iram_base, vdoa->iram_paddr, iram_size); vdoa->state = VDOA_INIT; dev_set_drvdata(dev, vdoa); @@ -491,7 +515,7 @@ static int __devexit vdoa_remove(struct platform_device *pdev) clk_put(vdoa->clk); clk_disable(vdoa->clk); - iram_free(vdoa->iram_paddr, VDOA_IRAM_SIZE); + iram_free(vdoa->iram_paddr, iram_size); iounmap(vdoa->reg_base); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { diff --git a/drivers/mxc/ipu3/vdoa.h b/drivers/mxc/ipu3/vdoa.h index 82b0ee1f2c3c..23d72497a0a7 100644 --- a/drivers/mxc/ipu3/vdoa.h +++ b/drivers/mxc/ipu3/vdoa.h @@ -60,7 +60,7 @@ struct vdoa_ipu_buf { struct vdoa_info; typedef void *vdoa_handle_t; -void vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params); +int vdoa_setup(vdoa_handle_t handle, struct vdoa_params *params); void vdoa_get_output_buf(vdoa_handle_t handle, struct vdoa_ipu_buf *buf); int vdoa_start(vdoa_handle_t handle, int timeout_ms); void vdoa_stop(vdoa_handle_t handle); diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 27dcf755debc..467b5355de89 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -195,6 +195,7 @@ struct flexcan_priv { struct clk *clk; struct flexcan_platform_data *pdata; enum flexcan_ip_version version; + int id; }; static struct can_bittiming_const flexcan_bittiming_const = { @@ -580,7 +581,8 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id) if (reg_esr & FLEXCAN_ESR_WAK_INT) { /* first clear stop request then wakeup irq status */ if (priv->version >= FLEXCAN_VER_10_0_12) - mxc_iomux_set_gpr_register(13, 28, 1, 0); + /* CAN1/CAN2_STOP_REQ bit 28/29 in group 13 */ + mxc_iomux_set_gpr_register(13, 28 + priv->id, 1, 0); writel(FLEXCAN_ESR_WAK_INT, ®s->esr); } @@ -960,6 +962,9 @@ static int __devinit flexcan_probe(struct platform_device *pdev) resource_size_t mem_size; int err, irq; + if (pdev->id < 0) + return -ENODEV; + clk = clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "no clock defined\n"); @@ -1007,6 +1012,7 @@ static int __devinit flexcan_probe(struct platform_device *pdev) priv->base = base; priv->dev = dev; priv->clk = clk; + priv->id = pdev->id; priv->pdata = pdev->dev.platform_data; priv->version = pdev->id_entry->driver_data; @@ -1074,7 +1080,8 @@ static int flexcan_suspend(struct platform_device *pdev, pm_message_t state) /* enable stop request for wakeup */ if (priv->version >= FLEXCAN_VER_10_0_12) - mxc_iomux_set_gpr_register(13, 28, 1, 1); + /* CAN1/CAN2_STOP_REQ bit 28/29 in group 13 */ + mxc_iomux_set_gpr_register(13, 28 + priv->id, 1, 1); ret = irq_set_irq_wake(dev->irq, 1); if (ret) diff --git a/drivers/net/fec.c b/drivers/net/fec.c index 6e710e11f1a4..acb2965ae77d 100755 --- a/drivers/net/fec.c +++ b/drivers/net/fec.c @@ -71,17 +71,14 @@ #define FEC_QUIRK_SWAP_FRAME (1 << 1) static struct platform_device_id fec_devtype[] = { -#ifdef CONFIG_SOC_IMX6Q { - .name = DRIVER_NAME, + .name = "enet", .driver_data = FEC_QUIRK_ENET_MAC, }, -#else { - .name = DRIVER_NAME, + .name = "fec", .driver_data = 0, }, -#endif { .name = "imx28-fec", .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME, @@ -146,12 +143,11 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address"); #define FEC_ENET_MII_CLK ((uint)2500000) #define FEC_ENET_HOLD_TIME ((uint)0x100) /* 2 internal clock cycle*/ -#if defined(CONFIG_FEC_1588) && (defined(CONFIG_ARCH_MX28) || \ - defined(CONFIG_ARCH_MX6)) -#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII | \ - FEC_ENET_TS_AVAIL | FEC_ENET_TS_TIMER) -#else #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) +#if defined(CONFIG_FEC_1588) +#define FEC_1588_IMASK (FEC_ENET_TS_AVAIL | FEC_ENET_TS_TIMER) +#else +#define FEC_1588_IMASK 0 #endif /* The FEC stores dest/src/type, data, and checksum for receive packets. @@ -1032,7 +1028,7 @@ static int fec_enet_mii_probe(struct net_device *ndev) } /* mask with MAC supported features */ - if (cpu_is_mx6()) + if (cpu_is_mx6q() || cpu_is_mx6dl()) phy_dev->supported &= PHY_GBIT_FEATURES; else phy_dev->supported &= PHY_BASIC_FEATURES; @@ -1091,7 +1087,7 @@ static int fec_enet_mii_init(struct platform_device *pdev) (FEC_ENET_MII_CLK << 2)) << 1; /* set hold time to 2 internal clock cycle */ - if (cpu_is_mx6()) + if (cpu_is_mx6q() || cpu_is_mx6dl()) fep->phy_speed |= FEC_ENET_HOLD_TIME; writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); @@ -1546,14 +1542,14 @@ fec_restart(struct net_device *dev, int duplex) udelay(10); /* - * enet-mac reset will reset mac address registers too, - * so need to reconfigure it. + /* if uboot don't set MAC address, get MAC address + * from command line; if command line don't set MAC + * address, get from OCOTP; otherwise, allocate random + * address. */ - if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) { - memcpy(&temp_mac, dev->dev_addr, ETH_ALEN); - writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); - writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); - } + memcpy(&temp_mac, dev->dev_addr, ETH_ALEN); + writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW); + writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH); /* Clear any outstanding interrupt. */ writel(0xffc00000, fep->hwp + FEC_IEVENT); @@ -1623,23 +1619,24 @@ fec_restart(struct net_device *dev, int duplex) val |= (1 << 9); writel(val, fep->hwp + FEC_R_CNTRL); + } - if (fep->ptimer_present) { - /* Set Timer count */ - ret = fec_ptp_start(fep->ptp_priv); - if (ret) { - fep->ptimer_present = 0; - reg = 0x0; - } else + if (fep->ptimer_present) { + /* Set Timer count */ + ret = fec_ptp_start(fep->ptp_priv); + if (ret) { + fep->ptimer_present = 0; + reg = 0x0; + } else #if defined(CONFIG_SOC_IMX28) || defined(CONFIG_ARCH_MX6) - reg = 0x00000010; + reg = 0x00000010; #else - reg = 0x0; + reg = 0x0; #endif } else reg = 0x0; -#ifdef FEC_MIIGSK_ENR + if (cpu_is_mx25() || cpu_is_mx53() || cpu_is_mx6sl()) { if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { /* disable the gasket and wait */ writel(0, fep->hwp + FEC_MIIGSK_ENR); @@ -1654,8 +1651,14 @@ fec_restart(struct net_device *dev, int duplex) /* re-enable the gasket */ writel(2, fep->hwp + FEC_MIIGSK_ENR); + udelay(10); + if (!(readl(fep->hwp + FEC_MIIGSK_ENR) & 4)) { + udelay(100); + if (!(readl(fep->hwp + FEC_MIIGSK_ENR) & 4)) + dev_err(&fep->pdev->dev, + "switch to RMII failed!\n"); + } } -#endif } /* ENET enable */ @@ -1668,7 +1671,7 @@ fec_restart(struct net_device *dev, int duplex) fep->phy_dev->speed == SPEED_1000) val |= (0x1 << 5); - if (cpu_is_mx6()) { + if (cpu_is_mx6q() || cpu_is_mx6dl()) { /* enable endian swap */ val |= (0x1 << 8); /* enable ENET store and forward mode */ @@ -1679,7 +1682,11 @@ fec_restart(struct net_device *dev, int duplex) writel(0, fep->hwp + FEC_R_DES_ACTIVE); /* Enable interrupts we wish to service */ - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + if (cpu_is_mx6q() || cpu_is_mx6dl() || cpu_is_mx2() || cpu_is_mx3()) + val = (FEC_1588_IMASK | FEC_DEFAULT_IMASK); + else + val = FEC_DEFAULT_IMASK; + writel(val, fep->hwp + FEC_IMASK); } static void @@ -1699,7 +1706,7 @@ fec_stop(struct net_device *dev) writel(1, fep->hwp + FEC_ECNTRL); udelay(10); - if (cpu_is_mx6()) + if (cpu_is_mx6q() || cpu_is_mx6dl()) /* FIXME: we have to enable enet to keep mii interrupt works. */ writel(2, fep->hwp + FEC_ECNTRL); @@ -1707,6 +1714,8 @@ fec_stop(struct net_device *dev) if (fep->ptimer_present) fec_ptp_stop(fep->ptp_priv); writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + netif_stop_queue(dev); + fep->link = 0; } static int __devinit diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 8145ff85c8ab..6e53cce3c7fd 100755 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -219,6 +219,15 @@ config CHARGER_MAX8903 pins based on the status of charger connections with interrupt handlers. +config SABRESD_MAX8903 + tristate "Sabresd Board Battery DC-DC Charger for USB and Adapter Power" + depends on GENERIC_HARDIRQS + depends on TOUCHSCREEN_MAX11801 + help + Say Y to enable support for the MAX8903 DC-DC charger and sysfs on + sabresd board.The driver supports controlling charger and battery + based on the status of charger connections with interrupt handlers. + config CHARGER_TWL4030 tristate "OMAP TWL4030 BCI charger driver" depends on TWL4030_CORE diff --git a/drivers/power/Makefile b/drivers/power/Makefile index ad6493affec8..1f359ba8a03c 100755 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -37,3 +37,4 @@ obj-$(CONFIG_CHARGER_MAX8903) += max8903_charger.o obj-$(CONFIG_CHARGER_TWL4030) += twl4030_charger.o obj-$(CONFIG_CHARGER_GPIO) += gpio-charger.o obj-$(CONFIG_BATTERY_DA9052) += da9052-battery.o +obj-$(CONFIG_SABRESD_MAX8903) += sabresd_battery.o diff --git a/drivers/power/max8903_battery.c b/drivers/power/max8903_battery.c new file mode 100755 index 000000000000..84b5373cbb2f --- /dev/null +++ b/drivers/power/max8903_battery.c @@ -0,0 +1,748 @@ +/* + * max8903_battery.c - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * Based on max8903_charger.c + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/power_supply.h> +#include <linux/platform_device.h> +#include <linux/power/max8903_battery.h> +#include <linux/sort.h> + + +#define BATTERY_UPDATE_INTERVAL 5 /*seconds*/ +#define LOW_VOLT_THRESHOLD 2800000 +#define HIGH_VOLT_THRESHOLD 4200000 +#define ADC_SAMPLE_COUNT 4 + +struct max8903_data { + struct max8903_pdata *pdata; + struct device *dev; + struct power_supply psy; + bool fault; + bool usb_in; + bool ta_in; + bool chg_state; + struct delayed_work work; + unsigned int interval; + unsigned short thermal_raw; + int voltage_uV; + int current_uA; + int battery_status; + int charger_online; + int charger_voltage_uV; + int real_capacity; + int percent; + int old_percent; + struct power_supply bat; + struct mutex work_lock; +}; + +typedef struct { + u32 voltage; + u32 percent; +} battery_capacity , *pbattery_capacity; + +static bool capacity_changed_flag; + +static battery_capacity chargingTable[] = { + {4148, 100}, + {4126, 99}, + {4123, 98}, + {4120, 97}, + {4105, 96}, + {4090, 96}, + {4075, 95}, + {4060, 94}, + {4045, 93}, + {4030, 92}, + {4015, 91}, + {4000, 90}, + {3900, 85}, + {3790, 80}, + {3760, 75}, + {3730, 70}, + {3700, 65}, + {3680, 60}, + {3660, 55}, + {3640, 50}, + {3600, 45}, + {3550, 40}, + {3510, 35}, + {3450, 30}, + {3310, 25}, + {3240, 20}, + {3180, 15}, + {3030, 10}, + {2820, 5}, + {2800, 0}, + {0, 0} +}; +static battery_capacity dischargingTable[] = { + {4100, 100}, + {4090, 99}, + {4080, 98}, + {4060, 97}, + {4040, 96}, + {3920, 96}, + {3900, 95}, + {3970, 94}, + {3940, 93}, + {3910, 92}, + {3890, 91}, + {3860, 90}, + {3790, 85}, + {3690, 80}, + {3660, 75}, + {3630, 70}, + {3600, 65}, + {3580, 60}, + {3560, 55}, + {3540, 50}, + {3500, 45}, + {3450, 40}, + {3410, 35}, + {3350, 30}, + {3310, 25}, + {3240, 20}, + {3180, 15}, + {3030, 10}, + {2820, 5}, + {2800, 0}, + {0, 0} +}; + +u32 calibrate_battery_capability_percent(struct max8903_data *data) +{ + u8 i; + pbattery_capacity pTable; + u32 tableSize; + if (data->battery_status == POWER_SUPPLY_STATUS_DISCHARGING) { + pTable = dischargingTable; + tableSize = sizeof(dischargingTable)/sizeof(dischargingTable[0]); + } else { + pTable = chargingTable; + tableSize = sizeof(chargingTable)/sizeof(chargingTable[0]); + } + for (i = 0; i < tableSize; i++) { + if (data->voltage_uV >= pTable[i].voltage) + return pTable[i].percent; + } + + return 0; +} + +static enum power_supply_property max8903_charger_props[] = { + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_HEALTH, +}; + +static enum power_supply_property max8903_battery_props[] = { + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, +}; + +extern u32 max11801_read_adc(void); + +static void max8903_charger_update_status(struct max8903_data *data) +{ + if (data->usb_in || data->ta_in) { + data->charger_online = 1; + } else { + data->charger_online = 0; + } + if (data->charger_online == 0) { + data->battery_status = POWER_SUPPLY_STATUS_DISCHARGING; + } else { + if (data->pdata->chg) { + if (gpio_get_value(data->pdata->chg) == 0) { + data->battery_status = POWER_SUPPLY_STATUS_CHARGING; + } else if ((data->usb_in || data->ta_in) && + gpio_get_value(data->pdata->chg) == 1) { + data->battery_status = POWER_SUPPLY_STATUS_NOT_CHARGING; + } + } + } + pr_debug("chg: %d \n", gpio_get_value(data->pdata->chg)); +} +static int cmp_func(const void *_a, const void *_b) +{ + const int *a = _a, *b = _b; + + if (*a > *b) + return 1; + if (*a < *b) + return -1; + return 0; +} +u32 calibration_voltage(struct max8903_data *data) +{ + int volt[ADC_SAMPLE_COUNT]; + u32 voltage_data; + int i; + for (i = 0; i < ADC_SAMPLE_COUNT; i++) { + if (data->charger_online == 0) { + /* ADC offset when battery is discharger*/ + volt[i] = max11801_read_adc()-1880; + } else { + volt[i] = max11801_read_adc()-1960; + } + } + sort(volt, i, 4, cmp_func, NULL); + for (i = 0; i < ADC_SAMPLE_COUNT; i++) + pr_debug("volt_sorted[%2d]: %d\n", i, volt[i]); + /* get the average of second max/min of remained. */ + voltage_data = (volt[1] + volt[i - 2]) / 2; + return voltage_data; +} + +static void max8903_battery_update_status(struct max8903_data *data) +{ + static int counter; +#if 0 + data->voltage_uV = max11801_read_adc(); +#endif + mutex_lock(&data->work_lock); + data->voltage_uV = calibration_voltage(data); + data->percent = calibrate_battery_capability_percent(data); + if (data->percent != data->old_percent) { + data->old_percent = data->percent; + capacity_changed_flag = true; + } + if ((capacity_changed_flag == true) && (data->charger_online)) { + counter++; + if (counter > 2) { + counter = 0; + capacity_changed_flag = false; + power_supply_changed(&data->bat); + } + } + mutex_unlock(&data->work_lock); +} + +static int max8903_battery_get_property(struct power_supply *bat, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8903_data *di = container_of(bat, + struct max8903_data, bat); + static unsigned long last; + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + if (di->pdata->chg) { + if (gpio_get_value(di->pdata->chg) == 0) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + } else if ((di->usb_in || di->ta_in) && gpio_get_value(di->pdata->chg) == 1) { + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + } else { + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + } + } + di->battery_status = val->intval; + return 0; + default: + break; + } + if (!last || time_after(jiffies, last + HZ / 2)) { + last = jiffies; + max8903_charger_update_status(di); + max8903_battery_update_status(di); + } + switch (psp) { + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = di->voltage_uV; + break; +#if 0 + case POWER_SUPPLY_PROP_CURRENT_NOW: + val->intval = di->current_uA; + break; +#endif + case POWER_SUPPLY_PROP_CHARGE_NOW: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = HIGH_VOLT_THRESHOLD; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: + val->intval = LOW_VOLT_THRESHOLD; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = 1; + break; + case POWER_SUPPLY_PROP_CAPACITY: + val->intval = di->percent < 0 ? 0 : + (di->percent > 100 ? 100 : di->percent); + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = 0; + if (di->usb_in || di->ta_in) + val->intval = 1; + di->charger_online = val->intval; + break; + default: + return -EINVAL; + } + + return 0; +} +static int max8903_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8903_data *data = container_of(psy, + struct max8903_data, psy); + + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + if (data->pdata->chg) { + if (gpio_get_value(data->pdata->chg) == 0) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + } + else if ((data->usb_in || data->ta_in) && + gpio_get_value(data->pdata->chg) == 1) { + val->intval = POWER_SUPPLY_STATUS_NOT_CHARGING; + } else { + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + } + } + data->battery_status = val->intval; + break; + case POWER_SUPPLY_PROP_ONLINE: + val->intval = 0; + if (data->usb_in || data->ta_in) + val->intval = 1; + data->charger_online = val->intval; + break; + case POWER_SUPPLY_PROP_HEALTH: + val->intval = POWER_SUPPLY_HEALTH_GOOD; + if (data->fault) + val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + default: + return -EINVAL; + } + return 0; +} + +static irqreturn_t max8903_dcin(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool ta_in; + enum power_supply_type old_type; + + ta_in = gpio_get_value(pdata->dok) ? false : true; + + if (ta_in == data->ta_in) + return IRQ_HANDLED; + + data->ta_in = ta_in; +#if 0 + /* Set Current-Limit-Mode 1:DC 0:USB */ + if (pdata->dcm) + gpio_set_value(pdata->dcm, ta_in ? 1 : 0); + /* Charger Enable / Disable (cen is negated) */ + if (pdata->cen) + gpio_set_value(pdata->cen, ta_in ? 0 : + (data->usb_in ? 0 : 1)); +#endif + pr_info("TA(DC-IN) Charger %s.\n", ta_in ? + "Connected" : "Disconnected"); + + old_type = data->psy.type; + + if (data->ta_in) + data->psy.type = POWER_SUPPLY_TYPE_MAINS; + else if (data->usb_in) + data->psy.type = POWER_SUPPLY_TYPE_USB; + else + data->psy.type = POWER_SUPPLY_TYPE_BATTERY; + + if (old_type != data->psy.type) { + power_supply_changed(&data->psy); + power_supply_changed(&data->bat); + } + return IRQ_HANDLED; +} + +static irqreturn_t max8903_usbin(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool usb_in; + enum power_supply_type old_type; + + usb_in = gpio_get_value(pdata->uok) ? false : true; + + if (usb_in == data->usb_in) + return IRQ_HANDLED; + + data->usb_in = usb_in; + +#if 0 + /* Do not touch Current-Limit-Mode */ + + /* Charger Enable / Disable (cen is negated) */ + if (pdata->cen) + gpio_set_value(pdata->cen, usb_in ? 0 : + (data->ta_in ? 0 : 1)); +#endif + pr_info("USB Charger %s.\n", usb_in ? + "Connected" : "Disconnected"); + + old_type = data->psy.type; + + if (data->ta_in) + data->psy.type = POWER_SUPPLY_TYPE_MAINS; + else if (data->usb_in) + data->psy.type = POWER_SUPPLY_TYPE_USB; + else + data->psy.type = POWER_SUPPLY_TYPE_BATTERY; + + if (old_type != data->psy.type) { + power_supply_changed(&data->psy); + power_supply_changed(&data->bat); + } + return IRQ_HANDLED; +} + +static irqreturn_t max8903_fault(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool fault; + + fault = gpio_get_value(pdata->flt) ? false : true; + + if (fault == data->fault) + return IRQ_HANDLED; + + data->fault = fault; + + if (fault) + dev_err(data->dev, "Charger suffers a fault and stops.\n"); + else + dev_err(data->dev, "Charger recovered from a fault.\n"); + return IRQ_HANDLED; +} + +static irqreturn_t max8903_chg(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + int chg_state; + + chg_state = gpio_get_value(pdata->chg) ? false : true; + + if (chg_state == data->chg_state) + return IRQ_HANDLED; + + data->chg_state = chg_state; +#if 0 + if (chg_state) + pr_info("Charger stop.\n "); + else + pr_info("Charger start.\n "); +#endif + return IRQ_HANDLED; +} + +static void max8903_battery_work(struct work_struct *work) +{ + struct max8903_data *data; + data = container_of(work, struct max8903_data, work.work); + data->interval = HZ * BATTERY_UPDATE_INTERVAL; + + max8903_charger_update_status(data); + max8903_battery_update_status(data); + + pr_debug("battery voltage: %4d mV\n" , data->voltage_uV); + pr_debug("charger online status: %d\n" , data->charger_online); + pr_debug("battery status : %d\n" , data->battery_status); + pr_debug("battery capacity percent: %3d\n" , data->percent); + pr_debug("data->usb_in: %x , data->ta_in: %x \n" , data->usb_in, data->ta_in); + /* reschedule for the next time */ + schedule_delayed_work(&data->work, data->interval); +} +static __devinit int max8903_probe(struct platform_device *pdev) +{ + struct max8903_data *data; + struct device *dev = &pdev->dev; + struct max8903_pdata *pdata = pdev->dev.platform_data; + int ret = 0; + int gpio = 0; + int ta_in = 0; + int usb_in = 0; + int retval; + + data = kzalloc(sizeof(struct max8903_data), GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + data->pdata = pdata; + data->dev = dev; + + platform_set_drvdata(pdev, data); + capacity_changed_flag = false; + data->usb_in = 0; + data->ta_in = 0; + + if (pdata->dc_valid == false && pdata->usb_valid == false) { + dev_err(dev, "No valid power sources.\n"); + printk(KERN_INFO "No valid power sources.\n"); + ret = -EINVAL; + goto err; + } + if (pdata->dc_valid) { +#if 0 + if (pdata->dok && gpio_is_valid(pdata->dok) && + pdata->dcm && gpio_is_valid(pdata->dcm)) { +#endif + if (pdata->dok && gpio_is_valid(pdata->dok)) { + gpio = pdata->dok; /* PULL_UPed Interrupt */ + ta_in = gpio_get_value(gpio) ? 0 : 1; +#if 0 + gpio = pdata->dcm; /* Output */ + gpio_set_value(gpio, ta_in); +#endif + } else if (pdata->dok && gpio_is_valid(pdata->dok) && pdata->dcm_always_high) { + ta_in = pdata->dok; /* PULL_UPed Interrupt */ + ta_in = gpio_get_value(gpio) ? 0 : 1; + } else { + dev_err(dev, "When DC is wired, DOK and DCM should" + " be wired as well." + " or set dcm always high\n"); + ret = -EINVAL; + goto err; + } + } + if (pdata->usb_valid) { + if (pdata->uok && gpio_is_valid(pdata->uok)) { + gpio = pdata->uok; + usb_in = gpio_get_value(gpio) ? 0 : 1; + } else { + dev_err(dev, "When USB is wired, UOK should be wired." + "as well.\n"); + ret = -EINVAL; + goto err; + } + } + if (pdata->chg) { + if (!gpio_is_valid(pdata->chg)) { + dev_err(dev, "Invalid pin: chg.\n"); + ret = -EINVAL; + goto err; + } + } + + if (pdata->flt) { + if (!gpio_is_valid(pdata->flt)) { + dev_err(dev, "Invalid pin: flt.\n"); + ret = -EINVAL; + goto err; + } + } + + if (pdata->usus) { + if (!gpio_is_valid(pdata->usus)) { + dev_err(dev, "Invalid pin: usus.\n"); + ret = -EINVAL; + goto err; + } + } + mutex_init(&data->work_lock); + data->fault = false; + data->ta_in = ta_in; + data->usb_in = usb_in; + data->psy.name = "max8903-ac"; + data->psy.type = (ta_in) ? POWER_SUPPLY_TYPE_MAINS : + ((usb_in) ? POWER_SUPPLY_TYPE_USB : + POWER_SUPPLY_TYPE_BATTERY); + data->psy.get_property = max8903_get_property; + data->psy.properties = max8903_charger_props; + data->psy.num_properties = ARRAY_SIZE(max8903_charger_props); + ret = power_supply_register(dev, &data->psy); + if (ret) { + dev_err(dev, "failed: power supply register.\n"); + goto err_psy; + } + data->bat.name = "max8903-charger"; + data->bat.type = POWER_SUPPLY_TYPE_BATTERY; + data->bat.properties = max8903_battery_props; + data->bat.num_properties = ARRAY_SIZE(max8903_battery_props); + data->bat.get_property = max8903_battery_get_property; + data->bat.use_for_apm = 1; + retval = power_supply_register(&pdev->dev, &data->bat); + if (retval) { + dev_err(data->dev, "failed to register battery\n"); + goto battery_failed; + } + INIT_DELAYED_WORK(&data->work, max8903_battery_work); + schedule_delayed_work(&data->work, data->interval); + if (pdata->dc_valid) { + ret = request_threaded_irq(gpio_to_irq(pdata->dok), + NULL, max8903_dcin, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 DC IN", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for DC (%d)\n", + gpio_to_irq(pdata->dok), ret); + goto err_usb_irq; + } + } + + if (pdata->usb_valid) { + ret = request_threaded_irq(gpio_to_irq(pdata->uok), + NULL, max8903_usbin, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 USB IN", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for USB (%d)\n", + gpio_to_irq(pdata->uok), ret); + goto err_dc_irq; + } + } + + if (pdata->flt) { + ret = request_threaded_irq(gpio_to_irq(pdata->flt), + NULL, max8903_fault, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 Fault", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for Fault (%d)\n", + gpio_to_irq(pdata->flt), ret); + goto err_flt_irq; + } + } + + if (pdata->chg) { + ret = request_threaded_irq(gpio_to_irq(pdata->chg), + NULL, max8903_chg, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 Fault", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for Fault (%d)\n", + gpio_to_irq(pdata->flt), ret); + goto err_chg_irq; + } + } + return 0; +err_psy: + power_supply_unregister(&data->psy); +battery_failed: + power_supply_unregister(&data->bat); +err_usb_irq: + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + cancel_delayed_work(&data->work); +err_dc_irq: + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + cancel_delayed_work(&data->work); +err_flt_irq: + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + cancel_delayed_work(&data->work); +err_chg_irq: + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + cancel_delayed_work(&data->work); +err: + kfree(data); + return ret; +} + +static __devexit int max8903_remove(struct platform_device *pdev) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + if (data) { + struct max8903_pdata *pdata = data->pdata; + if (pdata->flt) + free_irq(gpio_to_irq(pdata->flt), data); + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->chg), data); + cancel_delayed_work_sync(&data->work); + power_supply_unregister(&data->psy); + power_supply_unregister(&data->bat); + kfree(data); + } + return 0; +} + +static int max8903_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + + cancel_delayed_work(&data->work); + return 0; +} + +static int max8903_resume(struct platform_device *pdev) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + + schedule_delayed_work(&data->work, BATTERY_UPDATE_INTERVAL); + return 0; + +} + +static struct platform_driver max8903_driver = { + .probe = max8903_probe, + .remove = __devexit_p(max8903_remove), + .suspend = max8903_suspend, + .resume = max8903_resume, + .driver = { + .name = "max8903-charger", + .owner = THIS_MODULE, + }, +}; + +static int __init max8903_init(void) +{ + return platform_driver_register(&max8903_driver); +} +module_init(max8903_init); + +static void __exit max8903_exit(void) +{ + platform_driver_unregister(&max8903_driver); +} +module_exit(max8903_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MAX8903 Battery Driver"); +MODULE_ALIAS("max8903_battery"); diff --git a/drivers/power/max8903_charger.c b/drivers/power/max8903_charger.c index 492df4310228..fee8191767f0 100644 --- a/drivers/power/max8903_charger.c +++ b/drivers/power/max8903_charger.c @@ -246,13 +246,13 @@ static __devinit int max8903_probe(struct platform_device *pdev) gpio = pdata->dok; /* PULL_UPed Interrupt */ error = gpio_request(gpio, "chg_dc"); - error = gpio_direction_input(gpio); if (error < 0) { dev_err(dev, "failed to configure" " request/direction for GPIO %d, error %d\n", gpio, error); goto err; } + gpio_direction_input(gpio); ta_in = gpio_get_value(gpio) ? 0 : 1; @@ -283,15 +283,15 @@ static __devinit int max8903_probe(struct platform_device *pdev) if (pdata->uok && gpio_is_valid(pdata->uok)) { gpio = pdata->uok; error = gpio_request(gpio, "chg_usb"); - error = gpio_direction_input(gpio); if (error < 0) { dev_err(dev, "failed to configure" " request/direction for GPIO %d, error %d\n", gpio, error); goto err; } - usb_in = gpio_get_value(gpio) ? 0 : 1; + gpio_direction_input(gpio); + usb_in = gpio_get_value(gpio) ? 0 : 1; if (usb_in) data->usb_in = true; else @@ -321,13 +321,13 @@ static __devinit int max8903_probe(struct platform_device *pdev) goto err; } error = gpio_request(pdata->chg, "chg_status"); - error = gpio_direction_input(pdata->chg); if (error < 0) { dev_err(dev, "failed to configure" " request/direction for GPIO %d, error %d\n", pdata->chg, error); goto err; } + error = gpio_direction_input(pdata->chg); } if (pdata->flt) { @@ -337,13 +337,13 @@ static __devinit int max8903_probe(struct platform_device *pdev) goto err; } error = gpio_request(pdata->flt, "chg_fault"); - error = gpio_direction_input(pdata->flt); if (error < 0) { dev_err(dev, "failed to configure" " request/direction for GPIO %d, error %d\n", pdata->flt, error); goto err; } + error = gpio_direction_input(pdata->flt); } if (pdata->usus) { diff --git a/drivers/power/sabresd_battery.c b/drivers/power/sabresd_battery.c new file mode 100755 index 000000000000..75d07b178083 --- /dev/null +++ b/drivers/power/sabresd_battery.c @@ -0,0 +1,701 @@ +/* + * sabresd_battery.c - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * Based on max8903_charger.c + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/slab.h> +#include <linux/power_supply.h> +#include <linux/platform_device.h> +#include <linux/power/sabresd_battery.h> +#include <linux/sort.h> + + +#define BATTERY_UPDATE_INTERVAL 5 /*seconds*/ +#define LOW_VOLT_THRESHOLD 2800000 +#define HIGH_VOLT_THRESHOLD 4200000 +#define ADC_SAMPLE_COUNT 6 + +struct max8903_data { + struct max8903_pdata *pdata; + struct device *dev; + struct power_supply psy; + bool fault; + bool usb_in; + bool ta_in; + bool chg_state; + struct delayed_work work; + unsigned int interval; + unsigned short thermal_raw; + int voltage_uV; + int current_uA; + int battery_status; + int charger_online; + int charger_voltage_uV; + int real_capacity; + int percent; + int old_percent; + struct power_supply bat; + struct mutex work_lock; +}; + +typedef struct { + u32 voltage; + u32 percent; +} battery_capacity , *pbattery_capacity; + +static bool capacity_changed_flag; + +static battery_capacity chargingTable[] = { + {4146, 100}, + {4133, 99}, + {4123, 98}, + {4115, 97}, + {4090, 96}, + {4075, 95}, + {4060, 94}, + {4045, 93}, + {4030, 92}, + {4015, 91}, + {4000, 90}, + {3900, 85}, + {3790, 80}, + {3760, 75}, + {3730, 70}, + {3700, 65}, + {3680, 60}, + {3660, 55}, + {3640, 50}, + {3600, 45}, + {3550, 40}, + {3510, 35}, + {3450, 30}, + {3310, 25}, + {3240, 20}, + {3180, 15}, + {3030, 10}, + {2820, 5}, + {2800, 0}, + {0, 0} +}; +static battery_capacity dischargingTable[] = { + {4110, 100}, + {4020, 99}, + {3950, 98}, + {3920, 97}, + {3890, 96}, + {3860, 96}, + {3830, 95}, + {3800, 94}, + {3760, 93}, + {3730, 92}, + {3700, 91}, + {3670, 90}, + {3630, 85}, + {3600, 80}, + {3570, 75}, + {3545, 70}, + {3515, 65}, + {3480, 60}, + {3445, 55}, + {3410, 50}, + {3375, 45}, + {3340, 40}, + {3300, 35}, + {3250, 30}, + {3200, 25}, + {3150, 20}, + {3090, 15}, + {3020, 10}, + {2820, 5}, + {2800, 0}, + {0, 0} +}; + +u32 calibrate_battery_capability_percent(struct max8903_data *data) +{ + u8 i; + pbattery_capacity pTable; + u32 tableSize; + if (data->battery_status == POWER_SUPPLY_STATUS_DISCHARGING) { + pTable = dischargingTable; + tableSize = sizeof(dischargingTable)/sizeof(dischargingTable[0]); + } else { + pTable = chargingTable; + tableSize = sizeof(chargingTable)/sizeof(chargingTable[0]); + } + for (i = 0; i < tableSize; i++) { + if (data->voltage_uV >= pTable[i].voltage) + return pTable[i].percent; + } + + return 0; +} + +static enum power_supply_property max8903_charger_props[] = { + POWER_SUPPLY_PROP_ONLINE, +}; + +static enum power_supply_property max8903_battery_props[] = { + POWER_SUPPLY_PROP_VOLTAGE_NOW, + POWER_SUPPLY_PROP_STATUS, + POWER_SUPPLY_PROP_PRESENT, + POWER_SUPPLY_PROP_CAPACITY, + POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, + POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN, + POWER_SUPPLY_PROP_HEALTH, +}; + +extern u32 max11801_read_adc(void); + +static void max8903_charger_update_status(struct max8903_data *data) +{ + if (data->usb_in || data->ta_in) + data->charger_online = 1; + else + data->charger_online = 0; + if (data->charger_online == 0) { + data->battery_status = POWER_SUPPLY_STATUS_DISCHARGING; + } else { + if (data->pdata->chg) { + if (gpio_get_value(data->pdata->chg) == 0) { + data->battery_status = POWER_SUPPLY_STATUS_CHARGING; + } else if ((data->usb_in || data->ta_in) && + gpio_get_value(data->pdata->chg) == 1) { + if (data->percent == 100) + data->battery_status = POWER_SUPPLY_STATUS_FULL; + else + data->battery_status = POWER_SUPPLY_STATUS_NOT_CHARGING; + } + } + } + pr_debug("chg: %d \n", gpio_get_value(data->pdata->chg)); +} +static int cmp_func(const void *_a, const void *_b) +{ + const int *a = _a, *b = _b; + + if (*a > *b) + return 1; + if (*a < *b) + return -1; + return 0; +} +u32 calibration_voltage(struct max8903_data *data) +{ + int volt[ADC_SAMPLE_COUNT]; + u32 voltage_data; + int i; + for (i = 0; i < ADC_SAMPLE_COUNT; i++) { + if (data->charger_online == 0) { + /* ADC offset when battery is discharger*/ + volt[i] = max11801_read_adc()-1494; + } else { + volt[i] = max11801_read_adc()-1545; + } + } + sort(volt, i, 4, cmp_func, NULL); + for (i = 0; i < ADC_SAMPLE_COUNT; i++) + pr_debug("volt_sorted[%2d]: %d\n", i, volt[i]); + /* get the average of second max/min of remained. */ + voltage_data = (volt[2] + volt[ADC_SAMPLE_COUNT - 3]) / 2; + return voltage_data; +} + +static void max8903_battery_update_status(struct max8903_data *data) +{ + static int counter; + mutex_lock(&data->work_lock); + data->voltage_uV = calibration_voltage(data); + data->percent = calibrate_battery_capability_percent(data); + if (data->percent != data->old_percent) { + data->old_percent = data->percent; + capacity_changed_flag = true; + } + if ((capacity_changed_flag == true) && (data->charger_online)) { + counter++; + if (counter > 2) { + counter = 0; + capacity_changed_flag = false; + power_supply_changed(&data->bat); + } + } + mutex_unlock(&data->work_lock); +} + +static int max8903_battery_get_property(struct power_supply *bat, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8903_data *di = container_of(bat, + struct max8903_data, bat); + static unsigned long last; + switch (psp) { + case POWER_SUPPLY_PROP_STATUS: + val->intval = POWER_SUPPLY_STATUS_UNKNOWN; + if (di->pdata->chg) { + if ((di->usb_in || di->ta_in) && gpio_get_value(di->pdata->chg) == 0) { + val->intval = POWER_SUPPLY_STATUS_CHARGING; + } else if ((di->usb_in || di->ta_in) && gpio_get_value(di->pdata->chg) == 1) { + if (di->percent == 100) + di->battery_status = POWER_SUPPLY_STATUS_FULL; + else + di->battery_status = POWER_SUPPLY_STATUS_NOT_CHARGING; + } + else { + val->intval = POWER_SUPPLY_STATUS_DISCHARGING; + } + } + di->battery_status = val->intval; + return 0; + default: + break; + } + if (!last || time_after(jiffies, last + HZ / 2)) { + last = jiffies; + max8903_charger_update_status(di); + max8903_battery_update_status(di); + } + switch (psp) { + case POWER_SUPPLY_PROP_VOLTAGE_NOW: + val->intval = di->voltage_uV; + break; + case POWER_SUPPLY_PROP_CHARGE_NOW: + val->intval = 0; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN: + val->intval = HIGH_VOLT_THRESHOLD; + break; + case POWER_SUPPLY_PROP_VOLTAGE_MIN_DESIGN: + val->intval = LOW_VOLT_THRESHOLD; + break; + case POWER_SUPPLY_PROP_PRESENT: + val->intval = 1; + break; + case POWER_SUPPLY_PROP_CAPACITY: + val->intval = di->percent < 0 ? 0 : + (di->percent > 100 ? 100 : di->percent); + break; + case POWER_SUPPLY_PROP_HEALTH: + val->intval = POWER_SUPPLY_HEALTH_GOOD; + if (di->fault) + val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + break; + default: + return -EINVAL; + } + + return 0; +} +static int max8903_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct max8903_data *data = container_of(psy, + struct max8903_data, psy); + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + val->intval = 0; + if (data->usb_in || data->ta_in) + val->intval = 1; + data->charger_online = val->intval; + break; + default: + return -EINVAL; + } + return 0; +} + +static irqreturn_t max8903_dcin(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool ta_in; + + ta_in = gpio_get_value(pdata->dok) ? false : true; + + if (ta_in == data->ta_in) + return IRQ_HANDLED; + + data->ta_in = ta_in; + pr_info("TA(DC-IN) Charger %s.\n", ta_in ? + "Connected" : "Disconnected"); + power_supply_changed(&data->psy); + power_supply_changed(&data->bat); + return IRQ_HANDLED; +} + +static irqreturn_t max8903_usbin(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool usb_in; + + usb_in = gpio_get_value(pdata->uok) ? false : true; + + if (usb_in == data->usb_in) + return IRQ_HANDLED; + + data->usb_in = usb_in; + + pr_info("USB Charger %s.\n", usb_in ? + "Connected" : "Disconnected"); + power_supply_changed(&data->psy); + power_supply_changed(&data->bat); + return IRQ_HANDLED; +} + +static irqreturn_t max8903_fault(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + bool fault; + + fault = gpio_get_value(pdata->flt) ? false : true; + + if (fault == data->fault) + return IRQ_HANDLED; + + data->fault = fault; + + if (fault) + dev_err(data->dev, "Charger suffers a fault and stops.\n"); + else + dev_err(data->dev, "Charger recovered from a fault.\n"); + return IRQ_HANDLED; +} + +static irqreturn_t max8903_chg(int irq, void *_data) +{ + struct max8903_data *data = _data; + struct max8903_pdata *pdata = data->pdata; + int chg_state; + + chg_state = gpio_get_value(pdata->chg) ? false : true; + + if (chg_state == data->chg_state) + return IRQ_HANDLED; + + data->chg_state = chg_state; + return IRQ_HANDLED; +} + +static void max8903_battery_work(struct work_struct *work) +{ + struct max8903_data *data; + data = container_of(work, struct max8903_data, work.work); + data->interval = HZ * BATTERY_UPDATE_INTERVAL; + + max8903_charger_update_status(data); + max8903_battery_update_status(data); + + pr_debug("battery voltage: %4d mV\n" , data->voltage_uV); + pr_debug("charger online status: %d\n" , data->charger_online); + pr_debug("battery status : %d\n" , data->battery_status); + pr_debug("battery capacity percent: %3d\n" , data->percent); + pr_debug("data->usb_in: %x , data->ta_in: %x \n" , data->usb_in, data->ta_in); + /* reschedule for the next time */ + schedule_delayed_work(&data->work, data->interval); +} +static __devinit int max8903_probe(struct platform_device *pdev) +{ + struct max8903_data *data; + struct device *dev = &pdev->dev; + struct max8903_pdata *pdata = pdev->dev.platform_data; + int ret = 0; + int gpio = 0; + int ta_in = 0; + int usb_in = 0; + int retval; + + data = kzalloc(sizeof(struct max8903_data), GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + data->pdata = pdata; + data->dev = dev; + + platform_set_drvdata(pdev, data); + capacity_changed_flag = false; + data->usb_in = 0; + data->ta_in = 0; + + if (pdata->dc_valid == false && pdata->usb_valid == false) { + dev_err(dev, "No valid power sources.\n"); + printk(KERN_INFO "No valid power sources.\n"); + ret = -EINVAL; + goto err; + } + if (pdata->dc_valid) { + if (pdata->dok && gpio_is_valid(pdata->dok)) { + gpio = pdata->dok; /* PULL_UPed Interrupt */ + /* set DOK gpio input */ + ret = gpio_request(gpio, "max8903-DOK"); + if (ret) { + printk(KERN_ERR"request max8903-DOK error!!\n"); + goto err; + } else { + gpio_direction_input(gpio); + } + ta_in = gpio_get_value(gpio) ? 0 : 1; + } else if (pdata->dok && gpio_is_valid(pdata->dok) && pdata->dcm_always_high) { + ta_in = pdata->dok; /* PULL_UPed Interrupt */ + ta_in = gpio_get_value(gpio) ? 0 : 1; + } else { + dev_err(dev, "When DC is wired, DOK and DCM should" + " be wired as well." + " or set dcm always high\n"); + ret = -EINVAL; + goto err; + } + } + if (pdata->usb_valid) { + if (pdata->uok && gpio_is_valid(pdata->uok)) { + gpio = pdata->uok; + /* set UOK gpio input */ + ret = gpio_request(gpio, "max8903-UOK"); + if (ret) { + printk(KERN_ERR"request max8903-UOK error!!\n"); + goto err; + } else { + gpio_direction_input(gpio); + } + usb_in = gpio_get_value(gpio) ? 0 : 1; + } else { + dev_err(dev, "When USB is wired, UOK should be wired." + "as well.\n"); + ret = -EINVAL; + goto err; + } + } + if (pdata->chg) { + if (!gpio_is_valid(pdata->chg)) { + dev_err(dev, "Invalid pin: chg.\n"); + ret = -EINVAL; + goto err; + } + /* set CHG gpio input */ + ret = gpio_request(pdata->chg, "max8903-CHG"); + if (ret) { + printk(KERN_ERR"request max8903-CHG error!!\n"); + goto err; + } else { + gpio_direction_input(pdata->chg); + } + } + if (pdata->flt) { + if (!gpio_is_valid(pdata->flt)) { + dev_err(dev, "Invalid pin: flt.\n"); + ret = -EINVAL; + goto err; + } + /* set FLT gpio input */ + ret = gpio_request(pdata->flt, "max8903-FLT"); + if (ret) { + printk(KERN_ERR"request max8903-FLT error!!\n"); + goto err; + } else { + gpio_direction_input(pdata->flt); + } + } + if (pdata->usus) { + if (!gpio_is_valid(pdata->usus)) { + dev_err(dev, "Invalid pin: usus.\n"); + ret = -EINVAL; + goto err; + } + } + mutex_init(&data->work_lock); + data->fault = false; + data->ta_in = ta_in; + data->usb_in = usb_in; + data->psy.name = "max8903-ac"; + data->psy.type = POWER_SUPPLY_TYPE_MAINS; + data->psy.get_property = max8903_get_property; + data->psy.properties = max8903_charger_props; + data->psy.num_properties = ARRAY_SIZE(max8903_charger_props); + ret = power_supply_register(dev, &data->psy); + if (ret) { + dev_err(dev, "failed: power supply register.\n"); + goto err_psy; + } + data->bat.name = "max8903-charger"; + data->bat.type = POWER_SUPPLY_TYPE_BATTERY; + data->bat.properties = max8903_battery_props; + data->bat.num_properties = ARRAY_SIZE(max8903_battery_props); + data->bat.get_property = max8903_battery_get_property; + data->bat.use_for_apm = 1; + retval = power_supply_register(&pdev->dev, &data->bat); + if (retval) { + dev_err(data->dev, "failed to register battery\n"); + goto battery_failed; + } + INIT_DELAYED_WORK(&data->work, max8903_battery_work); + schedule_delayed_work(&data->work, data->interval); + if (pdata->dc_valid) { + ret = request_threaded_irq(gpio_to_irq(pdata->dok), + NULL, max8903_dcin, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 DC IN", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for DC (%d)\n", + gpio_to_irq(pdata->dok), ret); + goto err_usb_irq; + } + } + + if (pdata->usb_valid) { + ret = request_threaded_irq(gpio_to_irq(pdata->uok), + NULL, max8903_usbin, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 USB IN", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for USB (%d)\n", + gpio_to_irq(pdata->uok), ret); + goto err_dc_irq; + } + } + + if (pdata->flt) { + ret = request_threaded_irq(gpio_to_irq(pdata->flt), + NULL, max8903_fault, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 Fault", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for Fault (%d)\n", + gpio_to_irq(pdata->flt), ret); + goto err_flt_irq; + } + } + + if (pdata->chg) { + ret = request_threaded_irq(gpio_to_irq(pdata->chg), + NULL, max8903_chg, + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + "MAX8903 Fault", data); + if (ret) { + dev_err(dev, "Cannot request irq %d for Fault (%d)\n", + gpio_to_irq(pdata->flt), ret); + goto err_chg_irq; + } + } + return 0; +err_psy: + power_supply_unregister(&data->psy); +battery_failed: + power_supply_unregister(&data->bat); +err_usb_irq: + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + cancel_delayed_work(&data->work); +err_dc_irq: + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + cancel_delayed_work(&data->work); +err_flt_irq: + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + cancel_delayed_work(&data->work); +err_chg_irq: + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + cancel_delayed_work(&data->work); +err: + if (pdata->uok) + gpio_free(pdata->uok); + if (pdata->dok) + gpio_free(pdata->dok); + if (pdata->flt) + gpio_free(pdata->flt); + if (pdata->chg) + gpio_free(pdata->chg); + kfree(data); + return ret; +} + +static __devexit int max8903_remove(struct platform_device *pdev) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + if (data) { + struct max8903_pdata *pdata = data->pdata; + if (pdata->flt) + free_irq(gpio_to_irq(pdata->flt), data); + if (pdata->usb_valid) + free_irq(gpio_to_irq(pdata->uok), data); + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->dok), data); + if (pdata->dc_valid) + free_irq(gpio_to_irq(pdata->chg), data); + cancel_delayed_work_sync(&data->work); + power_supply_unregister(&data->psy); + power_supply_unregister(&data->bat); + kfree(data); + } + return 0; +} + +static int max8903_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + + cancel_delayed_work(&data->work); + return 0; +} + +static int max8903_resume(struct platform_device *pdev) +{ + struct max8903_data *data = platform_get_drvdata(pdev); + + schedule_delayed_work(&data->work, BATTERY_UPDATE_INTERVAL); + return 0; + +} + +static struct platform_driver max8903_driver = { + .probe = max8903_probe, + .remove = __devexit_p(max8903_remove), + .suspend = max8903_suspend, + .resume = max8903_resume, + .driver = { + .name = "max8903-charger", + .owner = THIS_MODULE, + }, +}; + +static int __init max8903_init(void) +{ + return platform_driver_register(&max8903_driver); +} +module_init(max8903_init); + +static void __exit max8903_exit(void) +{ + platform_driver_unregister(&max8903_driver); +} +module_exit(max8903_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("Sabresd Battery Driver"); +MODULE_ALIAS("sabresd_battery"); diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 0a6deb268b38..a79163f0ae40 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -276,7 +276,7 @@ static ssize_t regulator_uV_show(struct device *dev, return ret; } static ssize_t regulator_uV_store(struct device *dev, - struct device_attribute *attr, char *buf, + struct device_attribute *attr, const char *buf, size_t count) { struct regulator_dev *rdev = dev_get_drvdata(dev); diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c index 34ca0fb45961..e2aaa2d4e889 100644 --- a/drivers/regulator/pfuze100-regulator.c +++ b/drivers/regulator/pfuze100-regulator.c @@ -657,6 +657,21 @@ static int __devexit pfuze100_regulator_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_MX6_INTER_LDO_BYPASS +int cpu_freq_suspend_in; /*judge for in suspend or not*/ +static int pfuze100_regulator_suspend(struct platform_device *pdev, + pm_message_t state) +{ + cpu_freq_suspend_in = 1; + return 0; +} + +static int pfuze100_regulator_resume(struct platform_device *pdev) +{ + cpu_freq_suspend_in = 0; + return 0; +} +#endif static struct platform_driver pfuze100_regulator_driver = { .driver = { .name = "pfuze100-regulator", @@ -664,6 +679,10 @@ static struct platform_driver pfuze100_regulator_driver = { }, .remove = __devexit_p(pfuze100_regulator_remove), .probe = pfuze100_regulator_probe, +#ifdef CONFIG_MX6_INTER_LDO_BYPASS + .suspend = pfuze100_regulator_suspend, + .resume = pfuze100_regulator_resume, +#endif }; static int __init pfuze100_regulator_init(void) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 781e11f5cf34..beba18533371 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -215,6 +215,12 @@ struct imx_port { wait_queue_head_t dma_wait; }; +struct imx_port_ucrs { + unsigned int ucr1; + unsigned int ucr2; + unsigned int ucr3; +}; + #ifdef CONFIG_IRDA #define USE_IRDA(sport) ((sport)->use_irda) #else @@ -222,6 +228,27 @@ struct imx_port { #endif /* + * Save and restore functions for UCR1, UCR2 and UCR3 registers + */ +static void imx_port_ucrs_save(struct uart_port *port, + struct imx_port_ucrs *ucr) +{ + /* save control registers */ + ucr->ucr1 = readl(port->membase + UCR1); + ucr->ucr2 = readl(port->membase + UCR2); + ucr->ucr3 = readl(port->membase + UCR3); +} + +static void imx_port_ucrs_restore(struct uart_port *port, + struct imx_port_ucrs *ucr) +{ + /* restore control registers */ + writel(ucr->ucr1, port->membase + UCR1); + writel(ucr->ucr2, port->membase + UCR2); + writel(ucr->ucr3, port->membase + UCR3); +} + +/* * Handle any change of modem status signal since we were last called. */ static void imx_mctrl_check(struct imx_port *sport) @@ -553,10 +580,8 @@ static irqreturn_t imx_rxint(int irq, void *dev_id) continue; } - spin_unlock_irqrestore(&sport->port.lock, flags); if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) continue; - spin_lock_irqsave(&sport->port.lock, flags); if (unlikely(rx & URXD_ERR)) { if (rx & URXD_BRK) @@ -1406,6 +1431,70 @@ imx_verify_port(struct uart_port *port, struct serial_struct *ser) return ret; } +#if defined(CONFIG_CONSOLE_POLL) +static int imx_poll_get_char(struct uart_port *port) +{ + struct imx_port_ucrs old_ucr; + unsigned int status; + unsigned char c; + + /* save control registers */ + imx_port_ucrs_save(port, &old_ucr); + + /* disable interrupts */ + writel(UCR1_UARTEN, port->membase + UCR1); + writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), + port->membase + UCR2); + writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), + port->membase + UCR3); + + /* poll */ + do { + status = readl(port->membase + USR2); + } while (~status & USR2_RDR); + + /* read */ + c = readl(port->membase + URXD0); + + /* restore control registers */ + imx_port_ucrs_restore(port, &old_ucr); + + return c; +} + +static void imx_poll_put_char(struct uart_port *port, unsigned char c) +{ + struct imx_port_ucrs old_ucr; + unsigned int status; + + /* save control registers */ + imx_port_ucrs_save(port, &old_ucr); + + /* disable interrupts */ + writel(UCR1_UARTEN, port->membase + UCR1); + writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), + port->membase + UCR2); + writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), + port->membase + UCR3); + + /* drain */ + do { + status = readl(port->membase + USR1); + } while (~status & USR1_TRDY); + + /* write */ + writel(c, port->membase + URTX0); + + /* flush */ + do { + status = readl(port->membase + USR2); + } while (~status & USR2_TXDC); + + /* restore control registers */ + imx_port_ucrs_restore(port, &old_ucr); +} +#endif + static struct uart_ops imx_pops = { .tx_empty = imx_tx_empty, .set_mctrl = imx_set_mctrl, @@ -1423,6 +1512,10 @@ static struct uart_ops imx_pops = { .request_port = imx_request_port, .config_port = imx_config_port, .verify_port = imx_verify_port, +#if defined(CONFIG_CONSOLE_POLL) + .poll_get_char = imx_poll_get_char, + .poll_put_char = imx_poll_put_char, +#endif }; static struct imx_port *imx_ports[UART_NR]; @@ -1445,15 +1538,22 @@ static void imx_console_write(struct console *co, const char *s, unsigned int count) { struct imx_port *sport = imx_ports[co->index]; - unsigned int old_ucr1, old_ucr2, ucr1; + struct imx_port_ucrs old_ucr; + unsigned int ucr1; unsigned long flags; + int locked = 1; + + local_irq_save(flags); + if (sport->port.sysrq) + locked = 0; + else + spin_lock(&sport->port.lock); - spin_lock_irqsave(&sport->port.lock, flags); /* - * First, save UCR1/2 and then disable interrupts + * First, save UCR1/2/3 and then disable interrupts */ - ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); - old_ucr2 = readl(sport->port.membase + UCR2); + imx_port_ucrs_save(&sport->port, &old_ucr); + ucr1 = old_ucr.ucr1; if (cpu_is_mx1()) ucr1 |= MX1_UCR1_UARTCLKEN; @@ -1462,19 +1562,21 @@ imx_console_write(struct console *co, const char *s, unsigned int count) writel(ucr1, sport->port.membase + UCR1); - writel(old_ucr2 | UCR2_TXEN, sport->port.membase + UCR2); + writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); uart_console_write(&sport->port, s, count, imx_console_putchar); /* * Finally, wait for transmitter to become empty - * and restore UCR1/2 + * and restore UCR1/2/3 */ while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); - writel(old_ucr1, sport->port.membase + UCR1); - writel(old_ucr2, sport->port.membase + UCR2); - spin_unlock_irqrestore(&sport->port.lock, flags); + imx_port_ucrs_restore(&sport->port, &old_ucr); + + if (locked) + spin_unlock(&sport->port.lock); + local_irq_restore(flags); } /* diff --git a/drivers/usb/gadget/zero.c b/drivers/usb/gadget/zero.c index 5440b0eb71ac..c6e5d054b8bc 100644 --- a/drivers/usb/gadget/zero.c +++ b/drivers/usb/gadget/zero.c @@ -107,16 +107,26 @@ module_param(loopdefault, bool, S_IRUGO|S_IWUSR); #else #define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ #define DRIVER_PRODUCT_NUM 0xbadd -#define DEFAULT_AUTORESUME 5 +#define DEFAULT_AUTORESUME 5000 #endif +static unsigned startms; + /* If the optional "autoresume" mode is enabled, it provides good * functional coverage for the "USBCV" test harness from USB-IF. * It's always set if OTG mode is enabled. */ -unsigned autoresume = DEFAULT_AUTORESUME; +static unsigned autoresume = DEFAULT_AUTORESUME; module_param(autoresume, uint, S_IRUGO); -MODULE_PARM_DESC(autoresume, "zero, or seconds before remote wakeup"); +MODULE_PARM_DESC(autoresume, "minimum milliseconds before sending remote wakeup"); + +static unsigned interval; +module_param(interval, uint, S_IRUGO); +MODULE_PARM_DESC(interval, "zero, or milliseconds for interval remote wakeup time"); + +static unsigned endms = 5000; +module_param(endms, uint, S_IRUGO); +MODULE_PARM_DESC(endms, "max milliseconds before sending remote wakeup"); /*-------------------------------------------------------------------------*/ @@ -250,8 +260,11 @@ static void zero_suspend(struct usb_composite_dev *cdev) return; if (autoresume) { - mod_timer(&autoresume_timer, jiffies + (HZ * autoresume)); - DBG(cdev, "suspend, wakeup in %d seconds\n", autoresume); + mod_timer(&autoresume_timer, jiffies + msecs_to_jiffies(startms)); + DBG(cdev, "suspend, wakeup in %d milliseconds\n", startms); + startms += interval; + if (startms == endms) + startms = autoresume; } else DBG(cdev, "%s\n", __func__); } @@ -327,6 +340,10 @@ static int __ref zero_bind(struct usb_composite_dev *cdev) init_utsname()->sysname, init_utsname()->release, gadget->name); + startms = autoresume; + if (autoresume > 0 && autoresume < 5) + pr_warning("%s: time before sending remote wakeup is less than 5ms, should not send resume signal.\n", + longname); return 0; } @@ -336,6 +353,11 @@ static int zero_unbind(struct usb_composite_dev *cdev) return 0; } +static void zero_disconnect(struct usb_composite_dev *cdev) +{ + startms = autoresume; +} + static struct usb_composite_driver zero_driver = { .name = "zero", .dev = &device_desc, @@ -343,6 +365,7 @@ static struct usb_composite_driver zero_driver = { .unbind = zero_unbind, .suspend = zero_suspend, .resume = zero_resume, + .disconnect = zero_disconnect, }; MODULE_AUTHOR("David Brownell"); diff --git a/drivers/video/mxc/Kconfig b/drivers/video/mxc/Kconfig index fe9de7362544..f0afddc95bd3 100644 --- a/drivers/video/mxc/Kconfig +++ b/drivers/video/mxc/Kconfig @@ -104,6 +104,17 @@ config FB_MXC_EINK_AUTO_UPDATE_MODE default n depends on FB_MXC_EINK_PANEL +config FB_MXC_SIPIX_PANEL + depends on FB_MXC + depends on DMA_ENGINE + select FB_DEFERRED_IO + tristate "SIPIX Panel Framebuffer" + +config FB_MXC_SIPIX_AUTO_UPDATE_MODE + bool "SIPIX Auto-update Mode Support" + default n + depends on FB_MXC_SIPIX_PANEL + config FB_MXC_ELCDIF_FB depends on FB && ARCH_MXC tristate "Support MXC ELCDIF framebuffer" diff --git a/drivers/video/mxc/Makefile b/drivers/video/mxc/Makefile index 084837c70929..21aef052ecd6 100644 --- a/drivers/video/mxc/Makefile +++ b/drivers/video/mxc/Makefile @@ -25,4 +25,5 @@ obj-$(CONFIG_FB_MXC_SEIKO_WVGA_SYNC_PANEL) += mxcfb_seiko_wvga.o obj-$(CONFIG_FB_MXC_TVOUT_CH7024) += ch7024.o obj-$(CONFIG_FB_MXC_CH7026) += mxcfb_ch7026.o obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o +obj-$(CONFIG_FB_MXC_SIPIX_PANEL) += mxc_spdc_fb.o obj-$(CONFIG_FB_MXC_ELCDIF_FB) += mxc_elcdif_fb.o diff --git a/drivers/video/mxc/epdc_regs.h b/drivers/video/mxc/epdc_regs.h index 50d352e7a212..cc7b5000db18 100644 --- a/drivers/video/mxc/epdc_regs.h +++ b/drivers/video/mxc/epdc_regs.h @@ -163,9 +163,7 @@ extern void __iomem *epdc_base; #define EPDC_PIGEON_15_0 (epdc_base + 0xBC0) #define EPDC_PIGEON_15_1 (epdc_base + 0xBD0) #define EPDC_PIGEON_15_2 (epdc_base + 0xBE0) -#define EPDC_PIGEON_16_0 (epdc_base + 0xC00) -#define EPDC_PIGEON_16_1 (epdc_base + 0xC10) -#define EPDC_PIGEON_16_2 (epdc_base + 0xC20) +#define EPDC_WB_ADDR_TCE (epdc_base + 0xC10) /* * Register field definitions diff --git a/drivers/video/mxc/ldb.c b/drivers/video/mxc/ldb.c index 493abd662036..8b84498fd285 100644 --- a/drivers/video/mxc/ldb.c +++ b/drivers/video/mxc/ldb.c @@ -457,6 +457,17 @@ static int ldb_disp_init(struct mxc_dispdrv_handle *disp, else ldb->mode = plat_data->mode; + if ((ldb->mode == LDB_SIN0) || (ldb->mode == LDB_SIN1)) { + ret = ldb->mode - LDB_SIN0; + if (plat_data->disp_id != ret) { + dev_warn(&ldb->pdev->dev, + "change IPU DI%d to IPU DI%d for LDB " + "channel%d.\n", + plat_data->disp_id, ret, ret); + plat_data->disp_id = ret; + } + } + if (ldb->mode == LDB_SPL_DI0) { reg |= LDB_SPLIT_MODE_EN | LDB_CH0_MODE_EN_TO_DI0 | LDB_CH1_MODE_EN_TO_DI0; diff --git a/drivers/video/mxc/mxc_edid.c b/drivers/video/mxc/mxc_edid.c index e8a2b9761b65..f86313df7dea 100644 --- a/drivers/video/mxc/mxc_edid.c +++ b/drivers/video/mxc/mxc_edid.c @@ -350,6 +350,16 @@ int mxc_edid_parse_ext_blk(unsigned char *edid, break; } case 0x4: /*Speaker allocation block*/ + { + i = 0; + while (i < blklen) { + cfg->speaker_alloc = edid[index + 1]; + index += 3; + i += 3; + DPRINTK("Speaker Alloc : %02x\n", cfg->speaker_alloc); + } + break; + } case 0x7: /*User extended block*/ default: /* skip */ diff --git a/drivers/video/mxc/mxc_elcdif_fb.c b/drivers/video/mxc/mxc_elcdif_fb.c index 7a5fa6d1900c..2c96eecc111f 100644 --- a/drivers/video/mxc/mxc_elcdif_fb.c +++ b/drivers/video/mxc/mxc_elcdif_fb.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. */ /* @@ -128,8 +128,10 @@ static inline void setup_dotclk_panel(u32 pixel_clk, __raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS, elcdif_base + HW_ELCDIF_CTRL_CLR); + __raw_writel(BM_ELCDIF_CTRL2_OUTSTANDING_REQS, + elcdif_base + HW_ELCDIF_CTRL2_CLR); __raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS - (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8), + (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_16), elcdif_base + HW_ELCDIF_CTRL2_SET); /* Recover on underflow */ @@ -824,7 +826,7 @@ static int mxc_elcdif_fb_set_par(struct fb_info *fbi) mxc_init_elcdif(); mxc_elcdif_init_panel(); - dev_dbg(fbi->device, "pixclock = %ul Hz\n", + dev_dbg(fbi->device, "pixclock = %lu Hz\n", (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); memset(&sig_cfg, 0, sizeof(sig_cfg)); @@ -1369,7 +1371,7 @@ static int mxc_elcdif_fb_suspend(struct platform_device *pdev, struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; int saved_blank; - acquire_console_sem(); + console_lock(); fb_set_suspend(fbi, 1); saved_blank = data->cur_blank; mxc_elcdif_fb_blank(FB_BLANK_POWERDOWN, fbi); @@ -1388,7 +1390,7 @@ static int mxc_elcdif_fb_suspend(struct platform_device *pdev, clk_disable(g_elcdif_axi_clk); g_elcdif_axi_clk_enable = false; } - release_console_sem(); + console_unlock(); return 0; } @@ -1397,10 +1399,10 @@ static int mxc_elcdif_fb_resume(struct platform_device *pdev) struct fb_info *fbi = platform_get_drvdata(pdev); struct mxc_elcdif_fb_data *data = (struct mxc_elcdif_fb_data *)fbi->par; - acquire_console_sem(); + console_lock(); mxc_elcdif_fb_blank(data->next_blank, fbi); fb_set_suspend(fbi, 0); - release_console_sem(); + console_unlock(); return 0; } diff --git a/drivers/video/mxc/mxc_epdc_fb.c b/drivers/video/mxc/mxc_epdc_fb.c index da77373e03a6..ef4916db0436 100644 --- a/drivers/video/mxc/mxc_epdc_fb.c +++ b/drivers/video/mxc/mxc_epdc_fb.c @@ -1130,6 +1130,7 @@ static void epdc_init_sequence(struct mxc_epdc_fb_data *fb_data) epdc_init_settings(fb_data); __raw_writel(fb_data->waveform_buffer_phys, EPDC_WVADDR); __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR); + __raw_writel(fb_data->working_buffer_phys, EPDC_WB_ADDR_TCE); fb_data->in_init = true; epdc_powerup(fb_data); draw_mode0(fb_data); @@ -4006,8 +4007,8 @@ static void mxc_epdc_fb_fw_handler(const struct firmware *fw, clk_enable(fb_data->epdc_clk_pix); rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk); - if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/200) || - (rounded_pix_clk <= target_pix_clk - target_pix_clk/200))) { + if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) || + (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) { /* Can't get close enough without changing parent clk */ epdc_parent = clk_get_parent(fb_data->epdc_clk_pix); rounded_parent_rate = clk_round_rate(epdc_parent, target_pix_clk); @@ -4018,8 +4019,8 @@ static void mxc_epdc_fb_fw_handler(const struct firmware *fw, clk_set_rate(epdc_parent, epdc_pix_rate); rounded_pix_clk = clk_round_rate(fb_data->epdc_clk_pix, target_pix_clk); - if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/200) || - (rounded_pix_clk <= target_pix_clk - target_pix_clk/200))) + if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) || + (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) /* Still can't get a good clock, provide warning */ dev_err(fb_data->dev, "Unable to get an accurate EPDC pix clk" "desired = %lu, actual = %lu\n", target_pix_clk, diff --git a/drivers/video/mxc/mxc_ipuv3_fb.c b/drivers/video/mxc/mxc_ipuv3_fb.c index 11bccff413a8..348bd818ee69 100644 --- a/drivers/video/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/mxc/mxc_ipuv3_fb.c @@ -316,15 +316,6 @@ static int mxcfb_set_par(struct fb_info *fbi) dev_dbg(fbi->device, "Reconfiguring framebuffer\n"); - if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->setup) { - retval = mxc_fbi->dispdrv->drv->setup(mxc_fbi->dispdrv, fbi); - if (retval < 0) { - dev_err(fbi->device, "setup error, dispdrv:%s.\n", - mxc_fbi->dispdrv->drv->name); - return -EINVAL; - } - } - ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq); ipu_disable_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_irq); ipu_clear_irq(mxc_fbi->ipu, mxc_fbi->ipu_ch_nf_irq); @@ -391,6 +382,15 @@ static int mxcfb_set_par(struct fb_info *fbi) if (mxc_fbi->next_blank != FB_BLANK_UNBLANK) return retval; + if (mxc_fbi->dispdrv && mxc_fbi->dispdrv->drv->setup) { + retval = mxc_fbi->dispdrv->drv->setup(mxc_fbi->dispdrv, fbi); + if (retval < 0) { + dev_err(fbi->device, "setup error, dispdrv:%s.\n", + mxc_fbi->dispdrv->drv->name); + return -EINVAL; + } + } + _setup_disp_channel1(fbi); if (!mxc_fbi->overlay) { diff --git a/drivers/video/mxc/mxc_spdc_fb.c b/drivers/video/mxc/mxc_spdc_fb.c new file mode 100644 index 000000000000..37938b9db712 --- /dev/null +++ b/drivers/video/mxc/mxc_spdc_fb.c @@ -0,0 +1,4168 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +/* + * Based on MXC EPDC Driver, Freescale Solutions, Inc All Rights Reserved. + */ + +#include "mxc_spdc_fb.h" + +#define MERGE_OK 0 +#define MERGE_FAIL 1 +#define MERGE_BLOCK 2 + +#define SPDC_DEFAULT_TEMP 30 +#define TEMP_NO_SET 0xFF +#define POWER_STATE_OFF 0 +#define POWER_STATE_ON 1 +#define POWER_READY_OFF false +#define POWER_READY_ON true + +#define INIT_UPDATE_MARKER 0x12345678 +#define PAN_UPDATE_MARKER 0x12345679 + +#define SPDC_MAX_NUM_UPDATES 32 +#define SPDC_MAX_NUM_BUFFERS 2 +#define SPDC_MAX_NUM_PREPROCESS 15 +#define NUM_SCREENS_MIN 2 +#define SPDC_DEFAULT_BPP 16 + +mxc_spdc_t *g_fb_data; + +static int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data, + struct fb_info *info); +static int mxc_spdc_fb_wait_update_complete(struct mxcfb_update_marker_data + *marker_data, struct fb_info *info); + +static const struct mxc_spdc_resolution_map_para spdc_gray_res_map[] = { +/*define Gray Mode resolution mapping*/ + {0x18, 600, 800, PORTRAIT}, + {0x19, 768, 1024, PORTRAIT}, + {0x1a, 0, 0, RESERVED}, + {0x1b, 600, 1024, PORTRAIT}, + {0x1c, 825, 1200, PORTRAIT}, + {0x1d, 1024, 1280, PORTRAIT}, + {0x1e, 1200, 1600, PORTRAIT}, + {0x10, 800, 1024, PORTRAIT}, + {0x11, 825, 1280, PORTRAIT}, + {0x12, 800, 1280, PORTRAIT}, + {0x13, 768, 1280, PORTRAIT}, + {0x14, 960, 1280, PORTRAIT}, + {0x0, 800, 600, LANDSCAPE}, + {0x1, 1024, 768, LANDSCAPE}, + {0x2, 0, 0, RESERVED}, + {0x3, 1024, 600, LANDSCAPE}, + {0x4, 1200, 825, LANDSCAPE}, + {0x5, 1280, 1024, LANDSCAPE}, + {0x6, 1600, 1200, LANDSCAPE}, + {0x7, 1024, 800, LANDSCAPE}, + {0x8, 1280, 825, LANDSCAPE}, + {0x9, 1280, 800, LANDSCAPE}, + {0xa, 1280, 768, LANDSCAPE}, + {0xb, 1280, 960, LANDSCAPE}, + {0xFFFF, 800, 600, LANDSCAPE}, +}; + +static const struct mxc_spdc_resolution_map_para spdc_rgbw_res_map[] = { +/*define RGBW Mode resolution mapping*/ + {0x18, 300, 400, PORTRAIT}, + {0x19, 384, 512, PORTRAIT}, + {0x1a, 0, 0, RESERVED}, + {0x1b, 300, 512, PORTRAIT}, + {0x1c, 0, 0, RESERVED}, + {0x1d, 512, 640, PORTRAIT}, + {0x1e, 600, 800, PORTRAIT}, + {0x10, 400, 512, PORTRAIT}, + {0x11, 0, 0, RESERVED}, + {0x12, 400, 640, PORTRAIT}, + {0x13, 384, 640, PORTRAIT}, + {0x14, 480, 640, PORTRAIT}, + {0x0, 400, 300, LANDSCAPE}, + {0x1, 512, 384, LANDSCAPE}, + {0x2, 0, 0, RESERVED}, + {0x3, 512, 300, LANDSCAPE}, + {0x4, 0, 0, RESERVED}, + {0x5, 640, 512, LANDSCAPE}, + {0x6, 800, 600, LANDSCAPE}, + {0x7, 512, 400, LANDSCAPE}, + {0x8, 0, 0, RESERVED}, + {0x9, 640, 400, LANDSCAPE}, + {0xa, 640, 384, LANDSCAPE}, + {0xb, 640, 480, LANDSCAPE}, + {0xFFFF, 400, 300, LANDSCAPE}, +}; + +static void get_panel_init_set(struct imx_spdc_panel_init_set* + panel_set, u32 *val) +{ + *val = panel_set->yoe_pol | + (panel_set->dual_gate << 1) | + (panel_set->ud << 7) | + (panel_set->rl << 8) | + (panel_set->data_filter_n << 9) | + (panel_set->power_ready << 10) | + (panel_set->rgbw_mode_enable << 11) | + (panel_set->hburst_len_en << 13) | + ((panel_set->resolution & 0x1F) << 2); +} + +static inline void spdc_intr_enable(mxc_spdc_t *fb_data, u32 int_type) +{ + u32 status; + + status = __raw_readl(fb_data->hwp + SPDC_INT_ENABLE); + status |= (int_type & SPDC_IRQ_ALL_MASK); + __raw_writel(status, fb_data->hwp + SPDC_INT_ENABLE); +} + +static bool spdc_is_update_finish(mxc_spdc_t *fb_data) +{ + u32 val = __raw_readl(fb_data->hwp + SPDC_INT_STA_CLR); + bool is_finish = (val & SPDC_IRQ_STA_FRAME_UPDATE) ? true : false; + + return is_finish; +} + +static int spdc_get_intr_stat(mxc_spdc_t *fb_data) +{ + u32 status = __raw_readl(fb_data->hwp + SPDC_INT_STA_CLR); + return status & 0xF; +} + +static inline void +spdc_intr_stat_clear(mxc_spdc_t *fb_data, u32 int_type) +{ + /* write 1 to clear status */ + u32 status = (int_type & SPDC_IRQ_STA_ALL_MASK); + __raw_writel(status, fb_data->hwp + SPDC_INT_STA_CLR); +} + +static inline void spdc_set_nextbuf_addr(mxc_spdc_t *fb_data) +{ + u32 addr = fb_data->fresh_param.buf_addr.next_buf_phys_addr; + __raw_writel(addr, fb_data->hwp + SPDC_NEXT_BUF); + dev_dbg(fb_data->dev, "add: 0x%x\n", addr); +} + +static inline void spdc_set_curbuf_addr(mxc_spdc_t *fb_data) +{ + u32 addr = fb_data->fresh_param.buf_addr.cur_buf_phys_addr; + __raw_writel(addr, fb_data->hwp + SPDC_CURRENT_BUF); +} + +static inline void spdc_set_prebuf_addr(mxc_spdc_t *fb_data) +{ + u32 addr = fb_data->fresh_param.buf_addr.pre_buf_phys_addr; + __raw_writel(addr, fb_data->hwp + SPDC_PRE_BUF); +} + +static inline void spdc_set_cntbuf_addr(mxc_spdc_t *fb_data) +{ + u32 addr = fb_data->fresh_param.buf_addr.frm_cnt_buf_phys_addr; + __raw_writel(addr, fb_data->hwp + SPDC_CNT_BUF); +} + +static inline void spdc_set_lutbuf_addr(mxc_spdc_t *fb_data) +{ + u32 addr = fb_data->fresh_param.buf_addr.lut_buf_phys_addr; + __raw_writel(addr, fb_data->hwp + SPDC_LUT_BUF); +} + +static inline void spdc_set_update_coord(mxc_spdc_t *fb_data) +{ + u32 x = fb_data->fresh_param.update_region.left; + u32 y = fb_data->fresh_param.update_region.top; + + if (!x) + x++; + if (!y) + y++; + + dev_dbg(fb_data->dev, "x:%d, y:%d\n", x, y); + x = (u32)(((x & SPDC_UPDATE_X_Y_MAX_SIZE) << 16) | + (y & SPDC_UPDATE_X_Y_MAX_SIZE)); + __raw_writel(x, fb_data->hwp + SPDC_UPDATA_X_Y); +} + +static inline void spdc_set_update_dimensions(mxc_spdc_t *fb_data) +{ + u32 w = fb_data->fresh_param.update_region.width; + u32 h = fb_data->fresh_param.update_region.height; + + if (!w) + w++; + if (!h) + h++; + + dev_dbg(fb_data->dev, "w:%d, h:%d\n", w, h); + w = (u32)(((w & SPDC_UPDATE_W_H_MAX_SIZE) << 16) | + (h & SPDC_UPDATE_W_H_MAX_SIZE)); + __raw_writel(w, fb_data->hwp + SPDC_UPDATE_W_H); +} + +static inline void spdc_set_update_temper(mxc_spdc_t *fb_data) +{ + s8 temper = (s8)(fb_data->fresh_param.temper & 0xFF) << 1; + + if (temper > -110 && temper < 200) + __raw_writel(temper, fb_data->hwp + SPDC_TEMP_INFO); + else + __raw_writel(SPDC_DEFAULT_TEMP, fb_data->hwp + SPDC_TEMP_INFO); +} + +static inline void spdc_trigger_update(mxc_spdc_t *fb_data) +{ + u32 val; + struct partial_refresh_param *fresh_param = &fb_data->fresh_param; + + if ((fresh_param->wave_mode & SPDC_WAV_MODE_MASK) && fresh_param->flash) + val = SPDC_DISP_TRIGGER_FLASH; + else + val = 0; + + val |= fresh_param->wave_mode << 1; + val |= SPDC_DISP_TRIGGER_ENABLE; + dev_dbg(fb_data->dev, "wave:%d\n", fresh_param->wave_mode); + __raw_writel(val, fb_data->hwp + SPDC_DISP_TRIGGER); +} + +static bool is_lut_checksum_ok(mxc_spdc_t *fb_data) +{ + u32 status; + + status = __raw_readl(fb_data->hwp + SPDC_STATUS); + status &= SPDC_IRQ_STA_ERR; + + return status ? true : false; +} + +static void spdc_clk_gate(mxc_spdc_t *fb_data, bool enable) +{ + if (enable) + __raw_writel(SPDC_SW_GATE_CLK_ENABLE, + fb_data->hwp + SPDC_SW_GATE_CLK); + else + __raw_writel(~SPDC_SW_GATE_CLK_ENABLE, + fb_data->hwp + SPDC_SW_GATE_CLK); +} + +static int update_panel_init_set(mxc_spdc_t *fb_data) +{ + int ret = 0; + u32 init_val; + + get_panel_init_set(&fb_data->panel_set, &init_val); + dev_dbg(fb_data->dev, "panel init setting:%x\n", init_val); + + __raw_writel(init_val, fb_data->hwp + SPDC_PANEL_INIT_SET); + + /*wait init setting update finish*/ + ret = wait_for_completion_timeout(&fb_data->init_finish, + msecs_to_jiffies(4000)); + if (!ret) + dev_err(fb_data->dev, "Timed out for init setting!\n"); + + return ret; +} + +static void spdc_panel_pwr_on(mxc_spdc_t *fb_data) +{ + fb_data->panel_set.power_ready = POWER_READY_ON; +} + +static void spdc_panel_pwr_down(mxc_spdc_t *fb_data) +{ + fb_data->panel_set.power_ready = POWER_READY_OFF; +} + +static void spdc_powerdown(mxc_spdc_t *fb_data) +{ + mutex_lock(&fb_data->power_mutex); + + /* If powering_down has been cleared, a powerup + * request is pre-empting this powerdown request. + */ + if (!fb_data->powering_down + || (fb_data->power_state == POWER_STATE_OFF)) { + mutex_unlock(&fb_data->power_mutex); + return; + } + + dev_dbg(fb_data->dev, "spdc Powerdown\n"); + + /* Disable power to the AUO panel */ + regulator_disable(fb_data->vcom_regulator); + regulator_disable(fb_data->display_regulator); + + /*enable spdc clock gating*/ + spdc_clk_gate(fb_data, true); + clk_disable(fb_data->spdc_clk_pix); + clk_disable(fb_data->spdc_clk_axi); + + /* Disable pins used by SPDC (to prevent leakage current) */ + if (fb_data->pdata->disable_pins) + fb_data->pdata->disable_pins(); + + /* turn off the V3p3 */ + regulator_disable(fb_data->v3p3_regulator); + + fb_data->power_state = POWER_STATE_OFF; + fb_data->powering_down = false; + spdc_panel_pwr_down(fb_data); + + if (fb_data->wait_for_powerdown) { + fb_data->wait_for_powerdown = false; + complete(&fb_data->powerdown_compl); + } + + mutex_unlock(&fb_data->power_mutex); +} + +static void spdc_powerup(mxc_spdc_t *fb_data) +{ + int ret = 0; + mutex_lock(&fb_data->power_mutex); + + /* + * If power down request is pending, clear + * powering_down to cancel the request. + */ + if (fb_data->powering_down) + fb_data->powering_down = false; + + if (fb_data->power_state == POWER_STATE_ON) { + mutex_unlock(&fb_data->power_mutex); + return; + } + + dev_dbg(fb_data->dev, "spdc Powerup\n"); + + /* Enable the v3p3 regulator */ + ret = regulator_enable(fb_data->v3p3_regulator); + if (IS_ERR((void *)ret)) { + dev_err(fb_data->dev, "Unable to enable V3P3 regulator." + "err = 0x%x\n", ret); + mutex_unlock(&fb_data->power_mutex); + return; + } + + msleep(1); + + /* Enable pins used by SPDC */ + if (fb_data->pdata->enable_pins) + fb_data->pdata->enable_pins(); + + /* Enable clocks to SPDC */ + clk_enable(fb_data->spdc_clk_axi); + clk_enable(fb_data->spdc_clk_pix); + + /*disable spdc gate*/ + spdc_clk_gate(fb_data, false); + + /* Enable power to the EPD panel */ + ret = regulator_enable(fb_data->display_regulator); + if (IS_ERR((void *)ret)) { + dev_err(fb_data->dev, "Unable to enable DISPLAY regulator." + "err = 0x%x\n", ret); + mutex_unlock(&fb_data->power_mutex); + return; + } + ret = regulator_enable(fb_data->vcom_regulator); + if (IS_ERR((void *)ret)) { + dev_err(fb_data->dev, "Unable to enable VCOM regulator." + "err = 0x%x\n", ret); + mutex_unlock(&fb_data->power_mutex); + return; + } + + fb_data->power_state = POWER_STATE_ON; + spdc_panel_pwr_on(fb_data); + + mutex_unlock(&fb_data->power_mutex); +} + +#ifdef DEBUG +static void +check_waveform(u32 *wv_buf_orig, u32 *wv_buf_cur, u32 wv_buf_size) +{ + int i; + bool is_mismatch = false; + for (i = 0; i < wv_buf_size; i++) { + if (wv_buf_orig[i] != wv_buf_cur[i]) { + is_mismatch = true; + printk(KERN_ERR "Waveform mismatch!\n"); + } + } + + if (!is_mismatch) + printk(KERN_DEBUG "No mismatches!\n"); +} +#else +static void +check_waveform(u32 *wv_buf_orig, u32 *wv_buf_cur, u32 wv_buf_size) {} +#endif + +static void get_spdc_version(mxc_spdc_t *fb_data) +{ + struct mxc_spdc_version *spdc_ver = &fb_data->spdc_ver; + u32 disp_id, tcon_id; + + disp_id = __raw_readl(fb_data->hwp + SPDC_DISP_VER); + tcon_id = __raw_readl(fb_data->hwp + SPDC_TCON_VER); + + spdc_ver->disp_ver.product_id = disp_id & 0xFFFF; + spdc_ver->disp_ver.lut_ver = (disp_id >> 16) & 0xFF; + spdc_ver->disp_ver.epd_type = (disp_id >> 24) & 0xFF; + spdc_ver->tcon_ver = tcon_id & 0xFF; + + dev_info(fb_data->dev, "EPD type ID:%x, Tcon ID:%x\n", + spdc_ver->disp_ver.product_id, spdc_ver->tcon_ver); +} + +static void spdc_set_update_concurrency(mxc_spdc_t *fb_data) +{ + u32 concur_mode; + + concur_mode = fb_data->fresh_param.concur & 0xFF; + concur_mode |= (SPDC_LUT_MODE_OFFSET << 8); + + __raw_writel(concur_mode, fb_data->hwp + SPDC_LUT_PARA_UPDATE); +} + +static bool is_preprocess_list_full(mxc_spdc_t *fb_data) +{ + /* Check to see if preprocess are full in this list */ + if (fb_data->upd_preprocess_num >= SPDC_MAX_NUM_PREPROCESS) + return true; + else + return false; +} + +static void spdc_submit_update(mxc_spdc_t *fb_data) +{ + fb_data->updates_active = true; + + spdc_set_nextbuf_addr(fb_data); + spdc_set_update_coord(fb_data); + spdc_set_update_dimensions(fb_data); + spdc_set_update_temper(fb_data); + spdc_trigger_update(fb_data); +} + +static int spdc_init_sequence(mxc_spdc_t *fb_data) +{ + struct fb_var_screeninfo *screeninfo = &fb_data->spdc_fb_var; + struct spdc_buffer_addr *buf_addr = &fb_data->fresh_param.buf_addr; + struct imx_spdc_panel_init_set *init_set = + fb_data->pdata->spdc_mode->init_set; + u32 xres, yres; + int ret = -EFAULT; + + /*init spdc power*/ + spdc_powerup(fb_data); + + /* enable all interrupt */ + spdc_intr_stat_clear(fb_data, SPDC_INT_STA_CLR); + spdc_intr_enable(fb_data, SPDC_IRQ_ALL_MASK); + /* set ACC concurrency update mode */ + if (fb_data->fresh_param.concur) + spdc_set_update_concurrency(fb_data); + + /* program SPDC register and trigger to process buffer*/ + buf_addr->next_buf_phys_addr = fb_data->phy_next_buf; + buf_addr->cur_buf_phys_addr = fb_data->phy_current_buf; + buf_addr->pre_buf_phys_addr = fb_data->phy_pre_buf; + buf_addr->frm_cnt_buf_phys_addr = fb_data->phy_cnt_buf; + buf_addr->lut_buf_phys_addr = fb_data->phy_lut_buf; + + /* Use unrotated (native) width/height */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres = screeninfo->yres; + yres = screeninfo->xres; + } else { + xres = screeninfo->xres; + yres = screeninfo->yres; + } + fb_data->fresh_param.update_region.left = 0; + fb_data->fresh_param.update_region.top = 0; + fb_data->fresh_param.update_region.width = xres; + fb_data->fresh_param.update_region.height = yres; + + /* set panel temperature as environment temperature */ + fb_data->fresh_param.temper = SPDC_DEFAULT_TEMP; + /* set waveform mode */ + fb_data->fresh_param.wave_mode = SPDC_WAV_MODE_DEFAULT; + + spdc_set_update_coord(fb_data); + spdc_set_update_dimensions(fb_data); + + spdc_set_update_temper(fb_data); + + spdc_set_nextbuf_addr(fb_data); + spdc_set_curbuf_addr(fb_data); + spdc_set_prebuf_addr(fb_data); + spdc_set_cntbuf_addr(fb_data); + + /* load waveform*/ + spdc_set_lutbuf_addr(fb_data); + ret = wait_for_completion_timeout(&fb_data->lut_down, + msecs_to_jiffies(4000)); + if (!ret) { + dev_err(fb_data->dev, + "Timed out for lut!\n"); + return ret; + } + + /* init SPDC setting, the setting get from platform data */ + fb_data->panel_set.yoe_pol = init_set->yoe_pol; + fb_data->panel_set.dual_gate = init_set->dual_gate; + fb_data->panel_set.ud = init_set->ud; + fb_data->panel_set.rl = init_set->rl; + fb_data->panel_set.data_filter_n = init_set->data_filter_n; + fb_data->panel_set.rgbw_mode_enable = init_set->rgbw_mode_enable; + fb_data->panel_set.hburst_len_en = init_set->hburst_len_en; + ret = update_panel_init_set(fb_data); + + return ret; +} + +static u32 mxc_spdc_partial_refresh_low(mxc_spdc_t *fb_data, void *buffer) +{ + u8 *fresh_addr; + void *pattern = buffer; + struct partial_refresh_param *fresh_param = &fb_data->fresh_param; + u32 fresh_size; + int ret = 0; + + fb_data->updates_active = true; + + fresh_addr = (u8 *)(fb_data->virt_start) + + (fresh_param->update_region.top * fresh_param->stride) + + ((fresh_param->update_region.left * fb_data->default_bpp) >> 3); + fresh_size = (u32)((fresh_param->update_region.width * + fresh_param->update_region.height * fb_data->default_bpp) >> 3); + + if (buffer != NULL) { + while (fresh_size > 0) { + memcpy((void *)fresh_addr, pattern, + fresh_param->update_region.width); + fresh_size -= fresh_param->update_region.width; + fresh_addr += fresh_param->update_region.top * + fresh_param->stride; + pattern += fresh_param->update_region.width; + } + } + + /* program SPDC register and trigger to process buffer*/ + fb_data->fresh_param.buf_addr.next_buf_phys_addr = + fb_data->info.fix.smem_start + fb_data->fb_offset; + fb_data->fresh_param.wave_mode = fb_data->wv_modes.mode_init; + spdc_submit_update(fb_data); + + ret = wait_for_completion_timeout(&fb_data->update_finish, + msecs_to_jiffies(3000)); + if (!ret) { + dev_err(fb_data->dev, + "display update timeout!\n"); + return -ETIMEDOUT; + } + + return ret; +} + +static u32 spdc_fb_dev_init(mxc_spdc_t *fb_data) +{ + fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE; + fb_data->fresh_param.wave_mode = SPDC_WAV_MODE_0; + fb_data->operation_mode = SPDC_NO_OPERATION; + fb_data->is_deep_fresh = false; + + /* Init the concurrency update */ + fb_data->fresh_param.concur = 0; + fb_data->upd_preprocess_num = 0; + fb_data->submit_upd_sta = 0; + + fb_data->fresh_param.temper = SPDC_DEFAULT_TEMP; + + return 0; +} + +/** + * mxc_spdc_device_is_busy - check spdc device busy status. + * Returns 0 if spdc device is idle. + */ +static int mxc_spdc_device_is_busy(mxc_spdc_t *fb_data) +{ + u32 status; + u32 orig_jiffies = jiffies; + + while (1) { + status = __raw_readl(fb_data->hwp + SPDC_STATUS); + if ((status & SPDC_PANEL_STAUTS_BUSY) && + ((status & 0xF0) == SPDC_TCON_STATUS_IDLE)) + break; + + if (signal_pending(current)) { + dev_dbg(fb_data->dev, "SPDC Interrupted\n"); + return -EINTR; + } + + if (time_after(jiffies, orig_jiffies + + msecs_to_jiffies(3000))) { + dev_dbg(fb_data->dev, "SPDC is busy\n"); + return -ETIMEDOUT; + } + + schedule(); + } + + return 0; +} + +static bool is_free_list_full(mxc_spdc_t *fb_data) +{ + int count = 0; + struct update_data_list *plist; + + /* Count buffers in free buffer list */ + list_for_each_entry(plist, &fb_data->upd_buf_free_list, list) + count++; + + /* Check to see if all buffers are in this list */ + if (count == fb_data->max_num_updates) + return true; + else + return false; +} + +static void spdc_draw_mode0(mxc_spdc_t *fb_data) +{ + struct mxcfb_update_data update; + struct mxcfb_update_marker_data upd_marker_data; + struct fb_var_screeninfo *screeninfo = &fb_data->spdc_fb_var; + u32 xres, yres; + int ret; + + fb_data->fresh_param.buf_addr.next_buf_phys_addr = + fb_data->phys_start; + + fb_data->hw_ready = true; + fb_data->hw_initializing = false; + + /* Use unrotated (native) width/height */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres = screeninfo->yres; + yres = screeninfo->xres; + } else { + xres = screeninfo->xres; + yres = screeninfo->yres; + } + + update.update_region.left = 0; + update.update_region.width = xres; + update.update_region.top = 0; + update.update_region.height = yres; + update.update_mode = UPDATE_MODE_FULL; + update.waveform_mode = fb_data->wv_modes.mode_init; + update.update_marker = INIT_UPDATE_MARKER; + update.temp = SPDC_DEFAULT_TEMP; + update.flags = 0; + + upd_marker_data.update_marker = update.update_marker; + + mxc_spdc_fb_send_update(&update, &fb_data->info); + + /* Block on initial update */ + ret = mxc_spdc_fb_wait_update_complete(&upd_marker_data, + &fb_data->info); + if (ret < 0) + dev_err(fb_data->dev, + "Wait for update complete failed, Err:%d", ret); +} + +static void +spdc_fb_fw_handler(const struct firmware *fw, void *context) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)context; + struct clk *spdc_parent; + unsigned long rounded_parent_rate, spdc_pix_rate, + rounded_pix_clk, target_pix_clk; + u8 *wv_file; + int ret; + + if (fw == NULL) { + /* If default FW file load failed, we give up */ + if (fb_data->fw_default_load) + return; + + /* Try to load default waveform */ + fb_data->fw_default_load = true; + + ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + fb_data->fw_str, fb_data->dev, GFP_KERNEL, + fb_data, spdc_fb_fw_handler); + if (ret) { + dev_err(fb_data->dev, + "Failed to load waveform image with err %d\n", ret); + return; + } + } + + wv_file = (u8 *)fw->data; + memcpy(fb_data->virt_lut_buf, wv_file, fw->size); + + check_waveform((u32 *)wv_file, (u32 *)fb_data->virt_lut_buf, + fw->size / 4); + release_firmware(fw); + + /* Enable clocks to access SPDC regs */ + clk_enable(fb_data->spdc_clk_axi); + + target_pix_clk = fb_data->cur_mode->vmode->pixclock; + /* Enable pix clk for SPDC */ + clk_enable(fb_data->spdc_clk_pix); + rounded_pix_clk = clk_round_rate(fb_data->spdc_clk_pix, target_pix_clk); + + if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) || + (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) { + /* Can't get close enough without changing parent clk */ + spdc_parent = clk_get_parent(fb_data->spdc_clk_pix); + rounded_parent_rate = + clk_round_rate(spdc_parent, target_pix_clk); + + spdc_pix_rate = target_pix_clk; + while (spdc_pix_rate < rounded_parent_rate) + spdc_pix_rate *= 2; + clk_set_rate(spdc_parent, spdc_pix_rate); + + rounded_pix_clk = + clk_round_rate(fb_data->spdc_clk_pix, target_pix_clk); + if (((rounded_pix_clk >= target_pix_clk + target_pix_clk/100) || + (rounded_pix_clk <= target_pix_clk - target_pix_clk/100))) + /* Still can't get a good clock, provide warning */ + dev_err(fb_data->dev, + "Unable to get an accurate SPDC pix clk" + "desired = %lu, actual = %lu\n", target_pix_clk, + rounded_pix_clk); + } + + clk_set_rate(fb_data->spdc_clk_pix, rounded_pix_clk); + + if (!spdc_init_sequence(fb_data)) + return; + + /* display log on picture */ + spdc_draw_mode0(fb_data); +} + + +static int spdc_fb_init_hw(struct fb_info *info) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int ret; + + fb_data->fw_default_load = false; + /* + * Create fw search string based on ID string in selected videomode. + * Format is "imx/spdc_[wave_timing].fw: spdc_pvi.fw, spdc_auo.fw" + */ + if (fb_data->cur_mode) { + memset(fb_data->fw_str, 0, sizeof(fb_data->fw_str)); + strcat(fb_data->fw_str, "imx/spdc_"); + strcat(fb_data->fw_str, fb_data->cur_mode->wave_timing); + strcat(fb_data->fw_str, ".fw"); + } else + strcat(fb_data->fw_str, "imx/spdc_pvi.fw"); + + ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG, + fb_data->fw_str, fb_data->dev, GFP_KERNEL, + fb_data, spdc_fb_fw_handler); + if (ret) { + dev_err(fb_data->dev, + "Failed to load waveform image with err %d\n", ret); + return ret; + } + + return ret; +} + +static int mxc_spdc_partial_refresh(mxc_spdc_t *fb_data, void *buffer) +{ + int ret = 0; + struct partial_refresh_param *fresh_param = &fb_data->fresh_param; + + if (!fb_data->panel_set.power_ready) + spdc_powerup(fb_data); + + if (!fresh_param->blocking) { + if (mxc_spdc_device_is_busy(fb_data)) { + dev_err(fb_data->dev, "spdc busy!\n"); + return (u32) -1; + } + } else { + while (mxc_spdc_device_is_busy(fb_data)) { + dev_err(fb_data->dev, "Waiting for spdc idle..\n"); + msleep(500); + } + } + + ret = mxc_spdc_partial_refresh_low(fb_data, buffer); + + return ret; +} + +static int mxc_operaton_update(mxc_spdc_t *fb_data) +{ + int ret = 0; + struct partial_refresh_param *fresh_param = &fb_data->fresh_param; + u32 operation_mode = fb_data->operation_mode; + + if (!fb_data->panel_set.power_ready) + spdc_powerup(fb_data); + + if (operation_mode != SPDC_SW_TCON_RESET) { + if (!fresh_param->blocking) { + if (mxc_spdc_device_is_busy(fb_data)) { + dev_err(fb_data->dev, "spdc busy\n"); + return (u32) -1; + } + } else { + while (mxc_spdc_device_is_busy(fb_data)) { + dev_err(fb_data->dev, "Waiting spdc idle...\n"); + msleep(500); + } + } + } else + operation_mode = SPDC_SW_TCON_RESET_SET; + + /* don't add to queue list */ + mutex_lock(&fb_data->queue_mutex); + __raw_writel(operation_mode, fb_data->hwp + SPDC_OPERATE); + mutex_unlock(&fb_data->queue_mutex); + + if (operation_mode == SPDC_SW_TCON_RESET_SET) { + dev_dbg(fb_data->dev, "reinit hw\n"); + mdelay(500); + + fb_data->hw_ready = false; + fb_data->operation_mode = SPDC_NO_OPERATION; + ret = spdc_fb_init_hw(&fb_data->info); + if (ret && !fb_data->hw_ready) + dev_err(fb_data->dev, "Failed to init HW!\n"); + } + + return ret; +} + +static int mxc_spdc_refresh_display(mxc_spdc_t *fb_data) +{ + struct partial_refresh_param *fresh_param = &fb_data->fresh_param; + u32 operation_mode = fb_data->operation_mode; + int ret = 0; + + fresh_param->update_region.left = 0; + fresh_param->update_region.top = 0; + fresh_param->update_region.width = fb_data->spdc_fb_var.xres; + fresh_param->update_region.height = fb_data->spdc_fb_var.yres; + fresh_param->stride = (fb_data->spdc_fb_var.xres * + fb_data->spdc_fb_var.bits_per_pixel) >> 3; + + if (operation_mode && operation_mode < SPDC_FULL_REFRESH) + ret = mxc_operaton_update(fb_data); + else + ret = mxc_spdc_partial_refresh(fb_data, NULL); + + return ret; +} + +static void mxc_spdc_find_match_mode(mxc_spdc_t *fb_data) +{ + struct imx_spdc_fb_mode *spdc_mode = + &fb_data->pdata->spdc_mode[0]; + const struct mxc_spdc_resolution_map_para *spdc_res_map; + u32 i = 0; + u32 j = 0; + u32 default_mode = 0xFF; + + if (fb_data->panel_set.rgbw_mode_enable) + spdc_res_map = &spdc_rgbw_res_map[0]; + else + spdc_res_map = &spdc_gray_res_map[0]; + + while (spdc_mode != NULL) { + while (spdc_res_map[j].resolution != 0xFFFF) { + if (spdc_mode->vmode->xres == spdc_res_map[j].res_x + && spdc_mode->vmode->yres == spdc_res_map[j].res_y) { + fb_data->panel_set.resolution = + spdc_res_map[j].resolution; + default_mode = i; + break; + } + j++; + } + + if (default_mode != 0xFF) + break; + j = 0; + i++; + spdc_mode = &fb_data->pdata->spdc_mode[i]; + } + + fb_data->cur_mode = spdc_mode; +} + +static int mxc_spdc_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + unsigned long start = vma->vm_start; + unsigned long size = vma->vm_end - vma->vm_start; + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; + unsigned long page, pos; + + if (offset + size > info->fix.smem_len) + return -EINVAL; + + pos = (unsigned long)info->fix.smem_start + offset; + + /* make buffers bufferable */ + vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); + vma->vm_flags |= VM_RESERVED | VM_IO; + + while (size > 0) { + page = pos; + if (io_remap_pfn_range(vma, start, page >> PAGE_SHIFT, + PAGE_SIZE, vma->vm_page_prot)) + return -EAGAIN; + + start += PAGE_SIZE; + pos += PAGE_SIZE; + if (size > PAGE_SIZE) + size -= PAGE_SIZE; + else + size = 0; + } + + return 0; +} + +static inline u_int _chan_to_field(u_int chan, struct fb_bitfield *bf) +{ + chan &= 0xffff; + chan >>= 16 - bf->length; + return chan << bf->offset; +} + +static int mxc_spdc_fb_setcolreg(u_int regno, u_int red, u_int green, + u_int blue, u_int transp, struct fb_info *info) +{ + if (regno >= 256) /* no. of hw registers */ + return 1; + + /* grayscale works only partially under directcolor */ + if (info->var.grayscale) { + /* grayscale = 0.30*R + 0.59*G + 0.11*B */ + red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; + } + +#define CNVT_TOHW(val, width) ((((val)<<(width))+0x7FFF-(val))>>16) + switch (info->fix.visual) { + case FB_VISUAL_TRUECOLOR: + case FB_VISUAL_PSEUDOCOLOR: + red = CNVT_TOHW(red, info->var.red.length); + green = CNVT_TOHW(green, info->var.green.length); + blue = CNVT_TOHW(blue, info->var.blue.length); + transp = CNVT_TOHW(transp, info->var.transp.length); + break; + case FB_VISUAL_DIRECTCOLOR: + red = CNVT_TOHW(red, 8); /* expect 8 bit DAC */ + green = CNVT_TOHW(green, 8); + blue = CNVT_TOHW(blue, 8); + /* hey, there is bug in transp handling... */ + transp = CNVT_TOHW(transp, 8); + break; + } +#undef CNVT_TOHW + /* Truecolor has hardware independent palette */ + if (info->fix.visual == FB_VISUAL_TRUECOLOR) { + if (regno >= 16) + return 1; + + ((u32 *) (info->pseudo_palette))[regno] = + (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + } + + return 0; +} + +void mxc_spdc_fb_flush_updates(mxc_spdc_t *fb_data) +{ + int ret; + + /* Grab queue lock to prevent any new updates from being submitted */ + mutex_lock(&fb_data->queue_mutex); + + /* + * 3 places to check for updates that are active or pending: + * 1) Updates in the pending list + * 2) Update buffers in use (e.g., PxP processing) + * 3) Active updates to panel - We can key off of SPDC + * power state to know if we have active updates. + */ + if (!list_empty(&fb_data->upd_pending_list) || + !is_free_list_full(fb_data) || + (fb_data->updates_active == true)) { + /* Initialize event signalling updates are done */ + init_completion(&fb_data->updates_done); + fb_data->waiting_for_idle = true; + + mutex_unlock(&fb_data->queue_mutex); + /* Wait for any currently active updates to complete */ + ret = wait_for_completion_timeout(&fb_data->updates_done, + msecs_to_jiffies(8000)); + if (!ret) + dev_err(fb_data->dev, + "Flush updates timeout! ret = 0x%x\n", ret); + + mutex_lock(&fb_data->queue_mutex); + fb_data->waiting_for_idle = false; + } + + mutex_unlock(&fb_data->queue_mutex); +} + +static int mxc_spdc_fb_setcmap(struct fb_cmap *cmap, struct fb_info *info) +{ + int count, index, r; + u16 *red, *green, *blue, *transp; + u16 trans = 0xffff; + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int i; + + dev_dbg(fb_data->dev, "setcmap\n"); + + if (info->fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) { + /* Only support an 8-bit, 256 entry lookup */ + if (cmap->len != 256) + return 1; + + mxc_spdc_fb_flush_updates(fb_data); + + mutex_lock(&fb_data->pxp_mutex); + /* + * Store colormap in pxp_conf structure for later transmit + * to PxP during update process to convert gray pixels. + * + * Since red=blue=green for pseudocolor visuals, we can + * just use red values. + */ + for (i = 0; i < 256; i++) + fb_data->pxp_conf.proc_data.lut_map[i] = + cmap->red[i] & 0xFF; + + fb_data->pxp_conf.proc_data.lut_map_updated = true; + + mutex_unlock(&fb_data->pxp_mutex); + } else { + red = cmap->red; + green = cmap->green; + blue = cmap->blue; + transp = cmap->transp; + index = cmap->start; + + for (count = 0; count < cmap->len; count++) { + if (transp) + trans = *transp++; + r = mxc_spdc_fb_setcolreg(index++, *red++, + *green++, *blue++, trans, info); + if (r != 0) + return r; + } + } + + return 0; +} + +static void adjust_coordinates(u32 xres, u32 yres, u32 rotation, + struct mxcfb_rect *update_region, struct mxcfb_rect *adj_update_region) +{ + u32 temp; + + /* If adj_update_region == NULL, pass result back in update_region */ + /* If adj_update_region == valid, use it to pass back result */ + if (adj_update_region) + switch (rotation) { + case FB_ROTATE_UR: + adj_update_region->top = update_region->top; + adj_update_region->left = update_region->left; + adj_update_region->width = update_region->width; + adj_update_region->height = update_region->height; + break; + case FB_ROTATE_CW: + adj_update_region->top = update_region->left; + adj_update_region->left = yres - + (update_region->top + update_region->height); + adj_update_region->width = update_region->height; + adj_update_region->height = update_region->width; + break; + case FB_ROTATE_UD: + adj_update_region->width = update_region->width; + adj_update_region->height = update_region->height; + adj_update_region->top = yres - + (update_region->top + update_region->height); + adj_update_region->left = xres - + (update_region->left + update_region->width); + break; + case FB_ROTATE_CCW: + adj_update_region->left = update_region->top; + adj_update_region->top = xres - + (update_region->left + update_region->width); + adj_update_region->width = update_region->height; + adj_update_region->height = update_region->width; + break; + } + else + switch (rotation) { + case FB_ROTATE_UR: + /* No adjustment needed */ + break; + case FB_ROTATE_CW: + temp = update_region->top; + update_region->top = update_region->left; + update_region->left = yres - + (temp + update_region->height); + temp = update_region->width; + update_region->width = update_region->height; + update_region->height = temp; + break; + case FB_ROTATE_UD: + update_region->top = yres - + (update_region->top + update_region->height); + update_region->left = xres - + (update_region->left + update_region->width); + break; + case FB_ROTATE_CCW: + temp = update_region->left; + update_region->left = update_region->top; + update_region->top = xres - + (temp + update_region->width); + temp = update_region->width; + update_region->width = update_region->height; + update_region->height = temp; + break; + } +} + +static int mxc_spdc_fb_set_fix(struct fb_info *info) +{ + struct fb_fix_screeninfo *fix = &info->fix; + struct fb_var_screeninfo *var = &info->var; + + fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; + + fix->type = FB_TYPE_PACKED_PIXELS; + fix->accel = FB_ACCEL_NONE; + if (var->grayscale) + fix->visual = FB_VISUAL_STATIC_PSEUDOCOLOR; + else + fix->visual = FB_VISUAL_TRUECOLOR; + fix->xpanstep = 1; + fix->ypanstep = 1; + + return 0; +} + +static int mxc_spdc_fb_set_par(struct fb_info *info) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + struct fb_var_screeninfo *screeninfo = &fb_data->info.var; + struct imx_spdc_fb_mode *spdc_modes = fb_data->pdata->spdc_mode; + struct pxp_config_data *pxp_conf = &fb_data->pxp_conf; + struct pxp_proc_data *proc_data = &pxp_conf->proc_data; + int i, ret; + __u32 xoffset_old, yoffset_old; + + /* + * Can't change the FB parameters until current updates have completed. + * This function returns when all active updates are done. + */ + mxc_spdc_fb_flush_updates(fb_data); + + mutex_lock(&fb_data->queue_mutex); + /* + * Set all screeninfo except for xoffset/yoffset + * Subsequent call to pan_display will handle those. + */ + xoffset_old = fb_data->spdc_fb_var.xoffset; + yoffset_old = fb_data->spdc_fb_var.yoffset; + fb_data->spdc_fb_var = *screeninfo; + fb_data->spdc_fb_var.xoffset = xoffset_old; + fb_data->spdc_fb_var.yoffset = yoffset_old; + mutex_unlock(&fb_data->queue_mutex); + + mutex_lock(&fb_data->pxp_mutex); + + /* + * Update PxP config data (used to process FB regions for updates) + * based on FB info and processing tasks required + */ + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = proc_data->srect.width = screeninfo->xres; + proc_data->drect.height = proc_data->srect.height = screeninfo->yres; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = screeninfo->rotate; + proc_data->bgcolor = 0; + proc_data->overlay_state = 0; + proc_data->lut_transform = PXP_LUT_NONE; + + /* + * configure S0 channel parameters + * Parameters should match FB format/width/height + */ + if (screeninfo->grayscale) + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_GY04; + else { + switch (screeninfo->bits_per_pixel) { + case 16: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + break; + case 24: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB24; + break; + case 32: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB32; + break; + default: + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + break; + } + } + pxp_conf->s0_param.width = screeninfo->xres_virtual; + pxp_conf->s0_param.height = screeninfo->yres; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* + * Initialize Output channel parameters + * Output is Y-only greyscale + * Output width/height will vary based on update region size + */ + pxp_conf->out_param.width = screeninfo->xres; + pxp_conf->out_param.height = screeninfo->yres; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GY04; + + mutex_unlock(&fb_data->pxp_mutex); + + /* active new config, If HW not yet initialized, + * check to see if we are being sent + * an initialization request. + */ + if (!fb_data->hw_ready) { + struct fb_videomode mode; + bool found_match = false; + u32 xres_temp; + + fb_var_to_videomode(&mode, screeninfo); + + /* When comparing requested fb mode, + * we need to use unrotated dimensions + */ + if ((screeninfo->rotate == FB_ROTATE_CW) || + (screeninfo->rotate == FB_ROTATE_CCW)) { + xres_temp = mode.xres; + mode.xres = mode.yres; + mode.yres = xres_temp; + } + + /* Match videomode against spdc modes */ + for (i = 0; i < fb_data->pdata->num_modes; i++) { + if (!fb_mode_is_equal(spdc_modes[i].vmode, &mode)) + continue; + fb_data->cur_mode = &spdc_modes[i]; + found_match = true; + break; + } + + if (!found_match) { + dev_err(fb_data->dev, + "Failed to match requested video mode\n"); + return EINVAL; + } + + /* Initialize SPDC settings and init panel */ + ret = + spdc_fb_init_hw((struct fb_info *)fb_data); + if (ret) { + dev_err(fb_data->dev, + "Failed to load panel waveform data\n"); + return ret; + } + } + + mxc_spdc_fb_set_fix(info); + + return 0; +} + +static int +mxc_spdc_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + + if (!var->xres) + var->xres = 1; + if (!var->yres) + var->yres = 1; + + if (var->xres_virtual < var->xoffset + var->xres) + var->xres_virtual = var->xoffset + var->xres; + if (var->yres_virtual < var->yoffset + var->yres) + var->yres_virtual = var->yoffset + var->yres; + + if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && + (var->bits_per_pixel != 16) && (var->bits_per_pixel != 8) && + (var->bits_per_pixel != 4)) + var->bits_per_pixel = SPDC_DEFAULT_BPP; + + switch (var->bits_per_pixel) { + case 4: + var->red.offset = 0; + var->red.length = var->bits_per_pixel; + var->green = var->red; + var->blue = var->red; + var->transp.offset = 0; + var->transp.length = 0; + break; + case 8: + if (var->grayscale != 0) { + var->red.length = 8; + var->red.offset = 0; + var->red.msb_right = 0; + + var->green = var->red; + var->blue = var->red; + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + } else { + var->red.length = 3; + var->red.offset = 5; + var->red.msb_right = 0; + + var->green.length = 3; + var->green.offset = 2; + var->green.msb_right = 0; + + var->blue.length = 2; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + } + break; + case 16: + var->red.length = 5; + var->red.offset = 11; + var->red.msb_right = 0; + + var->green.length = 6; + var->green.offset = 5; + var->green.msb_right = 0; + + var->blue.length = 5; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 24: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 0; + var->transp.offset = 0; + var->transp.msb_right = 0; + break; + case 32: + var->red.length = 8; + var->red.offset = 16; + var->red.msb_right = 0; + + var->green.length = 8; + var->green.offset = 8; + var->green.msb_right = 0; + + var->blue.length = 8; + var->blue.offset = 0; + var->blue.msb_right = 0; + + var->transp.length = 8; + var->transp.offset = 24; + var->transp.msb_right = 0; + break; + } + + switch (var->rotate) { + case FB_ROTATE_UR: + case FB_ROTATE_UD: + var->xres = fb_data->native_width; + var->yres = fb_data->native_height; + break; + case FB_ROTATE_CW: + case FB_ROTATE_CCW: + var->xres = fb_data->native_height; + var->yres = fb_data->native_width; + break; + default: + /* Invalid rotation value */ + var->rotate = 0; + dev_dbg(fb_data->dev, "Invalid rotation request\n"); + return -EINVAL; + } + + var->xres_virtual = ALIGN(var->xres, 32); + var->yres_virtual = ALIGN(var->yres, 128) * fb_data->num_screens; + + var->height = -1; + var->width = -1; + + return 0; +} + +void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes, + struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + + mutex_lock(&fb_data->queue_mutex); + + memcpy(&fb_data->wv_modes, modes, sizeof(struct mxcfb_waveform_modes)); + + mutex_unlock(&fb_data->queue_mutex); +} +EXPORT_SYMBOL(mxc_spdc_fb_set_waveform_modes); + +/* To stick with non-fractional degrees for the sake + * of API consistency with EPDC. + */ +int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + s8 temper = (s8)(temperature & 0xFF) << 1; + + mutex_lock(&fb_data->queue_mutex); + + if (temper > -110 && temper < 200) + __raw_writel(temper, fb_data->hwp + SPDC_TEMP_INFO); + else + __raw_writel(SPDC_DEFAULT_TEMP, fb_data->hwp + SPDC_TEMP_INFO); + + mutex_unlock(&fb_data->queue_mutex); + + return 0; +} +EXPORT_SYMBOL(mxc_spdc_fb_set_temperature); + + +int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + + dev_dbg(fb_data->dev, "Setting auto update mode to %d\n", auto_mode); + + if ((auto_mode == AUTO_UPDATE_MODE_AUTOMATIC_MODE) + || (auto_mode == AUTO_UPDATE_MODE_REGION_MODE)) + fb_data->auto_mode = auto_mode; + else { + dev_err(fb_data->dev, "Invalid auto update mode parameter.\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mxc_spdc_fb_set_auto_update); + + +int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + + dev_dbg(fb_data->dev, "Setting optimization level to %d\n", upd_scheme); + + /* + * Can't change the scheme until current updates have completed. + * This function returns when all active updates are done. + */ + mxc_spdc_fb_flush_updates(fb_data); + + if ((upd_scheme == UPDATE_SCHEME_SNAPSHOT) + || (upd_scheme == UPDATE_SCHEME_QUEUE) + || (upd_scheme == UPDATE_SCHEME_QUEUE_AND_MERGE)) + fb_data->upd_scheme = upd_scheme; + else { + dev_err(fb_data->dev, "Invalid update scheme specified.\n"); + return -EINVAL; + } + + return 0; +} +EXPORT_SYMBOL(mxc_spdc_fb_set_upd_scheme); + +/* Callback function triggered after PxP receives an EOF interrupt */ +static void pxp_dma_done(void *arg) +{ + struct pxp_tx_desc *tx_desc = to_tx_desc(arg); + struct dma_chan *chan = tx_desc->txd.chan; + struct pxp_channel *pxp_chan = to_pxp_channel(chan); + mxc_spdc_t *fb_data = pxp_chan->client; + + /* This call will signal wait_for_completion_timeout() + * in send_buffer_to_pxp + */ + complete(&fb_data->pxp_tx_cmpl); +} + +static bool chan_filter(struct dma_chan *chan, void *arg) +{ + if (imx_dma_is_pxp(chan)) + return true; + else + return false; +} + +/* Function to request PXP DMA channel */ +static int pxp_chan_init(mxc_spdc_t *fb_data) +{ + dma_cap_mask_t mask; + struct dma_chan *chan; + + /* + * Request a free channel + */ + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + dma_cap_set(DMA_PRIVATE, mask); + chan = dma_request_channel(mask, chan_filter, NULL); + if (!chan) { + dev_err(fb_data->dev, "Unsuccessfully received channel!!!!\n"); + return -EBUSY; + } + + fb_data->pxp_chan = to_pxp_channel(chan); + fb_data->pxp_chan->client = fb_data; + + init_completion(&fb_data->pxp_tx_cmpl); + + return 0; +} + +/* + * Function to call PxP DMA driver and send our latest FB update region + * through the PxP and out to an intermediate buffer. + * Note: This is a blocking call, so upon return the PxP tx should be complete. + */ +static int pxp_process_update(mxc_spdc_t *fb_data, + u32 src_width, u32 src_height, + struct mxcfb_rect *update_region) +{ + dma_cookie_t cookie; + struct scatterlist *sg = fb_data->sg; + struct dma_chan *dma_chan; + struct pxp_tx_desc *desc; + struct dma_async_tx_descriptor *txd; + struct pxp_config_data *pxp_conf = &fb_data->pxp_conf; + struct pxp_proc_data *proc_data = &fb_data->pxp_conf.proc_data; + int i, ret; + int length; + + /* First, check to see that we have acquired a PxP Channel object */ + if (fb_data->pxp_chan == NULL) { + /* + * PxP Channel has not yet been created and initialized, + * so let's go ahead and try + */ + ret = pxp_chan_init(fb_data); + if (ret) { + /* + * PxP channel init failed, and we can't use the + * PxP until the PxP DMA driver has loaded, so we abort + */ + dev_err(fb_data->dev, "PxP chan init failed\n"); + return -ENODEV; + } + } + + /* + * Init completion, so that we + * can be properly informed of the completion + * of the PxP task when it is done. + */ + init_completion(&fb_data->pxp_tx_cmpl); + + dma_chan = &fb_data->pxp_chan->dma_chan; + + txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2, + DMA_TO_DEVICE, + DMA_PREP_INTERRUPT); + if (!txd) { + dev_err(fb_data->info.device, + "Error preparing a DMA transaction descriptor.\n"); + return -EIO; + } + + txd->callback_param = txd; + txd->callback = pxp_dma_done; + + /* + * Configure PxP for processing of new update region + * The rest of our config params were set up in + * probe() and should not need to be changed. + */ + pxp_conf->s0_param.width = src_width; + pxp_conf->s0_param.height = src_height; + proc_data->srect.top = update_region->top; + proc_data->srect.left = update_region->left; + proc_data->srect.width = update_region->width; + proc_data->srect.height = update_region->height; + + /* + * Because only YUV/YCbCr image can be scaled, configure + * drect equivalent to srect, as such do not perform scaling. + */ + proc_data->drect.top = 0; + proc_data->drect.left = 0; + proc_data->drect.width = proc_data->srect.width; + proc_data->drect.height = proc_data->srect.height; + + /* PXP expects rotation in terms of degrees */ + proc_data->rotate = fb_data->spdc_fb_var.rotate * 90; + if (proc_data->rotate > 270) + proc_data->rotate = 0; + + pxp_conf->out_param.width = update_region->width; + pxp_conf->out_param.height = update_region->height; + + if ((proc_data->rotate == 90) || (proc_data->rotate == 270)) + pxp_conf->out_param.stride = update_region->height; + else + pxp_conf->out_param.stride = update_region->width; + + desc = to_tx_desc(txd); + length = desc->len; + for (i = 0; i < length; i++) { + if (i == 0) {/* S0 */ + memcpy(&desc->proc_data, proc_data, + sizeof(struct pxp_proc_data)); + pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]); + memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param, + sizeof(struct pxp_layer_param)); + } else if (i == 1) { + pxp_conf->out_param.paddr = sg_dma_address(&sg[1]); + memcpy(&desc->layer_param.out_param, + &pxp_conf->out_param, + sizeof(struct pxp_layer_param)); + } + /* TODO: OverLay */ + + desc = desc->next; + } + + /* Submitting our TX starts the PxP processing task */ + cookie = txd->tx_submit(txd); + if (cookie < 0) { + dev_err(fb_data->info.device, "Error sending FB through PxP\n"); + return -EIO; + } + + fb_data->txd = txd; + + /* trigger ePxP */ + dma_async_issue_pending(dma_chan); + + return 0; +} + +static int pxp_complete_update(mxc_spdc_t *fb_data, u32 *hist_stat) +{ + int ret; + /* + * Wait for completion event, which will be set + * through our TX callback function. + */ + ret = wait_for_completion_timeout(&fb_data->pxp_tx_cmpl, HZ / 10); + if (ret <= 0) { + dev_info(fb_data->info.device, + "PxP operation failed due to %s\n", + ret < 0 ? "user interrupt" : "timeout"); + dma_release_channel(&fb_data->pxp_chan->dma_chan); + fb_data->pxp_chan = NULL; + return ret ? : -ETIMEDOUT; + } + + if ((fb_data->pxp_conf.proc_data.lut_transform & EPDC_FLAG_USE_CMAP) && + fb_data->pxp_conf.proc_data.lut_map_updated) + fb_data->pxp_conf.proc_data.lut_map_updated = false; + + *hist_stat = to_tx_desc(fb_data->txd)->hist_status; + dma_release_channel(&fb_data->pxp_chan->dma_chan); + fb_data->pxp_chan = NULL; + + dev_dbg(fb_data->dev, "TX completed\n"); + + return 0; +} + +static void copy_to_next_buffer(mxc_spdc_t *fb_data, + struct update_data_list *upd_data_list) +{ + struct mxcfb_update_data *upd_data = + &upd_data_list->update_desc->upd_data; + unsigned char *temp_buf_ptr = fb_data->virt_addr_copybuf; + unsigned char *dst_ptr = upd_data_list->virt_addr; + struct mxcfb_rect adj_update_region; + int dst_stride, left_offs, line_width; + int i; + + switch (fb_data->spdc_fb_var.rotate) { + case FB_ROTATE_UR: + adj_update_region.top = upd_data->update_region.top; + adj_update_region.left = upd_data->update_region.left; + adj_update_region.width = upd_data->update_region.width; + adj_update_region.height = upd_data->update_region.height; + dst_stride = fb_data->spdc_fb_var.xres_virtual / 2; + break; + case FB_ROTATE_CW: + adj_update_region.top = upd_data->update_region.left; + adj_update_region.left = fb_data->spdc_fb_var.yres - + (upd_data->update_region.top + + upd_data->update_region.height); + adj_update_region.width = upd_data->update_region.height; + adj_update_region.height = upd_data->update_region.width; + dst_stride = fb_data->spdc_fb_var.yres / 2; + break; + case FB_ROTATE_UD: + adj_update_region.width = upd_data->update_region.width; + adj_update_region.height = upd_data->update_region.height; + adj_update_region.top = fb_data->spdc_fb_var.yres - + (upd_data->update_region.top + upd_data->update_region.height); + adj_update_region.left = fb_data->spdc_fb_var.xres - + (upd_data->update_region.left + + upd_data->update_region.width); + dst_stride = fb_data->spdc_fb_var.xres_virtual / 2; + break; + case FB_ROTATE_CCW: + adj_update_region.left = upd_data->update_region.top; + adj_update_region.top = fb_data->spdc_fb_var.xres - + (upd_data->update_region.left + + upd_data->update_region.width); + adj_update_region.width = upd_data->update_region.height; + adj_update_region.height = upd_data->update_region.width; + dst_stride = fb_data->spdc_fb_var.yres / 2; + break; + } + + /* pxp output Y4 data. + * Copy the raw data to related region in next buffer. + */ + left_offs = adj_update_region.left / 2; + line_width = adj_update_region.width / 2; + + dst_ptr += (adj_update_region.top * dst_stride + left_offs); + for (i = 0; i < adj_update_region.height; i++) { + /* Copy the full line */ + memcpy(dst_ptr, temp_buf_ptr, line_width); + + dst_ptr += dst_stride; + temp_buf_ptr += line_width; + } +} + +static int spdc_process_update(struct update_data_list *upd_data_list, + mxc_spdc_t *fb_data) +{ + /* Region of src buffer for update */ + struct mxcfb_rect *src_upd_region; + struct mxcfb_rect pxp_upd_region; + struct update_desc_list *upd_desc_list = upd_data_list->update_desc; + u32 src_width, src_height; + u32 offset_from_4, bytes_per_pixel; + u32 post_rotation_xcoord, post_rotation_ycoord, width_pxp_blocks; + u32 pxp_input_offs, pxp_output_offs, pxp_output_shift; + bool input_unaligned = false; + u32 hist_stat = 0; + bool use_temp_buf = false; + int ret; + + /* + * Are we using FB or an alternate (overlay) + * buffer for source of update? + */ + if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) { + src_width = upd_desc_list->upd_data.alt_buffer_data.width; + src_height = upd_desc_list->upd_data.alt_buffer_data.height; + src_upd_region = + &upd_desc_list->upd_data.alt_buffer_data.alt_update_region; + } else { + src_width = fb_data->spdc_fb_var.xres_virtual; + src_height = fb_data->spdc_fb_var.yres; + src_upd_region = &upd_desc_list->upd_data.update_region; + } + + if (!(src_upd_region->width == fb_data->spdc_fb_var.xres_virtual && + fb_data->spdc_fb_var.rotate == FB_ROTATE_UR)) + use_temp_buf = true; + + bytes_per_pixel = fb_data->spdc_fb_var.bits_per_pixel / 8; + + /* Grab pxp_mutex here so that we protect access + * to copybuf in addition to the PxP structures */ + mutex_lock(&fb_data->pxp_mutex); + + offset_from_4 = src_upd_region->left & 0x3; + input_unaligned = ((offset_from_4 * bytes_per_pixel % 4) != 0) ? + true : false; + + if (input_unaligned) { + /* Leave a gap between PxP input addr + * and update region pixels + */ + pxp_input_offs = + (src_upd_region->top * src_width + src_upd_region->left) + * bytes_per_pixel & 0xFFFFFFFC; + /* Update region left changes to reflect + * relative position to input ptr + */ + pxp_upd_region.left = (offset_from_4 * bytes_per_pixel % 4) + / bytes_per_pixel; + } else { + pxp_input_offs = + (src_upd_region->top * src_width + src_upd_region->left) + * bytes_per_pixel; + pxp_upd_region.left = 0; + } + pxp_upd_region.top = 0; + + /* Update region dimensions to meet 8x8 pixel requirement */ + if (fb_data->spdc_fb_var.rotate == 0) { + pxp_upd_region.width = ALIGN(src_upd_region->width, 8); + pxp_upd_region.height = ALIGN(src_upd_region->height, 8); + } else { + pxp_upd_region.width = + ALIGN(src_upd_region->width + pxp_upd_region.left, 8); + pxp_upd_region.height = ALIGN(src_upd_region->height, 8); + } + + switch (fb_data->spdc_fb_var.rotate) { + case FB_ROTATE_UR: + default: + post_rotation_xcoord = pxp_upd_region.left; + post_rotation_ycoord = pxp_upd_region.top; + width_pxp_blocks = pxp_upd_region.width; + break; + case FB_ROTATE_CW: + width_pxp_blocks = pxp_upd_region.height; + post_rotation_xcoord = width_pxp_blocks - + src_upd_region->height; + post_rotation_ycoord = pxp_upd_region.left; + break; + case FB_ROTATE_UD: + width_pxp_blocks = pxp_upd_region.width; + post_rotation_xcoord = width_pxp_blocks - + src_upd_region->width - pxp_upd_region.left; + post_rotation_ycoord = pxp_upd_region.height - + src_upd_region->height - pxp_upd_region.top; + break; + case FB_ROTATE_CCW: + width_pxp_blocks = pxp_upd_region.height; + post_rotation_xcoord = pxp_upd_region.top; + post_rotation_ycoord = pxp_upd_region.width - + src_upd_region->width - pxp_upd_region.left; + break; + } + + /* Update region start coord to force PxP to + * process full 8x8 regions + */ + pxp_upd_region.top &= ~0x7; + pxp_upd_region.left &= ~0x7; + + pxp_output_shift = ALIGN(post_rotation_xcoord, 8) + - post_rotation_xcoord; + pxp_output_offs = post_rotation_ycoord * width_pxp_blocks + + pxp_output_shift; + upd_desc_list->spdc_offs = ALIGN(pxp_output_offs, 8); + + /* Source address either comes from alternate buffer + provided in update data, or from the framebuffer. */ + if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_ALT_BUFFER) + sg_dma_address(&fb_data->sg[0]) = + upd_desc_list->upd_data.alt_buffer_data.phys_addr + + pxp_input_offs; + else { + sg_dma_address(&fb_data->sg[0]) = + fb_data->info.fix.smem_start + fb_data->fb_offset + + pxp_input_offs; + sg_set_page(&fb_data->sg[0], + virt_to_page(fb_data->info.screen_base), + fb_data->info.fix.smem_len, + offset_in_page(fb_data->info.screen_base)); + } + + /* Update sg[1] to point to output of PxP proc task */ + if (!use_temp_buf) { + sg_dma_address(&fb_data->sg[1]) = upd_data_list->phys_addr; + sg_set_page(&fb_data->sg[1], + virt_to_page(upd_data_list->virt_addr), + fb_data->max_pix_size, + offset_in_page(upd_data_list->virt_addr)); + } else { + sg_dma_address(&fb_data->sg[1]) = fb_data->phys_addr_copybuf; + sg_set_page(&fb_data->sg[1], + virt_to_page(fb_data->virt_addr_copybuf), + fb_data->max_pix_size, + offset_in_page(fb_data->virt_addr_copybuf)); + } + + /* + * Set PxP LUT transform type based on update flags. + */ + fb_data->pxp_conf.proc_data.lut_transform = 0; + if (upd_desc_list->upd_data.flags & EPDC_FLAG_ENABLE_INVERSION) + fb_data->pxp_conf.proc_data.lut_transform |= PXP_LUT_INVERT; + if (upd_desc_list->upd_data.flags & EPDC_FLAG_FORCE_MONOCHROME) + fb_data->pxp_conf.proc_data.lut_transform |= + PXP_LUT_BLACK_WHITE; + if (upd_desc_list->upd_data.flags & EPDC_FLAG_USE_CMAP) + fb_data->pxp_conf.proc_data.lut_transform |= + PXP_LUT_USE_CMAP; + + /* + * Toggle inversion processing if 8-bit + * inverted is the current pixel format. + */ + if (fb_data->spdc_fb_var.grayscale == GRAYSCALE_4BIT_INVERTED) + fb_data->pxp_conf.proc_data.lut_transform ^= PXP_LUT_INVERT; + + /* This is a blocking call, so upon return PxP tx should be done */ + ret = pxp_process_update(fb_data, src_width, src_height, + &pxp_upd_region); + if (ret) { + dev_err(fb_data->dev, "Unable to submit PxP update task.\n"); + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + /* If needed, enable SPDC HW while ePxP is processing */ + if ((fb_data->power_state == POWER_STATE_OFF) + || fb_data->powering_down) { + spdc_powerup(fb_data); + } + + /* This is a blocking call, so upon return PxP tx should be done */ + ret = pxp_complete_update(fb_data, &hist_stat); + if (ret) { + dev_err(fb_data->dev, "Unable to complete PxP update task.\n"); + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + if (use_temp_buf) + copy_to_next_buffer(fb_data, upd_data_list); + + mutex_unlock(&fb_data->pxp_mutex); + + /* Update waveform mode from PxP histogram results */ + if (upd_desc_list->upd_data.waveform_mode == WAVEFORM_MODE_AUTO) { + if (hist_stat & 0x1) + upd_desc_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_du; + else if (hist_stat & 0x2) + upd_desc_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc4; + else if (hist_stat & 0x4) + upd_desc_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc8; + else if (hist_stat & 0x8) + upd_desc_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc16; + else + upd_desc_list->upd_data.waveform_mode = + fb_data->wv_modes.mode_gc32; + + dev_dbg(fb_data->dev, "hist_stat = 0x%x, new waveform = 0x%x\n", + hist_stat, upd_desc_list->upd_data.waveform_mode); + } + + return 0; +} + +static bool spdc_submit_concur(mxc_spdc_t *fb_data, + struct update_desc_list *update_to_concur) +{ + struct mxcfb_update_data *a, *b; + struct mxcfb_rect *arect, *brect; + struct update_data_list *next_upd; + int i = 0; + + a = &update_to_concur->upd_data; + arect = &update_to_concur->upd_data.update_region; + + list_for_each_entry(next_upd, + &fb_data->upd_buf_preprocess_list, list) { + b = &next_upd->update_desc->upd_data; + brect = &next_upd->update_desc->upd_data.update_region; + + /* Updates with different waveform + * must be executed sequentially. + */ + if (a->waveform_mode != b->waveform_mode) + break; + + /* + * Concurrency update must has no overlay + */ + if (!(arect->left > (brect->left + brect->width) || + brect->left > (arect->left + arect->width) || + arect->top > (brect->top + brect->height) || + brect->top > (arect->top + arect->height))) + break; + + i++; + } + + if (i != fb_data->upd_preprocess_num) + return false; + + return true; +} + +static int spdc_submit_merge(struct update_desc_list *upd_desc_list, + struct update_desc_list *update_to_merge) +{ + struct mxcfb_update_data *a, *b; + struct mxcfb_rect *arect, *brect; + struct mxcfb_rect combine; + bool use_flags = false; + + a = &upd_desc_list->upd_data; + b = &update_to_merge->upd_data; + arect = &upd_desc_list->upd_data.update_region; + brect = &update_to_merge->upd_data.update_region; + + /* + * Updates with different flags must be executed sequentially. + * Halt the merge process to ensure this. + */ + if (a->flags != b->flags) { + /* + * Special exception: if update regions are identical, + * we may be able to merge them. + */ + if ((arect->left != brect->left) || + (arect->top != brect->top) || + (arect->width != brect->width) || + (arect->height != brect->height)) + return MERGE_BLOCK; + + use_flags = true; + } + + if (a->waveform_mode != b->waveform_mode) + a->waveform_mode = WAVEFORM_MODE_AUTO; + + if (arect->left > (brect->left + brect->width) || + brect->left > (arect->left + arect->width) || + arect->top > (brect->top + brect->height) || + brect->top > (arect->top + arect->height)) + return MERGE_FAIL; + + combine.left = arect->left < brect->left ? arect->left : brect->left; + combine.top = arect->top < brect->top ? arect->top : brect->top; + combine.width = (arect->left + arect->width) > + (brect->left + brect->width) ? + (arect->left + arect->width - combine.left) : + (brect->left + brect->width - combine.left); + combine.height = (arect->top + arect->height) > + (brect->top + brect->height) ? + (arect->top + arect->height - combine.top) : + (brect->top + brect->height - combine.top); + + *arect = combine; + + /* Use flags of the later update */ + if (use_flags) + a->flags = b->flags; + + /* Merge markers */ + list_splice_tail(&update_to_merge->upd_marker_list, + &upd_desc_list->upd_marker_list); + + return MERGE_OK; + +} + +static void spdc_submit_work_func(struct work_struct *work) +{ + struct update_desc_list *next_desc, *temp_desc; + mxc_spdc_t *fb_data = + container_of(work, mxc_spdc_t, spdc_submit_work); + struct update_data_list *upd_data_list = NULL; + struct mxcfb_rect adj_update_region, *upd_region; + struct update_marker_data *current_marker; + bool end_merge = false; + bool is_transform; + u32 update_addr; + + /* Protect access to buffer queues and to update HW */ + mutex_lock(&fb_data->queue_mutex); + + /* get a buffer from free list */ + if (list_empty(&fb_data->upd_buf_free_list)) { + mutex_unlock(&fb_data->queue_mutex); + return; + } + + if (fb_data->fresh_param.concur == SPDC_LUT_ACC_MODE) { + list_for_each_entry_safe(next_desc, temp_desc, + &fb_data->upd_pending_list, list) { + + current_marker = + list_entry((&next_desc->upd_marker_list)->next, + struct update_marker_data, upd_list); + + if (current_marker->update_marker) { + fb_data->submit_upd_sta = 0; + break; + } + + /* require free buffer list */ + if (list_empty(&fb_data->upd_buf_free_list)) { + dev_dbg(fb_data->dev, + "buf free list is empty\n"); + break; + } + + upd_data_list = + list_entry(fb_data->upd_buf_free_list.next, + struct update_data_list, list); + upd_data_list->update_desc = next_desc; + + if (!is_preprocess_list_full(fb_data)) { + if (fb_data->cur_update == NULL && + !fb_data->upd_preprocess_num) + list_del_init(&next_desc->list); + else if (spdc_submit_concur(fb_data, + next_desc)) { + list_del_init(&next_desc->list); + list_add_tail(&upd_data_list->list, + &fb_data->upd_buf_preprocess_list); + fb_data->upd_preprocess_num++; + fb_data->submit_upd_sta = + SPDC_CONCUR_UPD; + } else + break; + } else + break; + + /* submit to pxp process */ + list_del_init(&upd_data_list->list); + goto pxp_process; + } + + upd_data_list = NULL; + if (fb_data->submit_upd_sta == SPDC_CONCUR_UPD) + fb_data->submit_upd_sta |= SPDC_QUEUE_UPD; + else + fb_data->submit_upd_sta = SPDC_QUEUE_UPD; + } + + list_for_each_entry_safe(next_desc, temp_desc, + &fb_data->upd_pending_list, list) { + + if (!upd_data_list) { + + if (list_empty(&fb_data->upd_buf_free_list)) { + dev_dbg(fb_data->dev, + "buf_free_list is empty\n"); + break; + } + upd_data_list = + list_entry(fb_data->upd_buf_free_list.next, + struct update_data_list, list); + list_del_init(&upd_data_list->list); + upd_data_list->update_desc = next_desc; + list_del_init(&next_desc->list); + + if (fb_data->upd_scheme == UPDATE_SCHEME_QUEUE) + break; + } else { + switch (spdc_submit_merge(upd_data_list->update_desc, + next_desc)) { + case MERGE_OK: + dev_dbg(fb_data->dev, + "Update merged [queue]\n"); + list_del_init(&next_desc->list); + kfree(next_desc); + break; + case MERGE_FAIL: + dev_dbg(fb_data->dev, + "Update not merged [queue]\n"); + break; + case MERGE_BLOCK: + dev_dbg(fb_data->dev, + "Merge blocked [collision]\n"); + end_merge = true; + break; + } + + if (end_merge) + break; + } + } + + /* Is update list empty? */ + if (!upd_data_list) { + mutex_unlock(&fb_data->queue_mutex); + return; + } + +pxp_process: + /* + * If no processing required, skip update processing + * No processing means: + * - FB unrotated + * - FB pixel format = 4-bit grayscale + * - No look-up transformations (inversion, posterization, etc.) + */ + is_transform = upd_data_list->update_desc->upd_data.flags & + (EPDC_FLAG_ENABLE_INVERSION | + EPDC_FLAG_FORCE_MONOCHROME | EPDC_FLAG_USE_CMAP) ? + true : false; + if ((fb_data->spdc_fb_var.rotate == FB_ROTATE_UR) && + (fb_data->spdc_fb_var.grayscale == GRAYSCALE_4BIT) && + !is_transform) { + + /* If needed, enable SPDC HW while ePxP is processing */ + if ((fb_data->power_state == POWER_STATE_OFF) + || fb_data->powering_down) + spdc_powerup(fb_data); + + /* + * Set update buffer pointer to the start of + * the update region in the frame buffer. + */ + upd_region = + &upd_data_list->update_desc->upd_data.update_region; + update_addr = fb_data->info.fix.smem_start + + ((upd_region->top * fb_data->info.var.xres_virtual) + + upd_region->left) * fb_data->info.var.bits_per_pixel/8; + } else { + + /* Select from PxP output buffers */ + upd_data_list->phys_addr = + fb_data->phys_addr_updbuf[fb_data->upd_buffer_num]; + upd_data_list->virt_addr = + fb_data->virt_addr_updbuf[fb_data->upd_buffer_num]; + fb_data->upd_buffer_num++; + if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1) + fb_data->upd_buffer_num = 0; + dev_dbg(fb_data->dev, + "pxp out addr:0x%x\n", upd_data_list->phys_addr); + + /* Release buffer queues */ + mutex_unlock(&fb_data->queue_mutex); + + /* Perform PXP processing - SPDC power will also be enabled */ + if (spdc_process_update(upd_data_list, fb_data)) { + + dev_dbg(fb_data->dev, "PXP processing error.\n"); + /* Protect access to buffer queues and to update HW */ + mutex_lock(&fb_data->queue_mutex); + list_del_init(&upd_data_list->update_desc->list); + kfree(upd_data_list->update_desc); + upd_data_list->update_desc = NULL; + + /* Add to free buffer list */ + list_add_tail(&upd_data_list->list, + &fb_data->upd_buf_free_list); + /* Release buffer queues */ + mutex_unlock(&fb_data->queue_mutex); + return; + } + + /* Protect access to buffer queues and to update HW */ + mutex_lock(&fb_data->queue_mutex); + + /* output Y4 format */ + update_addr = upd_data_list->phys_addr + + + (upd_data_list->update_desc->spdc_offs / 2); + } + + /* Get rotation-adjusted coordinates */ + adjust_coordinates(fb_data->spdc_fb_var.xres, + fb_data->spdc_fb_var.yres, fb_data->spdc_fb_var.rotate, + &upd_data_list->update_desc->upd_data.update_region, + &adj_update_region); + + /* + * Is the working buffer idle? + * If the working buffer is busy, we must wait for the resource + * to become free. + */ + if (fb_data->cur_update != NULL && + fb_data->submit_upd_sta != SPDC_CONCUR_UPD) { + /* Initialize event signalling an update resource is free */ + init_completion(&fb_data->update_res_free); + + fb_data->waiting_for_wb = true; + + /* Leave spinlock while waiting for WB to complete */ + mutex_unlock(&fb_data->queue_mutex); + wait_for_completion(&fb_data->update_res_free); + mutex_lock(&fb_data->queue_mutex); + } + + if (fb_data->submit_upd_sta != SPDC_CONCUR_UPD) + fb_data->cur_update = upd_data_list; + + /* program SPDC register and trigger to process buffer*/ + fb_data->fresh_param.buf_addr.next_buf_phys_addr = update_addr; + + fb_data->fresh_param.update_region.left = adj_update_region.left; + fb_data->fresh_param.update_region.top = adj_update_region.top; + fb_data->fresh_param.update_region.width = adj_update_region.width; + fb_data->fresh_param.update_region.height = adj_update_region.height; + fb_data->fresh_param.temper = upd_data_list->update_desc->upd_data.temp; + fb_data->fresh_param.wave_mode = + upd_data_list->update_desc->upd_data.waveform_mode; + + spdc_submit_update(fb_data); + + /* Release buffer queues */ + mutex_unlock(&fb_data->queue_mutex); +} + +int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data, + struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + struct update_data_list *upd_data_list = NULL; + struct mxcfb_rect *screen_upd_region; /* Region on screen to update */ + struct update_desc_list *upd_desc; + struct update_marker_data *marker_data; + int ret; + + /* Has SPDC HW been initialized? */ + if (!fb_data->hw_ready) { + /* Throw message if we are not mid-initialization */ + if (!fb_data->hw_initializing) + dev_err(fb_data->dev, "Display HW not properly" + "initialized. Aborting update.\n"); + return -EPERM; + } + + if ((upd_data->waveform_mode > SPDC_WAV_MODE_5) && + (upd_data->waveform_mode != WAVEFORM_MODE_AUTO)) { + dev_err(fb_data->dev, + "Update waveform mode 0x%x is invalid." + " Aborting update.\n", + upd_data->waveform_mode); + return -EINVAL; + } + if ((upd_data->update_region.left + upd_data->update_region.width > + fb_data->spdc_fb_var.xres + 1) || + (upd_data->update_region.top + upd_data->update_region.height > + fb_data->spdc_fb_var.yres + 1)) { + dev_err(fb_data->dev, + "Update region is outside bounds of framebuffer." + "Aborting update.\n"); + return -EINVAL; + } + if (upd_data->flags & EPDC_FLAG_USE_ALT_BUFFER) { + if ((upd_data->update_region.width != + upd_data->alt_buffer_data.alt_update_region.width) || + (upd_data->update_region.height != + upd_data->alt_buffer_data.alt_update_region.height)) { + dev_err(fb_data->dev, + "Alternate update region dimensions must " + "match screen update region dimensions.\n"); + return -EINVAL; + } + /* Validate physical address parameter */ + if ((upd_data->alt_buffer_data.phys_addr < + fb_data->info.fix.smem_start) || + (upd_data->alt_buffer_data.phys_addr > + fb_data->info.fix.smem_start + fb_data->map_size)) { + dev_err(fb_data->dev, + "Invalid physical address for alternate " + "buffer. Aborting update...\n"); + return -EINVAL; + } + } + + mutex_lock(&fb_data->queue_mutex); + + /* + * If we are waiting to go into suspend, or the FB is blanked, + * we do not accept new updates + */ + if (fb_data->waiting_for_idle) { + dev_dbg(fb_data->dev, "SPDC not active." + "Update request abort.\n"); + mutex_unlock(&fb_data->queue_mutex); + return -EPERM; + } + + if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) { + int count = 0; + struct update_data_list *plist; + + /* Count buffers in free buffer list */ + list_for_each_entry(plist, &fb_data->upd_buf_free_list, list) + count++; + + /* Use count to determine if we have enough + * free buffers to handle this update request */ + if (count + fb_data->max_num_buffers + <= fb_data->max_num_updates) { + dev_err(fb_data->dev, + "No free intermediate buffers available.\n"); + mutex_unlock(&fb_data->queue_mutex); + return -ENOMEM; + } + + /* Grab first available buffer and delete from the free list */ + upd_data_list = + list_entry(fb_data->upd_buf_free_list.next, + struct update_data_list, list); + + list_del_init(&upd_data_list->list); + } + + /* + * Create new update data structure, fill it with new update + * data and add it to the list of pending updates + */ + upd_desc = kzalloc(sizeof(struct update_desc_list), GFP_KERNEL); + if (!upd_desc) { + dev_err(fb_data->dev, + "Insufficient system memory for update! Aborting.\n"); + if (fb_data->upd_scheme == UPDATE_SCHEME_SNAPSHOT) { + list_add(&upd_data_list->list, + &fb_data->upd_buf_free_list); + } + mutex_unlock(&fb_data->queue_mutex); + return -EPERM; + } + /* Initialize per-update marker list */ + INIT_LIST_HEAD(&upd_desc->upd_marker_list); + upd_desc->upd_data = *upd_data; + list_add_tail(&upd_desc->list, &fb_data->upd_pending_list); + + /* If marker specified, associate it with a completion */ + if (upd_data->update_marker != 0) { + + /* Allocate new update marker and set it up */ + marker_data = kzalloc(sizeof(struct update_marker_data), + GFP_KERNEL); + if (!marker_data) { + dev_err(fb_data->dev, "No memory for marker!\n"); + mutex_unlock(&fb_data->queue_mutex); + return -ENOMEM; + } + list_add_tail(&marker_data->upd_list, + &upd_desc->upd_marker_list); + marker_data->update_marker = upd_data->update_marker; + init_completion(&marker_data->update_completion); + + /* Add marker to master marker list */ + list_add_tail(&marker_data->full_list, + &fb_data->full_marker_list); + } + + if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) { + /* Queued update scheme processing */ + + mutex_unlock(&fb_data->queue_mutex); + + /* Signal workqueue to handle new update */ + queue_work(fb_data->spdc_submit_workqueue, + &fb_data->spdc_submit_work); + + return 0; + } + + /* Set descriptor for current update, delete from pending list */ + upd_data_list->update_desc = upd_desc; + list_del_init(&upd_desc->list); + + mutex_unlock(&fb_data->queue_mutex); + + /* + * Hold on to original screen update region, which we + * will ultimately use when telling SPDC where to update on panel + */ + screen_upd_region = &upd_desc->upd_data.update_region; + + /* Select from PxP output buffers */ + upd_data_list->phys_addr = + fb_data->phys_addr_updbuf[fb_data->upd_buffer_num]; + upd_data_list->virt_addr = + fb_data->virt_addr_updbuf[fb_data->upd_buffer_num]; + fb_data->upd_buffer_num++; + if (fb_data->upd_buffer_num > fb_data->max_num_buffers-1) + fb_data->upd_buffer_num = 0; + + ret = spdc_process_update(upd_data_list, fb_data); + if (ret) { + mutex_unlock(&fb_data->pxp_mutex); + return ret; + } + + /* Pass selected waveform mode back to user */ + upd_data->waveform_mode = upd_desc->upd_data.waveform_mode; + + /* Get rotation-adjusted coordinates */ + adjust_coordinates(fb_data->spdc_fb_var.xres, + fb_data->spdc_fb_var.yres, fb_data->spdc_fb_var.rotate, + &upd_desc->upd_data.update_region, NULL); + + /* Grab lock for queue manipulation and update submission */ + mutex_lock(&fb_data->queue_mutex); + + /* + * Is the working buffer idle? + * If either the working buffer is busy, or there are no LUTs available, + * then we return and let the ISR handle the update later + */ + if (fb_data->cur_update != NULL) { + + /* Add processed Y buffer to update list */ + list_add_tail(&upd_data_list->list, &fb_data->upd_buf_queue); + + /* Return and allow the update to be submitted by the ISR. */ + mutex_unlock(&fb_data->queue_mutex); + return 0; + } + + /* Save current update */ + fb_data->cur_update = upd_data_list; + + /* program SPDC register and trigger to process buffer*/ + fb_data->fresh_param.buf_addr.next_buf_phys_addr = + upd_data_list->phys_addr + (upd_data_list->update_desc->spdc_offs / 2); + + fb_data->fresh_param.update_region.left = screen_upd_region->left; + fb_data->fresh_param.update_region.top = screen_upd_region->top; + fb_data->fresh_param.update_region.width = screen_upd_region->width; + fb_data->fresh_param.update_region.height = screen_upd_region->height; + fb_data->fresh_param.temper = upd_desc->upd_data.temp; + fb_data->fresh_param.wave_mode = upd_desc->upd_data.waveform_mode; + spdc_submit_update(fb_data); + + mutex_unlock(&fb_data->queue_mutex); + return 0; +} +EXPORT_SYMBOL(mxc_spdc_fb_send_update); + +/* + * return 0 : spdc update is update + */ +int +mxc_spdc_fb_wait_update_complete(struct mxcfb_update_marker_data *marker_data, + struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + struct update_marker_data *next_marker; + struct update_marker_data *temp; + bool marker_found = false; + int ret = 0; + + /* 0 is an invalid update_marker value */ + if (marker_data->update_marker == 0) + return -EINVAL; + + /* + * Find completion associated with update_marker requested. + * Note: If update completed already, marker will have been + * cleared, it won't be found, and function will just return. + */ + + /* Grab queue lock to protect access to marker list */ + mutex_lock(&fb_data->queue_mutex); + + list_for_each_entry_safe(next_marker, temp, + &fb_data->full_marker_list, full_list) { + if (next_marker->update_marker == marker_data->update_marker) { + dev_dbg(fb_data->dev, "Waiting for marker %d\n", + marker_data->update_marker); + next_marker->waiting = true; + marker_found = true; + break; + } + } + + mutex_unlock(&fb_data->queue_mutex); + + /* + * If marker not found, it has either been signalled already + * or the update request failed. In either case, just return. + */ + if (!marker_found) + return ret; + + ret = wait_for_completion_timeout(&next_marker->update_completion, + msecs_to_jiffies(8000)); + if (!ret) { + dev_err(fb_data->dev, + "Timed out waiting for update completion\n"); + return -ETIMEDOUT; + } + + /** since SPDC don't support auto collision detect, + * there alway returns no collision + */ + marker_data->collision_test = false; + + /* Free update marker object */ + kfree(next_marker); + + return ret; +} +EXPORT_SYMBOL(mxc_spdc_fb_wait_update_complete); + +int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay, + struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + + fb_data->pwrdown_delay = pwrdown_delay; + + return 0; +} +EXPORT_SYMBOL(mxc_spdc_fb_set_pwrdown_delay); + +int mxc_spdc_get_pwrdown_delay(struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + + return fb_data->pwrdown_delay; +} +EXPORT_SYMBOL(mxc_spdc_get_pwrdown_delay); + +static int +mxc_spdc_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + void __user *argp = (void __user *)arg; + int ret = -EINVAL; + + dev_dbg(fb_data->dev, "cmd = %08X, arg = %08X\n", cmd, (u32)arg); + + switch (cmd) { + case MXCFB_SET_WAVEFORM_MODES: + { + struct mxcfb_waveform_modes modes; + if (!copy_from_user(&modes, argp, sizeof(modes))) { + mxc_spdc_fb_set_waveform_modes(&modes, info); + ret = 0; + } + break; + } + case MXCFB_SET_TEMPERATURE: + { + int temperature; + if (!get_user(temperature, (int32_t __user *) arg)) + ret = mxc_spdc_fb_set_temperature(temperature, + info); + break; + } + case MXCFB_SET_AUTO_UPDATE_MODE: + { + u32 auto_mode = 0; + if (!get_user(auto_mode, (__u32 __user *) arg)) + ret = mxc_spdc_fb_set_auto_update(auto_mode, + info); + break; + } + case MXCFB_SET_UPDATE_SCHEME: + { + u32 upd_scheme = 0; + if (!get_user(upd_scheme, (__u32 __user *) arg)) + ret = mxc_spdc_fb_set_upd_scheme(upd_scheme, + info); + break; + } + case MXCFB_SEND_UPDATE: + { + struct mxcfb_update_data upd_data; + if (!copy_from_user(&upd_data, argp, + sizeof(upd_data))) { + ret = mxc_spdc_fb_send_update(&upd_data, info); + if (ret == 0 && copy_to_user(argp, &upd_data, + sizeof(upd_data))) + ret = -EFAULT; + } else { + ret = -EFAULT; + } + + break; + } + case MXCFB_WAIT_FOR_UPDATE_COMPLETE: + { + struct mxcfb_update_marker_data upd_marker_data; + if (!copy_from_user(&upd_marker_data, argp, + sizeof(upd_marker_data))) { + ret = mxc_spdc_fb_wait_update_complete( + &upd_marker_data, info); + if (copy_to_user(argp, &upd_marker_data, + sizeof(upd_marker_data))) + ret = -EFAULT; + } else { + ret = -EFAULT; + } + + break; + } + case MXCFB_SET_PWRDOWN_DELAY: + { + int delay = 0; + if (!get_user(delay, (__u32 __user *) arg)) + ret = + mxc_spdc_fb_set_pwrdown_delay(delay, info); + break; + } + case MXCFB_GET_PWRDOWN_DELAY: + { + int pwrdown_delay = mxc_spdc_get_pwrdown_delay(info); + if (put_user(pwrdown_delay, (int __user *)arg)) + ret = -EFAULT; + break; + } + default: + dev_err(fb_data->dev, "IOCTL_CMD: not such command\n"); + return -ENOTTY; + } + + return ret; +} + +static void mxc_spdc_fb_update_pages(mxc_spdc_t *fb_data, u16 y1, u16 y2) +{ + struct mxcfb_update_data update; + + /* Do partial screen update, Update full horizontal lines */ + update.update_region.left = 0; + update.update_region.width = fb_data->spdc_fb_var.xres; + update.update_region.top = y1; + update.update_region.height = y2 - y1; + update.waveform_mode = WAVEFORM_MODE_AUTO; + update.update_mode = UPDATE_MODE_FULL; + update.update_marker = 0; + update.temp = SPDC_DEFAULT_TEMP; + update.flags = 0; + + mxc_spdc_fb_send_update(&update, &fb_data->info); +} + +/* this is called back from the deferred io workqueue */ +static void mxc_spdc_fb_deferred_io(struct fb_info *info, + struct list_head *pagelist) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + struct page *page; + unsigned long beg, end; + int y1, y2, miny, maxy; + + if (fb_data->auto_mode != AUTO_UPDATE_MODE_AUTOMATIC_MODE) + return; + + miny = INT_MAX; + maxy = 0; + list_for_each_entry(page, pagelist, lru) { + beg = page->index << PAGE_SHIFT; + end = beg + PAGE_SIZE - 1; + y1 = beg / info->fix.line_length; + y2 = end / info->fix.line_length; + if (y2 >= fb_data->spdc_fb_var.yres) + y2 = fb_data->spdc_fb_var.yres - 1; + if (miny > y1) + miny = y1; + if (maxy < y2) + maxy = y2; + } + + mxc_spdc_fb_update_pages(fb_data, miny, maxy); +} + +static int mxc_spdc_fb_blank(int blank, struct fb_info *info) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int ret = 0; + + dev_dbg(fb_data->dev, "blank = %d\n", blank); + + if (fb_data->blank == blank) + return 0; + + fb_data->blank = blank; + switch (blank) { + case FB_BLANK_POWERDOWN: + mxc_spdc_fb_flush_updates(fb_data); + /* Wait for powerdown */ + mutex_lock(&fb_data->power_mutex); + if ((fb_data->power_state == POWER_STATE_ON) && + (fb_data->pwrdown_delay == FB_POWERDOWN_DISABLE)) { + + /* Powerdown disabled, so we disable SPDC manually */ + int count = 0; + int sleep_ms = 10; + + mutex_unlock(&fb_data->power_mutex); + + /* If any active updates, wait for them to complete */ + while (fb_data->updates_active) { + /* Timeout after 1 sec */ + if ((count * sleep_ms) > 1000) + break; + msleep(sleep_ms); + count++; + } + + fb_data->powering_down = true; + spdc_powerdown(fb_data); + } else if (fb_data->power_state != POWER_STATE_OFF) { + fb_data->wait_for_powerdown = true; + init_completion(&fb_data->powerdown_compl); + mutex_unlock(&fb_data->power_mutex); + ret = + wait_for_completion_timeout(&fb_data->powerdown_compl, + msecs_to_jiffies(5000)); + if (!ret) { + dev_err(fb_data->dev, + "No powerdown received!\n"); + return -ETIMEDOUT; + } + } else + mutex_unlock(&fb_data->power_mutex); + break; + case FB_BLANK_VSYNC_SUSPEND: + case FB_BLANK_HSYNC_SUSPEND: + case FB_BLANK_NORMAL: + mxc_spdc_fb_flush_updates(fb_data); + break; + } + + return ret; +} + +static int mxc_spdc_fb_pan_display(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + mxc_spdc_t *fb_data = info ? + (mxc_spdc_t *)info:g_fb_data; + u_int y_bottom; + + dev_dbg(info->device, "%s: var->yoffset %d, info->var.yoffset %d\n", + __func__, var->yoffset, info->var.yoffset); + /* check if var is valid; also, xpan is not supported */ + if (!var || (var->xoffset != info->var.xoffset) || + (var->yoffset + var->yres > var->yres_virtual)) { + dev_dbg(info->device, "x panning not supported\n"); + return -EINVAL; + } + + if ((fb_data->spdc_fb_var.xoffset == var->xoffset) && + (fb_data->spdc_fb_var.yoffset == var->yoffset)) + return 0; /* No change, do nothing */ + + y_bottom = var->yoffset; + + if (!(var->vmode & FB_VMODE_YWRAP)) + y_bottom += var->yres; + + if (y_bottom > info->var.yres_virtual) + return -EINVAL; + + mutex_lock(&fb_data->queue_mutex); + + fb_data->fb_offset = (var->yoffset * var->xres_virtual + var->xoffset) + * (var->bits_per_pixel) / 8; + + fb_data->spdc_fb_var.xoffset = var->xoffset; + fb_data->spdc_fb_var.yoffset = var->yoffset; + + if (var->vmode & FB_VMODE_YWRAP) + info->var.vmode |= FB_VMODE_YWRAP; + else + info->var.vmode &= ~FB_VMODE_YWRAP; + + mutex_unlock(&fb_data->queue_mutex); + + return 0; +} + +static struct fb_ops mxc_spdc_fb_ops = { + .owner = THIS_MODULE, + .fb_check_var = mxc_spdc_fb_check_var, + .fb_set_par = mxc_spdc_fb_set_par, + .fb_setcmap = mxc_spdc_fb_setcmap, + .fb_setcolreg = mxc_spdc_fb_setcolreg, + .fb_pan_display = mxc_spdc_fb_pan_display, + .fb_ioctl = mxc_spdc_fb_ioctl, + .fb_mmap = mxc_spdc_fb_mmap, + .fb_blank = mxc_spdc_fb_blank, + .fb_fillrect = cfb_fillrect, + .fb_copyarea = cfb_copyarea, + .fb_imageblit = cfb_imageblit, +}; + +static struct fb_deferred_io mxc_spdc_fb_defio = { + .delay = HZ, + .deferred_io = mxc_spdc_fb_deferred_io, +}; + +static void spdc_done_work_func(struct work_struct *work) +{ + mxc_spdc_t *fb_data = + container_of(work, mxc_spdc_t, spdc_done_work.work); + spdc_powerdown(fb_data); +} + +static irqreturn_t mxc_spdc_irq_handler(int irq, void *dev_id) +{ + mxc_spdc_t *fb_data = (mxc_spdc_t *)dev_id; + ulong flags; + u32 int_events; + irqreturn_t ret = IRQ_NONE; + + spin_lock_irqsave(&fb_data->lock, flags); + + int_events = spdc_get_intr_stat(fb_data); + dev_dbg(fb_data->dev, "spdc int:%x\n", int_events); + + if (int_events & SPDC_IRQ_STA_ERR) { + ret = IRQ_HANDLED; + spdc_intr_stat_clear(fb_data, SPDC_IRQ_STA_ERR); + dev_err(fb_data->dev, "Error IRQ\n"); + return ret; + } + + /* + * If we just completed one-time panel init, bypass + * queue handling, clear interrupt and return + */ + if (fb_data->operation_mode && + (int_events & SPDC_IRQ_STA_FRAME_UPDATE)) { + mutex_lock(&fb_data->queue_mutex); + fb_data->updates_active = false; + complete(&fb_data->update_finish); + spdc_intr_stat_clear(fb_data, SPDC_IRQ_STA_FRAME_UPDATE); + + if ((fb_data->operation_mode == SPDC_DEEP_REFRESH) || + fb_data->is_deep_fresh) + fb_data->is_deep_fresh = false; + else + fb_data->operation_mode = SPDC_NO_OPERATION; + + mutex_unlock(&fb_data->queue_mutex); + + return IRQ_HANDLED; + } + + /* waveform loading to SPDC from memory */ + if (int_events & SPDC_IRQ_STA_LUT_DOWNLOAD) { + if (is_lut_checksum_ok(fb_data)) { + complete(&fb_data->lut_down); + spdc_intr_stat_clear(fb_data, + SPDC_IRQ_STA_LUT_DOWNLOAD); + } else + dev_dbg(fb_data->dev, "Lut checksum is err!\n"); + + return IRQ_HANDLED; + } + + /* SPDC init setting IRQ */ + if (int_events & SPDC_IRQ_STA_TCON_INIT) { + complete(&fb_data->init_finish); + spdc_intr_stat_clear(fb_data, SPDC_IRQ_STA_TCON_INIT); + + return IRQ_HANDLED; + } + + spin_unlock_irqrestore(&fb_data->lock, flags); + + if (spdc_is_update_finish(fb_data)) { + /* clear interrupt status */ + spdc_intr_stat_clear(fb_data, SPDC_IRQ_STA_FRAME_UPDATE); + queue_work(fb_data->spdc_intr_workqueue, + &fb_data->spdc_intr_work); + } + + return ret; +} + +static void spdc_intr_work_func(struct work_struct *work) +{ + mxc_spdc_t *fb_data = + container_of(work, mxc_spdc_t, spdc_intr_work); + struct mxcfb_rect *next_upd_region; + struct update_marker_data *next_marker; + struct update_marker_data *temp; + struct update_data_list *next_upd, *temp_upd; + + /* Protect access to buffer queues and to update HW */ + mutex_lock(&fb_data->queue_mutex); + + /* Check to see if all updates have completed */ + if (list_empty(&fb_data->upd_pending_list) && + is_free_list_full(fb_data) && + (fb_data->cur_update == NULL)) { + + fb_data->updates_active = false; + + if (fb_data->pwrdown_delay != FB_POWERDOWN_DISABLE) { + /* + * Set variable to prevent overlapping + * enable/disable requests + */ + fb_data->powering_down = true; + + /* Schedule task to disable SPDC HW until next update */ + schedule_delayed_work(&fb_data->spdc_done_work, + msecs_to_jiffies(fb_data->pwrdown_delay)); + + /* Reset counter to reduce chance of overflow */ + fb_data->order_cnt = 0; + } + + if (fb_data->waiting_for_idle) + complete(&fb_data->updates_done); + } + + if (mxc_spdc_device_is_busy(fb_data)) { + /* Can't submit another update until SPDC is idle */ + mutex_unlock(&fb_data->queue_mutex); + return; + } + + /* + * Were we waiting on working buffer? + * If so, update queues and check for collisions + */ + if (fb_data->cur_update != NULL) { + list_for_each_entry_safe(next_marker, temp, + &fb_data->cur_update->update_desc->upd_marker_list, + upd_list) { + + /* Del from per-update & full list */ + list_del_init(&next_marker->upd_list); + list_del_init(&next_marker->full_list); + + /* Signal completion of update */ + dev_dbg(fb_data->dev, + "Signaling marker %d\n", + next_marker->update_marker); + if (next_marker->waiting) + complete(&next_marker->update_completion); + else + kfree(next_marker); + } + + /* Free marker list and update descriptor */ + kfree(fb_data->cur_update->update_desc); + + /* Add to free buffer list */ + list_add_tail(&fb_data->cur_update->list, + &fb_data->upd_buf_free_list); + + if (fb_data->submit_upd_sta & SPDC_CONCUR_UPD) { + fb_data->upd_preprocess_num = 0; + fb_data->submit_upd_sta &= (~SPDC_CONCUR_UPD); + } + + /* free ACC update list */ + list_for_each_entry_safe(next_upd, temp_upd, + &fb_data->upd_buf_preprocess_list, list) { + next_marker = list_entry( + (&next_upd->update_desc->upd_marker_list)->next, + struct update_marker_data, upd_list); + + list_del_init(&next_marker->upd_list); + list_del_init(&next_marker->full_list); + + /* Signal completion of update */ + dev_dbg(fb_data->dev, + "Signaling marker %d\n", + next_marker->update_marker); + + if (next_marker->waiting) + complete(&next_marker->update_completion); + else + kfree(next_marker); + + + list_del_init(&next_upd->list); + /* Add to free buffer list */ + list_add_tail(&next_upd->list, + &fb_data->upd_buf_free_list); + kfree(next_upd->update_desc); + } + + /* Check to see if all updates have completed */ + if (list_empty(&fb_data->upd_pending_list) && + is_free_list_full(fb_data)) { + + fb_data->updates_active = false; + + if (fb_data->pwrdown_delay != + FB_POWERDOWN_DISABLE) { + /* + * Set variable to prevent overlapping + * enable/disable requests + */ + fb_data->powering_down = true; + + /* Schedule SPDC disable */ + schedule_delayed_work(&fb_data->spdc_done_work, + msecs_to_jiffies(fb_data->pwrdown_delay)); + + /* Reset counter to reduce chance of overflow */ + fb_data->order_cnt = 0; + } + + if (fb_data->waiting_for_idle) + complete(&fb_data->updates_done); + } + + /* Signal completion if submit workqueue was waiting on WB */ + if (fb_data->waiting_for_wb) { + dev_dbg(fb_data->dev, "free update_res_free\n"); + complete(&fb_data->update_res_free); + fb_data->waiting_for_wb = false; + } + + /* Clear current update */ + fb_data->cur_update = NULL; + } + + if (fb_data->upd_scheme != UPDATE_SCHEME_SNAPSHOT) { + /* Queued update scheme processing */ + /* Schedule task to submit collision and pending update */ + if (!fb_data->powering_down) + queue_work(fb_data->spdc_submit_workqueue, + &fb_data->spdc_submit_work); + + /* Release buffer queues */ + mutex_unlock(&fb_data->queue_mutex); + return; + } + + /* Snapshot update scheme processing */ + if (list_empty(&fb_data->upd_buf_queue)) { + dev_dbg(fb_data->dev, "No pending updates.\n"); + + /* No updates pending, so we are done */ + mutex_unlock(&fb_data->queue_mutex); + return; + } else { + dev_dbg(fb_data->dev, "Found a pending update!\n"); + + /* Process next item in update list */ + fb_data->cur_update = + list_entry(fb_data->upd_buf_queue.next, + struct update_data_list, list); + list_del_init(&fb_data->cur_update->list); + } + + /* program SPDC register and trigger to process buffer*/ + next_upd_region = + &fb_data->cur_update->update_desc->upd_data.update_region; + fb_data->fresh_param.buf_addr.next_buf_phys_addr = + fb_data->cur_update->phys_addr + + (fb_data->cur_update->update_desc->spdc_offs / 2); + + fb_data->fresh_param.update_region.left = next_upd_region->left; + fb_data->fresh_param.update_region.top = next_upd_region->top; + fb_data->fresh_param.update_region.width = next_upd_region->width; + fb_data->fresh_param.update_region.height = next_upd_region->height; + fb_data->fresh_param.temper = + fb_data->cur_update->update_desc->upd_data.temp; + fb_data->fresh_param.wave_mode = + fb_data->cur_update->update_desc->upd_data.waveform_mode; + spdc_submit_update(fb_data); + + mutex_unlock(&fb_data->queue_mutex); + + return; +} + +/* + * Sysfs functions + */ +static ssize_t show_update(struct device *device, + struct device_attribute *attr, char *buf) { + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + + return sprintf(buf, "mode%d\n", fb_data->fresh_param.wave_mode); +} + +static ssize_t store_update(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct mxcfb_update_data update; + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + if (strncmp(buf, "direct", 6) == 0) + update.waveform_mode = fb_data->wv_modes.mode_du; + else if (strncmp(buf, "gc16", 4) == 0) + update.waveform_mode = fb_data->wv_modes.mode_gc16; + else if (strncmp(buf, "gc4", 3) == 0) + update.waveform_mode = fb_data->wv_modes.mode_gc4; + else if (strncmp(buf, "init", 4) == 0) + update.waveform_mode = fb_data->wv_modes.mode_init; + else if (strncmp(buf, "gu", 2) == 0) + update.waveform_mode = SPDC_WAV_MODE_3; + else if (strncmp(buf, "auto", 4) == 0) + update.waveform_mode = WAVEFORM_MODE_AUTO; + + /* Now, request full screen update */ + update.update_region.left = 0; + update.update_region.width = fb_data->spdc_fb_var.xres; + update.update_region.top = 0; + update.update_region.height = fb_data->spdc_fb_var.yres; + update.update_mode = UPDATE_MODE_FULL; + update.temp = SPDC_DEFAULT_TEMP; + update.update_marker = 0; + update.flags = 0; + dev_dbg(fb_data->dev, "rotation:%d, gray:%d\n", + fb_data->spdc_fb_var.rotate, fb_data->spdc_fb_var.grayscale); + + mxc_spdc_fb_send_update(&update, info); + + return count; +} + +static ssize_t fresh_show(struct device *device, struct device_attribute *attr, + char *buf) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + + return sprintf(buf, "%d\n", fb_data->operation_mode); +} + +static ssize_t fresh_store(struct device *device, struct device_attribute *attr, + const char *buf, size_t count) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int ret, operation; + + ret = kstrtoint(buf, 10, &operation); + if (ret) + return ret; + + if (operation == SPDC_DEEP_REFRESH) + fb_data->is_deep_fresh = true; + fb_data->operation_mode = operation; + if (operation > SPDC_NO_OPERATION && + operation < SPDC_FULL_REFRESH) + mxc_operaton_update(fb_data); + else + mxc_spdc_refresh_display(fb_data); + + return count; +} + +static ssize_t temp_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int temp; + + temp = fb_data->fresh_param.temper >> 1; + return sprintf(buf, "%d\n", temp); +} + +static ssize_t initset_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + u32 init_val; + + get_panel_init_set(&fb_data->panel_set, &init_val); + return sprintf(buf, "%x\n", init_val); +} + +static ssize_t concurrency_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + bool temp; + + temp = (fb_data->fresh_param.concur ? 1 : 0); + return sprintf(buf, "%d\n", temp); +} + +static ssize_t concurrency_update(struct device *device, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct fb_info *info = dev_get_drvdata(device); + mxc_spdc_t *fb_data = (mxc_spdc_t *)info; + int ret, concur; + + ret = kstrtoint(buf, 10, &concur); + if (ret) + return ret; + + if (fb_data->fresh_param.concur != concur) { + fb_data->fresh_param.concur = concur; + spdc_set_update_concurrency(fb_data); + } + + return count; +} + +static DEVICE_ATTR(store_update, 0644, show_update, store_update); +static DEVICE_ATTR(fresh, 0644, fresh_show, fresh_store); +static DEVICE_ATTR(temp, 0644, temp_show, NULL); +static DEVICE_ATTR(initset, 0644, initset_show, NULL); +static DEVICE_ATTR(concurrency, 0644, concurrency_show, concurrency_update); + +static struct attribute *spdc_attributes[] = { + &dev_attr_store_update.attr, + &dev_attr_fresh.attr, + &dev_attr_temp.attr, + &dev_attr_initset.attr, + &dev_attr_concurrency.attr, + NULL +}; + +static const struct attribute_group spdc_attr_group = { + .attrs = spdc_attributes, +}; + +static int __devinit mxc_spdc_fb_probe(struct platform_device *pdev) +{ + struct fb_info *info; + mxc_spdc_t *fb_data; + struct resource *res, *mem; + struct fb_videomode *vmode; + int xres_virt, yres_virt, buf_size; + int xres_virt_rot, yres_virt_rot, pix_size_rot; + struct fb_var_screeninfo *var_info; + struct fb_fix_screeninfo *fix_info; + struct pxp_config_data *pxp_conf; + struct pxp_proc_data *proc_data; + struct scatterlist *sg; + struct update_data_list *upd_list; + struct update_data_list *plist, *temp_list; + char *options, *opt; + char *panel_str = NULL; + char name[] = "mxcspdcfb"; + unsigned long x_mem_size = 0; + u32 i, cmap_size; + int ret = 0; + + fb_data = (mxc_spdc_t *)framebuffer_alloc(sizeof(mxc_spdc_t), + &pdev->dev); + if (!fb_data) { + ret = -ENOMEM; + goto out; + } + + info = &fb_data->info; + fb_data->dev = &pdev->dev; + platform_set_drvdata(pdev, fb_data); + + fb_data->pdata = pdev->dev.platform_data; + if ((fb_data->pdata == NULL) || (fb_data->pdata->num_modes < 1) + || (fb_data->pdata->spdc_mode == NULL) + || (fb_data->pdata->spdc_mode->vmode == NULL)) { + ret = -EINVAL; + goto dealloc_fb; + } + + /*get panel para from command*/ + if (fb_get_options(name, &options)) { + ret = -ENODEV; + goto dealloc_fb; + } + if (options) + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) + continue; + if (!strncmp(opt, "bpp=", 4)) { + if (kstrtoint(opt + 4, 0, + &fb_data->default_bpp) < 0) + fb_data->default_bpp = 0; + } else if (!strncmp(opt, "x_mem=", 6)) + x_mem_size = memparse(opt + 6, NULL); + else + panel_str = opt; + } + + if (!fb_data->default_bpp) + fb_data->default_bpp = SPDC_DEFAULT_BPP; + + /* Set default (first defined mode) for a match */ + mxc_spdc_find_match_mode(fb_data); + + if (panel_str) + for (i = 0; i < fb_data->pdata->num_modes; i++) + if (!strcmp(fb_data->pdata->spdc_mode[i].vmode->name, + panel_str)) { + fb_data->cur_mode = + &fb_data->pdata->spdc_mode[i]; + break; + } + vmode = fb_data->cur_mode->vmode; + + /* Allocate color map for the FB */ + cmap_size = 256; + ret = fb_alloc_cmap(&info->cmap, cmap_size, 0); + if (ret) + goto dealloc_fb; + + /* + * GPU alignment restrictions dictate framebuffer parameters: + * - 32-byte alignment for buffer width + * - 128-byte alignment for buffer height + * => 4K buffer alignment for buffer start + */ + xres_virt = ALIGN(vmode->xres, 32); + yres_virt = ALIGN(vmode->yres, 128); + fb_data->max_pix_size = PAGE_ALIGN(xres_virt * yres_virt); + + /* + * Have to check to see if aligned buffer size when rotated + * is bigger than when not rotated, and use the max + */ + xres_virt_rot = ALIGN(vmode->yres, 32); + yres_virt_rot = ALIGN(vmode->xres, 128); + pix_size_rot = PAGE_ALIGN(xres_virt_rot * yres_virt_rot); + fb_data->max_pix_size = (fb_data->max_pix_size > pix_size_rot) ? + fb_data->max_pix_size : pix_size_rot; + buf_size = fb_data->max_pix_size * fb_data->default_bpp/8; + + /* Compute the number of screens needed based on X memory requested */ + if (x_mem_size > 0) { + fb_data->num_screens = DIV_ROUND_UP(x_mem_size, buf_size); + if (fb_data->num_screens < NUM_SCREENS_MIN) + fb_data->num_screens = NUM_SCREENS_MIN; + else if (buf_size * fb_data->num_screens > SZ_16M) + fb_data->num_screens = SZ_16M / buf_size; + } else + fb_data->num_screens = NUM_SCREENS_MIN; + + fb_data->map_size = buf_size * fb_data->num_screens; + dev_dbg(&pdev->dev, "memory allocate: %d\n", fb_data->map_size); + + /* get IO memory*/ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&pdev->dev, "failed to get memory register\n"); + ret = -ENXIO; + goto release_cmap; + } + + mem = request_mem_region(res->start, resource_size(res), pdev->name); + if (res == NULL) { + dev_err(&pdev->dev, "failed to get memory region\n"); + ret = -ENOENT; + goto release_cmap; + } + + fb_data->hwp = ioremap(res->start, SZ_4K); + if (fb_data->hwp == NULL) { + dev_err(&pdev->dev, "ioremap registers failed\n"); + ret = -ENOENT; + goto release_mem; + } + + /* Allocate FB memory */ + fb_data->virt_start = dma_alloc_writecombine(&pdev->dev, + fb_data->map_size, &fb_data->phys_start, GFP_DMA); + if (fb_data->virt_start == NULL) { + dev_err(&pdev->dev, "probe err - dma_alloc for framebuffer\n"); + ret = -ENOMEM; + goto release_hwp; + } + + var_info = &info->var; + var_info->activate = FB_ACTIVATE_TEST; + var_info->bits_per_pixel = fb_data->default_bpp; + var_info->xres = vmode->xres; + var_info->yres = vmode->yres; + var_info->xres_virtual = xres_virt; + var_info->yres_virtual = yres_virt * fb_data->num_screens; + var_info->pixclock = vmode->pixclock; + var_info->left_margin = vmode->left_margin; + var_info->right_margin = vmode->right_margin; + var_info->upper_margin = vmode->upper_margin; + var_info->lower_margin = vmode->lower_margin; + var_info->hsync_len = vmode->hsync_len; + var_info->vsync_len = vmode->vsync_len; + var_info->vmode = FB_VMODE_NONINTERLACED; + + switch (fb_data->default_bpp) { + case 32: + case 24: + var_info->red.offset = 16; + var_info->red.length = 8; + var_info->green.offset = 8; + var_info->green.length = 8; + var_info->blue.offset = 0; + var_info->blue.length = 8; + break; + case 16: + var_info->red.offset = 11; + var_info->red.length = 5; + var_info->green.offset = 5; + var_info->green.length = 6; + var_info->blue.offset = 0; + var_info->blue.length = 5; + break; + case 8: + var_info->grayscale = GRAYSCALE_8BIT; + + var_info->red.length = 8; + var_info->red.offset = 0; + var_info->red.msb_right = 0; + var_info->green.length = 8; + var_info->green.offset = 0; + var_info->green.msb_right = 0; + var_info->blue.length = 8; + var_info->blue.offset = 0; + var_info->blue.msb_right = 0; + break; + case 4: + var_info->grayscale = GRAYSCALE_4BIT; + + var_info->red.length = 4; + var_info->red.offset = 0; + var_info->red.msb_right = 0; + var_info->green.length = 4; + var_info->green.offset = 0; + var_info->green.msb_right = 0; + var_info->blue.length = 4; + var_info->blue.offset = 0; + var_info->blue.msb_right = 0; + break; + default: + dev_err(&pdev->dev, "unsupported bit-width:%d\n", + fb_data->default_bpp); + ret = -EINVAL; + goto release_dma_fb; + } + + fix_info = &info->fix; + strcpy(fix_info->id, SPDC_DRIVER_NAME); + fix_info->type = FB_TYPE_PACKED_PIXELS; + fix_info->visual = FB_VISUAL_TRUECOLOR; + fix_info->xpanstep = 0; + fix_info->ypanstep = 0; + fix_info->ywrapstep = 0; + fix_info->accel = FB_ACCEL_NONE; + fix_info->smem_start = fb_data->phys_start; + fix_info->smem_len = fb_data->map_size; + fix_info->ypanstep = 0; + + /* Set up FB info */ + fb_data->native_width = vmode->xres; + fb_data->native_height = vmode->yres; + info->screen_base = fb_data->virt_start; + info->screen_size = info->fix.smem_len; + info->fbops = &mxc_spdc_fb_ops; + info->var.activate = FB_ACTIVATE_NOW; + info->pseudo_palette = fb_data->pseudo_palette; + info->flags = FBINFO_FLAG_DEFAULT; + + mxc_spdc_fb_set_fix(info); + + /* use the same AXI and PIX clock source */ + fb_data->spdc_clk_axi = clk_get(fb_data->dev, "epdc_axi"); + if (IS_ERR(fb_data->spdc_clk_axi)) { + dev_err(&pdev->dev, "Unable to get AXI clk." + "err = 0x%x\n", (int)fb_data->spdc_clk_axi); + ret = -ENODEV; + goto release_dma_fb; + } + fb_data->spdc_clk_pix = clk_get(fb_data->dev, "epdc_pix"); + if (IS_ERR(fb_data->spdc_clk_pix)) { + dev_err(&pdev->dev, "Unable to get pix clk." + "err = 0x%x\n", (int)fb_data->spdc_clk_pix); + ret = -ENODEV; + goto release_dma_fb; + } + + /* + * Initialize update list and allocate buffer. + */ + INIT_LIST_HEAD(&fb_data->upd_pending_list); + INIT_LIST_HEAD(&fb_data->upd_buf_queue); + INIT_LIST_HEAD(&fb_data->upd_buf_free_list); + INIT_LIST_HEAD(&fb_data->upd_buf_preprocess_list); + INIT_LIST_HEAD(&fb_data->full_marker_list); + + fb_data->max_num_updates = SPDC_MAX_NUM_UPDATES; + fb_data->max_num_buffers = SPDC_MAX_NUM_BUFFERS; + + /* Allocate free buffers */ + for (i = 0; i < fb_data->max_num_updates; i++) { + upd_list = kzalloc(sizeof(*upd_list), GFP_KERNEL); + if (upd_list == NULL) { + ret = -ENOMEM; + goto release_dma_fb; + } + + /* Add newly allocated buffer to free list */ + list_add(&upd_list->list, &fb_data->upd_buf_free_list); + } + + /* Allocate PXP output buffer */ + fb_data->virt_addr_updbuf = + kzalloc(sizeof(void *) * fb_data->max_num_buffers, GFP_KERNEL); + fb_data->phys_addr_updbuf = + kzalloc(sizeof(dma_addr_t) * fb_data->max_num_buffers, + GFP_KERNEL); + for (i = 0; i < fb_data->max_num_buffers; i++) { + /* + * Allocate memory for PxP output buffer. + * Output raw data is Y4 format. + * Each update buffer is 1/2 byte per pixel, and can + * be as big as the full-screen frame buffer + */ + fb_data->virt_addr_updbuf[i] = + dma_alloc_coherent(fb_data->info.device, + fb_data->max_pix_size / 2, + &fb_data->phys_addr_updbuf[i], GFP_DMA); + if (fb_data->virt_addr_updbuf[i] == NULL) { + ret = -ENOMEM; + goto release_freebuf_lists; + } + } + /* Counter indicating which update buffer should be used next. */ + fb_data->upd_buffer_num = 0; + + /* Allocate memory for partical process region buffer. + * Output raw data is Y4 format. + */ + fb_data->virt_addr_copybuf = + dma_alloc_coherent(fb_data->info.device, + fb_data->max_pix_size / 2, + &fb_data->phys_addr_copybuf, GFP_DMA); + if (fb_data->virt_addr_copybuf == NULL) { + ret = -ENOMEM; + goto release_output_buf; + } + + /* Allocate next & current & privious & count & lut buffers. + * next buffer size is Y4 raw data + */ + fb_data->next_buf_size = + (fb_data->map_size / fb_data->num_screens) >> 1; + fb_data->virt_next_buf = + dma_alloc_coherent(&pdev->dev, fb_data->next_buf_size, + &fb_data->phy_next_buf, GFP_DMA); + if (fb_data->virt_next_buf == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for next buf!\n"); + ret = -ENOMEM; + goto release_copy_buf; + } + + fb_data->current_buf_size = + (fb_data->map_size / fb_data->num_screens) >> 1; + fb_data->virt_current_buf = + dma_alloc_coherent(&pdev->dev, fb_data->current_buf_size, + &fb_data->phy_current_buf, GFP_DMA); + if (fb_data->virt_current_buf == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for current buf!\n"); + ret = -ENOMEM; + goto release_next_buf; + } + + fb_data->pre_buf_size = + (fb_data->map_size / fb_data->num_screens) >> 1; + fb_data->virt_pre_buf = + dma_alloc_coherent(&pdev->dev, fb_data->pre_buf_size, + &fb_data->phy_pre_buf, GFP_DMA); + if (fb_data->virt_pre_buf == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for current buf!\n"); + ret = -ENOMEM; + goto release_current_buf; + } + + fb_data->cnt_buf_size = info->var.xres * info->var.yres; + fb_data->virt_cnt_buf = + dma_alloc_coherent(&pdev->dev, fb_data->cnt_buf_size, + &fb_data->phy_cnt_buf, GFP_DMA); + if (fb_data->virt_cnt_buf == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for current buf!\n"); + ret = -ENOMEM; + goto release_pre_buf; + } + + fb_data->lut_buf_size = SZ_1M; + fb_data->virt_lut_buf = + dma_alloc_coherent(&pdev->dev, fb_data->lut_buf_size, + &fb_data->phy_lut_buf, GFP_DMA); + if (fb_data->virt_lut_buf == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for current buf!\n"); + ret = -ENOMEM; + goto release_cnt_buf; + } + + /* Initialize SPDC pins */ + if (fb_data->pdata->get_pins) + fb_data->pdata->get_pins(); + + fb_data->hw_ready = false; + fb_data->hw_initializing = false; + + /* + * Set default waveform mode values. + * Should be overwritten via ioctl. + */ + fb_data->wv_modes.mode_init = SPDC_WAV_MODE_DEFAULT; + fb_data->wv_modes.mode_du = SPDC_WAV_MODE_4; + fb_data->wv_modes.mode_gc4 = SPDC_WAV_MODE_2; + fb_data->wv_modes.mode_gc8 = SPDC_WAV_MODE_1; + fb_data->wv_modes.mode_gc16 = SPDC_WAV_MODE_1; + fb_data->wv_modes.mode_gc32 = SPDC_WAV_MODE_1; + + fb_data->auto_mode = AUTO_UPDATE_MODE_REGION_MODE; + fb_data->upd_scheme = UPDATE_SCHEME_QUEUE_AND_MERGE; + fb_data->spdc_fb_var = *var_info; + fb_data->fb_offset = 0; + + fb_data->blank = FB_BLANK_UNBLANK; + fb_data->powering_down = false; + fb_data->power_state = POWER_STATE_OFF; + fb_data->pwrdown_delay = 0; + fb_data->cur_update = NULL; + fb_data->waiting_for_idle = false; + fb_data->order_cnt = 0; + fb_data->waiting_for_wb = false; + fb_data->wait_for_powerdown = false; + fb_data->updates_active = false; + + spin_lock_init(&fb_data->lock); + mutex_init(&fb_data->queue_mutex); + mutex_init(&fb_data->pxp_mutex); + mutex_init(&fb_data->power_mutex); + init_completion(&fb_data->lut_down); + init_completion(&fb_data->init_finish); + init_completion(&fb_data->update_finish); + INIT_DELAYED_WORK(&fb_data->spdc_done_work, spdc_done_work_func); + + fb_data->spdc_submit_workqueue = alloc_workqueue("SPDC Submit", + WQ_MEM_RECLAIM | WQ_HIGHPRI | + WQ_CPU_INTENSIVE | WQ_UNBOUND, 1); + INIT_WORK(&fb_data->spdc_submit_work, spdc_submit_work_func); + fb_data->spdc_intr_workqueue = alloc_workqueue("SPDC Interrupt", + WQ_MEM_RECLAIM | WQ_HIGHPRI | + WQ_CPU_INTENSIVE | WQ_UNBOUND, 1); + INIT_WORK(&fb_data->spdc_intr_work, spdc_intr_work_func); + + /* Retrieve spdc IRQ num */ + res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (res == NULL) { + dev_err(&pdev->dev, "cannot get IRQ resource\n"); + ret = -ENODEV; + goto release_lut_buf; + } + fb_data->spdc_irq = res->start; + ret = request_irq(fb_data->spdc_irq, mxc_spdc_irq_handler, 0, + "fb_dma", fb_data); + if (ret) { + dev_err(&pdev->dev, "request_irq (%d) failed with error %d\n", + fb_data->spdc_irq, ret); + ret = -ENODEV; + goto release_lut_buf; + } + + /* define deferred io */ + info->fbdefio = &mxc_spdc_fb_defio; +#ifdef CONFIG_FB_MXC_SIPIX_AUTO_UPDATE_MODE + fb_deferred_io_init(info); +#endif + + /* get pmic regulators */ + fb_data->display_regulator = regulator_get(NULL, "DISPLAY"); + if (IS_ERR(fb_data->display_regulator)) { + dev_err(&pdev->dev, "Unable to get display PMIC regulator." + "err = 0x%x\n", (int)fb_data->display_regulator); + ret = -ENODEV; + goto release_irq; + } + fb_data->vcom_regulator = regulator_get(NULL, "VCOM"); + if (IS_ERR(fb_data->vcom_regulator)) { + regulator_put(fb_data->display_regulator); + dev_err(&pdev->dev, "Unable to get VCOM regulator." + "err = 0x%x\n", (int)fb_data->vcom_regulator); + ret = -ENODEV; + goto release_regulator1; + } + fb_data->v3p3_regulator = regulator_get(NULL, "V3P3"); + if (IS_ERR(fb_data->v3p3_regulator)) { + regulator_put(fb_data->vcom_regulator); + regulator_put(fb_data->display_regulator); + dev_err(&pdev->dev, "Unable to get V3P3 regulator." + "err = 0x%x\n", (int)fb_data->vcom_regulator); + ret = -ENODEV; + goto release_regulator2; + } + + /* + * Fill out PxP config data structure based on FB info and + * processing tasks required + */ + pxp_conf = &fb_data->pxp_conf; + proc_data = &pxp_conf->proc_data; + + /* Initialize non-channel-specific PxP parameters */ + proc_data->drect.left = proc_data->srect.left = 0; + proc_data->drect.top = proc_data->srect.top = 0; + proc_data->drect.width = fb_data->info.var.xres; + proc_data->srect.width = fb_data->info.var.xres; + proc_data->drect.height = fb_data->info.var.yres; + proc_data->srect.height = fb_data->info.var.yres; + proc_data->scaling = 0; + proc_data->hflip = 0; + proc_data->vflip = 0; + proc_data->rotate = 0; + proc_data->bgcolor = 0; + proc_data->overlay_state = 0; + proc_data->lut_transform = PXP_LUT_NONE; + proc_data->lut_map = NULL; + + /* + * We initially configure PxP for RGB->YUV conversion, + * and only write out Y component of the result. + */ + + /* + * Initialize S0 channel parameters + * Parameters should match FB format/width/height + */ + pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->s0_param.width = fb_data->info.var.xres_virtual; + pxp_conf->s0_param.height = fb_data->info.var.yres; + pxp_conf->s0_param.color_key = -1; + pxp_conf->s0_param.color_key_enable = false; + + /* + * Initialize OL0 channel parameters + * No overlay will be used for PxP operation + */ + for (i = 0; i < 8; i++) { + pxp_conf->ol_param[i].combine_enable = false; + pxp_conf->ol_param[i].width = 0; + pxp_conf->ol_param[i].height = 0; + pxp_conf->ol_param[i].pixel_fmt = PXP_PIX_FMT_RGB565; + pxp_conf->ol_param[i].color_key_enable = false; + pxp_conf->ol_param[i].color_key = -1; + pxp_conf->ol_param[i].global_alpha_enable = false; + pxp_conf->ol_param[i].global_alpha = 0; + pxp_conf->ol_param[i].local_alpha_enable = false; + } + + /* + * Initialize Output channel parameters + * Output is Y-only greyscale + * Output width/height will vary based on update region size + */ + pxp_conf->out_param.width = fb_data->info.var.xres; + pxp_conf->out_param.height = fb_data->info.var.yres; + pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_GY04; + pxp_conf->out_param.stride = pxp_conf->out_param.width; + + /* Initialize color map for conversion of 8-bit gray pixels */ + fb_data->pxp_conf.proc_data.lut_map = kmalloc(256, GFP_KERNEL); + if (fb_data->pxp_conf.proc_data.lut_map == NULL) { + dev_err(&pdev->dev, "Can't allocate mem for lut map!\n"); + ret = -ENOMEM; + goto release_regulator3; + } + for (i = 0; i < 256; i++) + fb_data->pxp_conf.proc_data.lut_map[i] = i; + + fb_data->pxp_conf.proc_data.lut_map_updated = true; + + /* + * Ensure this is set to NULL here...we will initialize pxp_chan + * later in our thread. + */ + fb_data->pxp_chan = NULL; + + /* Initialize Scatter-gather list containing 2 buffer addresses. */ + sg = fb_data->sg; + sg_init_table(sg, 2); + + /* + * For use in PxP transfers: + * sg[0] holds the FB buffer pointer + * sg[1] holds the Output buffer pointer (configured before TX request) + */ + sg_dma_address(&sg[0]) = info->fix.smem_start; + sg_set_page(&sg[0], virt_to_page(info->screen_base), + info->fix.smem_len, offset_in_page(info->screen_base)); + + /* Register FB */ + ret = register_framebuffer(info); + if (ret) { + dev_err(&pdev->dev, + "register framebuffer failed\n"); + goto release_lutmap; + } + + ret = sysfs_create_group(&info->device->kobj, &spdc_attr_group); + if (ret) + dev_err(&pdev->dev, "Unable to create file from fb_attrs\n"); + + /* use for spdc test */ + g_fb_data = fb_data; + + /* hw init */ + spdc_fb_dev_init(fb_data); + + /*detect spdc epd disp & tcon version*/ + get_spdc_version(fb_data); + + goto out; + +release_lutmap: + kfree(fb_data->pxp_conf.proc_data.lut_map); +release_regulator3: + regulator_put(fb_data->v3p3_regulator); +release_regulator2: + regulator_put(fb_data->vcom_regulator); +release_regulator1: + regulator_put(fb_data->display_regulator); +release_irq: + free_irq(fb_data->spdc_irq, fb_data); +release_lut_buf: + dma_free_coherent(&pdev->dev, fb_data->pre_buf_size, + fb_data->virt_lut_buf, fb_data->phy_lut_buf); +release_cnt_buf: + dma_free_coherent(&pdev->dev, fb_data->cnt_buf_size, + fb_data->virt_cnt_buf, fb_data->phy_cnt_buf); +release_pre_buf: + dma_free_coherent(&pdev->dev, fb_data->pre_buf_size, + fb_data->virt_pre_buf, fb_data->phy_pre_buf); +release_current_buf: + dma_free_coherent(&pdev->dev, fb_data->current_buf_size, + fb_data->virt_current_buf, fb_data->phy_current_buf); +release_next_buf: + dma_free_coherent(&pdev->dev, fb_data->next_buf_size, + fb_data->virt_next_buf, fb_data->phy_next_buf); +release_copy_buf: + dma_free_writecombine(&pdev->dev, fb_data->max_pix_size / 2, + fb_data->virt_addr_copybuf, fb_data->phys_addr_copybuf); +release_output_buf: + for (i = 0; i < fb_data->max_num_buffers; i++) + if (fb_data->virt_addr_updbuf[i] != NULL) + dma_free_writecombine(&pdev->dev, + fb_data->max_pix_size / 2, fb_data->virt_addr_updbuf[i], + fb_data->phys_addr_updbuf[i]); + if (fb_data->virt_addr_updbuf != NULL) + kfree(fb_data->virt_addr_updbuf); + if (fb_data->phys_addr_updbuf != NULL) + kfree(fb_data->phys_addr_updbuf); +release_freebuf_lists: + list_for_each_entry_safe(plist, temp_list, &fb_data->upd_buf_free_list, + list) { + list_del(&plist->list); + kfree(plist); + } +release_dma_fb: + dma_free_writecombine(&pdev->dev, + fb_data->map_size, fb_data->virt_start, fb_data->phys_start); +release_hwp: + iounmap(fb_data->hwp); +release_mem: + release_resource(mem); +release_cmap: + fb_dealloc_cmap(&info->cmap); +dealloc_fb: + framebuffer_release(info); +out: + return ret; +} + +static int mxc_spdc_fb_remove(struct platform_device *pdev) +{ + struct update_data_list *plist, *temp_list; + mxc_spdc_t *fb_data = platform_get_drvdata(pdev); + struct fb_info *info = &fb_data->info; + int i; + + mxc_spdc_fb_blank(FB_BLANK_POWERDOWN, &fb_data->info); + + flush_workqueue(fb_data->spdc_submit_workqueue); + destroy_workqueue(fb_data->spdc_submit_workqueue); + + regulator_put(fb_data->display_regulator); + regulator_put(fb_data->vcom_regulator); + regulator_put(fb_data->v3p3_regulator); + + for (i = 0; i < fb_data->max_num_buffers; i++) + if (fb_data->virt_addr_updbuf[i] != NULL) + dma_free_writecombine(&pdev->dev, + fb_data->max_pix_size, + fb_data->virt_addr_updbuf[i], + fb_data->phys_addr_updbuf[i]); + if (fb_data->virt_addr_updbuf != NULL) + kfree(fb_data->virt_addr_updbuf); + if (fb_data->phys_addr_updbuf != NULL) + kfree(fb_data->phys_addr_updbuf); + + /* free output temporary buffer */ + dma_free_writecombine(&pdev->dev, fb_data->max_pix_size / 2, + fb_data->virt_addr_copybuf, fb_data->phys_addr_copybuf); + + list_for_each_entry_safe(plist, temp_list, + &fb_data->upd_buf_free_list, + list) { + list_del(&plist->list); + kfree(plist); + } + +#if defined(CONFIG_FB_MXC_SIPIX_AUTO_UPDATE_MODE) + fb_deferred_io_cleanup(&fb_data->info); +#endif + + /* free frame buffer */ + dma_free_writecombine(&pdev->dev, fb_data->map_size, + info->screen_base, fb_data->phys_start); + + /* free SPDC hw allocate buffer */ + dma_free_coherent(&pdev->dev, fb_data->next_buf_size, + fb_data->virt_next_buf, fb_data->phy_next_buf); + dma_free_coherent(&pdev->dev, fb_data->current_buf_size, + fb_data->virt_current_buf, fb_data->phy_current_buf); + dma_free_coherent(&pdev->dev, fb_data->pre_buf_size, + fb_data->virt_pre_buf, fb_data->phy_pre_buf); + dma_free_coherent(&pdev->dev, fb_data->cnt_buf_size, + fb_data->virt_cnt_buf, fb_data->phy_cnt_buf); + dma_free_coherent(&pdev->dev, fb_data->pre_buf_size, + fb_data->virt_lut_buf, fb_data->phy_lut_buf); + + sysfs_remove_group(&info->device->kobj, &spdc_attr_group); + unregister_framebuffer(info); + + if (fb_data->pdata->put_pins) + fb_data->pdata->put_pins(); + + free_irq(fb_data->spdc_irq, fb_data); + iounmap(fb_data->hwp); + + fb_dealloc_cmap(&info->cmap); + + framebuffer_release(info); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM +static int mxc_spdc_fb_suspend(struct platform_device *pdev, + pm_message_t state) +{ + mxc_spdc_t *data = platform_get_drvdata(pdev); + int ret; + + ret = mxc_spdc_fb_blank(FB_BLANK_POWERDOWN, &data->info); + + return ret; +} + +static int mxc_spdc_fb_resume(struct platform_device *pdev) +{ + mxc_spdc_t *data = platform_get_drvdata(pdev); + + mxc_spdc_fb_blank(FB_BLANK_UNBLANK, &data->info); + return 0; +} +#else +#define mxc_spdc_fb_suspend NULL +#define mxc_spdc_fb_resume NULL +#endif + +static struct platform_driver mxc_spdc_fb_driver = { + .probe = mxc_spdc_fb_probe, + .remove = mxc_spdc_fb_remove, + .suspend = mxc_spdc_fb_suspend, + .resume = mxc_spdc_fb_resume, + .driver = { + .name = SPDC_DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init mxc_spdc_fb_init(void) +{ + return platform_driver_register(&mxc_spdc_fb_driver); +} +late_initcall(mxc_spdc_fb_init); + +static void __exit mxc_spdc_fb_exit(void) +{ + platform_driver_unregister(&mxc_spdc_fb_driver); +} +module_exit(mxc_spdc_fb_exit); + +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("MXC SPDC framebuffer driver"); +MODULE_LICENSE("GPL"); +MODULE_SUPPORTED_DEVICE("fb"); diff --git a/drivers/video/mxc/mxc_spdc_fb.h b/drivers/video/mxc/mxc_spdc_fb.h new file mode 100644 index 000000000000..34373788e83e --- /dev/null +++ b/drivers/video/mxc/mxc_spdc_fb.h @@ -0,0 +1,352 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MXC_SPDC_FB_H__ +#define __MXC_SPDC_FB_H__ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/errno.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <linux/irq.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/delay.h> +#include <linux/interrupt.h> +#include <linux/fb.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/delay.h> +#include <linux/firmware.h> +#include <linux/dmaengine.h> +#include <linux/pxp_dma.h> +#include <linux/mxcfb.h> +#include <linux/list.h> +#include <linux/uaccess.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/clk.h> +#include <linux/regulator/driver.h> +#include <linux/dmaengine.h> +#include <linux/gpio.h> +#include <linux/kthread.h> +#include <mach/epdc.h> +#include <mach/dma.h> +#include <linux/platform_device.h> + +#include <linux/fsl_devices.h> +#include <linux/mxcfb.h> + +/************************************* +*Register addresses +*************************************/ +#define SPDC_DISP_TRIGGER (0x000) +#define SPDC_UPDATA_X_Y (0x004) +#define SPDC_UPDATE_W_H (0x008) +#define SPDC_LUT_PARA_UPDATE (0x00C) +#define SPDC_OPERATE (0x010) +#define SPDC_PANEL_INIT_SET (0x014) +#define SPDC_TEMP_INFO (0x018) +#define SPDC_NEXT_BUF (0x01C) +#define SPDC_CURRENT_BUF (0x020) +#define SPDC_PRE_BUF (0x024) +#define SPDC_CNT_BUF (0x028) +#define SPDC_LUT_BUF (0x02C) +#define SPDC_INT_ENABLE (0x030) +#define SPDC_INT_STA_CLR (0x034) +#define SPDC_INIT_STA_CLR (0x038) +#define SPDC_STATUS (0x03C) +#define SPDC_DISP_VER (0x040) +#define SPDC_TCON_VER (0x044) +#define SPDC_SW_GATE_CLK (0x048) + +/* + * Register field definitions + */ +enum { + SPDC_DISP_TRIGGER_ENABLE = 0x1, + SPDC_DISP_TRIGGER_FLASH = 0x10, + + /*SPDC clock gate*/ + SPDC_SW_GATE_CLK_ENABLE = 0x1, + + /* waveform mode mask */ + SPDC_WAV_MODE_MASK = (0x7 << 1), + + /* SPDC interrupt IRQ mask define */ + SPDC_IRQ_FRAME_UPDATE = (0x1 << 0), + SPDC_IRQ_TCON_INIT = (0x1 << 1), + SPDC_IRQ_LUT_DOWNLOAD = (0x1 << 2), + SPDC_IRQ_ERR = (0x1 << 3), + SPDC_IRQ_ALL_MASK = 0xF, + + /* SPDC interrupt status */ + SPDC_IRQ_STA_FRAME_UPDATE = (0x1 << 0), + SPDC_IRQ_STA_TCON_INIT = (0x1 << 1), + SPDC_IRQ_STA_LUT_DOWNLOAD = (0x1 << 2), + SPDC_IRQ_STA_ERR = (0x1 << 3), + SPDC_IRQ_STA_ALL_MASK = 0xF, + + /* SPDC update coordinate angle */ + SPDC_UPDATE_W_H_MAX_SIZE = ((0x1 << 12) - 1), + SPDC_UPDATE_X_Y_MAX_SIZE = ((0x1 << 12) - 1), + + /* SPDC TCON status */ + SPDC_PANEL_STAUTS_BUSY = 0x1, + SPDC_TCON_STATUS_IDLE = (0x4 << 4), + + /* SPDC EPD Operation mode */ + SPDC_NO_OPERATION = 0, + SPDC_DISP_REFRESH = 1, + SPDC_DEEP_REFRESH = 0x2, + SPDC_DISP_RESET = 0x4, + SPDC_SW_TCON_RESET = 0x5, + SPDC_SW_TCON_RESET_SET = 0x80000000, + SPDC_FULL_REFRESH = 0x6, + + /* SPDC Concurrency mechanism: ACC */ + SPDC_LUT_MODE_OFFSET = 0xb3, + SPDC_LUT_ACC_MODE = 0x4, + + /* SPDC waveform */ + SPDC_WAVEFORM_LUT_OFFSET_ADDR = 0x7600, + SPDC_LUT_PARA_LENTH = 0x100, + SPDC_LUT_FROM_MEM = 1, + SPDC_LUT_TO_MEM = 0, + + /* SPDC submit update status */ + SPDC_CONCUR_UPD = 0x4, + SPDC_QUEUE_UPD = 0x8, + SPDC_CONCUR_QUEUE = 0xc, +}; + +#define SPDC_DRIVER_NAME "imx_spdc_fb" + +/** + * SPDC EPD waveform display trigger mode + */ +enum { + SPDC_WAV_MODE_0 = 0, + SPDC_WAV_MODE_1, + SPDC_WAV_MODE_2, + SPDC_WAV_MODE_3, + SPDC_WAV_MODE_4, + SPDC_WAV_MODE_5, + SPDC_WAV_MODE_DEFAULT = SPDC_WAV_MODE_0, +}; + +/** + * SPDC controller ip version + */ +struct mxc_epd_disp_version { + u8 epd_type; + u8 lut_ver; + u16 product_id; +}; + +struct mxc_spdc_version { + struct mxc_epd_disp_version disp_ver; + u8 tcon_ver; +}; + +struct spdc_buffer_addr { + u32 next_buf_phys_addr; + u32 cur_buf_phys_addr; + u32 pre_buf_phys_addr; + u32 frm_cnt_buf_phys_addr; + u32 lut_buf_phys_addr; +}; + +struct partial_refresh_param { + struct spdc_buffer_addr buf_addr; + struct mxcfb_rect update_region; + int temper; + u32 blocking; + u32 wave_mode; + u32 stride; + u32 flash; /* only for waveform mode7 */ + u32 concur; /* Concurrency mechanism: ACC */ +}; + +/** + * SPDC lut data + */ +struct mxc_spdc_lut_para { + u8 lut_data[SPDC_LUT_PARA_LENTH]; + u8 lut_addr[SPDC_LUT_PARA_LENTH]; + bool lut_para_update_sta; +}; + +#define PORTRAIT "portrait" +#define LANDSCAPE "Landscape" +#define RESERVED "Reserved" +struct mxc_spdc_resolution_map_para { + u16 resolution; + u16 res_x; + u16 res_y; + char res_name[12]; +}; + +struct update_marker_data { + struct list_head full_list; + struct list_head upd_list; + u32 update_marker; + struct completion update_completion; + int lut_num; + bool collision_test; + bool waiting; +}; + +struct update_desc_list { + struct list_head list; + struct mxcfb_update_data upd_data; + u32 spdc_offs; + u32 spdc_stride; + struct list_head upd_marker_list; + u32 update_order; +}; + +/* This structure represents a list node containing both + * a memory region allocated as an output buffer for the PxP + * update processing task, and the update + * description (mode, region, etc.) + */ +struct update_data_list { + struct list_head list; + dma_addr_t phys_addr;/* Pointer to phys address of processed Y buf */ + void *virt_addr; + struct update_desc_list *update_desc; + int lut_num; + u64 collision_mask; /* SPDC cannot support collision detect, + * align with EPDC driver struct */ +}; + +typedef struct mxc_spdc_fb_param { + struct fb_info info; + struct fb_var_screeninfo spdc_fb_var; + + char fw_str[24]; + u32 pseudo_palette[16]; + struct mxc_spdc_version spdc_ver; + struct imx_spdc_fb_mode *cur_mode; + struct imx_spdc_fb_platform_data *pdata; + struct partial_refresh_param fresh_param; + int blank; + bool updates_active; + + u32 fb_offset; + u32 max_pix_size; + ssize_t map_size; + int native_width; + int native_height; + int default_bpp; + + dma_addr_t phys_start; + void *virt_start; + struct device *dev; + + int num_screens; + u32 order_cnt; + int max_num_updates; + u32 auto_mode; + u32 upd_scheme; + u32 operation_mode; + bool is_deep_fresh; + struct list_head full_marker_list; + struct list_head upd_pending_list; + struct list_head upd_buf_queue; + struct list_head upd_buf_free_list; + struct list_head upd_buf_preprocess_list; + u32 upd_preprocess_num; + int submit_upd_sta; + struct update_data_list *cur_update; + struct mutex queue_mutex; + struct imx_spdc_panel_init_set panel_set; + struct mxc_spdc_lut_para lut_para; + struct mxcfb_waveform_modes wv_modes; + + dma_addr_t phy_next_buf; + dma_addr_t phy_pre_buf; + dma_addr_t phy_current_buf; + dma_addr_t phy_cnt_buf; + dma_addr_t phy_lut_buf; + void *virt_next_buf; + void *virt_current_buf; + void *virt_pre_buf; + void *virt_cnt_buf; + void *virt_lut_buf; + u32 next_buf_size; + u32 current_buf_size; + u32 pre_buf_size; + u32 cnt_buf_size; + u32 lut_buf_size; + + dma_addr_t *phys_addr_updbuf; + void **virt_addr_updbuf; + u32 upd_buffer_num; + u32 max_num_buffers; + + /* copy the processed data to next buffer relative region */ + dma_addr_t phys_addr_copybuf; + void *virt_addr_copybuf; + + int spdc_irq; + char __iomem *hwp; + struct clk *spdc_clk_axi; + struct clk *spdc_clk_pix; + struct regulator *display_regulator; + struct regulator *vcom_regulator; + struct regulator *v3p3_regulator; + + spinlock_t lock; + int power_state; + bool powering_down; + int pwrdown_delay; + int wait_for_powerdown; + struct completion powerdown_compl; + struct mutex power_mutex; + bool fw_default_load; + bool hw_ready; + bool hw_initializing; + bool waiting_for_idle; + bool waiting_for_wb; + struct completion update_res_free; + struct completion lut_down; + struct completion init_finish; + struct completion update_finish; + struct completion updates_done; + struct delayed_work spdc_done_work; + struct workqueue_struct *spdc_submit_workqueue; + struct work_struct spdc_submit_work; + struct workqueue_struct *spdc_intr_workqueue; + struct work_struct spdc_intr_work; + + /* FB elements related to PxP DMA */ + struct completion pxp_tx_cmpl; + struct pxp_channel *pxp_chan; + struct pxp_config_data pxp_conf; + struct dma_async_tx_descriptor *txd; + dma_cookie_t cookie; + struct scatterlist sg[2]; + struct mutex pxp_mutex; /* protects access to PxP */ +} mxc_spdc_t; + +#endif diff --git a/drivers/video/mxc/mxcfb_seiko_wvga.c b/drivers/video/mxc/mxcfb_seiko_wvga.c index 0ba4d9ed064f..c96238d80cb2 100644 --- a/drivers/video/mxc/mxcfb_seiko_wvga.c +++ b/drivers/video/mxc/mxcfb_seiko_wvga.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -122,7 +122,7 @@ static struct notifier_block nb = { static int __devinit lcd_probe(struct platform_device *pdev) { int i; - struct mxc_lcd_platform_data *plat = pdev->dev.platform_data; + struct fsl_mxc_lcd_platform_data *plat = pdev->dev.platform_data; if (plat) { if (plat->reset) diff --git a/firmware/Makefile b/firmware/Makefile index 459d5b08473b..b1d024df873c 100644 --- a/firmware/Makefile +++ b/firmware/Makefile @@ -147,6 +147,7 @@ fw-shipped-$(CONFIG_SOC_IMX51) += imx/sdma/sdma-imx51-to3.bin fw-shipped-$(CONFIG_SOC_IMX53) += imx/sdma/sdma-imx53-to1.bin fw-shipped-$(CONFIG_SOC_IMX6Q) += imx/sdma/sdma-imx6q-to1.bin endif +fw-shipped-$(CONFIG_FB_MXC_SIPIX_PANEL) += imx/spdc_pvi.fw fw-shipped-$(CONFIG_FB_MXC_EINK_PANEL) += imx/epdc_E60_V110.fw \ imx/epdc_E60_V220.fw \ imx/epdc_E97_V110.fw \ diff --git a/firmware/imx/spdc_pvi.fw.ihex b/firmware/imx/spdc_pvi.fw.ihex new file mode 100644 index 000000000000..c0c1407d9736 --- /dev/null +++ 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+:1035E0004040404540656A6A6A6A6A6A6A6A6A6A0D +:1035F0004040808A8085A0A5AAAAAAAAAAAAAAAAA7 +:103600004040808A808A80A5A5AAAAAAAAAAAAAAB6 +:1036100040404040404A404A6560656A6A6A6A6A5A +:10362000404040808080808A8AA0A5A0AAAAAAAA39 +:1036300040404040808080A08A80AAA0A0AAAAAA78 +:10364000404040404040404060404A60606A6A6A92 +:10365000404040404080808080A0A0A0A0A0AAAAB6 +:10366000000000000000000000000000000000005A +:10367000000000000000000000000000000000004A +:10368000000000000000000000000000000000003A +:10369000000000000000000000000000000000002A +:1036A000000000000000000000000000000000001A +:1036B000000000000000000000000000000000000A +:1036C00000000000000000000000000000000000FA +:1036D00000000000000000000000000000000000EA +:1036E00000000000000000000000000000000000DA +:1036F00000000000000000000000000000000000CA +:00000001FF diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h index bec8fe9cd838..5437d3a4719e 100644 --- a/include/linux/fsl_devices.h +++ b/include/linux/fsl_devices.h @@ -238,6 +238,13 @@ struct fsl_mxc_ldb_platform_data { int sec_disp_id; }; +struct mxc_fb_platform_data { + struct fb_videomode *mode; + int num_modes; + char *mode_str; + u32 interface_pix_fmt; +}; + struct fsl_mxc_lcd_platform_data { char *io_reg; char *core_reg; @@ -280,12 +287,21 @@ struct fsl_mxc_hdmi_core_platform_data { int disp_id; }; +struct fsl_mxc_capture_platform_data { + int csi; + int ipu; + u8 mclk_source; + u8 is_mipi; +}; + + struct fsl_mxc_camera_platform_data { char *core_regulator; char *io_regulator; char *analog_regulator; char *gpo_regulator; u32 mclk; + u8 mclk_source; u32 csi; void (*pwdn)(int pwdn); void (*io_init)(void); diff --git a/include/linux/mxcfb.h b/include/linux/mxcfb.h index 5fb07b44063d..60e0aa09d0b8 100644 --- a/include/linux/mxcfb.h +++ b/include/linux/mxcfb.h @@ -69,6 +69,8 @@ struct mxcfb_rect { #define GRAYSCALE_8BIT 0x1 #define GRAYSCALE_8BIT_INVERTED 0x2 +#define GRAYSCALE_4BIT 0x3 +#define GRAYSCALE_4BIT_INVERTED 0x4 #define AUTO_UPDATE_MODE_REGION_MODE 0 #define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1 diff --git a/include/linux/mxcfb_epdc_kernel.h b/include/linux/mxcfb_epdc_kernel.h index 017202f8a861..06fea6fbb459 100644 --- a/include/linux/mxcfb_epdc_kernel.h +++ b/include/linux/mxcfb_epdc_kernel.h @@ -33,4 +33,17 @@ int mxc_epdc_fb_set_pwrdown_delay(u32 pwrdown_delay, int mxc_epdc_get_pwrdown_delay(struct fb_info *info); int mxc_epdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info); +void mxc_spdc_fb_set_waveform_modes(struct mxcfb_waveform_modes *modes, + struct fb_info *info); +int mxc_spdc_fb_set_temperature(int temperature, struct fb_info *info); +int mxc_spdc_fb_set_auto_update(u32 auto_mode, struct fb_info *info); +int mxc_spdc_fb_send_update(struct mxcfb_update_data *upd_data, + struct fb_info *info); +int mxc_spdc_fb_wait_update_complete( + struct mxcfb_update_marker_data *marker_data, + struct fb_info *info); +int mxc_spdc_fb_set_pwrdown_delay(u32 pwrdown_delay, + struct fb_info *info); +int mxc_spdc_get_pwrdown_delay(struct fb_info *info); +int mxc_spdc_fb_set_upd_scheme(u32 upd_scheme, struct fb_info *info); #endif diff --git a/include/linux/power/max8903_battery.h b/include/linux/power/max8903_battery.h new file mode 100755 index 000000000000..b28287053986 --- /dev/null +++ b/include/linux/power/max8903_battery.h @@ -0,0 +1,62 @@ +/* + * max8903_battery.h - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * Based on max8903_charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MAX8903_BATTERY_H__ +#define __MAX8903_BATTERY_H__ + +struct max8903_pdata { + /* + * GPIOs + * cen, chg, flt, and usus are optional. + * dok, dcm, and uok are not optional depending on the status of + * dc_valid and usb_valid. + */ + int cen; /* Charger Enable input */ + int dok; /* DC(Adapter) Power OK output */ + int uok; /* USB Power OK output */ + int chg; /* Charger status output */ + int flt; /* Fault output */ + int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */ + int usus; /* USB Suspend Input (1: suspended) */ + + /* DCM wired to Logic High + Set this true when DCM pin connect to Logic high.*/ + bool dcm_always_high; + + /* + * DC(Adapter/TA) is wired + * When dc_valid is true, + * dok and dcm should be valid. + * + * At least one of dc_valid or usb_valid should be true. + */ + bool dc_valid; + /* + * USB is wired + * When usb_valid is true, + * uok should be valid. + */ + bool usb_valid; +}; + +#endif /* __MAX8903_BATTERY_H__ */ diff --git a/include/linux/power/sabresd_battery.h b/include/linux/power/sabresd_battery.h new file mode 100644 index 000000000000..c251a748a0db --- /dev/null +++ b/include/linux/power/sabresd_battery.h @@ -0,0 +1,62 @@ +/* + * sabresd_battery.h - Maxim 8903 USB/Adapter Charger Driver + * + * Copyright (C) 2011 Samsung Electronics + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * Based on max8903_charger.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MAX8903_SABRESD_H__ +#define __MAX8903_SABRESD_H__ + +struct max8903_pdata { + /* + * GPIOs + * cen, chg, flt, and usus are optional. + * dok, dcm, and uok are not optional depending on the status of + * dc_valid and usb_valid. + */ + int cen; /* Charger Enable input */ + int dok; /* DC(Adapter) Power OK output */ + int uok; /* USB Power OK output */ + int chg; /* Charger status output */ + int flt; /* Fault output */ + int dcm; /* Current-Limit Mode input (1: DC, 2: USB) */ + int usus; /* USB Suspend Input (1: suspended) */ + + /* DCM wired to Logic High + Set this true when DCM pin connect to Logic high.*/ + bool dcm_always_high; + + /* + * DC(Adapter/TA) is wired + * When dc_valid is true, + * dok and dcm should be valid. + * + * At least one of dc_valid or usb_valid should be true. + */ + bool dc_valid; + /* + * USB is wired + * When usb_valid is true, + * uok should be valid. + */ + bool usb_valid; +}; + +#endif /* __SABRESD_BATTERY_H__ */ diff --git a/include/linux/pxp_dma.h b/include/linux/pxp_dma.h index bf63bf3570e5..1be6e395ec55 100644 --- a/include/linux/pxp_dma.h +++ b/include/linux/pxp_dma.h @@ -66,6 +66,7 @@ typedef unsigned char bool; /*! @name YUV Planar Formats */ /*! @{ */ #define PXP_PIX_FMT_GREY fourcc('G', 'R', 'E', 'Y') /*!< 8 Greyscale */ +#define PXP_PIX_FMT_GY04 fourcc('G', 'Y', '0', '4') /*!< 4 Greyscale */ #define PXP_PIX_FMT_YVU410P fourcc('Y', 'V', 'U', '9') /*!< 9 YVU 4:1:0 */ #define PXP_PIX_FMT_YUV410P fourcc('Y', 'U', 'V', '9') /*!< 9 YUV 4:1:0 */ #define PXP_PIX_FMT_YVU420P fourcc('Y', 'V', '1', '2') /*!< 12 YVU 4:2:0 */ diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 99d3806e7535..af1c3a9444ca 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -221,6 +221,9 @@ config SND_SOC_SN95031 config SND_SOC_CS42888 tristate +config SND_SOC_SI4763 + tristate + config SND_SOC_SPDIF tristate diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index 8efb5130dc1f..e08ff304aa9d 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -27,6 +27,7 @@ snd-soc-max9850-objs := max9850.o snd-soc-pcm3008-objs := pcm3008.o snd-soc-sgtl5000-objs := sgtl5000.o snd-soc-cs42888-objs := cs42888.o +snd-soc-si4763-objs := si4763.o snd-soc-alc5623-objs := alc5623.o snd-soc-sn95031-objs := sn95031.o snd-soc-spdif-objs := spdif_transciever.o @@ -123,6 +124,7 @@ obj-$(CONFIG_SND_SOC_MAX98095) += snd-soc-max98095.o obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o +obj-$(CONFIG_SND_SOC_SI4763) += snd-soc-si4763.o obj-$(CONFIG_SND_SOC_SN95031) +=snd-soc-sn95031.o obj-$(CONFIG_SND_SOC_SPDIF) += snd-soc-spdif.o obj-$(CONFIG_SND_SOC_SSM2602) += snd-soc-ssm2602.o diff --git a/sound/soc/codecs/cs42888.c b/sound/soc/codecs/cs42888.c index 63d244a8d00a..97a8fc85db11 100644 --- a/sound/soc/codecs/cs42888.c +++ b/sound/soc/codecs/cs42888.c @@ -743,12 +743,13 @@ static void cs42888_shutdown(struct snd_pcm_substream *substream, u8 val; /* Mute all the channels */ - val = snd_soc_read(codec, CS42888_MUTE); - - val |= CS42888_MUTE_ALL; - ret = snd_soc_write(codec, CS42888_MUTE, val); - if (ret < 0) - pr_err("i2c write failed\n"); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + val = snd_soc_read(codec, CS42888_MUTE); + val |= CS42888_MUTE_ALL; + ret = snd_soc_write(codec, CS42888_MUTE, val); + if (ret < 0) + pr_err("i2c write failed\n"); + } } diff --git a/sound/soc/codecs/mxc_hdmi.c b/sound/soc/codecs/mxc_hdmi.c index 62decb89d876..834d785b2c27 100644 --- a/sound/soc/codecs/mxc_hdmi.c +++ b/sound/soc/codecs/mxc_hdmi.c @@ -2,6 +2,12 @@ * MXC HDMI ALSA Soc Codec Driver * * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. + * + * Some code from patch_hdmi.c + * Copyright (c) 2008-2010 Intel Corporation. All rights reserved. + * Copyright (c) 2006 ATI Technologies Inc. + * Copyright (c) 2008 NVIDIA Corp. All rights reserved. + * Copyright (c) 2008 Wei Ni <wni@nvidia.com> */ /* @@ -88,6 +94,185 @@ static void dumpregs(void) static void dumpregs(void) {} #endif +enum cea_speaker_placement { + FL = (1 << 0), /* Front Left */ + FC = (1 << 1), /* Front Center */ + FR = (1 << 2), /* Front Right */ + FLC = (1 << 3), /* Front Left Center */ + FRC = (1 << 4), /* Front Right Center */ + RL = (1 << 5), /* Rear Left */ + RC = (1 << 6), /* Rear Center */ + RR = (1 << 7), /* Rear Right */ + RLC = (1 << 8), /* Rear Left Center */ + RRC = (1 << 9), /* Rear Right Center */ + LFE = (1 << 10), /* Low Frequency Effect */ + FLW = (1 << 11), /* Front Left Wide */ + FRW = (1 << 12), /* Front Right Wide */ + FLH = (1 << 13), /* Front Left High */ + FCH = (1 << 14), /* Front Center High */ + FRH = (1 << 15), /* Front Right High */ + TC = (1 << 16), /* Top Center */ +}; + +/* + * EDID SA bits in the CEA Speaker Allocation data block + */ +static int edid_speaker_allocation_bits[] = { + [0] = FL | FR, + [1] = LFE, + [2] = FC, + [3] = RL | RR, + [4] = RC, + [5] = FLC | FRC, + [6] = RLC | RRC, + [7] = FLW | FRW, + [8] = FLH | FRH, + [9] = TC, + [10] = FCH, +}; + +struct cea_channel_speaker_allocation { + int ca_index; + int speakers[8]; + + /* derived values, just for convenience */ + int channels; + int spk_mask; +}; + +/* + * This is an ordered list! + * + * The preceding ones have better chances to be selected by + * hdmi_channel_allocation(). + */ +static struct cea_channel_speaker_allocation channel_allocations[] = { +/* channel: 7 6 5 4 3 2 1 0 */ +{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } }, + /* 2.1 */ +{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } }, + /* Dolby Surround */ +{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } }, + /* surround40 */ +{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } }, + /* surround41 */ +{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } }, + /* surround50 */ +{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } }, + /* surround51 */ +{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } }, + /* 6.1 */ +{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } }, + /* surround71 */ +{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } }, + +{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } }, +{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } }, +{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } }, +{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } }, +{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } }, +{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } }, +{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } }, +{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } }, +{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } }, +{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } }, +{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } }, +{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } }, +{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } }, +{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } }, +{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } }, +{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } }, +{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } }, +{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } }, +}; + +/* + * Compute derived values in channel_allocations[]. + */ +static void init_channel_allocations(void) +{ + int i, j; + struct cea_channel_speaker_allocation *p; + + for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { + p = channel_allocations + i; + p->channels = 0; + p->spk_mask = 0; + for (j = 0; j < ARRAY_SIZE(p->speakers); j++) + if (p->speakers[j]) { + p->channels++; + p->spk_mask |= p->speakers[j]; + } + } +} + +/* + * The transformation takes two steps: + * + * speaker_alloc => (edid_speaker_allocation_bits[]) => spk_mask + * spk_mask => (channel_allocations[]) => CA + * + * TODO: it could select the wrong CA from multiple candidates. +*/ +static int hdmi_channel_allocation(int channels) +{ + int i; + int ca = 0; + int spk_mask = 0; + + /* + * CA defaults to 0 for basic stereo audio + */ + if (channels <= 2) + return 0; + + /* + * expand EDID's speaker allocation mask + * + * EDID tells the speaker mask in a compact(paired) form, + * expand EDID's notions to match the ones used by Audio InfoFrame. + */ + for (i = 0; i < ARRAY_SIZE(edid_speaker_allocation_bits); i++) { + if (edid_cfg.speaker_alloc & (1 << i)) + spk_mask |= edid_speaker_allocation_bits[i]; + } + + /* search for the first working match in the CA table */ + for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) { + if (channels == channel_allocations[i].channels && + (spk_mask & channel_allocations[i].spk_mask) == + channel_allocations[i].spk_mask) { + ca = channel_allocations[i].ca_index; + break; + } + } + + return ca; +} + static void hdmi_set_audio_flat(u8 value) { /* Indicates the subpacket represents a flatline sample */ @@ -103,12 +288,25 @@ static void hdmi_set_layout(unsigned int channels) HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK); } -static void hdmi_set_audio_infoframe(void) +static void hdmi_set_audio_infoframe(unsigned int channels) { - /* set to 0: means "refer to stream header" */ - hdmi_writeb(0x00, HDMI_FC_AUDICONF0); - hdmi_writeb(0x00, HDMI_FC_AUDICONF1); - hdmi_writeb(0x00, HDMI_FC_AUDICONF2); + unsigned char audiconf0, audiconf2; + + /* From CEA-861-D spec: + * NOTE: HDMI requires the CT, SS and SF fields to be set to 0 ("Refer + * to Stream Header") as these items are carried in the audio stream. + * + * So we only set the CC and CA fields. + */ + audiconf0 = ((channels - 1) << HDMI_FC_AUDICONF0_CC_OFFSET) & + HDMI_FC_AUDICONF0_CC_MASK; + + audiconf2 = hdmi_channel_allocation(channels); + + hdmi_writeb(audiconf0, HDMI_FC_AUDICONF0); + hdmi_writeb(0, HDMI_FC_AUDICONF1); + hdmi_writeb(audiconf2, HDMI_FC_AUDICONF2); + hdmi_writeb(0, HDMI_FC_AUDICONF3); } static int cea_audio_rates[HDMI_MAX_RATES] = { @@ -242,7 +440,6 @@ static int mxc_hdmi_codec_startup(struct snd_pcm_substream *substream, return ret; hdmi_set_audio_flat(0); - hdmi_set_audio_infoframe(); return 0; } @@ -252,6 +449,7 @@ static int mxc_hdmi_codec_prepare(struct snd_pcm_substream *substream, { struct snd_pcm_runtime *runtime = substream->runtime; + hdmi_set_audio_infoframe(runtime->channels); hdmi_set_layout(runtime->channels); hdmi_set_sample_rate(runtime->rate); dumpregs(); @@ -371,6 +569,8 @@ static int mxc_hdmi_codec_soc_probe(struct snd_soc_codec *codec) if (ret) goto e_add_ctrls; + init_channel_allocations(); + snd_soc_codec_set_drvdata(codec, hdmi_priv); return 0; diff --git a/sound/soc/codecs/mxc_spdif.c b/sound/soc/codecs/mxc_spdif.c index 2bcb4d68274b..0c93621201d6 100644 --- a/sound/soc/codecs/mxc_spdif.c +++ b/sound/soc/codecs/mxc_spdif.c @@ -81,10 +81,13 @@ struct spdif_mixer_control mxc_spdif_control; static unsigned long spdif_base_addr; #if MXC_SPDIF_DEBUG -static void dumpregs(void) +static void dumpregs(struct mxc_spdif_priv *priv) { unsigned int value, i; + if (!priv->tx_active || !priv->rx_active) + clk_enable(priv->plat_data->spdif_core_clk); + for (i = 0 ; i <= 0x38 ; i += 4) { value = readl(spdif_base_addr + i) & 0xffffff; pr_debug("reg 0x%02x = 0x%06x\n", i, value); @@ -97,9 +100,12 @@ static void dumpregs(void) i = 0x50; value = readl(spdif_base_addr + i) & 0xffffff; pr_debug("reg 0x%02x = 0x%06x\n", i, value); + + if (!priv->tx_active || !priv->rx_active) + clk_disable(priv->plat_data->spdif_core_clk); } #else -static void dumpregs(void) {} +static void dumpregs(struct mxc_spdif_priv *priv) {} #endif /* define each spdif interrupt handlers */ @@ -299,7 +305,13 @@ static void spdif_irq_bit_error(unsigned int bit, void *devid) */ static void spdif_irq_sym_error(unsigned int bit, void *devid) { + struct mxc_spdif_priv *spdif_priv = (struct mxc_spdif_priv *)devid; + pr_debug("SPDIF interrupt symbol error\n"); + if (!atomic_read(&spdif_priv->dpll_locked)) { + /* dpll unlocked seems no audio stream */ + spdif_intr_enable(INT_SYM_ERR, 0); + } } /* @@ -517,14 +529,15 @@ static int mxc_spdif_playback_startup(struct snd_pcm_substream *substream, struct snd_pcm_runtime *runtime = substream->runtime; struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; - int err; + int err = 0; if (!plat_data->spdif_tx) return -EINVAL; spdif_priv->tx_active = true; - clk_enable(plat_data->spdif_clk); - clk_enable(plat_data->spdif_audio_clk); + err = clk_enable(plat_data->spdif_clk); + if (err < 0) + goto failed_clk; err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, @@ -537,14 +550,15 @@ static int mxc_spdif_playback_startup(struct snd_pcm_substream *substream, goto failed; return 0; + failed: - clk_disable(plat_data->spdif_audio_clk); clk_disable(plat_data->spdif_clk); +failed_clk: spdif_priv->tx_active = false; return err; } -static int mxc_spdif_playback_prepare(struct snd_pcm_substream *substream, +static int mxc_spdif_playback_start(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; @@ -586,11 +600,11 @@ static int mxc_spdif_playback_prepare(struct snd_pcm_substream *substream, regval |= SCR_DMA_TX_EN; __raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr); - dumpregs(); + dumpregs(spdif_priv); return 0; } -static int mxc_spdif_playback_shutdown(struct snd_pcm_substream *substream, +static int mxc_spdif_playback_stop(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; @@ -601,7 +615,7 @@ static int mxc_spdif_playback_shutdown(struct snd_pcm_substream *substream, if (!plat_data->spdif_tx) return -EINVAL; - dumpregs(); + dumpregs(spdif_priv); pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS)); spdif_intr_status(); @@ -619,13 +633,41 @@ static int mxc_spdif_playback_shutdown(struct snd_pcm_substream *substream, regval |= SCR_LOW_POWER; __raw_writel(regval, SPDIF_REG_SCR + spdif_base_addr); - clk_disable(plat_data->spdif_audio_clk); clk_disable(plat_data->spdif_clk); spdif_priv->tx_active = false; return 0; } +static int mxc_spdif_playback_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); + struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; + int ret = 0; + + if (!plat_data->spdif_tx) + return -EINVAL; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + ret = mxc_spdif_playback_start(substream, dai); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + ret = mxc_spdif_playback_stop(substream, dai); + break; + default: + return -EINVAL; + } + + return ret; +} + static int mxc_spdif_capture_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { @@ -641,7 +683,9 @@ static int mxc_spdif_capture_startup(struct snd_pcm_substream *substream, spdif_priv->rx_active = true; /* enable rx bus clock */ - clk_enable(plat_data->spdif_clk); + err = clk_enable(plat_data->spdif_clk); + if (err < 0) + goto failed_clk; /* set hw param constraints */ err = snd_pcm_hw_constraint_list(runtime, 0, @@ -655,18 +699,16 @@ static int mxc_spdif_capture_startup(struct snd_pcm_substream *substream, if (err < 0) goto failed; - /* enable spdif dpll lock interrupt */ - spdif_intr_enable(INT_DPLL_LOCKED, 1); - return 0; failed: clk_disable(plat_data->spdif_clk); +failed_clk: spdif_priv->rx_active = false; return err; } -static int mxc_spdif_capture_prepare(struct snd_pcm_substream *substream, +static int mxc_spdif_capture_start(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; @@ -674,7 +716,7 @@ static int mxc_spdif_capture_prepare(struct snd_pcm_substream *substream, struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; unsigned long regval; - if (!plat_data->spdif_rx) + if (!plat_data->spdif_rx || !spdif_priv->rx_active) return -EINVAL; regval = __raw_readl(spdif_base_addr + SPDIF_REG_SCR); @@ -693,7 +735,7 @@ static int mxc_spdif_capture_prepare(struct snd_pcm_substream *substream, spdif_intr_enable(INT_SYM_ERR | INT_BIT_ERR | INT_URX_FUL | INT_URX_OV | INT_QRX_FUL | INT_QRX_OV | INT_UQ_SYNC | INT_UQ_ERR | INT_RX_RESYNC | - INT_LOSS_LOCK, 1); + INT_LOSS_LOCK | INT_DPLL_LOCKED, 1); /* setup rx clock source */ spdif_set_rx_clksrc(plat_data->spdif_rx_clk, SPDIF_DEFAULT_GAINSEL, 1); @@ -711,7 +753,7 @@ static int mxc_spdif_capture_prepare(struct snd_pcm_substream *substream, return 0; } -static int mxc_spdif_capture_shutdown(struct snd_pcm_substream *substream, +static int mxc_spdif_capture_stop(struct snd_pcm_substream *substream, struct snd_soc_dai *dai) { struct snd_soc_codec *codec = dai->codec; @@ -719,7 +761,7 @@ static int mxc_spdif_capture_shutdown(struct snd_pcm_substream *substream, struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; unsigned long regval; - if (!plat_data->spdif_rx) + if (!plat_data->spdif_rx || !spdif_priv->rx_active) return -EINVAL; pr_debug("SIS: 0x%08x\n", __raw_readl(spdif_base_addr + SPDIF_REG_SIS)); @@ -747,6 +789,35 @@ static int mxc_spdif_capture_shutdown(struct snd_pcm_substream *substream, return 0; } +static int mxc_spdif_capture_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_codec *codec = dai->codec; + struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); + struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; + int ret = 0; + + if (!plat_data->spdif_rx) + return -EINVAL; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + ret = mxc_spdif_capture_start(substream, dai); + break; + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + ret = mxc_spdif_capture_stop(substream, dai); + break; + default: + return -EINVAL; + } + + return ret; +} + /* * MXC SPDIF IEC958 controller(mixer) functions * @@ -1058,7 +1129,16 @@ static int mxc_spdif_startup(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = dai->codec; struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; - int ret; + int ret = 0; + + /* enable spdif_xtal_clk */ + ret = clk_enable(plat_data->spdif_core_clk); + if (ret < 0) + goto failed_clk; + + spdif_softreset(); + /* disable all the interrupts */ + spdif_intr_enable(0xffffff, 0); /* enable spdif_xtal_clk */ clk_enable(plat_data->spdif_core_clk); @@ -1071,6 +1151,7 @@ static int mxc_spdif_startup(struct snd_pcm_substream *substream, else ret = mxc_spdif_capture_startup(substream, dai); +failed_clk: return ret; } @@ -1080,33 +1161,27 @@ static void mxc_spdif_shutdown(struct snd_pcm_substream *substream, struct snd_soc_codec *codec = dai->codec; struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); struct mxc_spdif_platform_data *plat_data = spdif_priv->plat_data; - int ret; - if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - ret = mxc_spdif_playback_shutdown(substream, dai); - else - ret = mxc_spdif_capture_shutdown(substream, dai); /* disable spdif_core clock */ - clk_put(plat_data->spdif_clk); clk_disable(plat_data->spdif_core_clk); } -static int mxc_spdif_prepare(struct snd_pcm_substream *substream, - struct snd_soc_dai *dai) +static int mxc_spdif_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) { - int ret; + int ret = 0; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) - ret = mxc_spdif_playback_prepare(substream, dai); + ret = mxc_spdif_playback_trigger(substream, cmd, dai); else - ret = mxc_spdif_capture_prepare(substream, dai); + ret = mxc_spdif_capture_trigger(substream, cmd, dai); return ret; } struct snd_soc_dai_ops mxc_spdif_codec_dai_ops = { .startup = mxc_spdif_startup, - .prepare = mxc_spdif_prepare, + .trigger = mxc_spdif_trigger, .shutdown = mxc_spdif_shutdown, }; @@ -1128,65 +1203,9 @@ static int mxc_spdif_soc_remove(struct snd_soc_codec *codec) return 0; } -#ifdef CONFIG_PM -static int mxc_spdif_soc_suspend(struct snd_soc_codec *codec, - pm_message_t state) -{ - struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); - struct mxc_spdif_platform_data *plat_data; - - if (codec == NULL) - return -EINVAL; - - plat_data = spdif_priv->plat_data; - - if (spdif_priv->tx_active) { - clk_disable(plat_data->spdif_audio_clk); - clk_disable(plat_data->spdif_clk); - } - - if (spdif_priv->rx_active) - clk_disable(plat_data->spdif_clk); - - clk_disable(plat_data->spdif_core_clk); - - return 0; -} - -static int mxc_spdif_soc_resume(struct snd_soc_codec *codec) -{ - struct mxc_spdif_priv *spdif_priv = snd_soc_codec_get_drvdata(codec); - struct mxc_spdif_platform_data *plat_data; - - if (codec == NULL) - return -EINVAL; - - plat_data = spdif_priv->plat_data; - - clk_enable(plat_data->spdif_core_clk); - - if (spdif_priv->tx_active) { - clk_enable(plat_data->spdif_clk); - clk_enable(plat_data->spdif_audio_clk); - } - - if (spdif_priv->rx_active) - clk_enable(plat_data->spdif_clk); - - spdif_softreset(); - - return 0; -} -#else -#define mxc_spdif_soc_suspend NULL -#define mxc_spdif_soc_resume NULL -#endif /* CONFIG_PM */ - struct snd_soc_codec_driver soc_codec_dev_spdif = { .probe = mxc_spdif_soc_probe, .remove = mxc_spdif_soc_remove, - .suspend = mxc_spdif_soc_suspend, - .resume = mxc_spdif_soc_resume, }; static int __devinit mxc_spdif_probe(struct platform_device *pdev) @@ -1283,13 +1302,12 @@ static int __devinit mxc_spdif_probe(struct platform_device *pdev) goto card_err; } - dumpregs(); + dumpregs(spdif_priv); return 0; card_err: clk_put(plat_data->spdif_clk); - clk_disable(plat_data->spdif_core_clk); failed_clk: platform_set_drvdata(pdev, NULL); kfree(spdif_priv); diff --git a/sound/soc/codecs/si4763.c b/sound/soc/codecs/si4763.c new file mode 100644 index 000000000000..b2c5dc9924ad --- /dev/null +++ b/sound/soc/codecs/si4763.c @@ -0,0 +1,109 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/slab.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/platform_device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <sound/tlv.h> + +#define SI4763_RATES SNDRV_PCM_RATE_48000 + +#define SI4763_FORMATS SNDRV_PCM_FMTBIT_S16_LE + +static struct snd_soc_dai_driver si4763_codec_dai = { + .name = "si4763", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SI4763_RATES, + .formats = SI4763_FORMATS, + }, +}; + +static int mxc_si4763_codec_soc_probe(struct snd_soc_codec *codec) +{ + return 0; +} +static struct snd_soc_codec_driver soc_codec_dev_si4763 = { + .probe = mxc_si4763_codec_soc_probe, +}; + +static int si4763_probe(struct platform_device *pdev) +{ + int ret = 0; + dev_info(&pdev->dev, "SI4763 Audio codec\n"); + + ret = snd_soc_register_codec(&pdev->dev, &soc_codec_dev_si4763, + &si4763_codec_dai, 1); + if (ret) { + dev_err(&pdev->dev, "failed to register codec\n"); + return ret; + } + + return 0; + +} + +/* power down chip */ +static int si4763_remove(struct platform_device *pdev) +{ + return 0; +} + +static int si4763_suspend(struct platform_device *pdev, pm_message_t state) +{ + return 0; +} + +static int si4763_resume(struct platform_device *pdev) +{ + return 0; +} +struct platform_driver si4763_driver = { + .driver = { + .name = "si4763", + .owner = THIS_MODULE, + }, + .probe = si4763_probe, + .remove = si4763_remove, + .suspend = si4763_suspend, + .resume = si4763_resume, +}; + +static int __init si4763_codec_init(void) +{ + return platform_driver_register(&si4763_driver); +} + +static void __exit si4763_codec_exit(void) +{ + return platform_driver_unregister(&si4763_driver); +} + +module_init(si4763_codec_init); +module_exit(si4763_codec_exit); + +MODULE_DESCRIPTION("ASoC si4763 codec driver"); +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index ccf8883a7866..32481c6dc720 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -4097,6 +4097,16 @@ static int wm8962_probe(struct snd_soc_codec *codec) pdata->mic_cfg); } + /* set the default volume for headphpone and speaker */ + snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME, + WM8962_HPOUTL_VOL_MASK, 0x65); + snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME, + WM8962_HPOUTR_VOL_MASK, 0x65); + snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME, + WM8962_SPKOUTL_VOL_MASK, 0x72); + snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME, + WM8962_SPKOUTR_VOL_MASK, 0x72); + /* Latch volume update bits */ snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME, WM8962_IN_VU, WM8962_IN_VU); diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig index b9f08b52bd1d..72d85503d495 100644 --- a/sound/soc/imx/Kconfig +++ b/sound/soc/imx/Kconfig @@ -86,6 +86,14 @@ config SND_SOC_IMX_CS42888 Say Y if you want to add support for SoC audio on an i.MX board with a cs42888 codec +config SND_SOC_IMX_SI4763 + tristate "SoC Audio support for IMX SI4763" + select SND_MXC_SOC_SSI + select SND_SOC_SI4763 + help + Say Y if you want to add support for Soc audio for the AMFM Tuner chip + SI4763 module. + config SND_SOC_EUKREA_TLV320 tristate "Eukrea TLV320" depends on MACH_EUKREA_MBIMX27_BASEBOARD \ diff --git a/sound/soc/imx/Makefile b/sound/soc/imx/Makefile index 2a67c3250355..3c851809e26d 100644 --- a/sound/soc/imx/Makefile +++ b/sound/soc/imx/Makefile @@ -31,5 +31,6 @@ obj-$(CONFIG_SND_SOC_IMX_SGTL5000) += snd-soc-imx-sgtl5000.o obj-$(CONFIG_SND_SOC_IMX_CS42888) += snd-soc-imx-cs42888.o obj-$(CONFIG_SND_SOC_IMX_SPDIF) += snd-soc-imx-spdif.o obj-$(CONFIG_SND_SOC_IMX_HDMI) += snd-soc-imx-hdmi.o +obj-$(CONFIG_SND_SOC_IMX_SI4763) += snd-soc-imx-si4763.o AFLAGS_hdmi_pcm.o := -march=armv7-a -mtune=cortex-a8 -mfpu=neon -mfloat-abi=softfp diff --git a/sound/soc/imx/imx-si4763.c b/sound/soc/imx/imx-si4763.c new file mode 100644 index 000000000000..3bf7f0340ea9 --- /dev/null +++ b/sound/soc/imx/imx-si4763.c @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/device.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/fsl_devices.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/soc-dai.h> +#include <sound/soc-dapm.h> +#include <sound/initval.h> +#include <mach/audmux.h> +#include <mach/ssi.h> + +#include "imx-ssi.h" + +static struct imx_si4763_priv { + int sysclk; + int hw; + int active; + struct platform_device *pdev; +} card_priv; + +static int imx_audmux_config(int slave, int master) +{ + unsigned int ptcr, pdcr; + slave = slave - 1; + master = master - 1; + + ptcr = MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(slave) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_TCSEL(slave); + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(slave); + mxc_audmux_v2_configure_port(master, ptcr, pdcr); + + ptcr = MXC_AUDMUX_V2_PTCR_SYN; + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); + mxc_audmux_v2_configure_port(slave, ptcr, pdcr); + + return 0; +} + + +static int imx_3stack_si4763_startup(struct snd_pcm_substream *substream) +{ + struct imx_si4763_priv *priv = &card_priv; + + priv->active++; + return 0; +} + +static int imx_3stack_si4763_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + unsigned int channels = params_channels(params); + struct imx_ssi *ssi_mode = snd_soc_dai_get_drvdata(cpu_dai); + int ret = 0; + u32 dai_format; + dai_format = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS; + + ssi_mode->flags |= IMX_SSI_SYN; + + /* set i.MX active slot mask */ + snd_soc_dai_set_tdm_slot(cpu_dai, + channels == 1 ? 0xfffffffe : 0xfffffffc, + channels == 1 ? 0xfffffffe : 0xfffffffc, + 2, 32); + + /* set cpu DAI configuration */ + ret = snd_soc_dai_set_fmt(cpu_dai, dai_format); + if (ret < 0) + return ret; + + /* set the SSI system clock as input (unused) */ + snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, SND_SOC_CLOCK_IN); + + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PM, 9); + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_2, 1); + snd_soc_dai_set_clkdiv(cpu_dai, IMX_SSI_TX_DIV_PSR, 0); + return 0; +} + +static void imx_3stack_si4763_shutdown(struct snd_pcm_substream *substream) +{ + struct imx_si4763_priv *priv = &card_priv; + priv->active--; +} + +/* + * imx_3stack bt DAI opserations. + */ +static struct snd_soc_ops imx_3stack_si4763_ops = { + .startup = imx_3stack_si4763_startup, + .hw_params = imx_3stack_si4763_hw_params, + .shutdown = imx_3stack_si4763_shutdown, +}; + +static struct snd_soc_dai_link imx_3stack_dai = { + .name = "imx-si4763", + .stream_name = "imx-si4763", + .codec_dai_name = "si4763", + .codec_name = "si4763.0", + .cpu_dai_name = "imx-ssi.1", + .platform_name = "imx-pcm-audio.1", + .ops = &imx_3stack_si4763_ops, +}; + +static struct snd_soc_card snd_soc_card_imx_3stack = { + .name = "imx-audio-si4763", + .dai_link = &imx_3stack_dai, + .num_links = 1, +}; + +static int __init imx_3stack_si4763_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + card_priv.pdev = pdev; + card_priv.sysclk = plat->sysclk; + imx_audmux_config(plat->src_port, plat->ext_port); + + return 0; + +} + +static int __devexit imx_3stack_si4763_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver imx_3stack_si4763_driver = { + .probe = imx_3stack_si4763_probe, + .remove = __devexit_p(imx_3stack_si4763_remove), + .driver = { + .name = "imx-tuner-si4763", + .owner = THIS_MODULE, + }, +}; + +static struct platform_device *imx_3stack_snd_device; + +static int __init imx_3stack_asoc_init(void) +{ + int ret; + ret = platform_driver_register(&imx_3stack_si4763_driver); + if (ret < 0) + goto exit; + + imx_3stack_snd_device = platform_device_alloc("soc-audio", 6); + if (!imx_3stack_snd_device) + goto err_device_alloc; + + platform_set_drvdata(imx_3stack_snd_device, &snd_soc_card_imx_3stack); + ret = platform_device_add(imx_3stack_snd_device); + if (0 == ret) + goto exit; + + + platform_device_put(imx_3stack_snd_device); +err_device_alloc: + platform_driver_unregister(&imx_3stack_si4763_driver); +exit: + return ret; +} + +static void __exit imx_3stack_asoc_exit(void) +{ + platform_driver_unregister(&imx_3stack_si4763_driver); + platform_device_unregister(imx_3stack_snd_device); +} + +module_init(imx_3stack_asoc_init); +module_exit(imx_3stack_asoc_exit); + +/* Module information */ +MODULE_AUTHOR("Freescale Semiconductor, Inc."); +MODULE_DESCRIPTION("ALSA SoC si4763 imx"); +MODULE_LICENSE("GPL"); diff --git a/sound/soc/imx/imx-si4763.h b/sound/soc/imx/imx-si4763.h new file mode 100644 index 000000000000..8a641a6adcaa --- /dev/null +++ b/sound/soc/imx/imx-si4763.h @@ -0,0 +1,19 @@ +/* + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef _MXC_SI4763PCM_H +#define _MXC_SI4763PCM_H + +extern struct snd_soc_dai si4763_dai; +extern struct snd_soc_codec_device soc_codec_dev_si4763; +#endif diff --git a/sound/soc/imx/imx-wm8962.c b/sound/soc/imx/imx-wm8962.c index 9eff86a229c5..aa3122f6d765 100644 --- a/sound/soc/imx/imx-wm8962.c +++ b/sound/soc/imx/imx-wm8962.c @@ -38,6 +38,7 @@ #include <mach/clock.h> #include <mach/audmux.h> #include <mach/gpio.h> +#include <asm/mach-types.h> #include "imx-ssi.h" #include "../codecs/wm8962.h" @@ -55,16 +56,17 @@ struct imx_priv { unsigned int sample_format = SNDRV_PCM_FMTBIT_S16_LE; static struct imx_priv card_priv; static struct snd_soc_card snd_soc_card_imx; -struct clk *wm8962_mclk; static struct snd_soc_codec *gcodec; static int imx_hifi_startup(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct imx_priv *priv = &card_priv; + struct mxc_audio_platform_data *plat = priv->pdev->dev.platform_data; if (!codec_dai->active) - clk_enable(wm8962_mclk); + plat->clock_enable(1); return 0; } @@ -73,9 +75,11 @@ static void imx_hifi_shutdown(struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct imx_priv *priv = &card_priv; + struct mxc_audio_platform_data *plat = priv->pdev->dev.platform_data; if (!codec_dai->active) - clk_disable(wm8962_mclk); + plat->clock_enable(0); return; } @@ -165,7 +169,6 @@ static const struct snd_soc_dapm_route audio_map[] = { { "MICBIAS", NULL, "AMIC" }, { "IN3R", NULL, "MICBIAS" }, - { "DMIC", NULL, "MICBIAS" }, { "DMICDAT", NULL, "DMIC" }, @@ -259,7 +262,7 @@ static void amic_detect_handler(struct work_struct *work) if (priv->amic_status == 0) snprintf(buf, 32, "STATE=%d", 2); - else + else snprintf(buf, 32, "STATE=%d", 0); envp[0] = "NAME=amic"; @@ -366,7 +369,8 @@ static int imx_wm8962_init(struct snd_soc_pcm_runtime *rtd) snd_soc_dapm_nc_pin(&codec->dapm, "DMIC"); else snd_soc_dapm_enable_pin(&codec->dapm, "DMIC"); - } + } else if (!snd_soc_dapm_get_pin_status(&codec->dapm, "DMICDAT")) + snd_soc_dapm_nc_pin(&codec->dapm, "DMIC"); return 0; } @@ -427,12 +431,6 @@ static int __devinit imx_wm8962_probe(struct platform_device *pdev) struct imx_priv *priv = &card_priv; int ret = 0; - wm8962_mclk = clk_get(NULL, "clko_clk"); - if (IS_ERR(wm8962_mclk)) { - printk(KERN_ERR "can't get CLKO clock.\n"); - return PTR_ERR(wm8962_mclk); - } - priv->pdev = pdev; imx_audmux_config(plat->src_port, plat->ext_port); @@ -451,12 +449,11 @@ static int __devexit imx_wm8962_remove(struct platform_device *pdev) { struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + plat->clock_enable(0); + if (plat->finit) plat->finit(); - clk_disable(wm8962_mclk); - clk_put(wm8962_mclk); - return 0; } @@ -479,6 +476,11 @@ static int __init imx_asoc_init(void) if (ret < 0) goto exit; + if (machine_is_mx6q_sabresd()) + imx_dai[0].codec_name = "wm8962.0-001a"; + else if (machine_is_mx6sl_arm2()) + imx_dai[0].codec_name = "wm8962.1-001a"; + imx_snd_device = platform_device_alloc("soc-audio", 5); if (!imx_snd_device) goto err_device_alloc; |