diff options
| author | Andi Kleen <ak@suse.de> | 2006-10-22 00:59:04 +0000 |
|---|---|---|
| committer | Chris Wright <chrisw@sous-sol.org> | 2006-11-03 17:33:48 -0800 |
| commit | 5b44e45b5a7e3096b6665cabbe00463c1f33c676 (patch) | |
| tree | c64e0494537285f66d65e5ef71429b1bc8d47bcd | |
| parent | cea23cd94f286008d382ccee265ca417c9ce9a58 (diff) | |
[PATCH] x86-64: Fix C3 timer test
There was a typo in the C3 latency test to decide of the TSC
should be used or not. It used the C2 latency threshold, not the
C3 one. Fix that.
This should fix the time on various dual core laptops.
Acked-by: Len Brown <len.brown@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
| -rw-r--r-- | arch/x86_64/kernel/time.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c index 7a9b18224182..ffd1cb88fa75 100644 --- a/arch/x86_64/kernel/time.c +++ b/arch/x86_64/kernel/time.c @@ -960,7 +960,7 @@ __cpuinit int unsynchronized_tsc(void) if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) { #ifdef CONFIG_ACPI /* But TSC doesn't tick in C3 so don't use it there */ - if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 100) + if (acpi_fadt.length > 0 && acpi_fadt.plvl3_lat < 1000) return 1; #endif return 0; |