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authorDavid Dillow <dave@thedillows.org>2010-03-03 16:33:10 +0000
committerGreg Kroah-Hartman <gregkh@suse.de>2010-05-12 14:57:12 -0700
commit0c03e80e912e9332a8167b9172fd74d1323f3e9b (patch)
tree2d3e8d4528e2d53f93cc18b8deb023838194e809
parent150d8a1fe2e89b124bc5bc3628095b8db2435272 (diff)
r8169: use correct barrier between cacheable and non-cacheable memory
commit 4c020a961a812ffae9846b917304cea504c3a733 upstream. r8169 needs certain writes to be visible to other CPUs or the NIC before touching the hardware, but was using smp_wmb() which is only required to order cacheable memory access. Switch to wmb() which is required to order both cacheable and non-cacheable memory. Noticed by Catalin Marinas and Paul Mackerras. Signed-off-by: David Dillow <dave@thedillows.org> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/net/r8169.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index ab753234e35a..9d3dd3ce8e9c 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -4316,7 +4316,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
tp->cur_tx += frags + 1;
- smp_wmb();
+ wmb();
RTL_W8(TxPoll, NPQ); /* set polling bit */
@@ -4676,7 +4676,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
* until it does.
*/
tp->intr_mask = 0xffff;
- smp_wmb();
+ wmb();
RTL_W16(IntrMask, tp->intr_event);
}