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authorWill Deacon <will.deacon@arm.com>2015-09-02 18:49:28 +0100
committerJiri Slaby <jslaby@suse.cz>2015-09-30 11:00:03 +0200
commit3ebb37283c93282592beba3f01e46c8f8371dee8 (patch)
tree893a88b81012fa30dc2d5bab1d70baabfc461f69
parentcebbd84c2287bf8c0d89c589dd3042663215c76c (diff)
arm64: head.S: initialise mdcr_el2 in el2_setup
commit d10bcd473301888f957ec4b6b12aa3621be78d59 upstream. When entering the kernel at EL2, we fail to initialise the MDCR_EL2 register which controls debug access and PMU capabilities at EL1. This patch ensures that the register is initialised so that all traps are disabled and all the PMU counters are available to the host. When a guest is scheduled, KVM takes care to configure trapping appropriately. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
-rw-r--r--arch/arm64/kernel/head.S5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 7090c126797c..aca41b06dc7a 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -192,6 +192,11 @@ ENTRY(el2_setup)
msr hstr_el2, xzr // Disable CP15 traps to EL2
#endif
+ /* EL2 debug */
+ mrs x0, pmcr_el0 // Disable debug access traps
+ ubfx x0, x0, #11, #5 // to EL2 and allow access to
+ msr mdcr_el2, x0 // all PMU counters from EL1
+
/* Stage-2 translation */
msr vttbr_el2, xzr