diff options
author | Jason Liu <r64343@freescale.com> | 2015-01-06 11:23:59 +0800 |
---|---|---|
committer | Jason Liu <r64343@freescale.com> | 2015-02-02 14:17:16 +0800 |
commit | 27d58f08dde556957afcbe3da0abe2bb81084b2b (patch) | |
tree | 3a0d0223e5a5666b012d9124679462cd923dac67 | |
parent | 28a6e3238bd6c4cca05bae600db3f5d84702613e (diff) |
Need gate the QSPI2 and GPMI_IO clock during clock init
QSPI2/GPMI_IO share the same clock source but with the
different gate, need explicitely gate the QSPI2 & GPMI_IO
during the clock init phase according to the SOC design.
The topo of the clock for the GPMI_IO and NAND as below:
mux --> pre divider --> post divider --gate-- >GPMI_IO
|-gate-- >QSPI2
(Note: i.MX6SX:GPMI_NAND and GSPI2 is PINMUX conflicts.)
The SOC design spec required that if change the parent clock
of the GPMI_IO or QSPI2, need gate the GPMI_IO and QSPI2 first
otherwise, there will have some glitch which cause the divider
malfunciton. Thus, we need explicitely gate QSPI2 & GPMI_IO at
the clock initialization phase and then later on common clock
framework will gurantee that each time, the parent clock rate
changes after the child clock is disabled(gated).
Signed-off-by: Jason Liu <r64343@freescale.com>
(cherry picked from commit 7712fd2cfa2ba2d7577d2836cebd9ff7ac6d34a8)
(cherry picked from commit 110d63a5886e065e77a69f816216af044c096a44)
-rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 3b64dda4fafa..d9fed28fe89a 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -546,6 +546,14 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) */ writel_relaxed(readl_relaxed(base + 0x70) | 1 << CCM_CCGR_OFFSET(6), base + 0x70); + /* + * QSPI2/GPMI_IO share the same clock source but with the + * different gate, need explicitely gate the QSPI2 & GPMI_IO + * during the clock init phase according to the SOC design. + */ + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(5)), base + 0x78); + writel_relaxed(readl_relaxed(base + 0x78) & ~(3 << CCM_CCGR_OFFSET(14)), base + 0x78); + clk_data.clks = clks; clk_data.clk_num = ARRAY_SIZE(clks); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |