diff options
| author | Stefan Agner <stefan@agner.ch> | 2016-03-22 15:56:15 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-03-28 10:49:54 -0700 |
| commit | 820d9b0b575e1c3ccdbf79d1adb48b2d9dbbdf4c (patch) | |
| tree | dd9e1c43128839fa38655ab6b44c3f42b4506e81 | |
| parent | 67665fe2b04baaf555ce44a5e59beb999d725df8 (diff) | |
ARM: imx: clk-vf610: fix DCU clock tree
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).
Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus
clock (ipg_bus).
Since the clock has not been used far, there are no further changes
needed.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm/boot/dts/vfxxx.dtsi | 5 | ||||
| -rw-r--r-- | drivers/clk/imx/clk-vf610.c | 4 |
2 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 15ad0f8ad6e7..53a0bbc3e3f3 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -351,8 +351,9 @@ compatible = "fsl,vf610-dcu"; reg = <0x40058000 0x1200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DCU0>; - clock-names = "dcu"; + clocks = <&clks VF610_CLK_DCU0>, + <&clks VF610_CLK_DCU0_DIV>; + clock-names = "dcu", "pix"; fsl,tcon = <&tcon0>; status = "disabled"; }; diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c index 158720aee2a5..43be1cf3650f 100644 --- a/drivers/clk/imx/clk-vf610.c +++ b/drivers/clk/imx/clk-vf610.c @@ -321,11 +321,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); - clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8)); clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); - clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); + clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8)); clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13)); clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1", "platform_bus", CCM_CCGR7, CCM_CCGRx_CGn(13)); |