diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-07-18 22:40:36 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:06 +0800 |
| commit | 042f030b9014fc694f9e6352865febb4c6e22716 (patch) | |
| tree | 91e479647bb5f6c9b5df12ca63d3bd5b4be37f58 | |
| parent | ce1b32cea9b26c681856002a6b33ba0320fea48e (diff) | |
arm64: dts: imx8: gpu0: move into a separate ss dtsi
move gpu0 changes into a separate ss dtsi
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi | 36 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 30 |
2 files changed, 37 insertions, 29 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi new file mode 100644 index 000000000000..21ade5da3e39 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Dong Aisheng <aisheng.dong@nxp.com> + */ + +#include <dt-bindings/firmware/imx/rsrc.h> + +gpu_subsys: bus@53100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x53100000 0x0 0x53100000 0x40000>; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x53100000 0x40000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd IMX_SC_R_GPU_0_PID0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index ee452eab7ce1..a5fb08cfb83f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -269,35 +269,6 @@ fsl,heap-id = <0>; }; - gpu_subsys: bus@53100000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x53100000 0x0 0x53100000 0x40000>; - - gpu_3d0: gpu@53100000 { - compatible = "fsl,imx8-gpu"; - reg = <0x53100000 0x40000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; - clock-names = "core", "shader"; - assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>; - assigned-clock-rates = <700000000>, <850000000>; - power-domains = <&pd IMX_SC_R_GPU_0_PID0>; - status = "disabled"; - }; - - imx8_gpu_ss: imx8_gpu_ss { - compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; - cores = <&gpu_3d0>; - reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; - reg-names = "phys_baseaddr", "contiguous_mem"; - status = "disabled"; - }; - }; - rpmsg: rpmsg{ compatible = "fsl,imx8qxp-rpmsg"; /* up to now, the following channels are used in imx rpmsg @@ -315,6 +286,7 @@ /* sorted in register address */ #include "imx8-ss-cm40.dtsi" + #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-dc.dtsi" #include "imx8-ss-lvds.dtsi" |