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authorJuan Gutierrez <juan.gutierrez@nxp.com>2016-11-24 15:48:18 -0600
committerJuan Gutierrez <juan.gutierrez@nxp.com>2016-12-08 17:15:41 -0600
commit262b55dea11cec615c11540fc2b4fefdc21e6086 (patch)
treed9972c97196e7d32296ff8d091e7e71d5364b9ee
parent40cb7309b856ffd9eec8e720ec3c48ce160549c5 (diff)
MXSCM-235 dts: add support for scm qwks rev3
Add support for SCM i.MX6DQ 1Gb QWKS rev3 Support the next features for 1Gb qwks rev3 boards: - Support for fix lpddr2 mode - hdcp and enetirq - bluetooth and wifi for Murata ZP SDIO dongle Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts10
-rw-r--r--arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts147
-rw-r--r--arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts19
-rw-r--r--arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi77
5 files changed, 257 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a478fb650974..c505d0af1e6b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -349,7 +349,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6sxscm-1gb-evb-sai-ldo.dtb \
imx6sxscm-1gb-evb-btwifi-ldo.dtb \
imx6sxscm-epop-evb-ldo.dtb \
- imx6sxscm-epop-evb-m4-ldo.dtb
+ imx6sxscm-epop-evb-m4-ldo.dtb \
+ imx6dqscm-1gb-qwks-rev3-fix-ldo.dtb \
+ imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dtb \
+ imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb \
imx6sl-evk-btwifi.dtb \
diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts
new file mode 100644
index 000000000000..d376141dcb7a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dts
@@ -0,0 +1,10 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dqscm-1gb-qwks-rev3-fix-ldo.dts"
+#include "imx6dqscm-qwks-rev3-btwifi.dtsi"
diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts
new file mode 100644
index 000000000000..3a42eaa538ef
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-fix-ldo.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dqscm-1gb-qwks-rev2-fix-ldo.dts"
+
+/ {
+ regulators {
+ reg_usb_otg_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 15 0>;
+ enable-active-high;
+ };
+ };
+
+ v4l2_cap_1 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+};
+
+&i2c2 {
+ ov564x_mipi: ov564x_mipi@3c {
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks 201>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&sw4_reg>;
+ AVDD-supply = <&vgen3_reg>;
+ DVDD-supply = <&vgen2_reg>;
+ pwn-gpios = <&gpio1 19 1>;
+ rst-gpios = <&gpio1 20 0>;
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cam>;
+ };
+
+ pmic: pfuze100@08 {
+ regulators {
+ vgen5_reg: vgen5 {
+ regulator-max-microvolt = <2500000>;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ egalax_ts@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_egalax_int>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <14 0>;
+ wakeup-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mipi_csi {
+ status = "okay";
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+};
+
+&usdhc3 {
+ cd-gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-reset-gpios = <&gpio5 12 0>;
+ fsl,magic-packet;
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF >;
+ assigned-clock-rates = <50000000>;
+ status = "okay";
+};
+
+&iomuxc {
+ imx6dqscm-cam {
+ pinctrl_cam: camgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x13069
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x13069
+ >;
+ };
+ };
+
+ imx6qdl-sabresd {
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x17059
+ >;
+ };
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts
new file mode 100644
index 000000000000..1a789fe21858
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6dqscm-1gb-qwks-rev3-fix-ldo.dts"
+
+&hdmi_video {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_hdcp>;
+ fsl,hdcp;
+};
+
+&i2c2 {
+ status = "disable";
+};
diff --git a/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi b/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi
new file mode 100644
index 000000000000..3b6f08064848
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dqscm-qwks-rev3-btwifi.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ regulators {
+ wlreg_on: fixedregulator@100 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "wlreg_on";
+ gpio = <&gpio6 5 0>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+ };
+
+ bcmdhd_wlan_0: bcmdhd_wlan@0 {
+ compatible = "android,bcmdhd_wlan";
+ wlreg_on-supply = <&wlreg_on>;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4
+ &pinctrl_bt>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ cd-post;
+ pm-ignore-notify;
+ wifi-host;
+};
+
+&iomuxc {
+ imx6dqscm-murata-v2 {
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x13069
+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x13069
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x13069
+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x13069
+ >;
+ };
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1f0b1
+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1f0b1
+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
+ >;
+ };
+ };
+};