diff options
| author | Douglas Anderson <dianders@chromium.org> | 2018-11-05 13:09:20 -0800 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-11-28 17:25:42 -0600 |
| commit | 28d13d317bacd7b5316a8bd21488e9850b8e84c1 (patch) | |
| tree | 4b35bbccc680429782c207041f373f1909cf756c | |
| parent | 0567022c019ad1a1d7bb980a99797f7a7a11d7d3 (diff) | |
ARM: dts: qcom: Add SoC-specific string for sdhci-msm-v4 nodes
As per upstream discussion [1], we should have an SoC-specific
compatible string for Qualcomm's SDHCI nodes. Let's add it.
[1] https://lkml.kernel.org/r/20181105203657.GA32282@bogus
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom-apq8084.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 6 |
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 0e1e98707e3f..899f28533ed7 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -412,7 +412,7 @@ }; sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; @@ -425,7 +425,7 @@ }; sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <0 125 0>, <0 221 0>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c3470f9ec747..ca266a5f021d 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -604,7 +604,7 @@ }; sdhci@f9824900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, @@ -618,7 +618,7 @@ }; sdhci@f9864900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, @@ -632,7 +632,7 @@ }; sdhci@f98a4900 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |