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authorAnson Huang <b20788@freescale.com>2015-09-01 01:04:14 +0800
committerAnson Huang <b20788@freescale.com>2015-09-02 00:31:59 +0800
commit29492cb00a219238af05f524c0d9db36d5e8ec63 (patch)
treecea34232d0442df6dedb0f5ce17f6d2318217c72
parent7235ba5a4daddc399313600f2313ee0c54bd855c (diff)
MLK-11461-1 ARM: dts: imx6ul: add LDO bypass support for 9x9 EVK
i.MX6UL-9x9-EVK board has PFUZE3000, enable LDO bypass support. Signed-off-by: Anson Huang <b20788@freescale.com>
-rw-r--r--arch/arm/boot/dts/imx6ul-9x9-evk.dts34
1 files changed, 22 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/imx6ul-9x9-evk.dts b/arch/arm/boot/dts/imx6ul-9x9-evk.dts
index 42d88be739bc..57ae35e6c0a5 100644
--- a/arch/arm/boot/dts/imx6ul-9x9-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-9x9-evk.dts
@@ -139,9 +139,27 @@
};
&cpu0 {
- arm-supply = <&reg_arm>;
- soc-supply = <&reg_soc>;
- dc-supply = <&reg_gpio_dvfs>;
+ /*
+ * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
+ * to align with other platform and use the same cpufreq
+ * driver, still use the seperated OPP define for arm
+ * and soc.
+ */
+ operating-points = <
+ /* kHz uV */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+ arm-supply = <&sw1c_reg>;
+ soc-supply = <&sw1c_reg>;
+ fsl,arm-soc-shared = <1>;
};
&csi {
@@ -205,7 +223,7 @@
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
fsl,wdog-reset = <1>; /* watchdog select of reset source */
- fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+ fsl,ldo-bypass = <1>;
};
&i2c1 {
@@ -219,14 +237,6 @@
reg = <0x08>;
regulators {
- sw1a_reg: sw1a {
- regulator-min-microvolt = <700000>;
- regulator-max-microvolt = <1475000>;
- regulator-boot-on;
- regulator-always-on;
- regulator-ramp-delay = <6250>;
- };
-
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;