media: video: tegra: change resolution from 1450p to 1080p

Add 1080p resolution to supported resolutions in ar0832.
1080p output from sesnor makes it possible to bypass DZ scaling.
This helps improve recording and preview performance.

Bug 846591

Change-Id: Icab0e0ed19a609e56a52809dfe1caf9b6e9ff068
Reviewed-on: http://git-master/r/47390
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

1 files changed, 34 insertions, 34 deletions

diff --git a/drivers/media/video/tegra/ar0832_main.c b/drivers/media/video/tegra/ar0832_main.c
index 44d13689e16f..dc390ef128d4 100644
--- a/drivers/media/video/tegra/ar0832_main.c
+++ b/drivers/media/video/tegra/ar0832_main.c
@@ -220,7 +220,7 @@ static struct ar0832_reg mode_3264X2448[] = {
 	{ar0832_TABLE_END, 0x0000}
 };
 
-static struct ar0832_reg mode_2576x1450[] = {
+static struct ar0832_reg mode_2880X1620[] = {
 	{0x301A, 0x0058},	/* RESET_REGISTER */
 	{0x301A, 0x0050},	/* RESET_REGISTER */
 	{0x0104, 0x0100},	/* GROUPED_PARAMETER_HOLD */
@@ -235,6 +235,7 @@ static struct ar0832_reg mode_2576x1450[] = {
 	{0x31BC, 0x2A0D},	/* MIPI_TIMING_4 */
 	{ar0832_TABLE_WAIT_MS, 0x0005},
 	{0x0112, 0x0A0A},	/* CCP_DATA_FORMAT */
+
 	{0x3044, 0x0590},	/* RESERVED_MFR_3044 */
 	{0x306E, 0xFC80},	/* DATAPATH_SELECT */
 	{0x30B2, 0xC000},	/* RESERVED_MFR_30B2 */
@@ -313,21 +314,21 @@ static struct ar0832_reg mode_2576x1450[] = {
 	{0x3EE4, 0xC100},	/* RESERVED_MFR_3EE4 */
 	{0x3EE6, 0x0540},	/* RESERVED_MFR_3EE6 */
 	{0x3174, 0x8000},	/* RESERVED_MFR_3174 */
-	{0x0300, 0x0004}, 	/* VT_PIX_CLK_DIV */
+	{0x0300, 0x0004},	/* VT_PIX_CLK_DIV */
 	{0x0302, 0x0001},	/* VT_SYS_CLK_DIV */
 	{0x0304, 0x0002},	/* PRE_PLL_CLK_DIV */
-	{0x0306, 0x0042},	/* PLL_MULTIPLIER */
+	{0x0306, 0x0040},	/* PLL_MULTIPLIER */
 	{0x0308, 0x000A},	/* OP_PIX_CLK_DIV */
 	{0x030A, 0x0001},	/* OP_SYS_CLK_DIV */
 	{ar0832_TABLE_WAIT_MS, 0x0001},
 	{0x3064, 0x7400},	/* RESERVED_MFR_3064 */
 	{0x0104, 0x0100},	/* GROUPED_PARAMETER_HOLD */
-	{0x0344, 0x0160},	/* X_ADDR_START */
-	{0x0348, 0x0B6F},	/* X_ADDR_END */
-	{0x0346, 0x01FA},	/* Y_ADDR_START */
-	{0x034A, 0x07A3},	/* Y_ADDR_END */
-	{0x034C, 0x0A10},	/* X_OUTPUT_SIZE */
-	{0x034E, 0x05AA},	/* Y_OUTPUT_SIZE */
+	{0x0344, 0x00C8},	/* X_ADDR_START */
+	{0x0348, 0x0C07},	/* X_ADDR_END */
+	{0x0346, 0x01A6},	/* Y_ADDR_START */
+	{0x034A, 0x07F9},	/* Y_ADDR_END */
+	{0x034C, 0x0B40},	/* X_OUTPUT_SIZE */
+	{0x034E, 0x0654},	/* Y_OUTPUT_SIZE */
 	{0x3040, 0xC041},	/* READ_MODE */
 	{0x306E, 0xFC80},	/* DATAPATH_SELECT */
 	{0x0400, 0x0000},	/* SCALING_MODE */
@@ -335,10 +336,10 @@ static struct ar0832_reg mode_2576x1450[] = {
 	{0x3178, 0x0000},	/* RESERVED_MFR_3178 */
 	{0x3ED0, 0x1E24},	/* RESERVED_MFR_3ED0 */
 
-	{0x0342, 0x102E},	/* LINE_LENGTH_PCK */
-	{0x0340, 0x0639},	/* FRAME_LENGTH_LINES */
-	{0x0202, 0x0639},	/* COARSE_INTEGRATION_TIME */
-	{0x3014, 0x0702},	/* FINE_INTEGRATION_TIME */
+	{0x0342, 0x11B8},	/* LINE_LENGTH_PCK */
+	{0x0340, 0x06E3},	/* FRAME_LENGTH_LINES */
+	{0x0202, 0x06E3},	/* COARSE_INTEGRATION_TIME */
+	{0x3014, 0x0BD8},	/* FINE_INTEGRATION_TIME */
 	{0x3010, 0x0078},	/* FINE_CORRECTION */
 	{0x301A, 0x8250},	/* RESET_REGISTER */
 	{0x301A, 0x8650},	/* RESET_REGISTER */
@@ -353,7 +354,7 @@ static struct ar0832_reg mode_2576x1450[] = {
 	{ar0832_TABLE_END, 0x0000}
 };
 
-static struct ar0832_reg mode_2880X1620[] = {
+static struct ar0832_reg mode_1920X1080[] = {
 	{0x301A, 0x0058},	/* RESET_REGISTER */
 	{0x301A, 0x0050},	/* RESET_REGISTER */
 	{0x0104, 0x0100},	/* GROUPED_PARAMETER_HOLD */
@@ -368,7 +369,6 @@ static struct ar0832_reg mode_2880X1620[] = {
 	{0x31BC, 0x2A0D},	/* MIPI_TIMING_4 */
 	{ar0832_TABLE_WAIT_MS, 0x0005},
 	{0x0112, 0x0A0A},	/* CCP_DATA_FORMAT */
-
 	{0x3044, 0x0590},	/* RESERVED_MFR_3044 */
 	{0x306E, 0xFC80},	/* DATAPATH_SELECT */
 	{0x30B2, 0xC000},	/* RESERVED_MFR_30B2 */
@@ -456,12 +456,12 @@ static struct ar0832_reg mode_2880X1620[] = {
 	{ar0832_TABLE_WAIT_MS, 0x0001},
 	{0x3064, 0x7400},	/* RESERVED_MFR_3064 */
 	{0x0104, 0x0100},	/* GROUPED_PARAMETER_HOLD */
-	{0x0344, 0x00C8},	/* X_ADDR_START */
-	{0x0348, 0x0C07},	/* X_ADDR_END */
-	{0x0346, 0x01A6},	/* Y_ADDR_START */
-	{0x034A, 0x07F9},	/* Y_ADDR_END */
-	{0x034C, 0x0B40},	/* X_OUTPUT_SIZE */
-	{0x034E, 0x0654},	/* Y_OUTPUT_SIZE */
+	{0x0344, 0x028C},	/* X_ADDR_START */
+	{0x0348, 0x0A0B},	/* X_ADDR_END */
+	{0x0346, 0x006E},	/* Y_ADDR_START */
+	{0x034A, 0x04A5},	/* Y_ADDR_END */
+	{0x034C, 0x0780},	/* X_OUTPUT_SIZE */
+	{0x034E, 0x0438},	/* Y_OUTPUT_SIZE */
 	{0x3040, 0xC041},	/* READ_MODE */
 	{0x306E, 0xFC80},	/* DATAPATH_SELECT */
 	{0x0400, 0x0000},	/* SCALING_MODE */
@@ -469,10 +469,10 @@ static struct ar0832_reg mode_2880X1620[] = {
 	{0x3178, 0x0000},	/* RESERVED_MFR_3178 */
 	{0x3ED0, 0x1E24},	/* RESERVED_MFR_3ED0 */
 
-	{0x0342, 0x11B8},	/* LINE_LENGTH_PCK */
-	{0x0340, 0x06E3},	/* FRAME_LENGTH_LINES */
-	{0x0202, 0x06E3},	/* COARSE_INTEGRATION_TIME */
-	{0x3014, 0x0BD8},	/* FINE_INTEGRATION_TIME */
+	{0x0342, 0x103B},	/* LINE_LENGTH_PCK */
+	{0x0340, 0x05C4},	/* FRAME_LENGTH_LINES */
+	{0x0202, 0x05C4},	/* COARSE_INTEGRATION_TIME */
+	{0x3014, 0x0702},	/* FINE_INTEGRATION_TIME */
 	{0x3010, 0x0078},	/* FINE_CORRECTION */
 	{0x301A, 0x8250},	/* RESET_REGISTER */
 	{0x301A, 0x8650},	/* RESET_REGISTER */
@@ -488,8 +488,8 @@ static struct ar0832_reg mode_2880X1620[] = {
 };
 
 static struct ar0832_reg mode_1632X1224[] = {
-	{0x301A, 0x0058},	/* LG_CHANGE 0x0658 RESET_REGISTER */
-	{0x301A, 0x0050},	/* LG_CHANGE 0x0650 RESET_REGISTER */
+	{0x301A, 0x0058},	/* RESET_REGISTER */
+	{0x301A, 0x0050},	/* RESET_REGISTER */
 
 	/* SC-CHANGE: to-do 8 bit write */
 	{0x0104, 0x0100},	/* GROUPED_PARAMETER_HOLD */
@@ -504,7 +504,7 @@ static struct ar0832_reg mode_1632X1224[] = {
 	{0x31BA, 0x0710},	/* MIPI_TIMING_3 */
 	{0x31BC, 0x2A0D},	/* MIPI_TIMING_4 */
 	{ar0832_TABLE_WAIT_MS, 0x0005},
-	{0x0112, 0x0A0A},	/* LG_CHANGE CCP_DATA_FORMAT */
+	{0x0112, 0x0A0A},	/* CCP_DATA_FORMAT */
 	{0x3044, 0x0590},	/* RESERVED_MFR_3044 */
 	{0x306E, 0xFC80},	/* DATAPATH_SELECT */
 	{0x30B2, 0xC000},	/* RESERVED_MFR_30B2 */
@@ -531,7 +531,7 @@ static struct ar0832_reg mode_1632X1224[] = {
 	{0x3E12, 0x4B24},	/* RESERVED_MFR_3E12 */
 	{0x3E14, 0xA3CF},	/* RESERVED_MFR_3E14 */
 	{0x3E16, 0x8802},	/* RESERVED_MFR_3E16 */
-	{0x3E18, 0x84FF},	/* LG_CHANGE 0x8401 RESERVED_MFR_3E18 */
+	{0x3E18, 0x84FF},	/* RESERVED_MFR_3E18 */
 	{0x3E1A, 0x8601},	/* RESERVED_MFR_3E1A */
 	{0x3E1C, 0x8401},	/* RESERVED_MFR_3E1C */
 	{0x3E1E, 0x840A},	/* RESERVED_MFR_3E1E */
@@ -614,7 +614,7 @@ static struct ar0832_reg mode_1632X1224[] = {
 	{0x0202, 0x0557},	/* COARSE_INTEGRATION_TIME */
 	{0x3014, 0x0988},	/* FINE_INTEGRATION_TIME */
 	{0x3010, 0x0130},	/* FINE_CORRECTION */
-	{0x301A, 0x8250},	/* LGE_CHANGE 0x8650 RESET_REGISTER */
+	{0x301A, 0x8250},	/* RESET_REGISTER */
 	{0x301A, 0x8650},	/* RESET_REGISTER */
 	{0x301A, 0x8658},	/* RESET_REGISTER */
 
@@ -638,14 +638,14 @@ static struct ar0832_reg mode_end[] = {
 enum {
 	ar0832_MODE_3264X2448,
 	ar0832_MODE_2880X1620,
-	ar0832_MODE_2576X1450,
+	ar0832_MODE_1920X1080,
 	ar0832_MODE_1632X1224,
 };
 
 static struct ar0832_reg *mode_table[] = {
 	[ar0832_MODE_3264X2448] = mode_3264X2448,
 	[ar0832_MODE_2880X1620] = mode_2880X1620,
-	[ar0832_MODE_2576X1450] = mode_2576x1450,
+	[ar0832_MODE_1920X1080] = mode_1920X1080,
 	[ar0832_MODE_1632X1224] = mode_1632X1224,
 };
 
@@ -929,8 +929,8 @@ static int ar0832_set_mode(struct ar0832_dev *dev,
 		sensor_mode = ar0832_MODE_3264X2448;
 	else if (mode->xres == 2880 && mode->yres == 1620)
 		sensor_mode = ar0832_MODE_2880X1620;
-	else if (mode->xres == 2576 && mode->yres == 1450)
-		sensor_mode = ar0832_MODE_2576X1450;
+	else if (mode->xres == 1920 && mode->yres == 1080)
+		sensor_mode = ar0832_MODE_1920X1080;
 	else if (mode->xres == 1632 && mode->yres == 1224)
 		sensor_mode = ar0832_MODE_1632X1224;
 	else {