diff options
| author | Dong Aisheng <b29396@freescale.com> | 2011-11-17 19:24:54 +0800 |
|---|---|---|
| committer | Dong Aisheng <b29396@freescale.com> | 2011-11-21 15:08:08 +0800 |
| commit | 3f094c8cdeec0ccbd324f5b986fcf95de2383090 (patch) | |
| tree | a22e3c5c650bdc298aa37d43b71c9c0fb991b901 | |
| parent | cc21f45bf4b248e8592c22cb7c3d29d0b53db974 (diff) | |
ENGR00162506 mx6q: set a correct clock for asrc
The ASRC mem to mem mode does not work without this patch.
Bacause 1.5Mhz clock rate is not available which will cause
clock setting fail, change to 7.5Mhz (the mininum one) to make
ASRC work properly.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 465f160d159d..c5545153ffad 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -4842,12 +4842,12 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc, clk_set_rate(&gpu3d_core_clk[0], 528000000); /* - * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample rate convertion, - * however we found it only works when set to 1.5M clock and the - * parent is pll3_sw_clk. + * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample + * rate convertion and this clock frequency can not be too high, set + * it to the minimum value 7.5Mhz to make asrc work properly. */ clk_set_parent(&asrc_clk[1], &pll3_sw_clk); - clk_set_rate(&asrc_clk[1], 1500000); + clk_set_rate(&asrc_clk[1], 7500000); /* set the NAND to 11MHz. Too fast will cause dma timeout. */ clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000)); |