diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-12-08 16:18:47 -0700 |
|---|---|---|
| committer | paul <paul@twilight.(none)> | 2009-12-11 16:12:11 -0700 |
| commit | 55d8a65308a5099155683c5a9bba3b8577988111 (patch) | |
| tree | d1bb1d93c4bafa2275b91b2b7379075ba72f1120 | |
| parent | 06b16939a3d58aa128fee22b9aaf7dbc9a5b7c1c (diff) | |
OMAP2/3: move SDRC macros to mach-omap2/sdrc.h
clock34xx.c contains some macros which probably belong in mach-omap2/sdrc.h.
Move those macros to mach-omap2/sdrc.h.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/clock34xx.c | 14 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/sdrc.h | 16 |
2 files changed, 16 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 523978a58d4e..3344809e5fe5 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -322,22 +322,8 @@ static struct omap_clk omap34xx_clks[] = { #define MAX_DPLL_WAIT_TRIES 1000000 -#define MIN_SDRC_DLL_LOCK_FREQ 83000000 - #define CYCLES_PER_MHZ 1000000 -/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ -#define SDRC_MPURATE_SCALE 8 - -/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ -#define SDRC_MPURATE_BASE_SHIFT 9 - -/* - * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at - * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize - */ -#define SDRC_MPURATE_LOOPS 96 - /* * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks * that are sourced by DPLL5, and both of these require this clock diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h index 48207b018989..12fc7dafec2b 100644 --- a/arch/arm/mach-omap2/sdrc.h +++ b/arch/arm/mach-omap2/sdrc.h @@ -56,4 +56,20 @@ static inline u32 sms_read_reg(u16 reg) OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) #endif /* __ASSEMBLER__ */ +/* Minimum frequency that the SDRC DLL can lock at */ +#define MIN_SDRC_DLL_LOCK_FREQ 83000000 + +/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ +#define SDRC_MPURATE_SCALE 8 + +/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ +#define SDRC_MPURATE_BASE_SHIFT 9 + +/* + * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at + * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize + */ +#define SDRC_MPURATE_LOOPS 96 + + #endif |