ARM: vf610: PM: move handling of PLL3-PLL7 into clock driver

Since all drivers disable/unprepare the descendant clocks of the
PLL correctly, the driver PLLv3 handles the regular PLL's (PLL3-PLL7,
USB, Audio, Video and Ethernet): The driver disables the PLL's
through the "unprepare" callback before entering suspend mode and
reenables them using the "prepare" callback. Only the system PLL's
(PLL1/PLL2) need to be handled by the PM driver.

We still need to store and restore the current PLL's control register
since the clock framework assumes that the clock registers are kept
persistent accross the low power mode. LPSTOP modes however reverts the
PLL registers to their default values (this enables the bypass bit
for instance).

2 files changed, 17 insertions, 35 deletions

diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
index f74f718e3a42..bec1c5420444 100644
--- a/arch/arm/mach-imx/clk-vf610.c
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -118,6 +118,11 @@ static struct clk_div_table pll4_audio_div_table[] = {
 static struct clk *clk[VF610_CLK_END];
 static struct clk_onecell_data clk_data;
 
+static u32 anadig_pll3_ctrl;
+static u32 anadig_pll4_ctrl;
+static u32 anadig_pll5_ctrl;
+static u32 anadig_pll6_ctrl;
+static u32 anadig_pll7_ctrl;
 static u32 ccpgr0;
 static u32 cscmr1;
 static u32 cscmr2;
@@ -148,6 +153,12 @@ static int vf610_clk_suspend(void)
 {
 	int i;
 
+	anadig_pll3_ctrl = readl_relaxed(PLL3_CTRL);
+	anadig_pll4_ctrl = readl_relaxed(PLL4_CTRL);
+	anadig_pll5_ctrl = readl_relaxed(PLL5_CTRL);
+	anadig_pll6_ctrl = readl_relaxed(PLL6_CTRL);
+	anadig_pll7_ctrl = readl_relaxed(PLL7_CTRL);
+
 	ccpgr0 = readl_relaxed(CCM_CCPGR0);
 	cscmr1 = readl_relaxed(CCM_CSCMR1);
 	cscmr2 = readl_relaxed(CCM_CSCMR2);
@@ -166,6 +177,12 @@ static void vf610_clk_resume(void)
 {
 	int i;
 
+	writel_relaxed(anadig_pll3_ctrl, PLL3_CTRL);
+	writel_relaxed(anadig_pll4_ctrl, PLL4_CTRL);
+	writel_relaxed(anadig_pll5_ctrl, PLL5_CTRL);
+	writel_relaxed(anadig_pll6_ctrl, PLL6_CTRL);
+	writel_relaxed(anadig_pll7_ctrl, PLL7_CTRL);
+
 	writel_relaxed(ccpgr0, CCM_CCPGR0);
 	writel_relaxed(cscmr1, CCM_CSCMR1);
 	writel_relaxed(cscmr2, CCM_CSCMR2);
diff --git a/arch/arm/mach-imx/pm-vf610.c b/arch/arm/mach-imx/pm-vf610.c
index 0d381723d40f..4af521bec760 100644
--- a/arch/arm/mach-imx/pm-vf610.c
+++ b/arch/arm/mach-imx/pm-vf610.c
@@ -79,11 +79,6 @@
 #define ANATOP_PLL1_CTRL		0x270
 #define ANATOP_PLL2_CTRL		0x30
 #define ANATOP_PLL2_PFD			0x100
-#define ANATOP_PLL3_CTRL		0x10
-#define ANATOP_PLL4_CTRL		0x70
-#define ANATOP_PLL5_CTRL		0xe0
-#define ANATOP_PLL6_CTRL		0xa0
-#define ANATOP_PLL7_CTRL		0x20
 #define BM_PLL_POWERDOWN	(0x1 << 12)
 #define BM_PLL_ENABLE		(0x1 << 13)
 #define BM_PLL_BYPASS		(0x1 << 16)
@@ -282,10 +277,6 @@ int vf610_set_lpm(enum vf610_cpu_pwr_mode mode)
 		gpc_pgcr |= BM_PGCR_HP_OFF;
 		gpc_pgcr |= BM_PGCR_PG_PD1;
 		writel_relaxed(gpc_pgcr, gpc_base + GPC_PGCR);
-
-		vf610_clr(anatop + ANATOP_PLL3_CTRL, BM_PLL_USB_POWER);
-		vf610_clr(anatop + ANATOP_PLL5_CTRL, BM_PLL_ENABLE);
-		vf610_clr(anatop + ANATOP_PLL7_CTRL, BM_PLL_USB_POWER);
 		break;
 	case VF610_STOP:
 		cclpcr &= ~BM_CLPCR_ANADIG_STOP_MODE;
@@ -325,9 +316,6 @@ int vf610_set_lpm(enum vf610_cpu_pwr_mode mode)
 		writel_relaxed(ccsr, ccm_base + CCSR);
 		vf610_uart_reinit(4000000UL, 115200);
 
-		vf610_clr(anatop + ANATOP_PLL7_CTRL, BM_PLL_USB_POWER);
-		vf610_clr(anatop + ANATOP_PLL5_CTRL, BM_PLL_ENABLE);
-		vf610_clr(anatop + ANATOP_PLL3_CTRL, BM_PLL_USB_POWER);
 		vf610_set(anatop + ANATOP_PLL1_CTRL, BM_PLL_BYPASS);
 		writel_relaxed(BM_LPMR_STOP, gpc_base + GPC_LPMR);
 		break;
@@ -347,29 +335,6 @@ int vf610_set_lpm(enum vf610_cpu_pwr_mode mode)
 		if (pm_info->ccm_ccsr & BM_CCSR_DDRC_CLK_SEL)
 			vf610_set(anatop + ANATOP_PLL2_CTRL, BM_PLL_POWERDOWN);
 
-		vf610_clr(anatop + ANATOP_PLL3_CTRL, BM_PLL_BYPASS);
-		vf610_set(anatop + ANATOP_PLL3_CTRL, BM_PLL_ENABLE);
-		vf610_set(anatop + ANATOP_PLL3_CTRL, BM_PLL_USB_POWER);
-		vf610_set(anatop + ANATOP_PLL3_CTRL, BM_PLL_EN_USB_CLKS);
-
-		while(!(readl(anatop + ANATOP_PLL3_CTRL) & BM_PLL_LOCK));
-
-		vf610_set(anatop + ANATOP_PLL5_CTRL, BM_PLL_ENABLE);
-		vf610_clr(anatop + ANATOP_PLL5_CTRL, BM_PLL_BYPASS);
-		vf610_clr(anatop + ANATOP_PLL5_CTRL, BM_PLL_POWERDOWN);
-
-		while(!(readl(anatop + ANATOP_PLL5_CTRL) & BM_PLL_LOCK));
-
-		vf610_clr(anatop + ANATOP_PLL7_CTRL, BM_PLL_BYPASS);
-		vf610_set(anatop + ANATOP_PLL7_CTRL, BM_PLL_ENABLE);
-		vf610_set(anatop + ANATOP_PLL7_CTRL, BM_PLL_USB_POWER);
-		vf610_set(anatop + ANATOP_PLL7_CTRL, BM_PLL_EN_USB_CLKS);
-
-		/*
-		 * TODO: Why is PLL7 not comming up as PLL3 does?
-		 *while(!(readl(anatop + ANATOP_PLL7_CTRL) & BM_PLL_LOCK));
-		 */
-
 		break;
 	default:
 		return -EINVAL;