ARM: tegra: Disable pre-si features at run time

Disable the the remainder of the silicon only features at
run time instead of the Kconfig file. This change covers
THERMAL_THROTTLE, EDP_LIMITS and DYNAMIC_PWRDET.

Change HZ to 100 for all pre-si configs, not just FPGA. We
cannot change this field at run time. A faster tick doesn't
help sim or Qt CPUs go faster.

This change is a part of the effort to enable runtime
platform detection and reduce compile-time conditionals.

Bug 1333554

Change-Id: I24a865bf192347e487c743fdae3a3369e3ba89d1
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Signed-off-by: Chetan Kumar N G <chetankumarn@nvidia.com>
Reviewed-on: http://git-master/r/264034
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>

3 files changed, 17 insertions, 10 deletions

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 7ef49b8c9e8e..a03358d1f53d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -457,7 +457,6 @@ config TEGRA_ARB_SEMAPHORE
 
 config TEGRA_THERMAL_THROTTLE
 	bool "Enable throttling of CPU speed on overtemp"
-	depends on TEGRA_SILICON_PLATFORM
 	depends on CPU_FREQ
 	depends on THERMAL
 	default y
@@ -557,7 +556,6 @@ config TEGRA_ERRATA_977223
 
 config TEGRA_EDP_LIMITS
 	bool "Enforce electrical design limits on CPU rail"
-	depends on TEGRA_SILICON_PLATFORM
 	depends on CPU_FREQ
 	depends on THERMAL
 	default y if ARCH_TEGRA_3x_SOC
@@ -610,7 +608,6 @@ config TEGRA_EHCI_BOOST_CPU_FREQ
 
 config TEGRA_DYNAMIC_PWRDET
 	bool "Enable dynamic activation of IO level auto-detection"
-	depends on TEGRA_SILICON_PLATFORM
 	default n
 	help
 	  This option allows turning off tegra IO level auto-detection
@@ -831,8 +828,7 @@ config TEGRA_USE_DFLL_RANGE
 	depends on ARCH_TEGRA_HAS_CL_DVFS
 	range 0 2
 	default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
-	default "1" if TEGRA_SILICON_PLATFORM
-	default "0"
+	default "1"
 	help
 	  Defines default range for dynamic frequency lock loop (DFLL)
 	  to be used as CPU clock source:
@@ -851,7 +847,7 @@ config REGULATOR_TEGRA_DFLL_BYPASS
 
 config TEGRA_TIMER_HZ
 	int "Kernel HZ (jiffies per second)"
-	default "100" if TEGRA_FPGA_PLATFORM
+	default "100" if TEGRA_PRE_SILICON_SUPPORT
 	default "1000"
 
 config TEGRA_SOCTHERM
diff --git a/arch/arm/mach-tegra/powerdetect.c b/arch/arm/mach-tegra/powerdetect.c
index ea8f61d220ad..4797a585c89e 100644
--- a/arch/arm/mach-tegra/powerdetect.c
+++ b/arch/arm/mach-tegra/powerdetect.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-tegra/powerdetect.c
  *
- * Copyright (c) 2011, NVIDIA Corporation.
+ * Copyright (c) 2011 - 2013, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,6 +26,8 @@
 #include <linux/regulator/consumer.h>
 #include <linux/module.h>
 
+#include <mach/hardware.h>
+
 #include "board.h"
 #include "fuse.h"
 #include "iomap.h"
@@ -312,6 +314,9 @@ int __init tegra_pwr_detect_cell_init(void)
 	unsigned long flags;
 	bool rails_found = true;
 
+	if (!tegra_platform_is_silicon())
+		return -ENOSYS;
+
 	i = tegra_package_id();
 	if ((i != -1) && (i & (~0x1F))) {
 		pr_err("tegra: not supported package id %d - io power detection"
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c
index b77f62e38b1b..c2eaa5ee1c16 100644
--- a/arch/arm/mach-tegra/tegra12_clocks.c
+++ b/arch/arm/mach-tegra/tegra12_clocks.c
@@ -578,6 +578,12 @@ static unsigned long tegra12_clk_cap_shared_bus(struct clk *bus,
 static bool detach_shared_bus;
 module_param(detach_shared_bus, bool, 0644);
 
+/* Defines default range for dynamic frequency lock loop (DFLL)
+   to be used as CPU clock source:
+   "0" - DFLL is not used,
+   "1" - DFLL is used as a source for all CPU rates
+   "2" - DFLL is used only for high rates above crossover with PLL dvfs curve
+*/
 static int use_dfll;
 
 /**
@@ -3821,11 +3827,11 @@ static void __init tegra12_dfll_cpu_late_init(struct clk *c)
 	if (!ret) {
 		c->state = OFF;
 		c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device);
-
-		use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
+		if (tegra_platform_is_silicon())
+			use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE;
 		tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll);
 		tegra_cl_dvfs_debug_init(c);
-		pr_info("Tegra CPU DFLL is initialized with use_dfll = %d \n", use_dfll);
+		pr_info("Tegra CPU DFLL is initialized with use_dfll = %d\n", use_dfll);
 	}
 #endif
 }