ENGR00142950-3 - MSL: Port EPDC/PxP driver support to 2.6.38

- Ported EPDC driver MSL layer code to 2.6.38
- Ported PxP driver MSL layer code to 2.6.38
- Ported Maxim 17135 EPD PMIC driver MSL layer code to 2.6.38

Signed-off-by: Danny Nold <dannynold@freescale.com>

3 files changed, 487 insertions, 2 deletions

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index effc6f9dae35..ff27eb4bc245 100755
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -76,7 +76,9 @@ config MACH_MX50_RDP
 	select IMX_HAVE_PLATFORM_IMX_OCOTP
 	select IMX_HAVE_PLATFORM_IMX_DCP
 	select IMX_HAVE_PLATFORM_RANDOM_RNGC
-	select IMX_HAVE_PLATFORM_PERFMON
+    select IMX_HAVE_PLATFORM_PERFMON
+    select IMX_HAVE_PLATFORM_IMX_PXP
+	select IMX_HAVE_PLATFORM_IMX_EPDC
 	help
 	  Include support for MX50 reference design platform (RDP) board. This
 	  includes specific configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index 759b128dcd45..03b339b4b647 100755
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -23,10 +23,15 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max17135.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx50.h>
+#include <mach/epdc.h>
 
 #include <asm/irq.h>
 #include <asm/setup.h>
@@ -42,9 +47,47 @@
 #define FEC_RESET_B	IMX_GPIO_NR(4, 12)
 #define MX50_RDP_CSPI_CS0	IMX_GPIO_NR(4, 13)
 #define MX50_RDP_CSPI_CS1	IMX_GPIO_NR(4, 11)
+#define MX50_RDP_EPDC_D0        IMX_GPIO_NR(3, 0)
+#define MX50_RDP_EPDC_D1        IMX_GPIO_NR(3, 1)
+#define MX50_RDP_EPDC_D2        IMX_GPIO_NR(3, 2)
+#define MX50_RDP_EPDC_D3        IMX_GPIO_NR(3, 3)
+#define MX50_RDP_EPDC_D4        IMX_GPIO_NR(3, 4)
+#define MX50_RDP_EPDC_D5        IMX_GPIO_NR(3, 5)
+#define MX50_RDP_EPDC_D6        IMX_GPIO_NR(3, 6)
+#define MX50_RDP_EPDC_D7        IMX_GPIO_NR(3, 7)
+#define MX50_RDP_EPDC_GDCLK     IMX_GPIO_NR(3, 16)
+#define MX50_RDP_EPDC_GDSP      IMX_GPIO_NR(3, 17)
+#define MX50_RDP_EPDC_GDOE      IMX_GPIO_NR(3, 18)
+#define MX50_RDP_EPDC_GDRL      IMX_GPIO_NR(3, 19)
+#define MX50_RDP_EPDC_SDCLK     IMX_GPIO_NR(3, 20)
+#define MX50_RDP_EPDC_SDOEZ     IMX_GPIO_NR(3, 21)
+#define MX50_RDP_EPDC_SDOED     IMX_GPIO_NR(3, 22)
+#define MX50_RDP_EPDC_SDOE      IMX_GPIO_NR(3, 23)
+#define MX50_RDP_EPDC_SDLE      IMX_GPIO_NR(3, 24)
+#define MX50_RDP_EPDC_SDCLKN    IMX_GPIO_NR(3, 25)
+#define MX50_RDP_EPDC_SDSHR     IMX_GPIO_NR(3, 26)
+#define MX50_RDP_EPDC_PWRCOM    IMX_GPIO_NR(3, 27)
+#define MX50_RDP_EPDC_PWRSTAT   IMX_GPIO_NR(3, 28)
+#define MX50_RDP_EPDC_PWRCTRL0  IMX_GPIO_NR(3, 29)
+#define MX50_RDP_EPDC_PWRCTRL1  IMX_GPIO_NR(3, 30)
+#define MX50_RDP_EPDC_PWRCTRL2  IMX_GPIO_NR(3, 31)
+#define MX50_RDP_EPDC_PWRCTRL3  IMX_GPIO_NR(4, 20)
+#define MX50_RDP_EPDC_BDR0      IMX_GPIO_NR(4, 23)
+#define MX50_RDP_EPDC_BDR1      IMX_GPIO_NR(4, 24)
+#define MX50_RDP_EPDC_SDCE0     IMX_GPIO_NR(4, 25)
+#define MX50_RDP_EPDC_SDCE1     IMX_GPIO_NR(4, 26)
+#define MX50_RDP_EPDC_SDCE2     IMX_GPIO_NR(4, 27)
+#define MX50_RDP_EPDC_SDCE3     IMX_GPIO_NR(4, 28)
+#define MX50_RDP_EPDC_SDCE4     IMX_GPIO_NR(4, 29)
+#define MX50_RDP_EPDC_SDCE5     IMX_GPIO_NR(4, 30)
+#define MX50_RDP_EPDC_PMIC_WAKE IMX_GPIO_NR(6, 16)
+#define MX50_RDP_EPDC_PMIC_INT  IMX_GPIO_NR(6, 17)
+#define MX50_RDP_EPDC_VCOM      IMX_GPIO_NR(4, 21)
 
 extern int mx50_rdp_init_mc13892(void);
 
+static int max17135_regulator_init(struct max17135 *max17135);
+
 static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
 	/* SD1 */
 	MX50_PAD_ECSPI2_SS0__GPIO_4_19,
@@ -179,6 +222,429 @@ static const struct fec_platform_data fec_data __initconst = {
 	.phy = PHY_INTERFACE_MODE_RMII,
 };
 
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+static struct regulator_consumer_supply display_consumers[] = {
+	{
+		/* MAX17135 */
+		.supply = "DISPLAY",
+	},
+};
+
+static struct regulator_consumer_supply vcom_consumers[] = {
+	{
+		/* MAX17135 */
+		.supply = "VCOM",
+	},
+};
+
+static struct regulator_init_data max17135_init_data[] __initdata = {
+	{
+		.constraints = {
+			.name = "DISPLAY",
+			.valid_ops_mask =  REGULATOR_CHANGE_STATUS,
+		},
+		.num_consumer_supplies = ARRAY_SIZE(display_consumers),
+		.consumer_supplies = display_consumers,
+	}, {
+		.constraints = {
+			.name = "GVDD",
+			.min_uV = V_to_uV(20),
+			.max_uV = V_to_uV(20),
+		},
+	}, {
+		.constraints = {
+			.name = "GVEE",
+			.min_uV = V_to_uV(-22),
+			.max_uV = V_to_uV(-22),
+		},
+	}, {
+		.constraints = {
+			.name = "HVINN",
+			.min_uV = V_to_uV(-22),
+			.max_uV = V_to_uV(-22),
+		},
+	}, {
+		.constraints = {
+			.name = "HVINP",
+			.min_uV = V_to_uV(20),
+			.max_uV = V_to_uV(20),
+		},
+	}, {
+		.constraints = {
+			.name = "VCOM",
+			.min_uV = mV_to_uV(-4325),
+			.max_uV = mV_to_uV(-500),
+			.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+			REGULATOR_CHANGE_STATUS,
+		},
+		.num_consumer_supplies = ARRAY_SIZE(vcom_consumers),
+		.consumer_supplies = vcom_consumers,
+	}, {
+		.constraints = {
+			.name = "VNEG",
+			.min_uV = V_to_uV(-15),
+			.max_uV = V_to_uV(-15),
+		},
+	}, {
+		.constraints = {
+			.name = "VPOS",
+			.min_uV = V_to_uV(15),
+			.max_uV = V_to_uV(15),
+		},
+	},
+};
+
+static struct platform_device max17135_sensor_device = {
+	.name = "max17135_sensor",
+	.id = 0,
+};
+
+static struct max17135_platform_data max17135_pdata __initdata = {
+	.vneg_pwrup = 1,
+	.gvee_pwrup = 1,
+	.vpos_pwrup = 2,
+	.gvdd_pwrup = 1,
+	.gvdd_pwrdn = 1,
+	.vpos_pwrdn = 2,
+	.gvee_pwrdn = 1,
+	.vneg_pwrdn = 1,
+	.gpio_pmic_pwrgood = MX50_RDP_EPDC_PWRSTAT,
+	.gpio_pmic_vcom_ctrl = MX50_RDP_EPDC_VCOM,
+	.gpio_pmic_wakeup = MX50_RDP_EPDC_PMIC_WAKE,
+	.gpio_pmic_intr = MX50_RDP_EPDC_PMIC_INT,
+	.regulator_init = max17135_init_data,
+	.init = max17135_regulator_init,
+};
+
+static int max17135_regulator_init(struct max17135 *max17135)
+{
+	struct max17135_platform_data *pdata = &max17135_pdata;
+	int i, ret;
+
+	max17135->gvee_pwrup = pdata->gvee_pwrup;
+	max17135->vneg_pwrup = pdata->vneg_pwrup;
+	max17135->vpos_pwrup = pdata->vpos_pwrup;
+	max17135->gvdd_pwrup = pdata->gvdd_pwrup;
+	max17135->gvdd_pwrdn = pdata->gvdd_pwrdn;
+	max17135->vpos_pwrdn = pdata->vpos_pwrdn;
+	max17135->vneg_pwrdn = pdata->vneg_pwrdn;
+	max17135->gvee_pwrdn = pdata->gvee_pwrdn;
+
+	max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
+		pdata->gvdd_pwrup + pdata->gvee_pwrup;
+
+	max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
+	max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
+	max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
+	max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
+
+	gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake");
+	gpio_direction_output(max17135->gpio_pmic_wakeup, 0);
+
+	gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom");
+	gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0);
+
+	gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int");
+	gpio_direction_input(max17135->gpio_pmic_intr);
+
+	gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat");
+	gpio_direction_input(max17135->gpio_pmic_pwrgood);
+
+	max17135->vcom_setup = false;
+	max17135->init_done = false;
+
+	for (i = 0; i <= MAX17135_VPOS; i++) {
+		ret = max17135_register_regulator(max17135, i,
+			&pdata->regulator_init[i]);
+		if (ret != 0) {
+			printk(KERN_ERR"max17135 regulator init failed: %d\n",
+				ret);
+			return ret;
+		}
+	}
+
+	regulator_has_full_constraints();
+
+	return 0;
+}
+
+static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
+	{
+	 I2C_BOARD_INFO("max17135", 0x48),
+	 .platform_data = &max17135_pdata,
+	 },
+	 {
+	 .type = "mma8450",
+	 .addr = 0x1c,
+	 },
+	 {
+	 .type = "eeprom",
+	 .addr = 0x50,
+	 },
+};
+
+static int epdc_get_pins(void)
+{
+	int ret = 0;
+
+	/* Claim GPIOs for EPDC pins - used during power up/down */
+	ret |= gpio_request(MX50_RDP_EPDC_D0, "epdc_d0");
+	ret |= gpio_request(MX50_RDP_EPDC_D1, "epdc_d1");
+	ret |= gpio_request(MX50_RDP_EPDC_D2, "epdc_d2");
+	ret |= gpio_request(MX50_RDP_EPDC_D3, "epdc_d3");
+	ret |= gpio_request(MX50_RDP_EPDC_D4, "epdc_d4");
+	ret |= gpio_request(MX50_RDP_EPDC_D5, "epdc_d5");
+	ret |= gpio_request(MX50_RDP_EPDC_D6, "epdc_d6");
+	ret |= gpio_request(MX50_RDP_EPDC_D7, "epdc_d7");
+	ret |= gpio_request(MX50_RDP_EPDC_GDCLK, "epdc_gdclk");
+	ret |= gpio_request(MX50_RDP_EPDC_GDSP, "epdc_gdsp");
+	ret |= gpio_request(MX50_RDP_EPDC_GDOE, "epdc_gdoe");
+	ret |= gpio_request(MX50_RDP_EPDC_GDRL, "epdc_gdrl");
+	ret |= gpio_request(MX50_RDP_EPDC_SDCLK, "epdc_sdclk");
+	ret |= gpio_request(MX50_RDP_EPDC_SDOE, "epdc_sdoe");
+	ret |= gpio_request(MX50_RDP_EPDC_SDLE, "epdc_sdle");
+	ret |= gpio_request(MX50_RDP_EPDC_SDSHR, "epdc_sdshr");
+	ret |= gpio_request(MX50_RDP_EPDC_BDR0, "epdc_bdr0");
+	ret |= gpio_request(MX50_RDP_EPDC_SDCE0, "epdc_sdce0");
+	ret |= gpio_request(MX50_RDP_EPDC_SDCE1, "epdc_sdce1");
+	ret |= gpio_request(MX50_RDP_EPDC_SDCE2, "epdc_sdce2");
+
+	return ret;
+}
+
+static void epdc_put_pins(void)
+{
+	gpio_free(MX50_RDP_EPDC_D0);
+	gpio_free(MX50_RDP_EPDC_D1);
+	gpio_free(MX50_RDP_EPDC_D2);
+	gpio_free(MX50_RDP_EPDC_D3);
+	gpio_free(MX50_RDP_EPDC_D4);
+	gpio_free(MX50_RDP_EPDC_D5);
+	gpio_free(MX50_RDP_EPDC_D6);
+	gpio_free(MX50_RDP_EPDC_D7);
+	gpio_free(MX50_RDP_EPDC_GDCLK);
+	gpio_free(MX50_RDP_EPDC_GDSP);
+	gpio_free(MX50_RDP_EPDC_GDOE);
+	gpio_free(MX50_RDP_EPDC_GDRL);
+	gpio_free(MX50_RDP_EPDC_SDCLK);
+	gpio_free(MX50_RDP_EPDC_SDOE);
+	gpio_free(MX50_RDP_EPDC_SDLE);
+	gpio_free(MX50_RDP_EPDC_SDSHR);
+	gpio_free(MX50_RDP_EPDC_BDR0);
+	gpio_free(MX50_RDP_EPDC_SDCE0);
+	gpio_free(MX50_RDP_EPDC_SDCE1);
+	gpio_free(MX50_RDP_EPDC_SDCE2);
+}
+
+static iomux_v3_cfg_t mx50_epdc_pads_enabled[] = {
+	MX50_PAD_EPDC_D0__EPDC_D0,
+	MX50_PAD_EPDC_D1__EPDC_D1,
+	MX50_PAD_EPDC_D2__EPDC_D2,
+	MX50_PAD_EPDC_D3__EPDC_D3,
+	MX50_PAD_EPDC_D4__EPDC_D4,
+	MX50_PAD_EPDC_D5__EPDC_D5,
+	MX50_PAD_EPDC_D6__EPDC_D6,
+	MX50_PAD_EPDC_D7__EPDC_D7,
+	MX50_PAD_EPDC_GDCLK__EPDC_GDCLK,
+	MX50_PAD_EPDC_GDSP__EPDC_GDSP,
+	MX50_PAD_EPDC_GDOE__EPDC_GDOE,
+	MX50_PAD_EPDC_GDRL__EPDC_GDRL,
+	MX50_PAD_EPDC_SDCLK__EPDC_SDCLK,
+	MX50_PAD_EPDC_SDOE__EPDC_SDOE,
+	MX50_PAD_EPDC_SDLE__EPDC_SDLE,
+	MX50_PAD_EPDC_SDSHR__EPDC_SDSHR,
+	MX50_PAD_EPDC_BDR0__EPDC_BDR0,
+	MX50_PAD_EPDC_SDCE0__EPDC_SDCE0,
+	MX50_PAD_EPDC_SDCE1__EPDC_SDCE1,
+	MX50_PAD_EPDC_SDCE2__EPDC_SDCE2,
+};
+
+static iomux_v3_cfg_t mx50_epdc_pads_disabled[] = {
+	MX50_PAD_EPDC_D0__GPIO_3_0,
+	MX50_PAD_EPDC_D1__GPIO_3_1,
+	MX50_PAD_EPDC_D2__GPIO_3_2,
+	MX50_PAD_EPDC_D3__GPIO_3_3,
+	MX50_PAD_EPDC_D4__GPIO_3_4,
+	MX50_PAD_EPDC_D5__GPIO_3_5,
+	MX50_PAD_EPDC_D6__GPIO_3_6,
+	MX50_PAD_EPDC_D7__GPIO_3_7,
+	MX50_PAD_EPDC_GDCLK__GPIO_3_16,
+	MX50_PAD_EPDC_GDSP__GPIO_3_17,
+	MX50_PAD_EPDC_GDOE__GPIO_3_18,
+	MX50_PAD_EPDC_GDRL__GPIO_3_19,
+	MX50_PAD_EPDC_SDCLK__GPIO_3_20,
+	MX50_PAD_EPDC_SDOE__GPIO_3_23,
+	MX50_PAD_EPDC_SDLE__GPIO_3_24,
+	MX50_PAD_EPDC_SDSHR__GPIO_3_26,
+	MX50_PAD_EPDC_BDR0__GPIO_4_23,
+	MX50_PAD_EPDC_SDCE0__GPIO_4_25,
+	MX50_PAD_EPDC_SDCE1__GPIO_4_26,
+	MX50_PAD_EPDC_SDCE2__GPIO_4_27,
+};
+
+static void epdc_enable_pins(void)
+{
+	/* Configure MUX settings to enable EPDC use */
+	mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_enabled, \
+				ARRAY_SIZE(mx50_epdc_pads_enabled));
+
+	gpio_direction_input(MX50_RDP_EPDC_D0);
+	gpio_direction_input(MX50_RDP_EPDC_D1);
+	gpio_direction_input(MX50_RDP_EPDC_D2);
+	gpio_direction_input(MX50_RDP_EPDC_D3);
+	gpio_direction_input(MX50_RDP_EPDC_D4);
+	gpio_direction_input(MX50_RDP_EPDC_D5);
+	gpio_direction_input(MX50_RDP_EPDC_D6);
+	gpio_direction_input(MX50_RDP_EPDC_D7);
+	gpio_direction_input(MX50_RDP_EPDC_GDCLK);
+	gpio_direction_input(MX50_RDP_EPDC_GDSP);
+	gpio_direction_input(MX50_RDP_EPDC_GDOE);
+	gpio_direction_input(MX50_RDP_EPDC_GDRL);
+	gpio_direction_input(MX50_RDP_EPDC_SDCLK);
+	gpio_direction_input(MX50_RDP_EPDC_SDOE);
+	gpio_direction_input(MX50_RDP_EPDC_SDLE);
+	gpio_direction_input(MX50_RDP_EPDC_SDSHR);
+	gpio_direction_input(MX50_RDP_EPDC_BDR0);
+	gpio_direction_input(MX50_RDP_EPDC_SDCE0);
+	gpio_direction_input(MX50_RDP_EPDC_SDCE1);
+	gpio_direction_input(MX50_RDP_EPDC_SDCE2);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to
+	 * GPIO and drive to 0. */
+	mxc_iomux_v3_setup_multiple_pads(mx50_epdc_pads_disabled, \
+				ARRAY_SIZE(mx50_epdc_pads_disabled));
+
+	gpio_direction_output(MX50_RDP_EPDC_D0, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D1, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D2, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D3, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D4, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D5, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D6, 0);
+	gpio_direction_output(MX50_RDP_EPDC_D7, 0);
+	gpio_direction_output(MX50_RDP_EPDC_GDCLK, 0);
+	gpio_direction_output(MX50_RDP_EPDC_GDSP, 0);
+	gpio_direction_output(MX50_RDP_EPDC_GDOE, 0);
+	gpio_direction_output(MX50_RDP_EPDC_GDRL, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDCLK, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDOE, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDLE, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDSHR, 0);
+	gpio_direction_output(MX50_RDP_EPDC_BDR0, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDCE0, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDCE1, 0);
+	gpio_direction_output(MX50_RDP_EPDC_SDCE2, 0);
+}
+
+static struct fb_videomode e60_v110_mode = {
+	.name = "E60_V110",
+	.refresh = 50,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 18604700,
+	.left_margin = 8,
+	.right_margin = 178,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+
+static struct fb_videomode e60_v220_mode = {
+	.name = "E60_V220",
+	.refresh = 85,
+	.xres = 800,
+	.yres = 600,
+	.pixclock = 32000000,
+	.left_margin = 8,
+	.right_margin = 166,
+	.upper_margin = 4,
+	.lower_margin = 26,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+
+static struct fb_videomode e97_v110_mode = {
+	.name = "E97_V110",
+	.refresh = 50,
+	.xres = 1200,
+	.yres = 825,
+	.pixclock = 32000000,
+	.left_margin = 12,
+	.right_margin = 128,
+	.upper_margin = 4,
+	.lower_margin = 10,
+	.hsync_len = 20,
+	.vsync_len = 4,
+	.sync = 0,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+
+static struct imx_epdc_fb_mode panel_modes[] = {
+	{
+		&e60_v110_mode,
+		4,	/* vscan_holdoff */
+		10,	/* sdoed_width */
+		20,	/* sdoed_delay */
+		10,	/* sdoez_width */
+		20,	/* sdoez_delay */
+		428,	/* gdclk_hp_offs */
+		20,	/* gdsp_offs */
+		0,	/* gdoe_offs */
+		1,	/* gdclk_offs */
+		1,	/* num_ce */
+	},
+	{
+		&e60_v220_mode,
+		4,	/* vscan_holdoff */
+		10,	/* sdoed_width */
+		20,	/* sdoed_delay */
+		10,	/* sdoez_width */
+		20,	/* sdoez_delay */
+		428,	/* gdclk_hp_offs */
+		20,	/* gdsp_offs */
+		0,	/* gdoe_offs */
+		1,	/* gdclk_offs */
+		1,	/* num_ce */
+	},
+	{
+		&e97_v110_mode,
+		8,	/* vscan_holdoff */
+		10,	/* sdoed_width */
+		20,	/* sdoed_delay */
+		10,	/* sdoez_width */
+		20,	/* sdoez_delay */
+		632,	/* gdclk_hp_offs */
+		20,	/* gdsp_offs */
+		0,	/* gdoe_offs */
+		1,	/* gdclk_offs */
+		3,	/* num_ce */
+	}
+};
+
+static struct imx_epdc_fb_platform_data epdc_data = {
+	.epdc_mode = panel_modes,
+	.num_modes = ARRAY_SIZE(panel_modes),
+	.get_pins = epdc_get_pins,
+	.put_pins = epdc_put_pins,
+	.enable_pins = epdc_enable_pins,
+	.disable_pins = epdc_disable_pins,
+};
+
 static inline void mx50_rdp_fec_reset(void)
 {
 	gpio_request(FEC_EN, "fec-en");
@@ -263,13 +729,19 @@ static void __init mx50_rdp_board_init(void)
 	imx50_add_imx_uart(0, NULL);
 	imx50_add_imx_uart(1, NULL);
 	imx50_add_srtc();
+	imx50_add_imx_pxp();
+	imx50_add_imx_pxp_client();
 	mx50_rdp_fec_reset();
 	imx50_add_fec(&fec_data);
 	imx50_add_gpmi(&mx50_gpmi_nfc_platform_data);
 	imx50_add_imx_i2c(0, &i2c_data);
 	imx50_add_imx_i2c(1, &i2c_data);
 	imx50_add_imx_i2c(2, &i2c_data);
-	imx50_add_mxc_gpu(&gpu_data);
+	i2c_register_board_info(0, mxc_i2c0_board_info,
+				ARRAY_SIZE(mxc_i2c0_board_info));
+	mxc_register_device(&max17135_sensor_device, NULL);
+    imx50_add_imx_epdc(&epdc_data);
+    imx50_add_mxc_gpu(&gpu_data);
 	imx50_add_sdhci_esdhc_imx(0, NULL);
 	imx50_add_sdhci_esdhc_imx(1, NULL);
 	imx50_add_sdhci_esdhc_imx(2, NULL);
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
index cf8af0eefd6e..53a3e2520ebc 100755
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -40,6 +40,17 @@ extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
 #define imx50_add_imx_i2c(id, pdata)	\
 	imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
 extern const struct imx_mxc_gpu_data imx50_gpu_data __initconst;
+extern const struct imx_pxp_data imx50_pxp_data __initconst;
+#define imx50_add_imx_pxp()   \
+    imx_add_imx_pxp(&imx50_pxp_data)
+
+#define imx50_add_imx_pxp_client()   \
+    imx_add_imx_pxp_client()
+
+extern const struct imx_epdc_data imx50_epdc_data __initconst;
+#define imx50_add_imx_epdc(pdata)	\
+	imx_add_imx_epdc(&imx50_epdc_data, pdata)
+
 #define imx50_add_mxc_gpu(pdata) \
 	imx_add_mxc_gpu(&imx50_gpu_data, pdata)
 extern const struct imx_sdhci_esdhc_imx_data imx50_sdhci_esdhc_imx_data[] __initconst;