diff options
| author | Lucas Stach <dev@lynxeye.de> | 2018-06-24 23:27:26 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2018-07-09 18:51:01 +0200 |
| commit | 6c468f109884c2cd8d8bc042945fdd861f375523 (patch) | |
| tree | fe522eeb37950888b252320cdb10de1c52267d7e | |
| parent | 8ab11f8068ef57e5763e1cc91b3dfe23a2482e68 (diff) | |
ARM: dts: tegra: add Tegra20 NAND flash controller node
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/tegra20.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 86d8cd6f9548..15b73bd377f0 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -432,6 +432,21 @@ status = "disabled"; }; + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + assigned-clock-rates = <150000000>; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>; |