diff options
| author | ling.ma@intel.com <ling.ma@intel.com> | 2009-06-25 10:59:22 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-07-01 11:20:44 -0700 |
| commit | 6ff4fd05676bc5b5c930bef25901e489f7843660 (patch) | |
| tree | 82a9e18779ffd332a6715f413cc8e5513ef7b667 | |
| parent | 7662c8bd6545c12ac7b2b39e4554c3ba34789c50 (diff) | |
drm/i915: Set SSC frequency for 8xx chips correctly
All 8xx class chips have the 66/48 split, not just 855.
Signed-off-by: Ma Ling <ling.ma@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_bios.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 716409a57244..da22863c05c0 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv, dev_priv->lvds_use_ssc = general->enable_ssc; if (dev_priv->lvds_use_ssc) { - if (IS_I855(dev_priv->dev)) - dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48; - else - dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96; + if (IS_I85X(dev_priv->dev)) + dev_priv->lvds_ssc_freq = + general->ssc_freq ? 66 : 48; + else + dev_priv->lvds_ssc_freq = + general->ssc_freq ? 100 : 96; } } } |