diff options
| author | Haley Teng <hteng@nvidia.com> | 2012-02-24 13:19:25 +0800 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-02-28 19:39:13 -0800 |
| commit | 70a4633ed36da3ffd0ad85e6037ccbf1158a0186 (patch) | |
| tree | 7715962b326c3e0d21270bf9764a9cb8ce56f758 | |
| parent | 263c05efb89c9dec256275db6147003ff93dfdbb (diff) | |
ARM: tegra: invalidate volatile CPU state after resume from suspend or hotplug
In the CPU hotplug startup routine, besides invalidate d-cache, we also
need,
- invalidate BTAC, i-cache, branch predict array, TLB
- invalidate SCU tags
- enable i-cache, branch prediction
Bug 926063
Bug 925488
Change-Id: I3751192f6aee65d93f6654e768d93ef7a5092023
Signed-off-by: Haley Teng <hteng@nvidia.com>
Change-Id: I35af9d4bbe5d60df2d648d9e7dcc18762194fb11
Reviewed-on: http://git-master/r/84759
Reviewed-by: Foster Cho <ycho@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 36 |
1 files changed, 34 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 5bb68433050a..21ff460d160a 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -48,7 +48,7 @@ * of secondary CPUs. */ ENTRY(tegra_secondary_startup) - bl tegra_invalidate_l1 + bl __invalidate_cpu_state b secondary_startup ENDPROC(tegra_secondary_startup) #endif @@ -62,7 +62,7 @@ ENDPROC(tegra_secondary_startup) * re-enabling sdram. */ ENTRY(tegra_resume) - bl tegra_invalidate_l1 + bl __invalidate_cpu_state cpu_id r0 cmp r0, #0 @ CPU0? @@ -94,6 +94,38 @@ ENDPROC(tegra_resume) #endif /* + * __invalidate_cpu_state + * + * Invalidates volatile CPU state (SCU tags, caches, branch address + * arrays, exclusive monitor, etc.) so that they can be safely enabled + * instruction caching and branch predicition enabled + */ +__invalidate_cpu_state: + clrex + mov r0, #0 + mcr p15, 0, r0, c1, c0, 1 @ disable SMP, prefetch, broadcast + isb + mcr p15, 0, r0, c7, c5, 0 @ invalidate BTAC, i-cache + mcr p15, 0, r0, c7, c5, 6 @ invalidate branch pred array + mcr p15, 0, r0, c8, c7, 0 @ invalidate unified TLB + dsb + isb + + cpu_id r0 + cmp r0, #0 + mov32 r1, (TEGRA_ARM_PERIF_BASE + 0xC) + movne r0, r0, lsl #2 + movne r2, #0xf + movne r2, r2, lsl r0 + strne r2, [r1] @ invalidate SCU tags for CPU + + dsb + mov r0, #0x1800 + mcr p15, 0, r0, c1, c0, 0 @ enable branch prediction, i-cache + isb + /* fall through */ + +/* * tegra_invalidate_l1 * * Invalidates the L1 data cache (no clean) during initial boot of a cpu |