diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-01-17 15:19:56 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-02-25 15:50:35 +0800 |
| commit | 73a14019d0d4ccf3d0acbd20e8a6f980ceb7035b (patch) | |
| tree | f50d5704e6d091b192a94a04ae4a06530ce49344 | |
| parent | 041b7a6f981bbf4785c83d747f71684b131f1ebd (diff) | |
MLK-23233-4 arm64: dts: refine pcie dts and add the pcieax2 and pciebx1 usecase
Different usecase maybe used by customer, add the PCIEA two lanes and
PCIEB one lane usecase into fsl-imx8qm-pcieax2pciebx1.dts.
Refine the PCIE dts nodes, add the requrired HSIO peripheral clocks for
different consumers.
PCIEB has one more PER clock, since the PCIEA CSR register would be
configuired when PCIEB is initialized.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi | 15 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts | 57 |
3 files changed, 69 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 66918738ce76..c205e89bcab6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-mek-domu-dpu1-hdmi.dtb \ fsl-imx8qm-mek-root.dtb \ fsl-imx8qm-mek-inmate.dtb \ + fsl-imx8qm-pcieax2pciebx1.dtb \ fsl-imx8qm-lpddr4-arm2-dp.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi.dtb \ fsl-imx8qm-lpddr4-arm2-hdmi-in.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index b7733b1c3e19..952954294f95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -4110,8 +4110,11 @@ <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, - <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 73 4>, @@ -4153,8 +4156,12 @@ <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, - <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic 0 105 4>, diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts new file mode 100644 index 000000000000..6bac94c0b44c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-pcieax2pciebx1.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP + */ + + +#include "fsl-imx8qm-mek.dts" + +/* + * Add the PCIeA x2 lanes and PCIeB x1 lane usecase + * hsio-cfg = <PCIEAX2PCIEBX1> + * NOTE: In this case, the HSIO nodes contained + * hsio-cfg = <PCIEAX1PCIEBX1SATA> would be re-configured. + */ +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on-supply = <&epdev_on>; + num-lanes = <2>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&pcieb{ + ext_osc = <1>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pciex2_per", + "pcie_inbound_axi", "phy_per", "misc_per"; + power-domains = <&pd_pcie1>; + hsio-cfg = <PCIEAX2PCIEBX1>; + status = "okay"; +}; + +&sata { + status = "disabled"; +}; + |