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authorSrinivas Kandagatla <srinivas.kandagatla@linaro.org>2016-02-23 14:14:45 +0000
committerAndy Gross <andy.gross@linaro.org>2016-02-26 13:15:49 -0600
commit7788d439ae08852cf5b54260b2132401761b745a (patch)
tree25308529269eb9b78456bada73a4721dbaed0b68
parent492731cbd058928378fa8aade418c171084dd894 (diff)
ARM: dts: apq8064: add missing i2c2 pinctrl info
This patch adds missing i2c2 pinctrl information in i2c2 node. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
-rw-r--r--arch/arm/boot/dts/qcom-apq8064-pins.dtsi26
-rw-r--r--arch/arm/boot/dts/qcom-apq8064.dtsi2
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 0b7b10e8ba5c..0a342d31c0a2 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -39,6 +39,32 @@
};
};
+ i2c2_pins: i2c2 {
+ mux {
+ pins = "gpio24", "gpio25";
+ function = "gsbi2";
+ };
+
+ pinconf {
+ pins = "gpio24", "gpio25";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins_sleep: i2c2_pins_sleep {
+ mux {
+ pins = "gpio24", "gpio25";
+ function = "gpio";
+ };
+
+ pinconf {
+ pins = "gpio24", "gpio25";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
i2c3_pins: i2c3 {
mux {
pins = "gpio8", "gpio9";
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index d46d460d621e..20da87306bb3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -255,6 +255,8 @@
gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
+ pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
+ pinctrl-names = "default", "sleep";
interrupts = <0 196 IRQ_TYPE_NONE>;
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
clock-names = "core", "iface";