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authorJuan Gutierrez <juan.gutierrez@nxp.com>2016-11-03 18:06:21 -0500
committerJason Liu <jason.hui.liu@nxp.com>2019-02-12 10:25:24 +0800
commit8d8d26d593fcb744ef204fe0875f510a547a149d (patch)
tree1d5e2f77a139539e936c9feade8460aa3d75fc87
parent1a55324c46e0781e151d087160508c0a7d5a128a (diff)
MXSCM-217 imx: keep weak 2p5 power up when ENET WOL wakeup is enabled
When ENET wake up is enabled by wake-on-lan (WOL), the weak 2P5 ldo needs to keep power up even for LPDDR2 due to the ENET_PLL is feed by the weak 2p5 ldo during DSM. If the weak 2P5 ldo is power down the ENET module is power off hence it is not able to sense the WOL interrupt and trigger the system resume. Signed-off-by: Juan Gutierrez <juan.gutierrez@nxp.com>
-rw-r--r--arch/arm/mach-imx/anatop.c4
-rw-r--r--arch/arm/mach-imx/common.h1
-rw-r--r--arch/arm/mach-imx/gpc.c14
3 files changed, 17 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index fe4fda991045..e6e55723d9cf 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -150,7 +150,7 @@ void imx_anatop_pre_suspend(void)
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) &&
- !imx_gpc_usb_wakeup_enabled())
+ !imx_gpc_usb_wakeup_enabled() && !imx_gpc_enet_wakeup_enabled())
imx_anatop_enable_2p5_pulldown(true);
else
imx_anatop_enable_weak2p5(true);
@@ -180,7 +180,7 @@ void imx_anatop_post_resume(void)
if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 ||
imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) &&
- !imx_gpc_usb_wakeup_enabled())
+ !imx_gpc_usb_wakeup_enabled() && !imx_gpc_enet_wakeup_enabled())
imx_anatop_enable_2p5_pulldown(false);
else
imx_anatop_enable_weak2p5(false);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c86bdd41216c..ecf1f47494c8 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -187,6 +187,7 @@ void imx6ull_low_power_idle(void);
void imx6sl_low_power_idle(void);
void imx6sll_low_power_idle(void);
bool imx_gpc_usb_wakeup_enabled(void);
+bool imx_gpc_enet_wakeup_enabled(void);
#ifdef CONFIG_SUSPEND
void v7_cpu_resume(void);
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 52fe8abdd3d0..e0ab6807ef54 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -49,6 +49,9 @@
/* for irq #74 and #75 */
#define GPC_USB_VBUS_WAKEUP_IRQ_MASK 0xc00
+/* for irq #150 and #151 */
+#define GPC_ENET_WAKEUP_IRQ_MASK 0xC00000
+
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -139,6 +142,17 @@ bool imx_gpc_usb_wakeup_enabled(void)
return false;
}
+bool imx_gpc_enet_wakeup_enabled(void)
+{
+ if (!cpu_is_imx6q())
+ return false;
+
+ if (gpc_wake_irqs[3] & GPC_ENET_WAKEUP_IRQ_MASK)
+ return true;
+
+ return false;
+}
+
unsigned int imx_gpc_is_mf_mix_off(void)
{
return readl_relaxed(gpc_base + GPC_PGC_MF_PDN);