diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2012-04-24 16:53:38 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-04-24 14:57:58 -0700 |
| commit | 9843f2c0728f88144fab716109e325b6b68e18d4 (patch) | |
| tree | fc3cf4fd75acee94bf8cc8c75027b76a594fc6c2 | |
| parent | 41eb9f8f4c7b7ff06df127e111755f5b4f1dc35d (diff) | |
ARM: tegra: cardhu: open drain pin need not to set tristate
When open drian pin is set as gpio-input, the pin is set as
tristate and hence need not to set this again tristate from
pinmux controller.
Setting the pin in normal in pinmux controller and then
- setting HIGH by gpio-input and pull-up so that pin is
tristated through gpio controller.
- Setting LOW by gpio-output and drive to LOW. As pin is in
normal state in the pinmux, the output will be set to LOW.
bug 973591
bug 969182
Change-Id: Ia9518f79987c9562bb57f95a468bdc5b5e143b87
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98434
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/board-cardhu-pinmux.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-pinmux.c b/arch/arm/mach-tegra/board-cardhu-pinmux.c index 112fcc976715..fd0a6ae34ffc 100644 --- a/arch/arm/mach-tegra/board-cardhu-pinmux.c +++ b/arch/arm/mach-tegra/board-cardhu-pinmux.c @@ -442,8 +442,8 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu[] = { /* Power rails GPIO */ DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_RST_N, RSVD3, PULL_UP, TRISTATE, INPUT), - DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_RST_N, RSVD3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GMI_CS0_N, GMI, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(GMI_CS1_N, GMI, PULL_UP, TRISTATE, INPUT), @@ -466,8 +466,8 @@ static __initdata struct tegra_pingroup_config cardhu_pinmux_cardhu_a03[] = { /* Power rails GPIO */ DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD3, PULL_UP, TRISTATE, INPUT), - DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD3, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD3, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD3, PULL_UP, NORMAL, INPUT), }; static __initdata struct tegra_pingroup_config cardhu_pinmux_e1291_a04[] = { |