diff options
| author | Pradeep Kumar <pgoudagunta@nvidia.com> | 2012-08-06 23:01:18 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-08-07 15:23:08 -0700 |
| commit | b8b641f5e81434ebb721b3998218645b5190bc25 (patch) | |
| tree | d82cd59ef84d3ddde0478abb38b2f329db87b4da | |
| parent | e3c885a945febae6e9b2bc1c82863494d5db9a79 (diff) | |
Merge commit 'main-jb-2012.08.03-B4' into t114-0806
Conflicts:
arch/arm/boot/compressed/Makefile
arch/arm/boot/compressed/atags_to_fdt.c
arch/arm/boot/compressed/head.S
arch/arm/boot/dts/tegra30.dtsi
arch/arm/include/asm/bug.h
arch/arm/kernel/traps.c
arch/arm/mach-tegra/Makefile.boot
arch/arm/mach-tegra/board-cardhu-sdhci.c
arch/arm/mach-tegra/board-cardhu.c
arch/arm/mach-tegra/board-enterprise-sdhci.c
arch/arm/mach-tegra/board-enterprise.c
arch/arm/mach-tegra/board-harmony.c
arch/arm/mach-tegra/board-kai-sdhci.c
arch/arm/mach-tegra/board-ventana.c
arch/arm/mach-tegra/board-whistler.c
arch/arm/mach-tegra/clock.h
arch/arm/mach-tegra/fuse.h
arch/arm/mach-tegra/tegra2_usb_phy.c
arch/arm/mach-tegra/tegra3_clocks.c
arch/arm/mach-tegra/tegra3_dvfs.c
arch/arm/mach-tegra/tegra3_speedo.c
arch/arm/mach-tegra/timer.c
arch/arm/mach-tegra/usb_phy.c
arch/arm/mach-tegra/wakeups-t3.c
drivers/cpufreq/cpufreq_interactive.c
drivers/input/touchscreen/atmel_mxt_ts.c
drivers/mfd/tps65090.c
drivers/mmc/core/mmc.c
drivers/mmc/host/sdhci-tegra.c
drivers/mmc/host/sdhci.c
drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c
drivers/regulator/Kconfig
drivers/regulator/core.c
drivers/regulator/tps80031-regulator.c
drivers/spi/Makefile
drivers/staging/nvec/nvec.c
drivers/tty/serial/Makefile
include/linux/mmc/card.h
sound/soc/tegra/tegra_max98095.c
sound/usb/card.c
Change-Id: I65043bc6ce9e97d0592683462215a39e50f403fd
Reviewed-on: http://git-master/r/121392
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
144 files changed, 9118 insertions, 1123 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 40589ceb8c98..9f140c0c505e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1,3 +1,16 @@ +# Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. config ARM bool default y @@ -248,6 +261,10 @@ config GENERIC_BUG def_bool y depends on BUG +config GENERIC_BUG + def_bool y + depends on BUG + source "init/Kconfig" source "kernel/Kconfig.freezer" diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index bb267562e7ed..cc67dd13bc1f 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -111,6 +111,23 @@ ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y) OBJS += $(libfdt_objs) atags_to_fdt.o endif +# Borrowed libfdt files for the ATAG compatibility mode + +libfdt := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c +libfdt_hdrs := fdt.h libfdt.h libfdt_internal.h + +libfdt_objs := $(addsuffix .o, $(basename $(libfdt))) + +$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/% + $(call cmd,shipped) + +$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \ + $(addprefix $(obj)/,$(libfdt_hdrs)) + +ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y) +OBJS += $(libfdt_objs) atags_to_fdt.o +endif + targets := vmlinux vmlinux.lds \ piggy.$(suffix_y) piggy.$(suffix_y).o \ lib1funcs.o lib1funcs.S ashldi3.o ashldi3.S \ diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c index 797f04bedb47..e7a26fef2135 100644 --- a/arch/arm/boot/compressed/atags_to_fdt.c +++ b/arch/arm/boot/compressed/atags_to_fdt.c @@ -89,6 +89,11 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space) initrd_start); setprop_cell(fdt, "/chosen", "linux,initrd-end", initrd_start + initrd_size); + } else if (atag->hdr.tag == ATAG_SERIAL) { + uint32_t serial[2]; + serial[0] = cpu_to_fdt32(atag->u.serialnr.high); + serial[1] = cpu_to_fdt32(atag->u.serialnr.low); + setprop(fdt, "/", "serial-num", serial, 8); } } diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 6e8447dc0202..6e8447dc0202 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index dbf1c5a171c2..dbf1c5a171c2 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts new file mode 100644 index 000000000000..39f199755d5c --- /dev/null +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra2 Ventana evaluation board"; + compatible = "nvidia,ventana", "nvidia,tegra20"; +}; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts new file mode 100644 index 000000000000..e3a5939a42aa --- /dev/null +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "NVIDIA Tegra20 Whistler evaluation board"; + compatible = "nvidia,whistler", "nvidia,tegra20"; +}; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts new file mode 100644 index 000000000000..35dce0bfb191 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-cardhu.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Cardhu evaluation board"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; +}; diff --git a/arch/arm/boot/dts/tegra30-enterprise.dts b/arch/arm/boot/dts/tegra30-enterprise.dts new file mode 100644 index 000000000000..c78821ca9b15 --- /dev/null +++ b/arch/arm/boot/dts/tegra30-enterprise.dts @@ -0,0 +1,8 @@ +/dts-v1/; + +/include/ "tegra30.dtsi" + +/ { + model = "NVIDIA Tegra30 Enterprise evaluation board"; + compatible = "nvidia,enterprise", "nvidia,tegra30"; +}; diff --git a/arch/arm/configs/tegra3_android_defconfig b/arch/arm/configs/tegra3_android_defconfig index b2ecba6603ac..3d37c2f5ac1a 100644 --- a/arch/arm/configs/tegra3_android_defconfig +++ b/arch/arm/configs/tegra3_android_defconfig @@ -50,6 +50,7 @@ CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_FREQ=y @@ -179,6 +180,7 @@ CONFIG_CAIF=y CONFIG_NFC=y CONFIG_PN544_NFC=y # CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y diff --git a/arch/arm/configs/tegra_android_defconfig b/arch/arm/configs/tegra_android_defconfig index 19b1ec705bd4..7571c447540c 100644 --- a/arch/arm/configs/tegra_android_defconfig +++ b/arch/arm/configs/tegra_android_defconfig @@ -46,6 +46,7 @@ CONFIG_PREEMPT=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_HIGHMEM=y +CONFIG_USE_OF=y CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_CPU_FREQ=y @@ -166,6 +167,7 @@ CONFIG_CFG80211=y CONFIG_RFKILL=y CONFIG_RFKILL_GPIO=y # CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_PROC_DEVICETREE=y CONFIG_BLK_DEV_LOOP=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y diff --git a/arch/arm/configs/tegra_p1852_android_defconfig b/arch/arm/configs/tegra_p1852_android_defconfig new file mode 100644 index 000000000000..4550c9ec6405 --- /dev/null +++ b/arch/arm/configs/tegra_p1852_android_defconfig @@ -0,0 +1,339 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_CROSS_COMPILE="arm-eabi-" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_SCHED=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_ELF_CORE is not set +CONFIG_ASHMEM=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_TEGRA=y +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_TEGRA_3x_SOC=y +CONFIG_MACH_P1852=y +CONFIG_TEGRA_DEBUG_UARTB=y +CONFIG_TEGRA_PWM=y +# CONFIG_TEGRA_CPU_DVFS is not set +CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y +CONFIG_USB_HOTPLUG=y +CONFIG_ARM_ERRATA_743622=y +CONFIG_ARM_ERRATA_751472=y +CONFIG_ARM_ERRATA_752520=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_VFP=y +CONFIG_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_INET_ESP=y +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_LOG=y +CONFIG_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_INGRESS=y +CONFIG_NET_CLS_U32=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_NET_ACT_MIRRED=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_NAND_TEGRA=y +CONFIG_MTD_NAND=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_MISC_DEVICES=y +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_APDS9802ALS=y +CONFIG_SENSORS_NCT1008=y +CONFIG_UID_STAT=y +CONFIG_BCM4329_RFKILL=y +CONFIG_TEGRA_CRYPTO_DEV=y +CONFIG_MAX1749_VIBRATOR=y +CONFIG_EEPROM_AT24=y +CONFIG_TI_ST=y +CONFIG_ST_GPS=m +CONFIG_MPU_SENSORS_TIMERIRQ=y +CONFIG_MPU_SENSORS_MPU3050=m +CONFIG_MPU_SENSORS_MPU6050B1=m +CONFIG_MPU_SENSORS_KXTF9=m +CONFIG_MPU_SENSORS_MPU6050_ACCEL=m +CONFIG_MPU_SENSORS_AK8963=m +CONFIG_MPU_SENSORS_AK8975=m +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=y +CONFIG_DM_UEVENT=y +CONFIG_NETDEVICES=y +CONFIG_DUMMY=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_USB_NET_RAW_IP=y +CONFIG_PPP=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=y +CONFIG_PPP_SYNC_TTY=y +CONFIG_PPP_DEFLATE=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_MPPE=y +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_TEGRA=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_TEGRA=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_TEGRA=y +CONFIG_SPI=y +CONFIG_SPI_TEGRA=y +CONFIG_SPI_SLAVE_TEGRA=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_PDA_POWER=y +CONFIG_BATTERY_BQ20Z75=y +CONFIG_BATTERY_BQ27x00=y +CONFIG_CHARGER_SMB349=y +CONFIG_BATTERY_MAX17048=y +CONFIG_CHARGER_GPIO=y +CONFIG_SENSORS_TEGRA_TSENSOR=y +CONFIG_SENSORS_INA219=y +CONFIG_THERMAL=y +CONFIG_MFD_TPS6586X=y +CONFIG_MFD_TPS65910=y +CONFIG_MFD_MAX77663=y +CONFIG_MFD_TPS6591X=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_TPS6591X=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_VIDEO_DEV=y +# CONFIG_TEGRA_AVP is not set +# CONFIG_TEGRA_MEDIASERVER is not set +CONFIG_TEGRA_NVAVP=y +# CONFIG_VGA_ARB is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_TEGRA_GRHOST=y +CONFIG_TEGRA_DC=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_SOC=y +CONFIG_SND_SOC_TEGRA=y +CONFIG_SND_SOC_TEGRA_P1852=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_WDM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_LIBUSUAL=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=y +CONFIG_USB_SERIAL_BASEBAND=m +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VBUS_DRAW=500 +CONFIG_USB_TEGRA=y +CONFIG_USB_G_ANDROID=y +CONFIG_USB_TEGRA_OTG=y +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_EMBEDDED_SDIO=y +CONFIG_MMC_PARANOID_SD_INIT=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_BLOCK_DEFERRED_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_SWITCH=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_TEGRA=y +CONFIG_STAGING=y +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_RAM_CONSOLE=y +CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_IIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +# CONFIG_DNOTIFY is not set +CONFIG_FUSE_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_ROOT_NFS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_EFI_PARTITION=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_PREEMPT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_VM=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig index e6b401c23e2b..7e4f4ab3e750 100644 --- a/arch/arm/configs/tegra_p1852_gnu_linux_defconfig +++ b/arch/arm/configs/tegra_p1852_gnu_linux_defconfig @@ -192,6 +192,8 @@ CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y # CONFIG_DNOTIFY is not set CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y CONFIG_VFAT_FS=y CONFIG_TMPFS=y # CONFIG_MISC_FILESYSTEMS is not set diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h index 7af5c6c3653a..deb6f1418061 100644 --- a/arch/arm/include/asm/bug.h +++ b/arch/arm/include/asm/bug.h @@ -1,3 +1,20 @@ +/* + * arch/arm/include/asm/bug.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ #ifndef _ASMARM_BUG_H #define _ASMARM_BUG_H diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c index bee7f9d47f02..01619825a253 100644 --- a/arch/arm/kernel/devtree.c +++ b/arch/arm/kernel/devtree.c @@ -75,6 +75,9 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) unsigned int score, mdesc_score = ~1; unsigned long dt_root; const char *model; + __be32 *serial_prop; + u64 serial = 0; + unsigned long len; if (!dt_phys) return NULL; @@ -118,7 +121,16 @@ struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) model = of_get_flat_dt_prop(dt_root, "compatible", NULL); if (!model) model = "<unknown>"; - pr_info("Machine: %s, model: %s\n", mdesc_best->name, model); + + serial_prop = of_get_flat_dt_prop(dt_root, "serial-num", &len); + if (serial_prop) { + serial = of_read_number(serial_prop, len / 4); + } + system_serial_high = serial >> 32; + system_serial_low = serial; + + pr_info("Machine: %s, model: %s, serial: %llu\n", mdesc_best->name, + model, serial); /* Retrieve various information from the /chosen node */ of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line); diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 3647170e9a16..13f606d658db 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c @@ -4,6 +4,8 @@ * Copyright (C) 1995-2009 Russell King * Fragments that appear the same as linux/arch/i386/kernel/traps.c (C) Linus Torvalds * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 43a31fb06318..432e112ddf6a 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -1,3 +1,21 @@ +/* + * arch/arm/kernel/vmlinux.lds.S + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + /* ld script to make ARM Linux kernel * taken from the i386 version by Russell King * Written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> diff --git a/arch/arm/mach-tegra/baseband-xmm-power.c b/arch/arm/mach-tegra/baseband-xmm-power.c index 31d39240fd69..a1c6a9c15ebe 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.c +++ b/arch/arm/mach-tegra/baseband-xmm-power.c @@ -77,18 +77,9 @@ static struct gpio tegra_baseband_gpios[] = { { -1, GPIOF_IN, "IPC_HSIC_SUS_REQ" }, }; -static enum { - IPC_AP_WAKE_UNINIT, - IPC_AP_WAKE_IRQ_READY, - IPC_AP_WAKE_INIT1, - IPC_AP_WAKE_INIT2, - IPC_AP_WAKE_L, - IPC_AP_WAKE_H, -} ipc_ap_wake_state; - static enum baseband_xmm_powerstate_t baseband_xmm_powerstate; +static enum ipc_ap_wake_state_t ipc_ap_wake_state; static struct workqueue_struct *workqueue; -static struct work_struct init1_work; static struct work_struct init2_work; static struct work_struct L2_resume_work; static struct work_struct autopm_resume_work; @@ -256,7 +247,6 @@ static int xmm_power_on(struct platform_device *device) /* reset the state machine */ baseband_xmm_powerstate = BBXMM_PS_INIT; modem_sleep_flag = false; - ipc_ap_wake_state = IPC_AP_WAKE_INIT2; pr_debug("%s wake_st(%d) modem version %lu\n", __func__, ipc_ap_wake_state, modem_ver); @@ -264,6 +254,8 @@ static int xmm_power_on(struct platform_device *device) /* register usb host controller */ if (!modem_flash) { pr_debug("%s - %d\n", __func__, __LINE__); + + ipc_ap_wake_state = IPC_AP_WAKE_INIT2; /* register usb host controller only once */ if (register_hsic_device) { pr_debug("%s: register usb host controller\n", @@ -291,7 +283,7 @@ static int xmm_power_on(struct platform_device *device) pr_debug("%s: reset flash modem\n", __func__); modem_power_on = false; - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + ipc_ap_wake_state = IPC_AP_WAKE_IRQ_READY; gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); xmm_power_reset_on(pdata); @@ -552,41 +544,11 @@ void baseband_xmm_set_power_status(unsigned int status) } EXPORT_SYMBOL_GPL(baseband_xmm_set_power_status); -irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) + +irqreturn_t xmm_power_ipc_ap_wake_irq(int value) { struct baseband_power_platform_data *data = xmm_power_drv_data.pdata; struct xmm_power_data *drv = &xmm_power_drv_data; - int value; - - value = gpio_get_value(data->modem.xmm.ipc_ap_wake); - pr_debug("%s g(%d), wake_st(%d)\n", __func__, value, ipc_ap_wake_state); - - /* modem initialization/bootup part*/ - if (unlikely(ipc_ap_wake_state < IPC_AP_WAKE_IRQ_READY)) { - pr_err("%s - spurious irq\n", __func__); - return IRQ_HANDLED; - } else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { - if (!value) { - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - got falling edge\n", __func__); - /* go to IPC_AP_WAKE_INIT1 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; - queue_work(workqueue, &init1_work); - } else - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - wait for falling edge\n", __func__); - return IRQ_HANDLED; - } else if (ipc_ap_wake_state == IPC_AP_WAKE_INIT1) { - if (!value) { - pr_debug("%s - got falling edge at INIT1\n", __func__); - /* go to IPC_AP_WAKE_INIT2 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT2; - queue_work(workqueue, &init2_work); - } else - pr_debug("%s - IPC_AP_WAKE_INIT1" - " - got rising edge\n", __func__); - return IRQ_HANDLED; - } /* modem wakeup part */ if (!value) { @@ -646,41 +608,41 @@ irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id) /* save gpio state */ ipc_ap_wake_state = IPC_AP_WAKE_H; } - return IRQ_HANDLED; } EXPORT_SYMBOL(xmm_power_ipc_ap_wake_irq); -static void xmm_power_init1_work(struct work_struct *work) +static irqreturn_t ipc_ap_wake_irq(int irq, void *dev_id) { - struct baseband_power_platform_data *pdata = xmm_power_drv_data.pdata; + struct baseband_power_platform_data *data = xmm_power_drv_data.pdata; int value; - pr_debug("%s {\n", __func__); - - /* check if IPC_HSIC_ACTIVE high */ - value = gpio_get_value(pdata->modem.xmm.ipc_hsic_active); - if (value != 1) { - pr_err("%s - expected IPC_HSIC_ACTIVE high!\n", __func__); - return; - } - - /* wait 100 ms */ - msleep(100); - - /* set IPC_HSIC_ACTIVE low */ - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 0); - - /* wait 10 ms */ - usleep_range(10000, 11000); - - /* set IPC_HSIC_ACTIVE high */ - gpio_set_value(pdata->modem.xmm.ipc_hsic_active, 1); + value = gpio_get_value(data->modem.xmm.ipc_ap_wake); + pr_debug("%s g(%d), wake_st(%d)\n", __func__, value, ipc_ap_wake_state); - /* wait 20 ms */ - msleep(20); + /* modem wakeup part */ + if (likely(ipc_ap_wake_state >= IPC_AP_WAKE_INIT2)) + return xmm_power_ipc_ap_wake_irq(value); - pr_debug("%s }\n", __func__); + /* modem initialization/bootup part*/ + if (unlikely(ipc_ap_wake_state < IPC_AP_WAKE_IRQ_READY)) { + pr_err("%s - spurious irq\n", __func__); + } else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { + if (value) { + /* make state ready for falling edge */ + ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + pr_debug("%s - got rising edge\n", __func__); + } + } else if (ipc_ap_wake_state == IPC_AP_WAKE_INIT1) { + if (!value) { + pr_debug("%s - got falling edge at INIT1\n", __func__); + /* go to IPC_AP_WAKE_INIT2 state */ + ipc_ap_wake_state = IPC_AP_WAKE_INIT2; + queue_work(workqueue, &init2_work); + } else + pr_debug("%s - unexpected rising edge\n", __func__); + } + return IRQ_HANDLED; } static void xmm_power_init2_work(struct work_struct *work) @@ -960,7 +922,7 @@ static int xmm_power_driver_probe(struct platform_device *device) ipc_ap_wake_state = IPC_AP_WAKE_UNINIT; err = request_threaded_irq( gpio_to_irq(pdata->modem.xmm.ipc_ap_wake), - NULL, xmm_power_ipc_ap_wake_irq, + NULL, ipc_ap_wake_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "IPC_AP_WAKE_IRQ", NULL); if (err < 0) { @@ -973,9 +935,9 @@ static int xmm_power_driver_probe(struct platform_device *device) if (err < 0) pr_err("%s: enable_irq_wake error\n", __func__); - pr_debug("%s: AP_WAKE_INIT1\n", __func__); - /* ver 1130 or later starts in INIT1 state */ - ipc_ap_wake_state = IPC_AP_WAKE_INIT1; + pr_debug("%s: set state IPC_AP_WAKE_IRQ_READY\n", __func__); + /* ver 1130 or later start in IRQ_READY state */ + ipc_ap_wake_state = IPC_AP_WAKE_IRQ_READY; } /* init work queue */ @@ -990,7 +952,6 @@ static int xmm_power_driver_probe(struct platform_device *device) queue_work(workqueue, &xmm_power_drv_data.work); /* init work objects */ - INIT_WORK(&init1_work, xmm_power_init1_work); INIT_WORK(&init2_work, xmm_power_init2_work); INIT_WORK(&L2_resume_work, xmm_power_l2_resume_work); INIT_WORK(&autopm_resume_work, xmm_power_autopm_resume); diff --git a/arch/arm/mach-tegra/baseband-xmm-power.h b/arch/arm/mach-tegra/baseband-xmm-power.h index 69140891319d..b9d85eafda1d 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power.h +++ b/arch/arm/mach-tegra/baseband-xmm-power.h @@ -15,7 +15,7 @@ */ #ifndef BASEBAND_XMM_POWER_H -#define BASREBAND_XMM_POWER_H +#define BASEBAND_XMM_POWER_H #include <linux/pm.h> #include <linux/suspend.h> @@ -102,9 +102,18 @@ enum baseband_xmm_powerstate_t { BBXMM_PS_LAST = -1, }; -irqreturn_t xmm_power_ipc_ap_wake_irq(int irq, void *dev_id); +enum ipc_ap_wake_state_t { + IPC_AP_WAKE_UNINIT, + IPC_AP_WAKE_IRQ_READY, + IPC_AP_WAKE_INIT1, + IPC_AP_WAKE_INIT2, + IPC_AP_WAKE_L, + IPC_AP_WAKE_H, +}; + +irqreturn_t xmm_power_ipc_ap_wake_irq(int value); void baseband_xmm_set_power_status(unsigned int status); extern struct xmm_power_data xmm_power_drv_data; -#endif /* BASREBAND_XMM_POWER_H */ +#endif /* BASEBAND_XMM_POWER_H */ diff --git a/arch/arm/mach-tegra/baseband-xmm-power2.c b/arch/arm/mach-tegra/baseband-xmm-power2.c index 3c6285c0a070..905759dca329 100644 --- a/arch/arm/mach-tegra/baseband-xmm-power2.c +++ b/arch/arm/mach-tegra/baseband-xmm-power2.c @@ -49,16 +49,7 @@ MODULE_PARM_DESC(XYZ, static struct workqueue_struct *workqueue; static bool free_ipc_ap_wake_irq; - -static enum { - IPC_AP_WAKE_UNINIT, - IPC_AP_WAKE_IRQ_READY, - IPC_AP_WAKE_INIT1, - IPC_AP_WAKE_INIT2, - IPC_AP_WAKE_L, - IPC_AP_WAKE_H, -} ipc_ap_wake_state; - +static enum ipc_ap_wake_state_t ipc_ap_wake_state; static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) { @@ -66,8 +57,6 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) struct xmm_power_data *data = dev_id; struct baseband_power_platform_data *pdata = data->pdata; - pr_debug("%s\n", __func__); - /* check for platform data */ if (!pdata) return IRQ_HANDLED; @@ -79,8 +68,8 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) pr_err("%s - spurious irq\n", __func__); else if (ipc_ap_wake_state == IPC_AP_WAKE_IRQ_READY) { if (!value) { - pr_debug("%s: IPC_AP_WAKE_INIT1 got falling edge\n", - __func__); + pr_debug("%s: IPC_AP_WAKE_IRQ_READY got falling edge\n", + __func__); /* go to IPC_AP_WAKE_INIT2 state */ ipc_ap_wake_state = IPC_AP_WAKE_INIT2; /* queue work */ @@ -88,7 +77,7 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) BBXMM_WORK_INIT_FLASHLESS_PM_STEP2; queue_work(workqueue, &data->work); } else - pr_debug("%s: IPC_AP_WAKE_INIT1" + pr_debug("%s: IPC_AP_WAKE_IRQ_READY" " wait for falling edge\n", __func__); } else { if (!value) { @@ -98,7 +87,7 @@ static irqreturn_t xmm_power2_ipc_ap_wake_irq(int irq, void *dev_id) pr_debug("%s - rising\n", __func__); ipc_ap_wake_state = IPC_AP_WAKE_H; } - return xmm_power_ipc_ap_wake_irq(irq, dev_id); + return xmm_power_ipc_ap_wake_irq(value); } return IRQ_HANDLED; diff --git a/arch/arm/mach-tegra/board-aruba-panel.c b/arch/arm/mach-tegra/board-aruba-panel.c index 01ade01a0eb6..2f33d34d6b59 100644 --- a/arch/arm/mach-tegra/board-aruba-panel.c +++ b/arch/arm/mach-tegra/board-aruba-panel.c @@ -50,8 +50,6 @@ static int aruba_backlight_init(struct device *dev) { ret = gpio_direction_output(aruba_bl_enb, 1); if (ret < 0) gpio_free(aruba_bl_enb); - else - tegra_gpio_enable(aruba_bl_enb); return ret; }; diff --git a/arch/arm/mach-tegra/board-aruba-sdhci.c b/arch/arm/mach-tegra/board-aruba-sdhci.c index 26b04a9021e1..cf29137b773f 100644 --- a/arch/arm/mach-tegra/board-aruba-sdhci.c +++ b/arch/arm/mach-tegra/board-aruba-sdhci.c @@ -224,9 +224,6 @@ static int __init aruba_wifi_init(void) gpio_request(ARUBA_WLAN_PWR, "wlan_power"); gpio_request(ARUBA_WLAN_RST, "wlan_rst"); - tegra_gpio_enable(ARUBA_WLAN_PWR); - tegra_gpio_enable(ARUBA_WLAN_RST); - gpio_direction_output(ARUBA_WLAN_PWR, 0); gpio_direction_output(ARUBA_WLAN_RST, 0); diff --git a/arch/arm/mach-tegra/board-aruba-sensors.c b/arch/arm/mach-tegra/board-aruba-sensors.c index f5ba3d761634..34891ae6f6c2 100644 --- a/arch/arm/mach-tegra/board-aruba-sensors.c +++ b/arch/arm/mach-tegra/board-aruba-sensors.c @@ -43,14 +43,12 @@ static void aruba_isl29018_init(void) { - tegra_gpio_enable(ISL29018_IRQ_GPIO); gpio_request(ISL29018_IRQ_GPIO, "isl29018"); gpio_direction_input(ISL29018_IRQ_GPIO); } static void aruba_akm8975_init(void) { - tegra_gpio_enable(AKM8975_IRQ_GPIO); gpio_request(AKM8975_IRQ_GPIO, "akm8975"); gpio_direction_input(AKM8975_IRQ_GPIO); } diff --git a/arch/arm/mach-tegra/board-aruba.c b/arch/arm/mach-tegra/board-aruba.c index 4cb9572afa90..1d09f41d3e09 100644 --- a/arch/arm/mach-tegra/board-aruba.c +++ b/arch/arm/mach-tegra/board-aruba.c @@ -463,14 +463,6 @@ static struct platform_device *aruba_devices[] __initdata = { #endif }; -static void aruba_keys_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(aruba_keys); i++) - tegra_gpio_enable(aruba_keys[i].gpio); -} - static int __init aruba_touch_init(void) { return 0; @@ -523,7 +515,6 @@ static void __init tegra_aruba_init(void) aruba_i2c_init(); aruba_regulator_init(); aruba_touch_init(); - aruba_keys_init(); aruba_usb_init(); aruba_panel_init(); aruba_sensors_init(); diff --git a/arch/arm/mach-tegra/board-cardhu-kbc.c b/arch/arm/mach-tegra/board-cardhu-kbc.c index d83b19e57e57..875b03029967 100644 --- a/arch/arm/mach-tegra/board-cardhu-kbc.c +++ b/arch/arm/mach-tegra/board-cardhu-kbc.c @@ -123,6 +123,17 @@ int __init cardhu_scroll_init(void) .debounce_interval = 10, \ } +#define GPIO_SW_KEY(_id, _gpio, _iswake) \ + { \ + .code = _id, \ + .gpio = _gpio, \ + .active_low = 1, \ + .desc = #_id, \ + .type = EV_SW, \ + .wakeup = _iswake, \ + .debounce_interval = 1, \ + } + #define GPIO_IKEY(_id, _irq, _iswake, _deb) \ { \ .code = _id, \ @@ -166,6 +177,7 @@ static struct gpio_keys_button cardhu_keys_e1291[] = { [4] = GPIO_KEY(KEY_BACK, PQ0, 0), [5] = GPIO_KEY(KEY_MENU, PQ1, 0), [6] = GPIO_IKEY(KEY_POWER, TPS6591X_IRQ_BASE + TPS6591X_INT_PWRON, 1, 100), + [7] = GPIO_SW_KEY(SW_LID, TPS6591X_GPIO_5, 0), }; static struct gpio_keys_button cardhu_keys_e1291_a04[] = { @@ -177,6 +189,7 @@ static struct gpio_keys_button cardhu_keys_e1291_a04[] = { [5] = GPIO_KEY(KEY_MENU, PQ1, 0), [6] = GPIO_KEY(KEY_RESERVED, PV0, 1), [7] = GPIO_IKEY(KEY_POWER, TPS6591X_IRQ_BASE + TPS6591X_INT_PWRON, 1, 100), + [8] = GPIO_SW_KEY(SW_LID, TPS6591X_GPIO_5, 0), }; static struct gpio_keys_platform_data cardhu_keys_e1291_pdata = { diff --git a/arch/arm/mach-tegra/board-cardhu-panel.c b/arch/arm/mach-tegra/board-cardhu-panel.c index e7a1bb0b2741..9595811e3a32 100644 --- a/arch/arm/mach-tegra/board-cardhu-panel.c +++ b/arch/arm/mach-tegra/board-cardhu-panel.c @@ -875,13 +875,9 @@ static int cardhu_dsi_panel_disable(void) } else if (is_panel_218) { gpio_free(cardhu_dsi_pnl_reset); } else if (is_panel_1506) { - tegra_gpio_disable(e1506_bl_enb); gpio_free(e1506_bl_enb); - tegra_gpio_disable(cardhu_dsi_pnl_reset); gpio_free(cardhu_dsi_pnl_reset); - tegra_gpio_disable(e1506_panel_enb); gpio_free(e1506_panel_enb); - tegra_gpio_disable(e1506_dsi_vddio); gpio_free(e1506_dsi_vddio); } return err; @@ -1219,6 +1215,9 @@ static void cardhu_panel_preinit(void) cardhu_disp1_out.n_modes = ARRAY_SIZE(cardhu_panel_modes); cardhu_disp1_out.enable = cardhu_panel_enable; cardhu_disp1_out.disable = cardhu_panel_disable; + /* Set height and width in mm. */ + cardhu_disp1_out.height = 127; + cardhu_disp1_out.width = 216; cardhu_disp1_pdata.fb = &cardhu_fb_data; } else { @@ -1255,9 +1254,13 @@ static void cardhu_panel_preinit(void) cardhu_dsi.n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd_1506); cardhu_dsi.dsi_suspend_cmd = dsi_suspend_cmd_1506; - cardhu_dsi.panel_send_dc_frames = true, + cardhu_dsi.panel_send_dc_frames = true; + cardhu_dsi.suspend_aggr = DSI_HOST_SUSPEND_LV0; cardhu_dsi_fb_data.xres = 720; cardhu_dsi_fb_data.yres = 1280; + /* Set height and width in mm. */ + cardhu_disp1_out.height = 95; + cardhu_disp1_out.width = 53; } cardhu_disp1_pdata.fb = &cardhu_dsi_fb_data; @@ -1317,6 +1320,9 @@ int __init cardhu_panel_init(void) #else cardhu_disp1_out.depth = 24; #endif + /* Set height and width in mm. */ + cardhu_disp1_out.height = 127; + cardhu_disp1_out.width = 203; cardhu_fb_data.xres = 1920; cardhu_fb_data.yres = 1200; @@ -1365,7 +1371,6 @@ skip_lvds: gpio_direction_input(cardhu_hdmi_hpd); #if !(DC_CTRL_MODE & TEGRA_DC_OUT_ONE_SHOT_MODE) - tegra_gpio_enable(e1506_lcd_te); gpio_request(e1506_lcd_te, "lcd_te"); gpio_direction_input(e1506_lcd_te); #endif diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c index 47888944a749..fb1be89a157f 100644 --- a/arch/arm/mach-tegra/board-cardhu-power.c +++ b/arch/arm/mach-tegra/board-cardhu-power.c @@ -539,7 +539,10 @@ static struct regulator_consumer_supply fixed_reg_en_3v3_sys_supply[] = { REGULATOR_SUPPLY("hvdd_pex_pmu", NULL), REGULATOR_SUPPLY("avdd_hdmi", NULL), REGULATOR_SUPPLY("vpp_fuse", NULL), - REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), + REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), REGULATOR_SUPPLY("vdd_ddr_rx", NULL), REGULATOR_SUPPLY("vcore_nand", NULL), REGULATOR_SUPPLY("hvdd_sata", NULL), @@ -1159,25 +1162,30 @@ int __init cardhu_suspend_init(void) if (board_info.fab == BOARD_FAB_A03) cardhu_suspend_data.corereq_high = true; if (board_info.fab < BOARD_FAB_A03) - /* post E1291-A02 revisions WAKE19/USB1-VBUS wake supported */ + /* post E1291-A02 revisions VBUS wake supported */ tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); break; case BOARD_E1198: if (board_info.fab < BOARD_FAB_A02) - /* post E1198-A01 revisions WAKE19/USB1-VBUS wake supported */ + /* post E1198-A01 revisions VBUS wake supported */ tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); break; case BOARD_PM269: case BOARD_PM305: case BOARD_PM311: break; - case BOARD_E1187: - case BOARD_E1186: case BOARD_E1256: case BOARD_E1257: cardhu_suspend_data.cpu_timer = 5000; cardhu_suspend_data.cpu_off_timer = 5000; break; + case BOARD_E1187: + case BOARD_E1186: + /* VBUS repeated wakeup seen on older E1186 boards */ + tegra_disable_wake_source(TEGRA_WAKE_USB1_VBUS); + cardhu_suspend_data.cpu_timer = 5000; + cardhu_suspend_data.cpu_off_timer = 5000; + break; default: break; } diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c index 66876ab262e6..284a0e78b9a1 100644 --- a/arch/arm/mach-tegra/board-cardhu-sdhci.c +++ b/arch/arm/mach-tegra/board-cardhu-sdhci.c @@ -28,7 +28,7 @@ #include <mach/irqs.h> #include <mach/iomap.h> #include <mach/sdhci.h> -#include <mach/gpio-tegra.h> +#include <mach/io_dpd.h> #include "gpio-names.h" #include "board.h" @@ -241,11 +241,31 @@ static int cardhu_wifi_set_carddetect(int val) static int cardhu_wifi_power(int on) { + struct tegra_io_dpd *sd_dpd; + pr_debug("%s: %d\n", __func__, on); + + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * cardhu GPIO WLAN enable is part of SDMMC3 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } gpio_set_value(CARDHU_WLAN_PWR, on); mdelay(100); gpio_set_value(CARDHU_WLAN_RST, on); mdelay(200); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } diff --git a/arch/arm/mach-tegra/board-cardhu.c b/arch/arm/mach-tegra/board-cardhu.c index 37debb70c449..3888f3c382bc 100644 --- a/arch/arm/mach-tegra/board-cardhu.c +++ b/arch/arm/mach-tegra/board-cardhu.c @@ -1041,13 +1041,6 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_xmm_plat_ops, }; #endif @@ -1068,10 +1061,6 @@ void hsic_platform_open(void) gpio_direction_output(hsic_enable_gpio, 0 /* deasserted */); if (!reset_gpio) gpio_direction_output(hsic_reset_gpio, 0 /* asserted */); - if (!enable_gpio) - tegra_gpio_enable(hsic_enable_gpio); - if (!reset_gpio) - tegra_gpio_enable(hsic_reset_gpio); /* keep hsic reset asserted for 1 ms */ udelay(1000); /* enable (power on) hsic */ @@ -1131,13 +1120,6 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_plat_ops, }; @@ -1457,6 +1439,11 @@ static void __init tegra_cardhu_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *cardhu_dt_board_compat[] = { + "nvidia,cardhu", + NULL +}; + MACHINE_START(CARDHU, "cardhu") .atag_offset = 0x100, .soc = &tegra_soc_desc, @@ -1468,4 +1455,5 @@ MACHINE_START(CARDHU, "cardhu") .timer = &tegra_timer, .init_machine = tegra_cardhu_init, .restart = tegra_assert_system_reset, -MACHINE_END + .dt_compat = cardhu_dt_board_compat, +MACHaNE_END diff --git a/arch/arm/mach-tegra/board-cardhu.h b/arch/arm/mach-tegra/board-cardhu.h index d082076eb322..759e69bc1e42 100644 --- a/arch/arm/mach-tegra/board-cardhu.h +++ b/arch/arm/mach-tegra/board-cardhu.h @@ -231,7 +231,7 @@ extern struct tegra_uart_platform_data cardhu_irda_pdata; #define MPU_GYRO_BUS_NUM 2 #define MPU_GYRO_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } #define MPU_ACCEL_NAME "kxtf9" -#define MPU_ACCEL_IRQ_GPIO TEGRA_GPIO_PL1 +#define MPU_ACCEL_IRQ_GPIO 0 /* DISABLE ACCELIRQ: TEGRA_GPIO_PL1 */ #define MPU_ACCEL_ADDR 0x0F #define MPU_ACCEL_BUS_NUM 2 #define MPU_ACCEL_ORIENTATION { 0, -1, 0, -1, 0, 0, 0, 0, -1 } diff --git a/arch/arm/mach-tegra/board-enterprise-pinmux.c b/arch/arm/mach-tegra/board-enterprise-pinmux.c index 71aff6ef4f1f..52da73c434b5 100644 --- a/arch/arm/mach-tegra/board-enterprise-pinmux.c +++ b/arch/arm/mach-tegra/board-enterprise-pinmux.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise-pinmux.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -160,7 +160,6 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { /* SDMMC4 pinmux */ DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), @@ -199,47 +198,7 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(ULPI_DATA5, ULPI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA6, ULPI, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(ULPI_DATA7, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), - DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D0, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D1, SDMMC2, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D2, SDMMC2, NORMAL, NORMAL, INPUT), @@ -250,84 +209,27 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_MCLK, VI, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GMI_AD8, PWM0, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_AD9, NAND, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(GMI_AD10, NAND, NORMAL, NORMAL, OUTPUT), #if IS_EXTERNAL_PWM DEFAULT_PINMUX(GMI_AD11, PWM3, NORMAL, NORMAL, OUTPUT), #endif - DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), - DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(KB_ROW0, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW1, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW2, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_ROW3, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL0, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL1, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL2, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL4, KBC, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(KB_COL5, KBC, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), DEFAULT_PINMUX(CLK_32K_OUT, BLINK, PULL_DOWN, TRISTATE, OUTPUT), DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(CLK1_REQ, DAP, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), -#if 0 /* For HDA realtek Codec */ - DEFAULT_PINMUX(SPDIF_IN, DAP2, PULL_DOWN, NORMAL, INPUT), -#else - DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), -#endif -#if 0 /* For HDA realtek Codec */ - DEFAULT_PINMUX(DAP2_FS, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, HDA, PULL_DOWN, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, HDA, PULL_DOWN, NORMAL, INPUT), -#else - DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), -#endif DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(PEX_L0_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), @@ -340,25 +242,8 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), CEC_PINMUX(HDMI_CEC, CEC, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE), DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, TRISTATE, INPUT), - - /* Gpios */ - /* SDMMC1 CD gpio */ - DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), - /* SDMMC1 WP gpio */ DEFAULT_PINMUX(VI_D11, RSVD1, PULL_UP, NORMAL, INPUT), - - /* Touch panel GPIO */ - /* Touch IRQ */ - DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT), - - /* Touch RESET */ - DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), - DEFAULT_PINMUX(GMI_AD15, NAND, PULL_UP, TRISTATE, INPUT), - - /* Power rails GPIO */ - DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), - VI_PINMUX(VI_D6, VI, NORMAL, NORMAL, OUTPUT, DISABLE, DISABLE), VI_PINMUX(VI_D8, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), VI_PINMUX(VI_D9, SDMMC2, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), @@ -370,6 +255,97 @@ static __initdata struct tegra_pingroup_config enterprise_pinmux_common[] = { static __initdata struct tegra_pingroup_config enterprise_pinmux_a03[] = { DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, OUTPUT), DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, TRISTATE, INPUT), }; static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_common[] = { @@ -430,9 +406,100 @@ static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_common[] DEFAULT_PINMUX(SPI2_MISO, SPI2, PULL_DOWN, TRISTATE, OUTPUT), }; -static __initdata struct tegra_pingroup_config enterprise_unused_pinmux_a02[] = { - DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), - DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), +static __initdata struct tegra_pingroup_config enterprise_pinmux_a02[] = { + DEFAULT_PINMUX(LCD_D10, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_CLK, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_NXT, ULPI, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(ULPI_STP, ULPI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS0_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DC0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_CS1_N, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_M1, DISPLAYA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(LCD_DC1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU0, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, UARTA, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DIN, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PCC2, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV0, RSVD, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DIN, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, I2S0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_FS, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DIN, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, PULL_UP, NORMAL, INPUT), }; static struct tegra_gpio_table gpio_table[] = { @@ -519,6 +586,19 @@ static __initdata struct pin_info_low_power_mode enterprise_unused_gpio_pins_a02 PIN_GPIO_LPM("LCD_PWR0", TEGRA_GPIO_PB2, 0, 0), }; +static __initdata struct pin_info_low_power_mode enterprise_gpio_pins_a03[] = { + PIN_GPIO_LPM("GPIO_PV3", TEGRA_GPIO_PV3, 0, 0), + PIN_GPIO_LPM("LCD_DC0", TEGRA_GPIO_PN6, 0, 0), + PIN_GPIO_LPM("LCD_D5", TEGRA_GPIO_PE5, 0, 0), + PIN_GPIO_LPM("LCD_D20", TEGRA_GPIO_PM4, 0, 0), + PIN_GPIO_LPM("LCD_DC1", TEGRA_GPIO_PD2, 0, 0), + PIN_GPIO_LPM("GPIO_PU4", TEGRA_GPIO_PU4, 0, 0), + PIN_GPIO_LPM("KB_COL3", TEGRA_GPIO_PQ3, 0, 0), + PIN_GPIO_LPM("SPI1_MOSI", TEGRA_GPIO_PX4, 0, 0), + PIN_GPIO_LPM("SPI1_MISO", TEGRA_GPIO_PX7, 0, 0), + PIN_GPIO_LPM("SPI1_SCK", TEGRA_GPIO_PX5, 0, 0), +}; + static void enterprise_set_unused_pin_gpio(struct pin_info_low_power_mode *lpm_pin_info, int list_count) { @@ -569,13 +649,15 @@ int __init enterprise_pinmux_init(void) ARRAY_SIZE(enterprise_unused_gpio_pins_common)); if (board_info.fab < BOARD_FAB_A03) { - tegra_pinmux_config_table(enterprise_unused_pinmux_a02, - ARRAY_SIZE(enterprise_unused_pinmux_a02)); + tegra_pinmux_config_table(enterprise_pinmux_a02, + ARRAY_SIZE(enterprise_pinmux_a02)); enterprise_set_unused_pin_gpio(enterprise_unused_gpio_pins_a02, ARRAY_SIZE(enterprise_unused_gpio_pins_a02)); } else { tegra_pinmux_config_table(enterprise_pinmux_a03, ARRAY_SIZE(enterprise_pinmux_a03)); + enterprise_set_unused_pin_gpio(enterprise_gpio_pins_a03, + ARRAY_SIZE(enterprise_gpio_pins_a03)); } return 0; diff --git a/arch/arm/mach-tegra/board-enterprise-power.c b/arch/arm/mach-tegra/board-enterprise-power.c index 0c35b1aca4dc..857c893b243f 100644 --- a/arch/arm/mach-tegra/board-enterprise-power.c +++ b/arch/arm/mach-tegra/board-enterprise-power.c @@ -234,28 +234,30 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { REGULATOR_SUPPLY("usb_bat_chg", NULL), }; -#define TPS_PDATA_INIT(_id, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ +#define TPS_PDATA_INIT(_reg_id, _id, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, \ _flags, _ectrl, _delay) \ - static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ - .regulator = { \ - .constraints = { \ - .min_uV = (_minmv)*1000, \ - .max_uV = (_maxmv)*1000, \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - .apply_uV = _apply_uv, \ - }, \ - .num_consumer_supplies = \ - ARRAY_SIZE(tps80031_##_id##_supply_##_sname), \ - .consumer_supplies = tps80031_##_id##_supply_##_sname, \ - .supply_regulator = _supply_reg, \ + static struct regulator_init_data reg_idata_##_id##_##_sname = { \ + .constraints = { \ + .name = tps80031_rails(_id), \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + .apply_uV = _apply_uv, \ }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(tps80031_##_id##_supply_##_sname), \ + .consumer_supplies = tps80031_##_id##_supply_##_sname, \ + }; \ + static struct tps80031_regulator_platform_data pdata_##_id##_##_sname = { \ + .reg_init_data = ®_idata_##_id##_##_sname, \ + .regulator_id = TPS80031_REGULATOR_##_reg_id, \ .init_uV = _init_uV * 1000, \ .init_enable = _init_enable, \ .init_apply = _init_apply, \ @@ -264,31 +266,31 @@ static struct regulator_consumer_supply tps80031_battery_charge_supply[] = { .delay_us = _delay, \ } -TPS_PDATA_INIT(vio, a02, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(vio, a03, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(smps1, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ2 | PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo1, a02, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo1, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo2, common, 1000, 3300, 0, 1, 1, 1, 1000, 1, 1, 0, 0, 0); -TPS_PDATA_INIT(ldo3, common, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo4, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo5, common, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(ldo6, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo6, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo7, a02, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldo7, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a02, 1000, 3300, tps80031_rails(SMPS3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldoln, a03, 1000, 3300, tps80031_rails(VIO), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); -TPS_PDATA_INIT(vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); -TPS_PDATA_INIT(vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 1, 0, PWR_OFF_ON_SLEEP, 0); -TPS_PDATA_INIT(vbus, common, 0, 5000, 0, 0, 0, 0, -1, 0, 0, (VBUS_SW_ONLY | VBUS_DISCHRG_EN_PDN), 0, 100000); +TPS_PDATA_INIT(VIO, vio, a02, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(VIO, vio, a03, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(SMPS1, smps1, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ2 | PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(SMPS2, smps2, common, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(SMPS3, smps3, common, 600, 2100, 0, 1, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(SMPS4, smps4, a02, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(SMPS4, smps4, a03, 600, 2100, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO1, ldo1, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO1, ldo1, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO2, ldo2, common, 1000, 1000, 0, 1, 1, 1, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO3, ldo3, common, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(LDO4, ldo4, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO4, ldo4, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO5, ldo5, common, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(LDO6, ldo6, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO6, ldo6, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO7, ldo7, a02, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDO7, ldo7, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOLN, ldoln, a02, 1000, 3300, tps80031_rails(smps3), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOLN, ldoln, a03, 1000, 3300, tps80031_rails(vio), 0, 0, 0, -1, 0, 0, 0, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(LDOUSB, ldousb, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(LDOUSB, ldousb, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, USBLDO_INPUT_VSYS, PWR_REQ_INPUT_PREQ1, 0); +TPS_PDATA_INIT(VANA, vana, a02, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0); +TPS_PDATA_INIT(VANA, vana, a03, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0, PWR_OFF_ON_SLEEP, 0); +TPS_PDATA_INIT(VBUS, vbus, common, 0, 5000, 0, 0, 0, 0, -1, 0, 0, (VBUS_SW_ONLY | VBUS_DISCHRG_EN_PDN), 0, 100000); static struct tps80031_rtc_platform_data rtc_data = { .irq = ENT_TPS80031_IRQ_BASE + TPS80031_INT_RTC_ALARM, @@ -339,12 +341,6 @@ static struct tps80031_bg_platform_data battery_gauge_data = { .platform_data = &rtc_data, \ } -#define TPS_REG(_id, _data, _sname) \ - { \ - .id = TPS80031_ID_##_id, \ - .name = "tps80031-regulator", \ - .platform_data = &pdata_##_data##_##_sname, \ - } #define TPS_BATTERY() \ { \ .name = "tps80031-charger", \ @@ -361,45 +357,56 @@ static struct tps80031_bg_platform_data battery_gauge_data = { } #define TPS80031_DEVS_COMMON \ - TPS_REG(SMPS1, smps1, common), \ - TPS_REG(SMPS2, smps2, common), \ - TPS_REG(SMPS3, smps3, common), \ - TPS_REG(LDO2, ldo2, common), \ - TPS_REG(LDO3, ldo3, common), \ - TPS_REG(LDO5, ldo5, common), \ - TPS_REG(VBUS, vbus, common), \ TPS_RTC(), \ TPS_BATTERY(), \ TPS_BATTERY_GAUGE(), \ TPS_GPADC() -static struct tps80031_subdev_info tps80031_devs_a02[] = { - TPS_REG(VIO, vio, a02), - TPS80031_DEVS_COMMON, - TPS_REG(SMPS4, smps4, a02), - TPS_REG(LDO1, ldo1, a02), - TPS_REG(LDO4, ldo4, a02), - TPS_REG(LDO6, ldo6, a02), - TPS_REG(LDO7, ldo7, a02), - TPS_REG(LDOLN, ldoln, a02), - TPS_REG(LDOUSB, ldousb, a02), - TPS_REG(VANA, vana, a02), - +static struct tps80031_subdev_info tps80031_devs[] = { + TPS_RTC(), + TPS_BATTERY(), + TPS_BATTERY_GAUGE(), + TPS_GPADC() }; -static struct tps80031_subdev_info tps80031_devs_a03[] = { - TPS_REG(VIO, vio, a03), - TPS80031_DEVS_COMMON, - TPS_REG(SMPS4, smps4, a03), - TPS_REG(LDO1, ldo1, a03), - TPS_REG(LDO4, ldo4, a03), - TPS_REG(LDO6, ldo6, a03), - TPS_REG(LDO7, ldo7, a03), - TPS_REG(LDOLN, ldoln, a03), - TPS_REG(LDOUSB, ldousb, a03), - TPS_REG(VANA, vana, a03), - +#define TPS_REG_PDATA(_id, _sname) &pdata_##_id##_##_sname +static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a02[] = { + TPS_REG_PDATA(vio, a02), + TPS_REG_PDATA(smps1, common), + TPS_REG_PDATA(smps2, common), + TPS_REG_PDATA(smps3, common), + TPS_REG_PDATA(ldo2, common), + TPS_REG_PDATA(ldo3, common), + TPS_REG_PDATA(ldo5, common), + TPS_REG_PDATA(vbus, common), + TPS_REG_PDATA(smps4, a02), + TPS_REG_PDATA(ldo1, a02), + TPS_REG_PDATA(ldo4, a02), + TPS_REG_PDATA(ldo6, a02), + TPS_REG_PDATA(ldo7, a02), + TPS_REG_PDATA(ldoln, a02), + TPS_REG_PDATA(ldousb, a02), + TPS_REG_PDATA(vana, a02), +}; + +static struct tps80031_regulator_platform_data *tps80031_reg_pdata_a03[] = { + TPS_REG_PDATA(vio, a03), + TPS_REG_PDATA(smps1, common), + TPS_REG_PDATA(smps2, common), + TPS_REG_PDATA(smps3, common), + TPS_REG_PDATA(ldo2, common), + TPS_REG_PDATA(ldo3, common), + TPS_REG_PDATA(ldo5, common), + TPS_REG_PDATA(vbus, common), + TPS_REG_PDATA(smps4, a03), + TPS_REG_PDATA(ldo1, a03), + TPS_REG_PDATA(ldo4, a03), + TPS_REG_PDATA(ldo6, a03), + TPS_REG_PDATA(ldo7, a03), + TPS_REG_PDATA(ldoln, a03), + TPS_REG_PDATA(ldousb, a03), + TPS_REG_PDATA(vana, a03), }; static struct tps80031_clk32k_init_data clk32k_idata[] = { @@ -595,7 +602,7 @@ static struct gpio gpio_reg_sdmmc3_vdd_sel_gpios[] = { }, \ } -GPIO_REG(4, sdmmc3_vdd_sel, tps80031_rails(SMPS4), +GPIO_REG(4, sdmmc3_vdd_sel, tps80031_rails(smps4), true, false, 0, 1000, 3300); /* Macro for defining fixed regulator sub device data */ @@ -752,14 +759,15 @@ int __init enterprise_regulator_init(void) battery_gauge_data.battery_present = 0; } - tegra_gpio_enable(TEGRA_GPIO_PF7); + tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs); + tps_platform.subdevs = tps80031_devs; if (board_info.fab < BOARD_FAB_A03) { - tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs_a02); - tps_platform.subdevs = tps80031_devs_a02; + tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a02); + tps_platform.regulator_pdata = tps80031_reg_pdata_a02; } else { - tps_platform.num_subdevs = ARRAY_SIZE(tps80031_devs_a03); - tps_platform.subdevs = tps80031_devs_a03; + tps_platform.num_regulator_pdata = ARRAY_SIZE(tps80031_reg_pdata_a03); + tps_platform.regulator_pdata = tps80031_reg_pdata_a03; tps_platform.pupd_init_data = pupd_idata; tps_platform.pupd_init_data_size = ARRAY_SIZE(pupd_idata); tps_platform.gpio_init_data = gpio_idata_a03; diff --git a/arch/arm/mach-tegra/board-enterprise-sdhci.c b/arch/arm/mach-tegra/board-enterprise-sdhci.c index 368e4d824183..d06f6ff82614 100644 --- a/arch/arm/mach-tegra/board-enterprise-sdhci.c +++ b/arch/arm/mach-tegra/board-enterprise-sdhci.c @@ -27,7 +27,7 @@ #include <mach/irqs.h> #include <mach/iomap.h> #include <mach/sdhci.h> -#include <mach/gpio-tegra.h> +#include <mach/io_dpd.h> #include "gpio-names.h" #include "board.h" @@ -220,11 +220,31 @@ static int enterprise_wifi_set_carddetect(int val) static int enterprise_wifi_power(int on) { + struct tegra_io_dpd *sd_dpd; + pr_debug("%s: %d\n", __func__, on); + + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * enterprise GPIO WLAN enable is part of SDMMC1 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device0.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } gpio_set_value(ENTERPRISE_WLAN_PWR, on); mdelay(100); gpio_set_value(ENTERPRISE_WLAN_RST, on); mdelay(200); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } diff --git a/arch/arm/mach-tegra/board-enterprise.c b/arch/arm/mach-tegra/board-enterprise.c index 3b7f90bf6d52..104fcb68aaad 100644 --- a/arch/arm/mach-tegra/board-enterprise.c +++ b/arch/arm/mach-tegra/board-enterprise.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/board-enterprise.c * - * Copyright (c) 2011-2012, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -190,7 +190,6 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = { { "blink", "clk_32k", 32768, true}, { "i2s0", "pll_a_out0", 0, false}, { "i2s1", "pll_a_out0", 0, false}, - { "i2s2", "pll_a_out0", 0, false}, { "i2s3", "pll_a_out0", 0, false}, { "spdif_out", "pll_a_out0", 0, false}, { "d_audio", "clk_m", 12000000, false}, @@ -203,6 +202,19 @@ static __initdata struct tegra_clk_init_table enterprise_clk_init_table[] = { { "audio3", "i2s3_sync", 0, false}, { "vi", "pll_p", 0, false}, { "vi_sensor", "pll_p", 0, false}, + { "i2c5", "pll_p", 3200000, false}, + { NULL, NULL, 0, 0}, +}; + +static __initdata struct tegra_clk_init_table enterprise_clk_i2s2_table[] = { + /* name parent rate enabled */ + { "i2s2", "pll_a_out0", 0, false}, + { NULL, NULL, 0, 0}, +}; + +static __initdata struct tegra_clk_init_table enterprise_clk_i2s4_table[] = { + /* name parent rate enabled */ + { "i2s4", "pll_a_out0", 0, false}, { NULL, NULL, 0, 0}, }; @@ -246,7 +258,7 @@ static struct tegra_i2c_platform_data enterprise_i2c4_platform_data = { static struct tegra_i2c_platform_data enterprise_i2c5_platform_data = { .adapter_nr = 4, .bus_count = 1, - .bus_clk_rate = { 400000, 0 }, + .bus_clk_rate = { 390000, 0 }, .scl_gpio = {TEGRA_GPIO_PZ6, 0}, .sda_gpio = {TEGRA_GPIO_PZ7, 0}, .arb_recovery = arb_lost_recovery, @@ -510,14 +522,24 @@ static struct tegra_asoc_platform_data enterprise_audio_pdata = { .gpio_ext_mic_en = -1, .debounce_time_hp = -1, /*defaults for Enterprise board*/ - .audio_port_id = { - [HIFI_CODEC] = 0, - [BASEBAND] = 2, - [BT_SCO] = 3, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_I2S, + .sample_size = 16, }, - .baseband_param = { - .rate = 8000, - .channels = 1, + .i2s_param[BASEBAND] = { + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, + .rate = 8000, + .channels = 1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = 3, + .is_i2s_master = 1, + .i2s_mode = TEGRA_DAIFMT_DSP_A, + .sample_size = 16, }, }; @@ -715,18 +737,9 @@ static struct tegra_usb_platform_data tegra_ehci2_hsic_xmm_pdata = { .remote_wakeup_supported = false, .power_off_on_suspend = false, }, - .u_cfg.hsic = { - .sync_start_delay = 9, - .idle_wait_delay = 17, - .term_range_adj = 0, - .elastic_underrun_limit = 16, - .elastic_overrun_limit = 16, - }, .ops = &hsic_xmm_plat_ops, }; - - static struct tegra_usb_platform_data tegra_udc_pdata = { .port_otg = true, .has_hostpc = true, @@ -839,7 +852,6 @@ static struct platform_device *enterprise_audio_devices[] __initdata = { &tegra_dam_device2, &tegra_i2s_device0, &tegra_i2s_device1, - &tegra_i2s_device2, &tegra_i2s_device3, &tegra_spdif_device, &spdif_dit_device, @@ -857,7 +869,14 @@ static void enterprise_audio_init(void) tegra_get_board_info(&board_info); if (board_info.board_id == BOARD_E1197) - enterprise_audio_pdata.audio_port_id[HIFI_CODEC] = 1; + enterprise_audio_pdata.i2s_param[HIFI_CODEC].audio_port_id = 1; + else if (board_info.fab == BOARD_FAB_A04) { + enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 4; + platform_device_register(&tegra_i2s_device4); + } else { + enterprise_audio_pdata.i2s_param[BASEBAND].audio_port_id = 2; + platform_device_register(&tegra_i2s_device2); + } platform_add_devices(enterprise_audio_devices, ARRAY_SIZE(enterprise_audio_devices)); @@ -968,6 +987,13 @@ static void enterprise_nfc_init(void) static void __init tegra_enterprise_init(void) { + struct board_info board_info; + tegra_get_board_info(&board_info); + if (board_info.fab == BOARD_FAB_A04) + tegra_clk_init_from_table(enterprise_clk_i2s4_table); + else + tegra_clk_init_from_table(enterprise_clk_i2s2_table); + tegra_thermal_init(&thermal_data, throttle_list, ARRAY_SIZE(throttle_list)); @@ -1010,6 +1036,11 @@ static void __init tegra_enterprise_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *enterprise_dt_board_compat[] = { + "nvidia,enterprise", + NULL +}; + MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise") .atag_offset = 0x100, .soc = &tegra_soc_desc, @@ -1021,4 +1052,5 @@ MACHINE_START(TEGRA_ENTERPRISE, "tegra_enterprise") .timer = &tegra_timer, .init_machine = tegra_enterprise_init, .restart = tegra_assert_system_reset, + .dt_compat = enterprise_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/board-harmony-panel.c b/arch/arm/mach-tegra/board-harmony-panel.c index 932ad0b0b3e8..5856d0bc178c 100644 --- a/arch/arm/mach-tegra/board-harmony-panel.c +++ b/arch/arm/mach-tegra/board-harmony-panel.c @@ -58,8 +58,6 @@ static int harmony_backlight_init(struct device *dev) ret = gpio_direction_output(harmony_bl_enb, 1); if (ret < 0) gpio_free(harmony_bl_enb); - else - tegra_gpio_enable(harmony_bl_enb); return ret; } @@ -338,19 +336,15 @@ int __init harmony_panel_init(void) gpio_request(harmony_en_vdd_pnl, "en_vdd_pnl"); gpio_direction_output(harmony_en_vdd_pnl, 1); - tegra_gpio_enable(harmony_en_vdd_pnl); gpio_request(harmony_bl_vdd, "bl_vdd"); gpio_direction_output(harmony_bl_vdd, 1); - tegra_gpio_enable(harmony_bl_vdd); gpio_request(harmony_lvds_shutdown, "lvds_shdn"); gpio_direction_output(harmony_lvds_shutdown, 1); - tegra_gpio_enable(harmony_lvds_shutdown); gpio_request(harmony_hdmi_hpd, "hdmi_hpd"); gpio_direction_input(harmony_hdmi_hpd); - tegra_gpio_enable(harmony_hdmi_hpd); #if defined(CONFIG_TEGRA_NVMAP) harmony_carveouts[1].base = tegra_carveout_start; diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c index eaac24128240..6f716622c6c3 100644 --- a/arch/arm/mach-tegra/board-harmony.c +++ b/arch/arm/mach-tegra/board-harmony.c @@ -225,14 +225,6 @@ static struct platform_device harmony_gpio_keys_device = { } }; -static void harmony_keys_init(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(harmony_gpio_keys_buttons); i++) - tegra_gpio_enable(harmony_gpio_keys_buttons[i].gpio); -} - static struct tegra_wm8903_platform_data harmony_audio_pdata = { .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, .gpio_hp_det = TEGRA_GPIO_HP_DET, @@ -492,8 +484,6 @@ static int __init harmony_wifi_prepower(void) pr_warning("Unable to get gpio for WLAN Power and Reset\n"); else { - tegra_gpio_enable(TEGRA_GPIO_WLAN_PWR_LOW); - tegra_gpio_enable(TEGRA_GPIO_WLAN_RST_LOW); /* toggle in this order as per spec */ gpio_direction_output(TEGRA_GPIO_WLAN_PWR_LOW, 0); gpio_direction_output(TEGRA_GPIO_WLAN_RST_LOW, 0); @@ -520,8 +510,6 @@ static void __init tegra_harmony_init(void) harmony_pinmux_init(); - harmony_keys_init(); - harmony_uart_init(); tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; diff --git a/arch/arm/mach-tegra/board-kai-sdhci.c b/arch/arm/mach-tegra/board-kai-sdhci.c index 6f35cff27a93..3bfcc0ec1db9 100644 --- a/arch/arm/mach-tegra/board-kai-sdhci.c +++ b/arch/arm/mach-tegra/board-kai-sdhci.c @@ -28,7 +28,7 @@ #include <mach/irqs.h> #include <mach/iomap.h> #include <mach/sdhci.h> -#include <mach/gpio-tegra.h> +#include <mach/io_dpd.h> #include "gpio-names.h" #include "board.h" @@ -202,8 +202,21 @@ static int kai_wifi_set_carddetect(int val) static int kai_wifi_power(int power_on) { + struct tegra_io_dpd *sd_dpd; pr_err("Powering %s wifi\n", (power_on ? "on" : "off")); + /* + * FIXME : we need to revisit IO DPD code + * on how should multiple pins under DPD get controlled + * + * kai GPIO WLAN enable is part of SDMMC3 pin group + */ + sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_disable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } if (power_on) { gpio_set_value(KAI_WLAN_EN, 1); mdelay(15); @@ -214,6 +227,11 @@ static int kai_wifi_power(int power_on) } else { gpio_set_value(KAI_WLAN_EN, 0); } + if (sd_dpd) { + mutex_lock(&sd_dpd->delay_lock); + tegra_io_dpd_enable(sd_dpd); + mutex_unlock(&sd_dpd->delay_lock); + } return 0; } diff --git a/arch/arm/mach-tegra/board-p1852-pinmux.c b/arch/arm/mach-tegra/board-p1852-pinmux.c index 21f310b0ef16..bb28e278dc89 100644 --- a/arch/arm/mach-tegra/board-p1852-pinmux.c +++ b/arch/arm/mach-tegra/board-p1852-pinmux.c @@ -119,13 +119,8 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { SET_DRIVE(GMH, DISABLE, ENABLE, DIV_1, 0, 12, SLOWEST, SLOWEST), /* I2S/TDM */ -#ifdef CONFIG_TEGRA_MODS SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 20, 20, SLOWEST, SLOWEST), -#else - SET_DRIVE(DAP1, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), - SET_DRIVE(DAP3, ENABLE, ENABLE, DIV_1, 3, 3, SLOWEST, SLOWEST), -#endif /* SPI */ SET_DRIVE(UAD, DISABLE, ENABLE, DIV_1, 4, 1, SLOWEST, SLOWEST), @@ -184,6 +179,9 @@ static __initdata struct tegra_drive_pingroup_config p1852_drive_pinmux[] = { } +static __initdata struct tegra_pingroup_config p1852_pinmux_i2s4_master[] = { + DEFAULT_PINMUX(SDMMC4_CLK, NAND, PULL_UP, NORMAL, INPUT), +}; static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { /* SDMMC1 pinmux */ @@ -291,10 +289,10 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), /* DAP3 */ - LVPAD_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), - LVPAD_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_DAT4, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, I2S4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, I2S4, NORMAL, NORMAL, INPUT), /* NOR pinmux */ DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), @@ -427,7 +425,7 @@ static __initdata struct tegra_pingroup_config p1852_pinmux_common[] = { DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT), - LVPAD_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(SDMMC4_CLK, NAND, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(SDMMC3_DAT3, RSVD0, NORMAL, NORMAL, INPUT), DEFAULT_PINMUX(VI_D1, RSVD1, NORMAL, NORMAL, INPUT), @@ -445,6 +443,12 @@ int __init p1852_pinmux_init(void) return 0; } +int p1852_pinmux_set_i2s4_master(void) +{ + tegra_pinmux_config_table(p1852_pinmux_i2s4_master, + ARRAY_SIZE(p1852_pinmux_i2s4_master)); + return 0; +} #define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \ { \ .gpio_nr = _gpio, \ diff --git a/arch/arm/mach-tegra/board-p1852.c b/arch/arm/mach-tegra/board-p1852.c index 751ca49f97ff..e3c017431366 100644 --- a/arch/arm/mach-tegra/board-p1852.c +++ b/arch/arm/mach-tegra/board-p1852.c @@ -199,7 +199,6 @@ static void __init p1852_uart_init(void) platform_add_devices(p1852_uart_devices, ARRAY_SIZE(p1852_uart_devices)); } - #if defined(CONFIG_TEGRA_P1852_TDM) static struct tegra_p1852_platform_data p1852_audio_tdm_pdata = { .codec_info[0] = { @@ -242,6 +241,7 @@ static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = { .name = "tegra-i2s-1", .pcm_driver = "tegra-pcm-audio", .i2s_format = format_i2s, + /* Defines whether the Audio codec chip is master or slave */ .master = 1, }, .codec_info[1] = { @@ -251,6 +251,7 @@ static struct tegra_p1852_platform_data p1852_audio_i2s_pdata = { .name = "tegra-i2s-2", .pcm_driver = "tegra-pcm-audio", .i2s_format = format_i2s, + /* Defines whether the Audio codec chip is master or slave */ .master = 0, }, }; @@ -278,6 +279,8 @@ static struct platform_device tegra_snd_p1852 = { static void p1852_i2s_audio_init(void) { + struct tegra_p1852_platform_data *pdata; + platform_device_register(&tegra_pcm_device); platform_device_register(&tegra_tdm_pcm_device); platform_device_register(&generic_codec_1); @@ -286,6 +289,11 @@ static void p1852_i2s_audio_init(void) platform_device_register(&tegra_i2s_device4); platform_device_register(&tegra_ahub_device); platform_device_register(&tegra_snd_p1852); + + /* Change pinmux of I2S4 for master mode */ + pdata = tegra_snd_p1852.dev.platform_data; + if (!pdata->codec_info[1].master) + p1852_pinmux_set_i2s4_master(); } @@ -450,9 +458,6 @@ static __initdata struct tegra_clk_init_table spi_clk_init_table[] = { static int __init p1852_touch_init(void) { - tegra_gpio_enable(TOUCH_GPIO_IRQ_ATMEL_T9); - tegra_gpio_enable(TOUCH_GPIO_RST_ATMEL_T9); - gpio_request(TOUCH_GPIO_IRQ_ATMEL_T9, "atmel-irq"); gpio_direction_input(TOUCH_GPIO_IRQ_ATMEL_T9); @@ -472,6 +477,32 @@ static int __init p1852_touch_init(void) #endif // CONFIG_TOUCHSCREEN_ATMEL_MXT +#if defined(CONFIG_USB_G_ANDROID) +static struct tegra_usb_platform_data tegra_udc_pdata = { + .port_otg = false, + .has_hostpc = true, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .op_mode = TEGRA_USB_OPMODE_DEVICE, + .u_data.dev = { + .vbus_pmu_irq = 0, + .vbus_gpio = -1, + .charging_supported = false, + .remote_wakeup_supported = false, + }, + .u_cfg.utmi = { + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .elastic_limit = 16, + .term_range_adj = 6, + .xcvr_setup = 63, + .xcvr_setup_offset = 6, + .xcvr_use_fuses = 1, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_use_lsb = 1, + }, +}; +#else static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .port_otg = false, .has_hostpc = true, @@ -497,6 +528,7 @@ static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { .xcvr_use_lsb = 1, }, }; +#endif static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { .port_otg = false, @@ -552,9 +584,16 @@ static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { static void p1852_usb_init(void) { + /* Need to parse sku info to decide host/device mode */ + + /* G_ANDROID require device mode */ +#if defined(CONFIG_USB_G_ANDROID) + tegra_udc_device.dev.platform_data = &tegra_udc_pdata; + platform_device_register(&tegra_udc_device); +#else tegra_ehci1_device.dev.platform_data = &tegra_ehci1_utmi_pdata; platform_device_register(&tegra_ehci1_device); - +#endif tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata; platform_device_register(&tegra_ehci2_device); diff --git a/arch/arm/mach-tegra/board-p1852.h b/arch/arm/mach-tegra/board-p1852.h index 529bd3840e63..7de6a6b358e6 100644 --- a/arch/arm/mach-tegra/board-p1852.h +++ b/arch/arm/mach-tegra/board-p1852.h @@ -100,6 +100,7 @@ int p1852_sdhci_init(void); int p1852_pinmux_init(void); +int p1852_pinmux_set_i2s4_master(void); int p1852_panel_init(void); int p1852_gpio_init(void); int p1852_pins_state_init(void); diff --git a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c index 4bad72f0d931..f9b43447183a 100644 --- a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c +++ b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c @@ -41,11 +41,9 @@ static struct rmi_f19_button_map synaptics_button_map = { static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure) { if (configure) { - tegra_gpio_enable(SYNAPTICS_ATTN_GPIO); gpio_request(SYNAPTICS_ATTN_GPIO, "synaptics-irq"); gpio_direction_input(SYNAPTICS_ATTN_GPIO); - tegra_gpio_enable(SYNAPTICS_RESET_GPIO); gpio_request(SYNAPTICS_RESET_GPIO, "synaptics-reset"); gpio_direction_output(SYNAPTICS_RESET_GPIO, 0); @@ -55,8 +53,6 @@ static int synaptics_touchpad_gpio_setup(void *gpio_data, bool configure) } else { gpio_free(SYNAPTICS_ATTN_GPIO); gpio_free(SYNAPTICS_RESET_GPIO); - tegra_gpio_disable(SYNAPTICS_ATTN_GPIO); - tegra_gpio_disable(SYNAPTICS_RESET_GPIO); } return 0; } diff --git a/arch/arm/mach-tegra/board-touch-raydium_spi.c b/arch/arm/mach-tegra/board-touch-raydium_spi.c index 6fd9f0fee05b..601541838756 100644 --- a/arch/arm/mach-tegra/board-touch-raydium_spi.c +++ b/arch/arm/mach-tegra/board-touch-raydium_spi.c @@ -203,11 +203,9 @@ struct spi_board_info rm31080a_spi_board[1] = { int __init touch_init_raydium(int irq_gpio, int reset_gpio, int platform) { int err = 0; - tegra_gpio_enable(irq_gpio); gpio_request(irq_gpio, "raydium-irq"); gpio_direction_input(irq_gpio); - tegra_gpio_enable(reset_gpio); gpio_request(reset_gpio, "raydium-reset"); gpio_direction_output(reset_gpio, 0); diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c index 3dd44ad9021a..00fc459c6811 100644 --- a/arch/arm/mach-tegra/board-ventana.c +++ b/arch/arm/mach-tegra/board-ventana.c @@ -416,9 +416,6 @@ static struct i2c_board_info __initdata i2c_info[] = { static int __init ventana_touch_init_atmel(void) { i2c_info[0].irq = gpio_to_irq(TEGRA_GPIO_PV6); - tegra_gpio_enable(TEGRA_GPIO_PV6); - tegra_gpio_enable(TEGRA_GPIO_PQ7); - gpio_request(TEGRA_GPIO_PV6, "atmel-irq"); gpio_direction_input(TEGRA_GPIO_PV6); @@ -446,9 +443,6 @@ static struct i2c_board_info __initdata ventana_i2c_bus1_touch_info[] = { static int __init ventana_touch_init_panjit(void) { - tegra_gpio_enable(TEGRA_GPIO_PV6); - tegra_gpio_enable(TEGRA_GPIO_PQ7); - ventana_i2c_bus1_touch_info[0].irq = gpio_to_irq(TEGRA_GPIO_PV6); i2c_register_board_info(0, ventana_i2c_bus1_touch_info, 1); @@ -463,7 +457,6 @@ static int __init ventana_gps_init(void) clk_enable(clk32); } - tegra_gpio_enable(TEGRA_GPIO_PZ3); return 0; } @@ -520,9 +513,6 @@ static void ulpi_link_platform_open(void) gpio_request(reset_gpio, "ulpi_phy_reset"); gpio_direction_output(reset_gpio, 0); - tegra_gpio_enable(reset_gpio); - - gpio_direction_output(reset_gpio, 0); msleep(5); gpio_direction_output(reset_gpio, 1); } @@ -655,6 +645,11 @@ void __init tegra_ventana_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *ventana_dt_board_compat[] = { + "nvidia,ventana", + NULL +}; + MACHINE_START(VENTANA, "ventana") .atag_offset = 0x100, .soc = &tegra_soc_desc, @@ -666,4 +661,5 @@ MACHINE_START(VENTANA, "ventana") .timer = &tegra_timer, .init_machine = tegra_ventana_init, .restart = tegra_assert_system_reset, + .dt_compat = ventana_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c index 33fe75445346..bc83df6b52cb 100644 --- a/arch/arm/mach-tegra/board-whistler.c +++ b/arch/arm/mach-tegra/board-whistler.c @@ -529,6 +529,11 @@ void __init tegra_whistler_reserve(void) tegra_ram_console_debug_reserve(SZ_1M); } +static const char *whistler_dt_board_compat[] = { + "nvidia,whistler", + NULL +}; + MACHINE_START(WHISTLER, "whistler") .atag_offset = 0x100, .soc = &tegra_soc_desc, @@ -540,4 +545,5 @@ MACHINE_START(WHISTLER, "whistler") .timer = &tegra_timer, .init_machine = tegra_whistler_init, .restart = tegra_assert_system_reset, + .dt_compat = whistler_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index bece0b051ea3..9ed65faafebf 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -41,7 +41,7 @@ struct clk; #define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ #ifdef CONFIG_ARCH_TEGRA_3x_SOC -#define PLL_POST_LOCK_DELAY 2 /* Safety delay after lock is detected */ +#define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ #else #define PLL_POST_LOCK_DELAY 10 /* Safety delay after lock is detected */ #endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index ac4536bd0018..a268033be498 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -30,6 +30,7 @@ #include <linux/bitops.h> #include <linux/sched.h> #include <linux/cpufreq.h> +#include <linux/of.h> #include <asm/soc.h> #include <asm/hardware/cache-l2x0.h> @@ -849,11 +850,54 @@ __setup("audio_codec=", tegra_audio_codec_type); void tegra_get_board_info(struct board_info *bi) { - bi->board_id = (system_serial_high >> 16) & 0xFFFF; - bi->sku = (system_serial_high) & 0xFFFF; - bi->fab = (system_serial_low >> 24) & 0xFF; - bi->major_revision = (system_serial_low >> 16) & 0xFF; - bi->minor_revision = (system_serial_low >> 8) & 0xFF; +#ifdef CONFIG_OF + struct device_node *board_info; + u32 prop_val; + int err; + + board_info = of_find_node_by_path("/chosen/board_info"); + if (!IS_ERR_OR_NULL(board_info)) { + memset(bi, 0, sizeof(*bi)); + + err = of_property_read_u32(board_info, "id", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/id\n"); + else + bi->board_id = prop_val; + + err = of_property_read_u32(board_info, "sku", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/sku\n"); + else + bi->sku = prop_val; + + err = of_property_read_u32(board_info, "fab", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/fab\n"); + else + bi->fab = prop_val; + + err = of_property_read_u32(board_info, "major_revision", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/major_revision\n"); + else + bi->major_revision = prop_val; + + err = of_property_read_u32(board_info, "minor_revision", &prop_val); + if (err) + pr_err("failed to read /chosen/board_info/minor_revision\n"); + else + bi->minor_revision = prop_val; + } else { +#endif + bi->board_id = (system_serial_high >> 16) & 0xFFFF; + bi->sku = (system_serial_high) & 0xFFFF; + bi->fab = (system_serial_low >> 24) & 0xFF; + bi->major_revision = (system_serial_low >> 16) & 0xFF; + bi->minor_revision = (system_serial_low >> 8) & 0xFF; +#ifdef CONFIG_OF + } +#endif } static int __init tegra_pmu_board_info(char *info) diff --git a/arch/arm/mach-tegra/cpu-tegra3.c b/arch/arm/mach-tegra/cpu-tegra3.c index 830a66442af5..46e73d8084b9 100644 --- a/arch/arm/mach-tegra/cpu-tegra3.c +++ b/arch/arm/mach-tegra/cpu-tegra3.c @@ -3,7 +3,7 @@ * * CPU auto-hotplug for Tegra3 CPUs * - * Copyright (c) 2011-2012, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,7 +41,7 @@ #define INITIAL_STATE TEGRA_HP_DISABLED #define UP2G0_DELAY_MS 70 #define UP2Gn_DELAY_MS 100 -#define DOWN_DELAY_MS 500 +#define DOWN_DELAY_MS 2000 static struct mutex *tegra3_cpu_lock; @@ -189,10 +189,38 @@ enum { }; #define NR_FSHIFT 2 -static unsigned int nr_run_thresholds[] = { + +static unsigned int rt_profile_sel; + +/* avg run threads * 4 (e.g., 9 = 2.25 threads) */ + +static unsigned int rt_profile_default[] = { /* 1, 2, 3, 4 - on-line cpus target */ - 5, 9, 10, UINT_MAX /* avg run threads * 4 (e.g., 9 = 2.25 threads) */ + 5, 9, 10, UINT_MAX +}; + +static unsigned int rt_profile_1[] = { +/* 1, 2, 3, 4 - on-line cpus target */ + 8, 9, 10, UINT_MAX +}; + +static unsigned int rt_profile_2[] = { +/* 1, 2, 3, 4 - on-line cpus target */ + 5, 13, 14, UINT_MAX +}; + +static unsigned int rt_profile_off[] = { /* disables runable thread */ + 0, 0, 0, UINT_MAX +}; + +static unsigned int *rt_profiles[] = { + rt_profile_default, + rt_profile_1, + rt_profile_2, + rt_profile_off }; + + static unsigned int nr_run_hysteresis = 2; /* 0.5 thread */ static unsigned int nr_run_last; @@ -216,8 +244,10 @@ static noinline int tegra_cpu_speed_balance(void) * TEGRA_CPU_SPEED_BIASED to keep CPU core composition unchanged * TEGRA_CPU_SPEED_SKEWED to remove CPU core off-line */ - for (nr_run = 1; nr_run < ARRAY_SIZE(nr_run_thresholds); nr_run++) { - unsigned int nr_threshold = nr_run_thresholds[nr_run - 1]; + + unsigned int *current_profile = rt_profiles[rt_profile_sel]; + for (nr_run = 1; nr_run < ARRAY_SIZE(rt_profile_default); nr_run++) { + unsigned int nr_threshold = current_profile[nr_run - 1]; if (nr_run_last <= nr_run) nr_threshold += nr_run_hysteresis; if (avg_nr_run <= (nr_threshold << (FSHIFT - NR_FSHIFT))) @@ -527,6 +557,25 @@ static const struct file_operations hp_stats_fops = { .release = single_release, }; +static int rt_bias_get(void *data, u64 *val) +{ + *val = rt_profile_sel; + return 0; +} +static int rt_bias_set(void *data, u64 val) +{ + if (val < ARRAY_SIZE(rt_profiles)) + rt_profile_sel = (u32)val; + + pr_debug("rt_profile_sel set to %d\nthresholds are now [%d, %d, %d]\n", + rt_profile_sel, + rt_profiles[rt_profile_sel][0], + rt_profiles[rt_profile_sel][1], + rt_profiles[rt_profile_sel][2]); + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(rt_bias_fops, rt_bias_get, rt_bias_set, "%llu\n"); + static int min_cpus_get(void *data, u64 *val) { *val = pm_qos_request(PM_QOS_MIN_ONLINE_CPUS); @@ -577,6 +626,10 @@ static int __init tegra_auto_hotplug_debug_init(void) "stats", S_IRUGO, hp_debugfs_root, NULL, &hp_stats_fops)) goto err_out; + if (!debugfs_create_file( + "core_bias", S_IRUGO, hp_debugfs_root, NULL, &rt_bias_fops)) + goto err_out; + return 0; err_out: diff --git a/arch/arm/mach-tegra/dvfs.c b/arch/arm/mach-tegra/dvfs.c index ee535b24bca2..07f9dc8ff643 100644 --- a/arch/arm/mach-tegra/dvfs.c +++ b/arch/arm/mach-tegra/dvfs.c @@ -38,6 +38,7 @@ #include "board.h" #include "clock.h" #include "dvfs.h" +#include "timer.h" #define DVFS_RAIL_STATS_BIN 25 #define DVFS_RAIL_STATS_SCALE 2 @@ -308,6 +309,13 @@ static int dvfs_rail_connect_to_regulator(struct dvfs_rail *rail) rail->reg = reg; } + v = regulator_enable(rail->reg); + if (v < 0) { + pr_err("tegra_dvfs: failed on enabling regulator %s\n, err %d", + rail->reg_id, v); + return v; + } + v = regulator_get_voltage(rail->reg); if (v < 0) { pr_err("tegra_dvfs: failed initial get %s voltage\n", @@ -681,9 +689,13 @@ int __init tegra_dvfs_late_init(void) { bool connected = true; struct dvfs_rail *rail; + int cur_linear_age = tegra_get_linear_age(); mutex_lock(&dvfs_lock); + if (cur_linear_age >= 0) + tegra_dvfs_age_cpu(cur_linear_age); + list_for_each_entry(rail, &dvfs_rail_list, node) if (dvfs_rail_connect_to_regulator(rail)) connected = false; diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h index 5aae43570d28..6a7c6bd40d90 100644 --- a/arch/arm/mach-tegra/dvfs.h +++ b/arch/arm/mach-tegra/dvfs.h @@ -22,7 +22,7 @@ #define _TEGRA_DVFS_H_ #define MAX_DVFS_FREQS 40 -#define DVFS_RAIL_STATS_TOP_BIN 40 +#define DVFS_RAIL_STATS_TOP_BIN 42 struct clk; struct dvfs_rail; @@ -126,11 +126,14 @@ int tegra_cpu_dvfs_alter(int edp_thermal_index, const cpumask_t *cpus, #ifndef CONFIG_ARCH_TEGRA_2x_SOC int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail); int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail); +void tegra_dvfs_age_cpu(int cur_linear_age); #else static inline int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail) { return 0; } static inline int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail) { return 0; } +static inline void tegra_dvfs_age_cpu(int cur_linear_age) +{ return; } #endif #endif diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index 5a9b47e20b17..30e384496c4c 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c @@ -66,6 +66,21 @@ #endif +#define TEGRA_AGE_0_6 0x2cc /*Spare bit 34*/ +#define TEGRA_AGE_1_6 0x308 /*Spare bit 49*/ +#define TEGRA_AGE_0_5 0x2c8 /*Spare bit 33*/ +#define TEGRA_AGE_1_5 0x304 /*Spare bit 48*/ +#define TEGRA_AGE_0_4 0x2c4 /*Spare bit 32*/ +#define TEGRA_AGE_1_4 0x300 /*Spare bit 47*/ +#define TEGRA_AGE_0_3 0x2c0 /*Spare bit 31*/ +#define TEGRA_AGE_1_3 0x2fc /*Spare bit 46*/ +#define TEGRA_AGE_0_2 0x2bc /*Spare bit 30*/ +#define TEGRA_AGE_1_2 0x2f8 /*Spare bit 45*/ +#define TEGRA_AGE_0_1 0x2b8 /*Spare bit 29*/ +#define TEGRA_AGE_1_1 0x2f4 /*Spare bit 44*/ +#define TEGRA_AGE_0_0 0x2b4 /*Spare bit 28*/ +#define TEGRA_AGE_1_0 0x2f0 /*Spare bit 43*/ + struct tegra_id { enum tegra_chipid chipid; unsigned int major, minor, netlist, patch; @@ -187,6 +202,35 @@ int tegra_fuse_get_cpu_iddq_mA(u32 *iddq) } #endif +#define TEGRA_READ_AGE_BIT(n, bit, age) {\ + bit = tegra_fuse_readl(TEGRA_AGE_0_##n);\ + bit |= tegra_fuse_readl(TEGRA_AGE_1_##n);\ + bit = bit << n;\ + age |= bit;\ +} + +int tegra_get_age(void) +{ + int linear_age, age_bit; + linear_age = age_bit = 0; + + TEGRA_READ_AGE_BIT(6, age_bit, linear_age); + TEGRA_READ_AGE_BIT(5, age_bit, linear_age); + TEGRA_READ_AGE_BIT(4, age_bit, linear_age); + TEGRA_READ_AGE_BIT(3, age_bit, linear_age); + TEGRA_READ_AGE_BIT(2, age_bit, linear_age); + TEGRA_READ_AGE_BIT(1, age_bit, linear_age); + TEGRA_READ_AGE_BIT(0, age_bit, linear_age); + + /*Default Aug, 2012*/ + if (linear_age <= 0) + linear_age = 8; + + pr_info("TEGRA: Linear age: %d\n", linear_age); + + return linear_age; +} + unsigned long long tegra_chip_uid(void) { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h index 2e12d91854e0..9a084d8cba02 100644 --- a/arch/arm/mach-tegra/fuse.h +++ b/arch/arm/mach-tegra/fuse.h @@ -50,6 +50,7 @@ int tegra_soc_speedo_id(void); void tegra_init_speedo_data(void); int tegra_cpu_process_id(void); int tegra_core_process_id(void); +int tegra_get_age(void); #ifndef CONFIG_ARCH_TEGRA_2x_SOC int tegra_package_id(void); diff --git a/arch/arm/mach-tegra/i2c_error_recovery.c b/arch/arm/mach-tegra/i2c_error_recovery.c index 3b9bb98e675c..3a9a68268c68 100644 --- a/arch/arm/mach-tegra/i2c_error_recovery.c +++ b/arch/arm/mach-tegra/i2c_error_recovery.c @@ -46,7 +46,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) scl_gpio, ret);
return -EINVAL;;
}
- tegra_gpio_enable(scl_gpio);
ret = gpio_request(sda_gpio, "sda_gpio");
if (ret < 0) {
@@ -54,7 +53,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) sda_gpio, ret);
goto err;
}
- tegra_gpio_enable(sda_gpio);
gpio_direction_input(sda_gpio);
while (retry--) {
@@ -84,9 +82,7 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) }
gpio_free(scl_gpio);
- tegra_gpio_disable(scl_gpio);
gpio_free(sda_gpio);
- tegra_gpio_disable(sda_gpio);
if (likely(recovered_successfully)) {
pr_err("arbitration lost recovered by re-try-count 0x%08x\n",
@@ -99,7 +95,6 @@ int arb_lost_recovery(int scl_gpio, int sda_gpio) err:
gpio_free(scl_gpio);
- tegra_gpio_disable(scl_gpio);
return ret;
}
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index 2c825f0fca63..92b0e07e1f6e 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -25,6 +25,7 @@ #include <linux/pm.h> #include <linux/types.h> #include <drm/drm_fixed.h> +#include <linux/notifier.h> #define TEGRA_MAX_DC 2 #define DC_N_WINDOWS 3 @@ -645,4 +646,8 @@ struct tegra_dc_edid { struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc); void tegra_dc_put_edid(struct tegra_dc_edid *edid); +int tegra_dc_register_flip_notifier(struct notifier_block *nb); +int tegra_dc_unregister_flip_notifier(struct notifier_block *nb); +int tegra_dc_get_panel_sync_rate(void); + #endif diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index 27fd0339f6c5..91eeed3c0365 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/latency_allowance.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -100,6 +100,9 @@ printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__); \ } +/* Bug 995270 */ +#define HACK_LA_FIFO 1 + static struct dentry *latency_debug_dir; struct la_client_info { @@ -387,7 +390,9 @@ int tegra_set_latency_allowance(enum tegra_la_id id, int la_to_set; unsigned long reg_read; unsigned long reg_write; + unsigned int fifo_size_in_atoms; int bytes_per_atom = normal_atom_size; + const int fifo_scale = 4; /* 25% of the FIFO */ struct la_client_info *ci; VALIDATE_ID(id); @@ -397,11 +402,19 @@ int tegra_set_latency_allowance(enum tegra_la_id id, bytes_per_atom = fdc_atom_size; ci = &la_info[id]; + fifo_size_in_atoms = ci->fifo_size_in_atoms; + +#if HACK_LA_FIFO + /* pretend that our FIFO is only as deep as the lowest fullness + * we expect to see */ + if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) + fifo_size_in_atoms /= fifo_scale; +#endif if (bandwidth_in_mbps == 0) { la_to_set = MC_LA_MAX_VALUE; } else { - ideal_la = (ci->fifo_size_in_atoms * bytes_per_atom * 1000) / + ideal_la = (fifo_size_in_atoms * bytes_per_atom * 1000) / (bandwidth_in_mbps * ns_per_tick); la_to_set = ideal_la - (ci->expiration_in_ns/ns_per_tick) - 1; } @@ -412,11 +425,6 @@ int tegra_set_latency_allowance(enum tegra_la_id id, la_to_set = (la_to_set > MC_LA_MAX_VALUE) ? MC_LA_MAX_VALUE : la_to_set; scaling_info[id].actual_la_to_set = la_to_set; - /* until display can use latency allowance scaling, use a more - * aggressive LA setting. Bug 862709 */ - if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) - la_to_set /= 3; - spin_lock(&safety_lock); reg_read = readl(ci->reg_addr); reg_write = (reg_read & ~ci->mask) | diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index 39e2899f018c..ddab299bd3df 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -50,11 +50,13 @@ #define USB_USBSTS_SRI (1 << 7) #define USB_USBSTS_HCH (1 << 12) +#define USB_USBINTR 0x148 + #define USB_ASYNCLISTADDR 0x158 #define USB_TXFILLTUNING 0x164 #define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16) -#define USB_FIFO_TXFILL_MASK 0x1f0000 +#define USB_FIFO_TXFILL_MASK 0x3f0000 #define ULPI_VIEWPORT 0x170 #define ULPI_WAKEUP (1 << 31) @@ -72,6 +74,7 @@ #define USB_PORTSC_PP (1 << 12) #define USB_PORTSC_LS(x) (((x) & 0x3) << 10) #define USB_PORTSC_SUSP (1 << 7) +#define USB_PORTSC_RESUME (1 << 6) #define USB_PORTSC_OCC (1 << 5) #define USB_PORTSC_PEC (1 << 3) #define USB_PORTSC_PE (1 << 2) @@ -280,6 +283,11 @@ #define DBG(stuff...) do {} while (0) #endif +/* define HSIC phy params */ +#define HSIC_SYNC_START_DELAY 9 +#define HSIC_IDLE_WAIT_DELAY 17 +#define HSIC_ELASTIC_UNDERRUN_LIMIT 16 +#define HSIC_ELASTIC_OVERRUN_LIMIT 16 static DEFINE_SPINLOCK(utmip_pad_lock); static int utmip_pad_count; @@ -721,7 +729,8 @@ static int utmi_phy_power_off(struct tegra_usb_phy *phy) val |= USB_PHY_CLK_VALID_INT_ENB; writel(val, base + USB_SUSP_CTRL); } else { - /* Disable PHY clock valid interrupts while going into suspend*/ + /* Disable PHY clock valid interrupts + while going into suspend*/ val = readl(base + USB_SUSP_CTRL); val &= ~USB_PHY_CLK_VALID_INT_ENB; writel(val, base + USB_SUSP_CTRL); @@ -943,7 +952,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RESET, 0, 2500) < 0) { - pr_err("%s: timeout waiting for reset\n", __func__); + pr_err("%s: timeout waiting for reset\n", + __func__); } val = readl(base + USB_USBMODE_REG_OFFSET); @@ -960,7 +970,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) if (usb_phy_reg_status_wait(base + USB_USBCMD, USB_USBCMD_RS, USB_USBCMD_RS, 2500) < 0) { - pr_err("%s: timeout waiting for run bit\n", __func__); + pr_err("%s: timeout waiting for run bit\n", + __func__); } /* Enable Port Power */ @@ -970,7 +981,8 @@ static int utmi_phy_resume(struct tegra_usb_phy *phy) udelay(10); DBG("USB_USBSTS[0x%x] USB_PORTSC[0x%x]\n", - readl(base + USB_USBSTS), readl(base + USB_PORTSC)); + readl(base + USB_USBSTS), + readl(base + USB_PORTSC)); } } else { /* Restoring the pad powers */ @@ -1062,7 +1074,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; - struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); if (phy->phy_clk_on) { @@ -1088,13 +1099,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_SUSP_CTRL); val = readl(base + UTMIP_XCVR_UHSIC_HSRX_CFG0); - val |= UHSIC_IDLE_WAIT(config->idle_wait_delay); - val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit); - val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit); + val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY); + val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT); + val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT); writel(val, base + UTMIP_XCVR_UHSIC_HSRX_CFG0); val = readl(base + UHSIC_HSRX_CFG1); - val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay); + val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY); writel(val, base + UHSIC_HSRX_CFG1); val = readl(base + UHSIC_MISC_CFG0); @@ -1365,7 +1376,7 @@ static int ulpi_link_phy_open(struct tegra_usb_phy *phy) phy->ulpi_vp = otg_ulpi_create(&ulpi_viewport_access_ops, 0); phy->ulpi_vp->io_priv = phy->regs + ULPI_VIEWPORT; - + phy->linkphy_init = true; return err; } @@ -1461,49 +1472,74 @@ static int ulpi_link_phy_power_on(struct tegra_usb_phy *phy) } val = readl(base + USB_SUSP_CTRL); - val |= UHSIC_RESET; - writel(val, base + USB_SUSP_CTRL); - val = readl(base + ULPI_TIMING_CTRL_0); - val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; - writel(val, base + ULPI_TIMING_CTRL_0); + /* Case for lp0 */ + if (!(val & UHSIC_RESET)) { + val |= UHSIC_RESET; + writel(val, base + USB_SUSP_CTRL); - val = readl(base + USB_SUSP_CTRL); - val |= ULPI_PHY_ENABLE; - writel(val, base + USB_SUSP_CTRL); + val = 0; + writel(val, base + ULPI_TIMING_CTRL_1); - val = readl(base + USB_SUSP_CTRL); - val |= USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); + ulpi_set_trimmer(phy); - if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, - USB_PHY_CLK_VALID, 2500)) - pr_err("%s: timeout waiting for phy to stabilize\n", __func__); + val = readl(base + ULPI_TIMING_CTRL_0); + val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP; + writel(val, base + ULPI_TIMING_CTRL_0); +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, TEGRA_TRI_NORMAL); + tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, TEGRA_TRI_NORMAL); +#endif + val = readl(base + USB_SUSP_CTRL); + val |= ULPI_PHY_ENABLE; + writel(val, base + USB_SUSP_CTRL); - if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, USB_CLKEN, - USB_CLKEN, 2500)) - pr_err("%s: timeout waiting for AHB clock\n", __func__); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0) + pr_err("%s: timeout waiting for phy" \ + "to stabilize\n", __func__); - val = readl(base + USB_SUSP_CTRL); - val &= ~USB_SUSP_CLR; - writel(val, base + USB_SUSP_CTRL); + val = readl(base + USB_TXFILLTUNING); + if ((val & USB_FIFO_TXFILL_MASK) != + USB_FIFO_TXFILL_THRES(0x10)) { + val = USB_FIFO_TXFILL_THRES(0x10); + writel(val, base + USB_TXFILLTUNING); + } + } else { + /* Case for auto resume*/ + val = readl(base + USB_SUSP_CTRL); + val |= USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); - val = 0; - writel(val, base + ULPI_TIMING_CTRL_1); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PHY_CLK_VALID, USB_PHY_CLK_VALID, 2500) < 0) + pr_err("%s: timeout waiting for phy" \ + "to stabilize\n", __func__); - ulpi_set_trimmer(phy); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_CLKEN, USB_CLKEN, 2500) < 0) + pr_err("%s: timeout waiting for AHB clock\n", __func__); - /* Fix VbusInvalid due to floating VBUS */ - ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; + val = readl(base + USB_SUSP_CTRL); + val &= ~USB_SUSP_CLR; + writel(val, base + USB_SUSP_CTRL); } + if (phy->linkphy_init) { + /* To be done only incase of coldboot*/ + /* Fix VbusInvalid due to floating VBUS */ + ret = usb_phy_io_write(phy->ulpi_vp, 0x40, 0x08); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } - ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B); - if (ret) { - pr_err("%s: ulpi write failed\n", __func__); - return ret; + ret = usb_phy_io_write(phy->ulpi_vp, 0x80, 0x0B); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return ret; + } + phy->linkphy_init = false; } val = readl(base + USB_PORTSC); @@ -1521,6 +1557,7 @@ static inline void ulpi_link_phy_set_tristate(bool enable) #ifdef CONFIG_ARCH_TEGRA_2x_SOC int tristate = (enable) ? TEGRA_TRI_TRISTATE : TEGRA_TRI_NORMAL; + tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAA, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UAB, tristate); tegra_pinmux_set_tristate(TEGRA_PINGROUP_UDA, tristate); @@ -1546,6 +1583,7 @@ static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; + int ret; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -1554,6 +1592,13 @@ static void ulpi_link_phy_restore_end(struct tegra_usb_phy *phy) writel(val, base + ULPI_TIMING_CTRL_0); ulpi_link_phy_set_tristate(false); + + udelay(10); + ret = usb_phy_io_write(phy->ulpi_vp, 0x55, 0x04); + if (ret) { + pr_err("%s: ulpi write failed\n", __func__); + return; + } } static int ulpi_link_phy_resume(struct tegra_usb_phy *phy) @@ -1573,7 +1618,70 @@ static int ulpi_link_phy_resume(struct tegra_usb_phy *phy) return status; } -static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, bool enable) +static int ulpi_link_phy_pre_resume(struct tegra_usb_phy *phy, + bool remote_wakeup) +{ + int status = 0; + unsigned long val; + void __iomem *base = phy->regs; + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + + val = readl(base + USB_PORTSC); + if (val & USB_PORTSC_RESUME) { + + val = readl(base + USB_USBCMD); + val &= ~USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + + /* detect remote wakeup */ + msleep(20); + + val = readl(base + USB_PORTSC); + + /* Poll until the controller clears RESUME and SUSPEND */ + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_RESUME, 0, 2500)) + pr_err("%s: timeout waiting for RESUME\n", __func__); + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_SUSP, 0, 2500)) + pr_err("%s: timeout waiting for SUSPEND\n", __func__); + + /* Since we skip remote wakeup event, + put controller in suspend again and + resume port later */ + val = readl(base + USB_PORTSC); + val |= USB_PORTSC_SUSP; + writel(val, base + USB_PORTSC); + mdelay(4); + /* Wait until port suspend completes */ + if (usb_phy_reg_status_wait(base + USB_SUSP_CTRL, + USB_PORTSC_SUSP, USB_PORTSC_SUSP, 2500)) + pr_err("%s: timeout waiting for" \ + "PORT_SUSPEND\n", __func__); + + /* Disable interrupts */ + writel(0, base + USB_USBINTR); + /* Clear the run bit to stop SOFs - 2LS WAR */ + val = readl(base + USB_USBCMD); + val &= ~USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + if (usb_phy_reg_status_wait(base + USB_USBSTS, + USB_USBSTS_HCH, USB_USBSTS_HCH, 2000)) { + pr_err("%s: timeout waiting for" \ + "USB_USBSTS_HCH\n", __func__); + } + usb_phy_wait_for_sof(phy); + + val = readl(base + USB_USBCMD); + val |= USB_USBCMD_RS; + writel(val, base + USB_USBCMD); + } + return status; +} + + +static inline void ulpi_pinmux_bypass(struct tegra_usb_phy *phy, + bool enable) { unsigned long val; void __iomem *base = phy->regs; @@ -1806,7 +1914,8 @@ static int ulpi_null_phy_power_on(struct tegra_usb_phy *phy) val = readl(base + ULPIS2S_CTRL); val |= ULPIS2S_ENA; val |= ULPIS2S_SUPPORT_DISCONNECT; - val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) ? 3 : 1); + val |= ULPIS2S_SPARE((phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) + ? 3 : 1); val |= ULPIS2S_PLLU_MASTER_BLASTER60; writel(val, base + ULPIS2S_CTRL); @@ -1920,6 +2029,7 @@ static struct tegra_usb_phy_ops ulpi_link_phy_ops = { .power_off = ulpi_link_phy_power_off, .resume = ulpi_link_phy_resume, .post_suspend = phy_post_suspend, + .pre_resume = ulpi_link_phy_pre_resume, }; static struct tegra_usb_phy_ops ulpi_null_phy_ops = { diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c new file mode 100644 index 000000000000..828a806ff99f --- /dev/null +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -0,0 +1,5489 @@ +/* + * arch/arm/mach-tegra/tegra3_clocks.c + * + * Copyright (C) 2010-2012 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/cpufreq.h> +#include <linux/syscore_ops.h> + +#include <asm/clkdev.h> + +#include <mach/iomap.h> +#include <mach/edp.h> + +#include "clock.h" +#include "fuse.h" +#include "dvfs.h" +#include "pm.h" +#include "sleep.h" +#include "tegra3_emc.h" + +#define RST_DEVICES_L 0x004 +#define RST_DEVICES_H 0x008 +#define RST_DEVICES_U 0x00C +#define RST_DEVICES_V 0x358 +#define RST_DEVICES_W 0x35C +#define RST_DEVICES_SET_L 0x300 +#define RST_DEVICES_CLR_L 0x304 +#define RST_DEVICES_SET_V 0x430 +#define RST_DEVICES_CLR_V 0x434 +#define RST_DEVICES_NUM 5 + +#define CLK_OUT_ENB_L 0x010 +#define CLK_OUT_ENB_H 0x014 +#define CLK_OUT_ENB_U 0x018 +#define CLK_OUT_ENB_V 0x360 +#define CLK_OUT_ENB_W 0x364 +#define CLK_OUT_ENB_SET_L 0x320 +#define CLK_OUT_ENB_CLR_L 0x324 +#define CLK_OUT_ENB_SET_V 0x440 +#define CLK_OUT_ENB_CLR_V 0x444 +#define CLK_OUT_ENB_NUM 5 + +#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) +#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) + +#define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) +#define PERIPH_CLK_TO_RST_REG(c) \ + periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4) +#define PERIPH_CLK_TO_RST_SET_REG(c) \ + periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8) +#define PERIPH_CLK_TO_RST_CLR_REG(c) \ + periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8) + +#define PERIPH_CLK_TO_ENB_REG(c) \ + periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4) +#define PERIPH_CLK_TO_ENB_SET_REG(c) \ + periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8) +#define PERIPH_CLK_TO_ENB_CLR_REG(c) \ + periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8) + +#define CLK_MASK_ARM 0x44 +#define MISC_CLK_ENB 0x48 + +#define OSC_CTRL 0x50 +#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) +#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) +#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) +#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) +#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) +#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) +#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) +#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) +#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) + +#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) +#define OSC_CTRL_PLL_REF_DIV_1 (0<<26) +#define OSC_CTRL_PLL_REF_DIV_2 (1<<26) +#define OSC_CTRL_PLL_REF_DIV_4 (2<<26) + +#define PERIPH_CLK_SOURCE_I2S1 0x100 +#define PERIPH_CLK_SOURCE_EMC 0x19c +#define PERIPH_CLK_SOURCE_OSC 0x1fc +#define PERIPH_CLK_SOURCE_NUM1 \ + ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) + +#define PERIPH_CLK_SOURCE_G3D2 0x3b0 +#define PERIPH_CLK_SOURCE_SE 0x42c +#define PERIPH_CLK_SOURCE_NUM2 \ + ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) + +#define AUDIO_DLY_CLK 0x49c +#define AUDIO_SYNC_CLK_SPDIF 0x4b4 +#define PERIPH_CLK_SOURCE_NUM3 \ + ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) + +#define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ + PERIPH_CLK_SOURCE_NUM2 + \ + PERIPH_CLK_SOURCE_NUM3) + +#define CPU_SOFTRST_CTRL 0x380 + +#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF +#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF +#define PERIPH_CLK_SOURCE_DIV_SHIFT 0 +#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 +#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 +#define PERIPH_CLK_UART_DIV_ENB (1<<24) +#define PERIPH_CLK_VI_SEL_EX_SHIFT 24 +#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) +#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) +#define PERIPH_CLK_DTV_POLARITY_INV (1<<25) + +#define AUDIO_SYNC_SOURCE_MASK 0x0F +#define AUDIO_SYNC_DISABLE_BIT 0x10 +#define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) + +#define PLL_BASE 0x0 +#define PLL_BASE_BYPASS (1<<31) +#define PLL_BASE_ENABLE (1<<30) +#define PLL_BASE_REF_ENABLE (1<<29) +#define PLL_BASE_OVERRIDE (1<<28) +#define PLL_BASE_LOCK (1<<27) +#define PLL_BASE_DIVP_MASK (0x7<<20) +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVN_MASK (0x3FF<<8) +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVM_MASK (0x1F) +#define PLL_BASE_DIVM_SHIFT 0 + +#define PLL_OUT_RATIO_MASK (0xFF<<8) +#define PLL_OUT_RATIO_SHIFT 8 +#define PLL_OUT_OVERRIDE (1<<2) +#define PLL_OUT_CLKEN (1<<1) +#define PLL_OUT_RESET_DISABLE (1<<0) + +#define PLL_MISC(c) \ + (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) +#define PLL_MISC_LOCK_ENABLE(c) \ + (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) + +#define PLL_MISC_DCCON_SHIFT 20 +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) +#define PLL_MISC_VCOCON_SHIFT 0 +#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) +#define PLLD_MISC_CLKENABLE (1<<30) + +#define PLLU_BASE_POST_DIV (1<<20) + +#define PLLD_BASE_DSIB_MUX_SHIFT 25 +#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT) +#define PLLD_BASE_CSI_CLKENABLE (1<<26) +#define PLLD_MISC_DSI_CLKENABLE (1<<30) +#define PLLD_MISC_DIV_RST (1<<23) +#define PLLD_MISC_DCCON_SHIFT 12 + +#define PLLDU_LFCON_SET_DIVN 600 + +/* FIXME: OUT_OF_TABLE_CPCON per pll */ +#define OUT_OF_TABLE_CPCON 0x8 + +#define SUPER_CLK_MUX 0x00 +#define SUPER_STATE_SHIFT 28 +#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) +#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) +#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) +#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) +#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) +#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) +#define SUPER_LP_DIV2_BYPASS (0x1 << 16) +#define SUPER_SOURCE_MASK 0xF +#define SUPER_FIQ_SOURCE_SHIFT 12 +#define SUPER_IRQ_SOURCE_SHIFT 8 +#define SUPER_RUN_SOURCE_SHIFT 4 +#define SUPER_IDLE_SOURCE_SHIFT 0 + +#define SUPER_CLK_DIVIDER 0x04 +#define SUPER_CLOCK_SKIP_ENABLE (0x1 << 31) +#define SUPER_CLOCK_DIV_U71_SHIFT 16 +#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) +#define SUPER_CLOCK_SKIP_MUL_SHIFT 8 +#define SUPER_CLOCK_SKIP_MUL_MASK (0xff << SUPER_CLOCK_SKIP_MUL_SHIFT) +#define SUPER_CLOCK_SKIP_DIV_SHIFT 0 +#define SUPER_CLOCK_SKIP_DIV_MASK (0xff << SUPER_CLOCK_SKIP_DIV_SHIFT) +#define SUPER_CLOCK_SKIP_MASK \ + (SUPER_CLOCK_SKIP_MUL_MASK | SUPER_CLOCK_SKIP_DIV_MASK) +#define SUPER_CLOCK_SKIP_TERM_MAX 256 + +#define BUS_CLK_DISABLE (1<<3) +#define BUS_CLK_DIV_MASK 0x3 + +#define PMC_CTRL 0x0 + #define PMC_CTRL_BLINK_ENB (1 << 7) + +#define PMC_DPD_PADS_ORIDE 0x1c + #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) + +#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 +#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff +#define PMC_BLINK_TIMER_ENB (1 << 15) +#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 +#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff + +#define PMC_PLLP_WB0_OVERRIDE 0xf8 +#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) +#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE (1 << 11) +#define PMC_PLLM_WB0_OVERRIDE 0x1dc +#define PMC_PLLM_WB0_OVERRIDE_DIVP_MASK (0x7<<15) +#define PMC_PLLM_WB0_OVERRIDE_DIVP_SHIFT 15 +#define PMC_PLLM_WB0_OVERRIDE_DIVN_MASK (0x3FF<<5) +#define PMC_PLLM_WB0_OVERRIDE_DIVN_SHIFT 5 +#define PMC_PLLM_WB0_OVERRIDE_DIVM_MASK (0x1F) +#define PMC_PLLM_WB0_OVERRIDE_DIVM_SHIFT 0 + +#define UTMIP_PLL_CFG2 0x488 +#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) +#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) +#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) + +#define UTMIP_PLL_CFG1 0x484 +#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) +#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) +#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) +#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) +#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) + +#define PLLE_BASE_CML_ENABLE (1<<31) +#define PLLE_BASE_ENABLE (1<<30) +#define PLLE_BASE_DIVCML_SHIFT 24 +#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) +#define PLLE_BASE_DIVP_SHIFT 16 +#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT) +#define PLLE_BASE_DIVN_SHIFT 8 +#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT) +#define PLLE_BASE_DIVM_SHIFT 0 +#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT) +#define PLLE_BASE_DIV_MASK \ + (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \ + PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK) +#define PLLE_BASE_DIV(m, n, p, cml) \ + (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \ + ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT)) + +#define PLLE_MISC_SETUP_BASE_SHIFT 16 +#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT) +#define PLLE_MISC_READY (1<<15) +#define PLLE_MISC_LOCK (1<<11) +#define PLLE_MISC_LOCK_ENABLE (1<<9) +#define PLLE_MISC_SETUP_EX_SHIFT 2 +#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT) +#define PLLE_MISC_SETUP_MASK \ + (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK) +#define PLLE_MISC_SETUP_VALUE \ + ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT)) + +#define PLLE_SS_CTRL 0x68 +#define PLLE_SS_INCINTRV_SHIFT 24 +#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) +#define PLLE_SS_INC_SHIFT 16 +#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) +#define PLLE_SS_MAX_SHIFT 0 +#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) +#define PLLE_SS_COEFFICIENTS_MASK \ + (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) +#define PLLE_SS_COEFFICIENTS_12MHZ \ + ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ + (0x24<<PLLE_SS_MAX_SHIFT)) +#define PLLE_SS_DISABLE ((1<<14) | (1<<12) | (1<<11) | (1<<10)) + +#define PLLE_AUX 0x48c +#define PLLE_AUX_PLLP_SEL (1<<2) +#define PLLE_AUX_CML_SATA_ENABLE (1<<1) +#define PLLE_AUX_CML_PCIE_ENABLE (1<<0) + +#define PMC_SATA_PWRGT 0x1ac +#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5) +#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4) + +#define ROUND_DIVIDER_UP 0 +#define ROUND_DIVIDER_DOWN 1 + +/* PLLP default fixed rate in h/w controlled mode */ +#define PLLP_DEFAULT_FIXED_RATE 216000000 + +/* Threshold to engage CPU clock skipper during CPU rate change */ +#define SKIPPER_ENGAGE_RATE 800000000 + +static void tegra3_pllp_init_dependencies(unsigned long pllp_rate); +static int tegra3_clk_shared_bus_update(struct clk *bus); +static int tegra3_emc_relock_set_rate(struct clk *emc, unsigned long old_rate, + unsigned long new_rate, unsigned long new_pll_rate); + +static unsigned long cpu_stay_on_backup_max; +static struct clk *emc_bridge; +static struct clk *cpu_mode_sclk; + +static bool detach_shared_bus; +module_param(detach_shared_bus, bool, 0644); + +static int skipper_delay = 10; +module_param(skipper_delay, int, 0644); + +void tegra3_set_cpu_skipper_delay(int delay) +{ + skipper_delay = delay; +} + +/** +* Structure defining the fields for USB UTMI clocks Parameters. +*/ +struct utmi_clk_param +{ + /* Oscillator Frequency in KHz */ + u32 osc_frequency; + /* UTMIP PLL Enable Delay Count */ + u8 enable_delay_count; + /* UTMIP PLL Stable count */ + u8 stable_count; + /* UTMIP PLL Active delay count */ + u8 active_delay_count; + /* UTMIP PLL Xtal frequency count */ + u8 xtal_freq_count; +}; + +static const struct utmi_clk_param utmi_parameters[] = +{ +/* OSC_FREQUENCY, ENABLE_DLY, STABLE_CNT, ACTIVE_DLY, XTAL_FREQ_CNT */ + {13000000, 0x02, 0x33, 0x05, 0x7F}, + {19200000, 0x03, 0x4B, 0x06, 0xBB}, + {12000000, 0x02, 0x2F, 0x04, 0x76}, + {26000000, 0x04, 0x66, 0x09, 0xFE}, + {16800000, 0x03, 0x41, 0x0A, 0xA4}, +}; + +static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); +static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); +static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); + +#define MISC_GP_HIDREV 0x804 + +/* + * Some peripheral clocks share an enable bit, so refcount the enable bits + * in registers CLK_ENABLE_L, ... CLK_ENABLE_W, and protect refcount updates + * with lock + */ +static DEFINE_SPINLOCK(periph_refcount_lock); +static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; + +#define clk_writel(value, reg) \ + __raw_writel(value, (u32)reg_clk_base + (reg)) +#define clk_readl(reg) \ + __raw_readl((u32)reg_clk_base + (reg)) +#define pmc_writel(value, reg) \ + __raw_writel(value, (u32)reg_pmc_base + (reg)) +#define pmc_readl(reg) \ + __raw_readl((u32)reg_pmc_base + (reg)) +#define chipid_readl() \ + __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV) + +#define clk_writel_delay(value, reg) \ + do { \ + __raw_writel((value), (u32)reg_clk_base + (reg)); \ + udelay(2); \ + } while (0) + + +static inline int clk_set_div(struct clk *c, u32 n) +{ + return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n); +} + +static inline u32 periph_clk_to_reg( + struct clk *c, u32 reg_L, u32 reg_V, int offs) +{ + u32 reg = c->u.periph.clk_num / 32; + BUG_ON(reg >= RST_DEVICES_NUM); + if (reg < 3) { + reg = reg_L + (reg * offs); + } else { + reg = reg_V + ((reg - 3) * offs); + } + return reg; +} + +static int clk_div_x1_get_divider(unsigned long parent_rate, unsigned long rate, + u32 max_x, u32 flags, u32 round_mode) +{ + s64 divider_ux1 = parent_rate; + if (!rate) + return -EINVAL; + + if (!(flags & DIV_U71_INT)) + divider_ux1 *= 2; + + if (round_mode == ROUND_DIVIDER_UP) + divider_ux1 += rate - 1; + do_div(divider_ux1, rate); + + if (flags & DIV_U71_INT) + divider_ux1 *= 2; + + if (divider_ux1 - 2 < 0) + return 0; + + if (divider_ux1 - 2 > max_x) + return -EINVAL; + + return divider_ux1 - 2; +} + +static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, + u32 flags, u32 round_mode) +{ + return clk_div_x1_get_divider(parent_rate, rate, 0xFF, + flags, round_mode); +} + +static int clk_div151_get_divider(unsigned long parent_rate, unsigned long rate, + u32 flags, u32 round_mode) +{ + return clk_div_x1_get_divider(parent_rate, rate, 0xFFFF, + flags, round_mode); +} + +static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) +{ + s64 divider_u16; + + divider_u16 = parent_rate; + if (!rate) + return -EINVAL; + divider_u16 += rate - 1; + do_div(divider_u16, rate); + + if (divider_u16 - 1 < 0) + return 0; + + if (divider_u16 - 1 > 0xFFFF) + return -EINVAL; + + return divider_u16 - 1; +} + +/* clk_m functions */ +static unsigned long tegra3_clk_m_autodetect_rate(struct clk *c) +{ + u32 osc_ctrl = clk_readl(OSC_CTRL); + u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; + u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; + + c->rate = tegra_clk_measure_input_freq(); + switch (c->rate) { + case 12000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); + break; + case 13000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); + break; + case 19200000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); + break; + case 26000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); + break; + case 16800000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); + break; + case 38400000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); + break; + case 48000000: + auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; + BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); + break; + default: + pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); + BUG(); + } + clk_writel(auto_clock_control, OSC_CTRL); + return c->rate; +} + +static void tegra3_clk_m_init(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + tegra3_clk_m_autodetect_rate(c); +} + +static int tegra3_clk_m_enable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + return 0; +} + +static void tegra3_clk_m_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + WARN(1, "Attempting to disable main SoC clock\n"); +} + +static struct clk_ops tegra_clk_m_ops = { + .init = tegra3_clk_m_init, + .enable = tegra3_clk_m_enable, + .disable = tegra3_clk_m_disable, +}; + +static struct clk_ops tegra_clk_m_div_ops = { + .enable = tegra3_clk_m_enable, +}; + +/* PLL reference divider functions */ +static void tegra3_pll_ref_init(struct clk *c) +{ + u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; + pr_debug("%s on clock %s\n", __func__, c->name); + + switch (pll_ref_div) { + case OSC_CTRL_PLL_REF_DIV_1: + c->div = 1; + break; + case OSC_CTRL_PLL_REF_DIV_2: + c->div = 2; + break; + case OSC_CTRL_PLL_REF_DIV_4: + c->div = 4; + break; + default: + pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); + BUG(); + } + c->mul = 1; + c->state = ON; +} + +static struct clk_ops tegra_pll_ref_ops = { + .init = tegra3_pll_ref_init, + .enable = tegra3_clk_m_enable, + .disable = tegra3_clk_m_disable, +}; + +/* super clock functions */ +/* "super clocks" on tegra3 have two-stage muxes, fractional 7.1 divider and + * clock skipping super divider. We will ignore the clock skipping divider, + * since we can't lower the voltage when using the clock skip, but we can if + * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock + * only when its parent is a fixed rate PLL, since we can't change PLL rate + * in this case. + */ +static void tegra3_super_clk_init(struct clk *c) +{ + u32 val; + int source; + int shift; + const struct clk_mux_sel *sel; + + val = clk_readl(c->reg + SUPER_CLK_MUX); + c->state = ON; + BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && + ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); + shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? + SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; + source = (val >> shift) & SUPER_SOURCE_MASK; + if (c->flags & DIV_2) + source |= val & SUPER_LP_DIV2_BYPASS; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->value == source) + break; + } + BUG_ON(sel->input == NULL); + c->parent = sel->input; + + if (c->flags & DIV_U71) { + /* Init safe 7.1 divider value (does not affect PLLX path). + Super skipper is enabled to be ready for emergency throttle, + but set 1:1 */ + c->mul = 2; + c->div = 2; + if (!(c->parent->flags & PLLX)) { + val = clk_readl(c->reg + SUPER_CLK_DIVIDER); + val &= SUPER_CLOCK_DIV_U71_MASK; + val >>= SUPER_CLOCK_DIV_U71_SHIFT; + val = max(val, c->u.cclk.div71); + c->u.cclk.div71 = val; + c->div += val; + } + val = SUPER_CLOCK_SKIP_ENABLE + + (c->u.cclk.div71 << SUPER_CLOCK_DIV_U71_SHIFT); + clk_writel(val, c->reg + SUPER_CLK_DIVIDER); + } + else + clk_writel(0, c->reg + SUPER_CLK_DIVIDER); +} + +static int tegra3_super_clk_enable(struct clk *c) +{ + return 0; +} + +static void tegra3_super_clk_disable(struct clk *c) +{ + /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and + geared up g-mode super clock - mode switch may request to disable + either of them; accept request with no affect on h/w */ +} + +static int tegra3_super_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + int shift; + + val = clk_readl(c->reg + SUPER_CLK_MUX);; + BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && + ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); + shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? + SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + /* For LP mode super-clock switch between PLLX direct + and divided-by-2 outputs is allowed only when other + than PLLX clock source is current parent */ + if ((c->flags & DIV_2) && (p->flags & PLLX) && + ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) { + if (c->parent->flags & PLLX) + return -EINVAL; + val ^= SUPER_LP_DIV2_BYPASS; + clk_writel_delay(val, c->reg); + } + val &= ~(SUPER_SOURCE_MASK << shift); + val |= (sel->value & SUPER_SOURCE_MASK) << shift; + + /* 7.1 divider for CPU super-clock does not affect + PLLX path */ + if (c->flags & DIV_U71) { + u32 div = 0; + if (!(p->flags & PLLX)) { + div = clk_readl(c->reg + + SUPER_CLK_DIVIDER); + div &= SUPER_CLOCK_DIV_U71_MASK; + div >>= SUPER_CLOCK_DIV_U71_SHIFT; + } + c->div = div + 2; + c->mul = 2; + } + + if (c->refcnt) + clk_enable(p); + + clk_writel_delay(val, c->reg); + + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + return 0; + } + } + return -EINVAL; +} + +static DEFINE_SPINLOCK(super_divider_lock); + +static void tegra3_super_clk_divider_update(struct clk *c, u8 div) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&super_divider_lock, flags); + val = clk_readl(c->reg + SUPER_CLK_DIVIDER); + val &= ~SUPER_CLOCK_DIV_U71_MASK; + val |= div << SUPER_CLOCK_DIV_U71_SHIFT; + clk_writel(val, c->reg + SUPER_CLK_DIVIDER); + spin_unlock_irqrestore(&super_divider_lock, flags); + udelay(2); +} + +static void tegra3_super_clk_skipper_update(struct clk *c, u8 mul, u8 div) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&super_divider_lock, flags); + val = clk_readl(c->reg + SUPER_CLK_DIVIDER); + + /* multiplier or divider value = the respective field + 1 */ + if (mul && div) { + u32 old_mul = ((val & SUPER_CLOCK_SKIP_MUL_MASK) >> + SUPER_CLOCK_SKIP_MUL_SHIFT) + 1; + u32 old_div = ((val & SUPER_CLOCK_SKIP_DIV_MASK) >> + SUPER_CLOCK_SKIP_DIV_SHIFT) + 1; + + if (mul >= div) { + /* improper fraction is only used to reciprocate the + previous proper one - the division below is exact */ + old_mul /= div; + old_div /= mul; + } else { + old_mul *= mul; + old_div *= div; + } + mul = (old_mul <= SUPER_CLOCK_SKIP_TERM_MAX) ? + old_mul : SUPER_CLOCK_SKIP_TERM_MAX; + div = (old_div <= SUPER_CLOCK_SKIP_TERM_MAX) ? + old_div : SUPER_CLOCK_SKIP_TERM_MAX; + } + + if (!mul || (mul >= div)) { + mul = 1; + div = 1; + } + val &= ~SUPER_CLOCK_SKIP_MASK; + val |= SUPER_CLOCK_SKIP_ENABLE | + ((mul - 1) << SUPER_CLOCK_SKIP_MUL_SHIFT) | + ((div - 1) << SUPER_CLOCK_SKIP_DIV_SHIFT); + + clk_writel(val, c->reg + SUPER_CLK_DIVIDER); + spin_unlock_irqrestore(&super_divider_lock, flags); +} + +/* + * Do not use super clocks "skippers", since dividing using a clock skipper + * does not allow the voltage to be scaled down. Instead adjust the rate of + * the parent clock. This requires that the parent of a super clock have no + * other children, otherwise the rate will change underneath the other + * children. Special case: if fixed rate PLL is CPU super clock parent the + * rate of this PLL can't be changed, and it has many other children. In + * this case use 7.1 fractional divider to adjust the super clock rate. + */ +static int tegra3_super_clk_set_rate(struct clk *c, unsigned long rate) +{ + if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) { + int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate, + rate, c->flags, ROUND_DIVIDER_DOWN); + if (div < 0) + return div; + + tegra3_super_clk_divider_update(c, div); + c->u.cclk.div71 = div; + c->div = div + 2; + c->mul = 2; + return 0; + } + return clk_set_rate(c->parent, rate); +} + +static struct clk_ops tegra_super_ops = { + .init = tegra3_super_clk_init, + .enable = tegra3_super_clk_enable, + .disable = tegra3_super_clk_disable, + .set_parent = tegra3_super_clk_set_parent, + .set_rate = tegra3_super_clk_set_rate, +}; + +static int tegra3_twd_clk_set_rate(struct clk *c, unsigned long rate) +{ + /* The input value 'rate' is the clock rate of the CPU complex. */ + c->rate = (rate * c->mul) / c->div; + return 0; +} + +static struct clk_ops tegra3_twd_ops = { + .set_rate = tegra3_twd_clk_set_rate, +}; + +static struct clk tegra3_clk_twd = { + /* NOTE: The twd clock must have *NO* parent. It's rate is directly + updated by tegra3_cpu_cmplx_clk_set_rate() because the + frequency change notifer for the twd is called in an + atomic context which cannot take a mutex. */ + .name = "twd", + .ops = &tegra3_twd_ops, + .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */ + .mul = 1, + .div = 2, +}; + +/* virtual cpu clock functions */ +/* some clocks can not be stopped (cpu, memory bus) while the SoC is running. + To change the frequency of these clocks, the parent pll may need to be + reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, + and then the clock moved back to the pll. Clock skipper maybe temporarily + engaged during the switch to limit frequency jumps. To hide this sequence, + a virtual clock handles it. + */ +static void tegra3_cpu_clk_init(struct clk *c) +{ + c->state = (!is_lp_cluster() == (c->u.cpu.mode == MODE_G))? ON : OFF; +} + +static int tegra3_cpu_clk_enable(struct clk *c) +{ + return 0; +} + +static void tegra3_cpu_clk_disable(struct clk *c) +{ + /* since tegra 3 has 2 virtual CPU clocks - low power lp-mode clock + and geared up g-mode clock - mode switch may request to disable + either of them; accept request with no affect on h/w */ +} + +static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret = 0; + bool skipped = false; + bool skip = (c->u.cpu.mode == MODE_G) && skipper_delay; + bool skip_from_backup = skip && (rate >= SKIPPER_ENGAGE_RATE); + bool skip_to_backup = + skip && (clk_get_rate_all_locked(c) >= SKIPPER_ENGAGE_RATE); + + if (c->dvfs) { + if (!c->dvfs->dvfs_rail) + return -ENOSYS; + else if ((!c->dvfs->dvfs_rail->reg) && + (clk_get_rate_locked(c) < rate)) { + WARN(1, "Increasing CPU rate while regulator is not" + " ready may overclock CPU\n"); + return -ENOSYS; + } + } + + /* + * Take an extra reference to the main pll so it doesn't turn + * off when we move the cpu off of it + */ + clk_enable(c->u.cpu.main); + + if (c->parent->parent != c->u.cpu.backup) { + if (skip_to_backup) { + /* on G CPU use 1/2 skipper step for main <=> backup */ + skipped = true; + tegra3_super_clk_skipper_update(c->parent, 1, 2); + udelay(skipper_delay); + } + + ret = clk_set_parent(c->parent, c->u.cpu.backup); + if (ret) { + pr_err("Failed to switch cpu to clock %s\n", + c->u.cpu.backup->name); + goto out; + } + + if (skipped && !skip_from_backup) { + skipped = false; + tegra3_super_clk_skipper_update(c->parent, 2, 1); + } + } + + if (rate <= cpu_stay_on_backup_max) { + ret = clk_set_rate(c->parent, rate); + if (ret) + pr_err("Failed to set cpu rate %lu on backup source\n", + rate); + goto out; + } else { + ret = clk_set_rate(c->parent, c->u.cpu.backup_rate); + if (ret) { + pr_err("Failed to set cpu rate %lu on backup source\n", + c->u.cpu.backup_rate); + goto out; + } + } + + if (rate != clk_get_rate(c->u.cpu.main)) { + ret = clk_set_rate(c->u.cpu.main, rate); + if (ret) { + pr_err("Failed to change cpu pll to %lu\n", rate); + goto out; + } + } + + if (!skipped && skip_from_backup) { + skipped = true; + tegra3_super_clk_skipper_update(c->parent, 1, 2); + } + + ret = clk_set_parent(c->parent, c->u.cpu.main); + if (ret) { + pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name); + goto out; + } + +out: + if (skipped) { + udelay(skipper_delay); + tegra3_super_clk_skipper_update(c->parent, 2, 1); + } + clk_disable(c->u.cpu.main); + return ret; +} + +static struct clk_ops tegra_cpu_ops = { + .init = tegra3_cpu_clk_init, + .enable = tegra3_cpu_clk_enable, + .disable = tegra3_cpu_clk_disable, + .set_rate = tegra3_cpu_clk_set_rate, +}; + + +static void tegra3_cpu_cmplx_clk_init(struct clk *c) +{ + int i = !!is_lp_cluster(); + + BUG_ON(c->inputs[0].input->u.cpu.mode != MODE_G); + BUG_ON(c->inputs[1].input->u.cpu.mode != MODE_LP); + c->parent = c->inputs[i].input; +} + +/* cpu complex clock provides second level vitualization (on top of + cpu virtual cpu rate control) in order to hide the CPU mode switch + sequence */ +#if PARAMETERIZE_CLUSTER_SWITCH +static unsigned int switch_delay; +static unsigned int switch_flags; +static DEFINE_SPINLOCK(parameters_lock); + +void tegra_cluster_switch_set_parameters(unsigned int us, unsigned int flags) +{ + spin_lock(¶meters_lock); + switch_delay = us; + switch_flags = flags; + spin_unlock(¶meters_lock); +} +#endif + +static int tegra3_cpu_cmplx_clk_enable(struct clk *c) +{ + return 0; +} + +static void tegra3_cpu_cmplx_clk_disable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + + /* oops - don't disable the CPU complex clock! */ + BUG(); +} + +static int tegra3_cpu_cmplx_clk_set_rate(struct clk *c, unsigned long rate) +{ + unsigned long flags; + int ret; + struct clk *parent = c->parent; + + if (!parent->ops || !parent->ops->set_rate) + return -ENOSYS; + + clk_lock_save(parent, &flags); + + ret = clk_set_rate_locked(parent, rate); + + /* We can't parent the twd to directly to the CPU complex because + the TWD frequency update notifier is called in an atomic context + and the CPU frequency update requires a mutex. Update the twd + clock rate with the new CPU complex rate. */ + clk_set_rate(&tegra3_clk_twd, clk_get_rate_locked(parent)); + + clk_unlock_restore(parent, &flags); + + return ret; +} + +static int tegra3_cpu_cmplx_clk_set_parent(struct clk *c, struct clk *p) +{ + int ret; + unsigned int flags, delay; + const struct clk_mux_sel *sel; + unsigned long rate = clk_get_rate(c->parent); + + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + BUG_ON(c->parent->u.cpu.mode != (is_lp_cluster() ? MODE_LP : MODE_G)); + + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) + break; + } + if (!sel->input) + return -EINVAL; + +#if PARAMETERIZE_CLUSTER_SWITCH + spin_lock(¶meters_lock); + flags = switch_flags; + delay = switch_delay; + switch_flags = 0; + spin_unlock(¶meters_lock); + + if (flags) { + /* over/under-clocking after switch - allow, but update rate */ + if ((rate > p->max_rate) || (rate < p->min_rate)) { + unsigned long fl; + + rate = rate > p->max_rate ? p->max_rate : p->min_rate; + ret = clk_set_rate(c->parent, rate); + if (ret) { + pr_err("%s: Failed to set rate %lu for %s\n", + __func__, rate, p->name); + return ret; + } + clk_lock_save(c->parent, &fl); + clk_set_rate(&tegra3_clk_twd, + clk_get_rate_locked(c->parent)); + clk_unlock_restore(c->parent, &fl); + } + } else +#endif + { + if (p == c->parent) /* already switched - exit*/ + return 0; + + if (rate > p->max_rate) { /* over-clocking - no switch */ + pr_warn("%s: No %s mode switch to %s at rate %lu\n", + __func__, c->name, p->name, rate); + return -ECANCELED; + } + flags = TEGRA_POWER_CLUSTER_IMMEDIATE; + delay = 0; + } + flags |= (p->u.cpu.mode == MODE_LP) ? TEGRA_POWER_CLUSTER_LP : + TEGRA_POWER_CLUSTER_G; + + clk_enable(cpu_mode_sclk); /* set SCLK floor for cluster switch */ + + /* Since in both LP and G mode CPU main and backup sources are the + same, set rate on the new parent just synchronizes super-clock + muxes before mode switch with no PLL re-locking */ + ret = clk_set_rate(p, rate); + if (ret) { + pr_err("%s: Failed to set rate %lu for %s\n", + __func__, rate, p->name); + clk_disable(cpu_mode_sclk); + return ret; + } + + /* Enabling new parent scales new mode voltage rail in advanvce + before the switch happens*/ + if (c->refcnt) + clk_enable(p); + + /* switch CPU mode */ + ret = tegra_cluster_control(delay, flags); + if (ret) { + if (c->refcnt) + clk_disable(p); + pr_err("%s: Failed to switch %s mode to %s\n", + __func__, c->name, p->name); + clk_disable(cpu_mode_sclk); + return ret; + } + + /* Disabling old parent scales old mode voltage rail */ + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + clk_disable(cpu_mode_sclk); + return 0; +} + +static long tegra3_cpu_cmplx_round_rate(struct clk *c, + unsigned long rate) +{ + if (rate > c->parent->max_rate) + rate = c->parent->max_rate; + else if (rate < c->parent->min_rate) + rate = c->parent->min_rate; + return rate; +} + +static struct clk_ops tegra_cpu_cmplx_ops = { + .init = tegra3_cpu_cmplx_clk_init, + .enable = tegra3_cpu_cmplx_clk_enable, + .disable = tegra3_cpu_cmplx_clk_disable, + .set_rate = tegra3_cpu_cmplx_clk_set_rate, + .set_parent = tegra3_cpu_cmplx_clk_set_parent, + .round_rate = tegra3_cpu_cmplx_round_rate, +}; + +/* virtual cop clock functions. Used to acquire the fake 'cop' clock to + * reset the COP block (i.e. AVP) */ +static void tegra3_cop_clk_reset(struct clk *c, bool assert) +{ + unsigned long reg = assert ? RST_DEVICES_SET_L : RST_DEVICES_CLR_L; + + pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); + clk_writel(1 << 1, reg); +} + +static struct clk_ops tegra_cop_ops = { + .reset = tegra3_cop_clk_reset, +}; + +/* bus clock functions */ +static void tegra3_bus_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; + c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; + c->mul = 1; +} + +static int tegra3_bus_clk_enable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + val &= ~(BUS_CLK_DISABLE << c->reg_shift); + clk_writel(val, c->reg); + return 0; +} + +static void tegra3_bus_clk_disable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + val |= BUS_CLK_DISABLE << c->reg_shift; + clk_writel(val, c->reg); +} + +static int tegra3_bus_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val = clk_readl(c->reg); + unsigned long parent_rate = clk_get_rate(c->parent); + int i; + for (i = 1; i <= 4; i++) { + if (rate >= parent_rate / i) { + val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); + val |= (i - 1) << c->reg_shift; + clk_writel(val, c->reg); + c->div = i; + c->mul = 1; + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_bus_ops = { + .init = tegra3_bus_clk_init, + .enable = tegra3_bus_clk_enable, + .disable = tegra3_bus_clk_disable, + .set_rate = tegra3_bus_clk_set_rate, +}; + +/* Virtual system bus complex clock is used to hide the sequence of + changing sclk/hclk/pclk parents and dividers to configure requested + sclk target rate. */ +static void tegra3_sbus_cmplx_init(struct clk *c) +{ + unsigned long rate; + + c->max_rate = c->parent->max_rate; + c->min_rate = c->parent->min_rate; + + /* Threshold must be an exact proper factor of low range parent, + and both low/high range parents have 7.1 fractional dividers */ + rate = clk_get_rate(c->u.system.sclk_low->parent); + if (c->u.system.threshold) { + BUG_ON(c->u.system.threshold > rate) ; + BUG_ON((rate % c->u.system.threshold) != 0); + } + BUG_ON(!(c->u.system.sclk_low->flags & DIV_U71)); + BUG_ON(!(c->u.system.sclk_high->flags & DIV_U71)); +} + +/* This special sbus round function is implemented because: + * + * (a) fractional dividers can not be used to derive system bus clock with one + * exception: 1 : 2.5 divider is allowed at 1.2V and above (and we do need this + * divider to reach top sbus frequencies from high frequency source). + * + * (b) since sbus is a shared bus, and its frequency is set to the highest + * enabled shared_bus_user clock, the target rate should be rounded up divider + * ladder (if max limit allows it) - for pll_div and peripheral_div common is + * rounding down - special case again. + * + * Note that final rate is trimmed (not rounded up) to avoid spiraling up in + * recursive calls. Lost 1Hz is added in tegra3_sbus_cmplx_set_rate before + * actually setting divider rate. + */ +static unsigned long sclk_high_2_5_rate; +static bool sclk_high_2_5_valid; + +static long tegra3_sbus_cmplx_round_rate(struct clk *c, unsigned long rate) +{ + int i, divider; + unsigned long source_rate, round_rate; + struct clk *new_parent; + + rate = max(rate, c->min_rate); + + if (!sclk_high_2_5_rate) { + source_rate = clk_get_rate(c->u.system.sclk_high->parent); + sclk_high_2_5_rate = 2 * source_rate / 5; + i = tegra_dvfs_predict_millivolts(c, sclk_high_2_5_rate); + if (!IS_ERR_VALUE(i) && (i >= 1200) && + (sclk_high_2_5_rate <= c->max_rate)) + sclk_high_2_5_valid = true; + } + + new_parent = (rate <= c->u.system.threshold) ? + c->u.system.sclk_low : c->u.system.sclk_high; + source_rate = clk_get_rate(new_parent->parent); + + divider = clk_div71_get_divider(source_rate, rate, + new_parent->flags | DIV_U71_INT, ROUND_DIVIDER_DOWN); + if (divider < 0) + return divider; + + round_rate = source_rate * 2 / (divider + 2); + if (round_rate > c->max_rate) { + divider += 2; + round_rate = source_rate * 2 / (divider + 2); + } + + if (new_parent == c->u.system.sclk_high) { + /* Check if 1 : 2.5 ratio provides better approximation */ + if (sclk_high_2_5_valid) { + if (((sclk_high_2_5_rate < round_rate) && + (sclk_high_2_5_rate >= rate)) || + ((round_rate < sclk_high_2_5_rate) && + (round_rate < rate))) + round_rate = sclk_high_2_5_rate; + } + + if (round_rate <= c->u.system.threshold) + round_rate = c->u.system.threshold; + } + return round_rate; +} + +static int tegra3_sbus_cmplx_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + struct clk *new_parent; + + /* - select the appropriate sclk parent + - keep hclk at the same rate as sclk + - set pclk at 1:2 rate of hclk unless pclk minimum is violated, + in the latter case switch to 1:1 ratio */ + + if (rate >= c->u.system.pclk->min_rate * 2) { + ret = clk_set_div(c->u.system.pclk, 2); + if (ret) { + pr_err("Failed to set 1 : 2 pclk divider\n"); + return ret; + } + } + + new_parent = (rate <= c->u.system.threshold) ? + c->u.system.sclk_low : c->u.system.sclk_high; + + ret = clk_set_rate(new_parent, rate + 1); + if (ret) { + pr_err("Failed to set sclk source %s to %lu\n", + new_parent->name, rate); + return ret; + } + + if (new_parent != clk_get_parent(c->parent)) { + ret = clk_set_parent(c->parent, new_parent); + if (ret) { + pr_err("Failed to switch sclk source to %s\n", + new_parent->name); + return ret; + } + } + + if (rate < c->u.system.pclk->min_rate * 2) { + ret = clk_set_div(c->u.system.pclk, 1); + if (ret) { + pr_err("Failed to set 1 : 1 pclk divider\n"); + return ret; + } + } + + return 0; +} + +static struct clk_ops tegra_sbus_cmplx_ops = { + .init = tegra3_sbus_cmplx_init, + .set_rate = tegra3_sbus_cmplx_set_rate, + .round_rate = tegra3_sbus_cmplx_round_rate, + .shared_bus_update = tegra3_clk_shared_bus_update, +}; + +/* Blink output functions */ + +static void tegra3_blink_clk_init(struct clk *c) +{ + u32 val; + + val = pmc_readl(PMC_CTRL); + c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; + c->mul = 1; + val = pmc_readl(c->reg); + + if (val & PMC_BLINK_TIMER_ENB) { + unsigned int on_off; + + on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & + PMC_BLINK_TIMER_DATA_ON_MASK; + val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; + val &= PMC_BLINK_TIMER_DATA_OFF_MASK; + on_off += val; + /* each tick in the blink timer is 4 32KHz clocks */ + c->div = on_off * 4; + } else { + c->div = 1; + } +} + +static int tegra3_blink_clk_enable(struct clk *c) +{ + u32 val; + + val = pmc_readl(PMC_DPD_PADS_ORIDE); + pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); + + val = pmc_readl(PMC_CTRL); + pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); + + return 0; +} + +static void tegra3_blink_clk_disable(struct clk *c) +{ + u32 val; + + val = pmc_readl(PMC_CTRL); + pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); + + val = pmc_readl(PMC_DPD_PADS_ORIDE); + pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); +} + +static int tegra3_blink_clk_set_rate(struct clk *c, unsigned long rate) +{ + unsigned long parent_rate = clk_get_rate(c->parent); + if (rate >= parent_rate) { + c->div = 1; + pmc_writel(0, c->reg); + } else { + unsigned int on_off; + u32 val; + + on_off = DIV_ROUND_UP(parent_rate / 8, rate); + c->div = on_off * 8; + + val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << + PMC_BLINK_TIMER_DATA_ON_SHIFT; + on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; + on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; + val |= on_off; + val |= PMC_BLINK_TIMER_ENB; + pmc_writel(val, c->reg); + } + + return 0; +} + +static struct clk_ops tegra_blink_clk_ops = { + .init = &tegra3_blink_clk_init, + .enable = &tegra3_blink_clk_enable, + .disable = &tegra3_blink_clk_disable, + .set_rate = &tegra3_blink_clk_set_rate, +}; + +/* PLL Functions */ +static int tegra3_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg, u32 lock_bit) +{ +#if USE_PLL_LOCK_BITS + int i; + for (i = 0; i < c->u.pll.lock_delay; i++) { + udelay(2); /* timeout = 2 * lock time */ + if (clk_readl(lock_reg) & lock_bit) { + udelay(PLL_POST_LOCK_DELAY); + return 0; + } + } + pr_err("Timed out waiting for lock bit on pll %s", c->name); + return -1; +#endif + udelay(c->u.pll.lock_delay); + + return 0; +} + + +static void tegra3_utmi_param_configure(struct clk *c) +{ + u32 reg; + int i; + unsigned long main_rate = + clk_get_rate(c->parent->parent); + + for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { + if (main_rate == utmi_parameters[i].osc_frequency) { + break; + } + } + + if (i >= ARRAY_SIZE(utmi_parameters)) { + pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); + return; + } + + reg = clk_readl(UTMIP_PLL_CFG2); + + /* Program UTMIP PLL stable and active counts */ + /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ + reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); + reg |= UTMIP_PLL_CFG2_STABLE_COUNT( + utmi_parameters[i].stable_count); + + reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); + + reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( + utmi_parameters[i].active_delay_count); + + /* Remove power downs from UTMIP PLL control bits */ + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; + reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; + + clk_writel(reg, UTMIP_PLL_CFG2); + + /* Program UTMIP PLL delay and oscillator frequency counts */ + reg = clk_readl(UTMIP_PLL_CFG1); + reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); + + reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( + utmi_parameters[i].enable_delay_count); + + reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); + reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( + utmi_parameters[i].xtal_freq_count); + + /* Remove power downs from UTMIP PLL control bits */ + reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; + reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; + reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; + + clk_writel(reg, UTMIP_PLL_CFG1); +} + +static void tegra3_pll_m_override_update(struct clk *c, bool init) +{ + u32 val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); + + if (!(val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)) + return; + + /* override PLLM state with PMC settings */ + c->state = (val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE) ? ON : OFF; + + val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); + c->mul = (val & PMC_PLLM_WB0_OVERRIDE_DIVN_MASK) >> + PMC_PLLM_WB0_OVERRIDE_DIVN_SHIFT; + c->div = (val & PMC_PLLM_WB0_OVERRIDE_DIVM_MASK) >> + PMC_PLLM_WB0_OVERRIDE_DIVM_SHIFT; + c->div *= (0x1 << ((val & PMC_PLLM_WB0_OVERRIDE_DIVP_MASK) >> + PMC_PLLM_WB0_OVERRIDE_DIVP_SHIFT)); + + /* Save initial override settings in Scratch2 register; will be used by + LP0 entry code to restore PLLM boot configuration */ + if (init) + pmc_writel(val, PMC_SCRATCH2); +} + +static void tegra3_pll_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg + PLL_BASE); + + c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; + + if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { + const struct clk_pll_freq_table *sel; + unsigned long input_rate = clk_get_rate(c->parent); + c->u.pll.fixed_rate = PLLP_DEFAULT_FIXED_RATE; + + for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { + if (sel->input_rate == input_rate && + sel->output_rate == c->u.pll.fixed_rate) { + c->mul = sel->n; + c->div = sel->m * sel->p; + return; + } + } + pr_err("Clock %s has unknown fixed frequency\n", c->name); + BUG(); + } else if (val & PLL_BASE_BYPASS) { + c->mul = 1; + c->div = 1; + } else { + c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; + c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; + if (c->flags & PLLU) + c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; + else + c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> + PLL_BASE_DIVP_SHIFT)); + } + + if (c->flags & PLL_FIXED) { + c->u.pll.fixed_rate = clk_get_rate_locked(c); + } + + if (c->flags & PLLU) { + tegra3_utmi_param_configure(c); + } + + if (c->flags & PLLM) + tegra3_pll_m_override_update(c, true); +} + +static int tegra3_pll_clk_enable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + +#if USE_PLL_LOCK_BITS + val = clk_readl(c->reg + PLL_MISC(c)); + val |= PLL_MISC_LOCK_ENABLE(c); + clk_writel(val, c->reg + PLL_MISC(c)); +#endif + val = clk_readl(c->reg + PLL_BASE); + val &= ~PLL_BASE_BYPASS; + val |= PLL_BASE_ENABLE; + clk_writel(val, c->reg + PLL_BASE); + + if (c->flags & PLLM) { + val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); + val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; + pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); + pmc_readl(PMC_PLLP_WB0_OVERRIDE); + } + + tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); + + return 0; +} + +static void tegra3_pll_clk_disable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + + val = clk_readl(c->reg); + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); + clk_writel(val, c->reg); + + if (c->flags & PLLM) { + val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); + val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; + pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); + } +} + +static int tegra3_pllm_override_rate( + struct clk *c, const struct clk_pll_freq_table *sel, u32 p_div) +{ + u32 val, old_base; + + old_base = val = pmc_readl(PMC_PLLM_WB0_OVERRIDE); + + /* Keep default CPCON and DCCON in override configuration */ + val &= ~(PMC_PLLM_WB0_OVERRIDE_DIVM_MASK | + PMC_PLLM_WB0_OVERRIDE_DIVN_MASK | + PMC_PLLM_WB0_OVERRIDE_DIVP_MASK); + val |= (sel->m << PMC_PLLM_WB0_OVERRIDE_DIVM_SHIFT) | + (sel->n << PMC_PLLM_WB0_OVERRIDE_DIVN_SHIFT) | + (p_div << PMC_PLLM_WB0_OVERRIDE_DIVP_SHIFT); + + if (val != old_base) + pmc_writel(val, PMC_PLLM_WB0_OVERRIDE); + + return 0; +} + +static int tegra3_pll_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val, p_div, old_base; + unsigned long input_rate; + const struct clk_pll_freq_table *sel; + struct clk_pll_freq_table cfg; + + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + + if (c->flags & PLL_FIXED) { + int ret = 0; + if (rate != c->u.pll.fixed_rate) { + pr_err("%s: Can not change %s fixed rate %lu to %lu\n", + __func__, c->name, c->u.pll.fixed_rate, rate); + ret = -EINVAL; + } + return ret; + } + + if ((c->flags & PLLM) && (c->state == ON)) { + if (rate != clk_get_rate_locked(c)) { + pr_err("%s: Can not change memory %s rate in flight\n", + __func__, c->name); + return -EINVAL; + } + return 0; + } + + p_div = 0; + input_rate = clk_get_rate(c->parent); + + /* Check if the target rate is tabulated */ + for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { + if (sel->input_rate == input_rate && sel->output_rate == rate) { + if (c->flags & PLLU) { + BUG_ON(sel->p < 1 || sel->p > 2); + if (sel->p == 1) + p_div = PLLU_BASE_POST_DIV; + } else { + BUG_ON(sel->p < 1); + for (val = sel->p; val > 1; val >>= 1, p_div++); + p_div <<= PLL_BASE_DIVP_SHIFT; + } + break; + } + } + + /* Configure out-of-table rate */ + if (sel->input_rate == 0) { + unsigned long cfreq; + BUG_ON(c->flags & PLLU); + sel = &cfg; + + switch (input_rate) { + case 12000000: + case 26000000: + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; + break; + case 13000000: + cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; + break; + case 16800000: + case 19200000: + cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; + break; + default: + if (c->parent->flags & DIV_U71_FIXED) { + /* PLLP_OUT1 rate is not in PLLA table */ + pr_warn("%s: failed %s ref/out rates %lu/%lu\n", + __func__, c->name, input_rate, rate); + cfreq = input_rate/(input_rate/1000000); + break; + } + pr_err("%s: Unexpected reference rate %lu\n", + __func__, input_rate); + BUG(); + } + + /* Raise VCO to guarantee 0.5% accuracy */ + for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; + cfg.output_rate <<= 1, p_div++); + + cfg.p = 0x1 << p_div; + cfg.m = input_rate / cfreq; + cfg.n = cfg.output_rate / cfreq; + cfg.cpcon = OUT_OF_TABLE_CPCON; + + if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || + (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || + (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || + (cfg.output_rate > c->u.pll.vco_max)) { + pr_err("%s: Failed to set %s out-of-table rate %lu\n", + __func__, c->name, rate); + return -EINVAL; + } + p_div <<= PLL_BASE_DIVP_SHIFT; + } + + c->mul = sel->n; + c->div = sel->m * sel->p; + + if (c->flags & PLLM) { + val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); + if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE) + return tegra3_pllm_override_rate( + c, sel, p_div >> PLL_BASE_DIVP_SHIFT); + } + + old_base = val = clk_readl(c->reg + PLL_BASE); + val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | + ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); + val |= (sel->m << PLL_BASE_DIVM_SHIFT) | + (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; + if (val == old_base) + return 0; + + if (c->state == ON) { + tegra3_pll_clk_disable(c); + val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); + } + clk_writel(val, c->reg + PLL_BASE); + + if (c->flags & PLL_HAS_CPCON) { + val = clk_readl(c->reg + PLL_MISC(c)); + val &= ~PLL_MISC_CPCON_MASK; + val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; + if (c->flags & (PLLU | PLLD)) { + val &= ~PLL_MISC_LFCON_MASK; + if (sel->n >= PLLDU_LFCON_SET_DIVN) + val |= 0x1 << PLL_MISC_LFCON_SHIFT; + } else if (c->flags & (PLLX | PLLM)) { + val &= ~(0x1 << PLL_MISC_DCCON_SHIFT); + if (rate >= (c->u.pll.vco_max >> 1)) + val |= 0x1 << PLL_MISC_DCCON_SHIFT; + } + clk_writel(val, c->reg + PLL_MISC(c)); + } + + if (c->state == ON) + tegra3_pll_clk_enable(c); + + return 0; +} + +static struct clk_ops tegra_pll_ops = { + .init = tegra3_pll_clk_init, + .enable = tegra3_pll_clk_enable, + .disable = tegra3_pll_clk_disable, + .set_rate = tegra3_pll_clk_set_rate, +}; + +static void tegra3_pllp_clk_init(struct clk *c) +{ + tegra3_pll_clk_init(c); + tegra3_pllp_init_dependencies(c->u.pll.fixed_rate); +} + +#if defined(CONFIG_PM_SLEEP) +static void tegra3_pllp_clk_resume(struct clk *c) +{ + unsigned long rate = c->u.pll.fixed_rate; + tegra3_pll_clk_init(c); + BUG_ON(rate != c->u.pll.fixed_rate); +} +#endif + +static struct clk_ops tegra_pllp_ops = { + .init = tegra3_pllp_clk_init, + .enable = tegra3_pll_clk_enable, + .disable = tegra3_pll_clk_disable, + .set_rate = tegra3_pll_clk_set_rate, +}; + +static int +tegra3_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + u32 val, mask, reg; + + switch (p) { + case TEGRA_CLK_PLLD_CSI_OUT_ENB: + mask = PLLD_BASE_CSI_CLKENABLE; + reg = c->reg + PLL_BASE; + break; + case TEGRA_CLK_PLLD_DSI_OUT_ENB: + mask = PLLD_MISC_DSI_CLKENABLE; + reg = c->reg + PLL_MISC(c); + break; + case TEGRA_CLK_PLLD_MIPI_MUX_SEL: + if (!(c->flags & PLL_ALT_MISC_REG)) { + mask = PLLD_BASE_DSIB_MUX_MASK; + reg = c->reg + PLL_BASE; + break; + } + /* fall through - error since PLLD2 does not have MUX_SEL control */ + default: + return -EINVAL; + } + + val = clk_readl(reg); + if (setting) + val |= mask; + else + val &= ~mask; + clk_writel(val, reg); + return 0; +} + +static struct clk_ops tegra_plld_ops = { + .init = tegra3_pll_clk_init, + .enable = tegra3_pll_clk_enable, + .disable = tegra3_pll_clk_disable, + .set_rate = tegra3_pll_clk_set_rate, + .clk_cfg_ex = tegra3_plld_clk_cfg_ex, +}; + +static void tegra3_plle_clk_init(struct clk *c) +{ + u32 val; + + val = clk_readl(PLLE_AUX); + c->parent = (val & PLLE_AUX_PLLP_SEL) ? + tegra_get_clock_by_name("pll_p") : + tegra_get_clock_by_name("pll_ref"); + + val = clk_readl(c->reg + PLL_BASE); + c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; + c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; + c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT; + c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT; +} + +static void tegra3_plle_clk_disable(struct clk *c) +{ + u32 val; + pr_debug("%s on clock %s\n", __func__, c->name); + + val = clk_readl(c->reg + PLL_BASE); + val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); + clk_writel(val, c->reg + PLL_BASE); +} + +static void tegra3_plle_training(struct clk *c) +{ + u32 val; + + /* PLLE is already disabled, and setup cleared; + * create falling edge on PLLE IDDQ input */ + val = pmc_readl(PMC_SATA_PWRGT); + val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; + pmc_writel(val, PMC_SATA_PWRGT); + + val = pmc_readl(PMC_SATA_PWRGT); + val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; + pmc_writel(val, PMC_SATA_PWRGT); + + val = pmc_readl(PMC_SATA_PWRGT); + val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; + pmc_writel(val, PMC_SATA_PWRGT); + + do { + val = clk_readl(c->reg + PLL_MISC(c)); + } while (!(val & PLLE_MISC_READY)); +} + +static int tegra3_plle_configure(struct clk *c, bool force_training) +{ + u32 val; + const struct clk_pll_freq_table *sel; + unsigned long rate = c->u.pll.fixed_rate; + unsigned long input_rate = clk_get_rate(c->parent); + + for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { + if (sel->input_rate == input_rate && sel->output_rate == rate) + break; + } + + if (sel->input_rate == 0) + return -ENOSYS; + + /* disable PLLE, clear setup fiels */ + tegra3_plle_clk_disable(c); + + val = clk_readl(c->reg + PLL_MISC(c)); + val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); + clk_writel(val, c->reg + PLL_MISC(c)); + + /* training */ + val = clk_readl(c->reg + PLL_MISC(c)); + if (force_training || (!(val & PLLE_MISC_READY))) + tegra3_plle_training(c); + + /* configure dividers, setup, disable SS */ + val = clk_readl(c->reg + PLL_BASE); + val &= ~PLLE_BASE_DIV_MASK; + val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon); + clk_writel(val, c->reg + PLL_BASE); + c->mul = sel->n; + c->div = sel->m * sel->p; + + val = clk_readl(c->reg + PLL_MISC(c)); + val |= PLLE_MISC_SETUP_VALUE; + val |= PLLE_MISC_LOCK_ENABLE; + clk_writel(val, c->reg + PLL_MISC(c)); + + val = clk_readl(PLLE_SS_CTRL); + val |= PLLE_SS_DISABLE; + clk_writel(val, PLLE_SS_CTRL); + + /* enable and lock PLLE*/ + val = clk_readl(c->reg + PLL_BASE); + val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); + clk_writel(val, c->reg + PLL_BASE); + + tegra3_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); + +#if USE_PLLE_SS + /* configure spread spectrum coefficients */ + /* FIXME: coefficients for 216MHZ input? */ +#ifdef CONFIG_TEGRA_SILICON_PLATFORM + if (input_rate == 12000000) +#endif + { + val = clk_readl(PLLE_SS_CTRL); + val &= ~(PLLE_SS_COEFFICIENTS_MASK | PLLE_SS_DISABLE); + val |= PLLE_SS_COEFFICIENTS_12MHZ; + clk_writel(val, PLLE_SS_CTRL); + } +#endif + return 0; +} + +static int tegra3_plle_clk_enable(struct clk *c) +{ + pr_debug("%s on clock %s\n", __func__, c->name); + return tegra3_plle_configure(c, !c->set); +} + +static struct clk_ops tegra_plle_ops = { + .init = tegra3_plle_clk_init, + .enable = tegra3_plle_clk_enable, + .disable = tegra3_plle_clk_disable, +}; + +/* Clock divider ops (non-atomic shared register access) */ +static DEFINE_SPINLOCK(pll_div_lock); + +static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate); +static void tegra3_pll_div_clk_init(struct clk *c) +{ + if (c->flags & DIV_U71) { + u32 divu71; + u32 val = clk_readl(c->reg); + val >>= c->reg_shift; + c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; + if (!(val & PLL_OUT_RESET_DISABLE)) + c->state = OFF; + + if (c->u.pll_div.default_rate) { + int ret = tegra3_pll_div_clk_set_rate( + c, c->u.pll_div.default_rate); + if (!ret) + return; + } + divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; + c->div = (divu71 + 2); + c->mul = 2; + } else if (c->flags & DIV_2) { + c->state = ON; + if (c->flags & (PLLD | PLLX)) { + c->div = 2; + c->mul = 1; + } + else + BUG(); + } else { + c->state = ON; + c->div = 1; + c->mul = 1; + } +} + +static int tegra3_pll_div_clk_enable(struct clk *c) +{ + u32 val; + u32 new_val; + unsigned long flags; + + pr_debug("%s: %s\n", __func__, c->name); + if (c->flags & DIV_U71) { + spin_lock_irqsave(&pll_div_lock, flags); + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + + new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel_delay(val, c->reg); + spin_unlock_irqrestore(&pll_div_lock, flags); + return 0; + } else if (c->flags & DIV_2) { + return 0; + } + return -EINVAL; +} + +static void tegra3_pll_div_clk_disable(struct clk *c) +{ + u32 val; + u32 new_val; + unsigned long flags; + + pr_debug("%s: %s\n", __func__, c->name); + if (c->flags & DIV_U71) { + spin_lock_irqsave(&pll_div_lock, flags); + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + + new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel_delay(val, c->reg); + spin_unlock_irqrestore(&pll_div_lock, flags); + } +} + +static int tegra3_pll_div_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + u32 new_val; + int divider_u71; + unsigned long parent_rate = clk_get_rate(c->parent); + unsigned long flags; + + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + if (c->flags & DIV_U71) { + divider_u71 = clk_div71_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider_u71 >= 0) { + spin_lock_irqsave(&pll_div_lock, flags); + val = clk_readl(c->reg); + new_val = val >> c->reg_shift; + new_val &= 0xFFFF; + if (c->flags & DIV_U71_FIXED) + new_val |= PLL_OUT_OVERRIDE; + new_val &= ~PLL_OUT_RATIO_MASK; + new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; + + val &= ~(0xFFFF << c->reg_shift); + val |= new_val << c->reg_shift; + clk_writel_delay(val, c->reg); + c->div = divider_u71 + 2; + c->mul = 2; + spin_unlock_irqrestore(&pll_div_lock, flags); + return 0; + } + } else if (c->flags & DIV_2) + return clk_set_rate(c->parent, rate * 2); + + return -EINVAL; +} + +static long tegra3_pll_div_clk_round_rate(struct clk *c, unsigned long rate) +{ + int divider; + unsigned long parent_rate = clk_get_rate(c->parent); + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + + if (c->flags & DIV_U71) { + divider = clk_div71_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider < 0) + return divider; + return DIV_ROUND_UP(parent_rate * 2, divider + 2); + } else if (c->flags & DIV_2) + /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */ + return rate; + + return -EINVAL; +} + +static struct clk_ops tegra_pll_div_ops = { + .init = tegra3_pll_div_clk_init, + .enable = tegra3_pll_div_clk_enable, + .disable = tegra3_pll_div_clk_disable, + .set_rate = tegra3_pll_div_clk_set_rate, + .round_rate = tegra3_pll_div_clk_round_rate, +}; + +/* Periph clk ops */ +static inline u32 periph_clk_source_mask(struct clk *c) +{ + if (c->flags & MUX8) + return 7 << 29; + else if (c->flags & MUX_PWM) + return 3 << 28; + else if (c->flags & MUX_CLK_OUT) + return 3 << (c->u.periph.clk_num + 4); + else if (c->flags & PLLD) + return PLLD_BASE_DSIB_MUX_MASK; + else + return 3 << 30; +} + +static inline u32 periph_clk_source_shift(struct clk *c) +{ + if (c->flags & MUX8) + return 29; + else if (c->flags & MUX_PWM) + return 28; + else if (c->flags & MUX_CLK_OUT) + return c->u.periph.clk_num + 4; + else if (c->flags & PLLD) + return PLLD_BASE_DSIB_MUX_SHIFT; + else + return 30; +} + +static void tegra3_periph_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + const struct clk_mux_sel *mux = 0; + const struct clk_mux_sel *sel; + if (c->flags & MUX) { + for (sel = c->inputs; sel->input != NULL; sel++) { + if (((val & periph_clk_source_mask(c)) >> + periph_clk_source_shift(c)) == sel->value) + mux = sel; + } + BUG_ON(!mux); + + c->parent = mux->input; + } else { + c->parent = c->inputs[0].input; + } + + if (c->flags & DIV_U71) { + u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; + if (c->flags & DIV_U71_IDLE) { + val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << + PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); + val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << + PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); + clk_writel(val, c->reg); + } + c->div = divu71 + 2; + c->mul = 2; + } else if (c->flags & DIV_U151) { + u32 divu151 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; + if ((c->flags & DIV_U151_UART) && + (!(val & PERIPH_CLK_UART_DIV_ENB))) { + divu151 = 0; + } + c->div = divu151 + 2; + c->mul = 2; + } else if (c->flags & DIV_U16) { + u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; + c->div = divu16 + 1; + c->mul = 1; + } else { + c->div = 1; + c->mul = 1; + } + + c->state = ON; + + if (c->flags & PERIPH_NO_ENB) + return; + + if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) + c->state = OFF; + if (!(c->flags & PERIPH_NO_RESET)) + if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) + c->state = OFF; +} + +static int tegra3_periph_clk_enable(struct clk *c) +{ + unsigned long flags; + pr_debug("%s on clock %s\n", __func__, c->name); + + if (c->flags & PERIPH_NO_ENB) + return 0; + + spin_lock_irqsave(&periph_refcount_lock, flags); + + tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; + if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) { + spin_unlock_irqrestore(&periph_refcount_lock, flags); + return 0; + } + + clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); + if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) { + if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) { + udelay(5); /* reset propagation delay */ + clk_writel(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_RST_CLR_REG(c)); + } + } + spin_unlock_irqrestore(&periph_refcount_lock, flags); + return 0; +} + +static void tegra3_periph_clk_disable(struct clk *c) +{ + unsigned long val, flags; + pr_debug("%s on clock %s\n", __func__, c->name); + + if (c->flags & PERIPH_NO_ENB) + return; + + spin_lock_irqsave(&periph_refcount_lock, flags); + + if (c->refcnt) + tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; + + if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) { + /* If peripheral is in the APB bus then read the APB bus to + * flush the write operation in apb bus. This will avoid the + * peripheral access after disabling clock*/ + if (c->flags & PERIPH_ON_APB) + val = chipid_readl(); + + clk_writel_delay( + PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); + } + spin_unlock_irqrestore(&periph_refcount_lock, flags); +} + +static void tegra3_periph_clk_reset(struct clk *c, bool assert) +{ + unsigned long val; + pr_debug("%s %s on clock %s\n", __func__, + assert ? "assert" : "deassert", c->name); + + if (c->flags & PERIPH_NO_ENB) + return; + + if (!(c->flags & PERIPH_NO_RESET)) { + if (assert) { + /* If peripheral is in the APB bus then read the APB + * bus to flush the write operation in apb bus. This + * will avoid the peripheral access after disabling + * clock */ + if (c->flags & PERIPH_ON_APB) + val = chipid_readl(); + + clk_writel(PERIPH_CLK_TO_BIT(c), + PERIPH_CLK_TO_RST_SET_REG(c)); + } else + clk_writel(PERIPH_CLK_TO_BIT(c), + PERIPH_CLK_TO_RST_CLR_REG(c)); + } +} + +static int tegra3_periph_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + + if (!(c->flags & MUX)) + return (p == c->parent) ? 0 : (-EINVAL); + + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + val = clk_readl(c->reg); + val &= ~periph_clk_source_mask(c); + val |= (sel->value << periph_clk_source_shift(c)); + + if (c->refcnt) + clk_enable(p); + + clk_writel_delay(val, c->reg); + + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + return 0; + } + } + + return -EINVAL; +} + +static int tegra3_periph_clk_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + int divider; + unsigned long parent_rate = clk_get_rate(c->parent); + + if (c->flags & DIV_U71) { + divider = clk_div71_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider >= 0) { + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; + val |= divider; + clk_writel_delay(val, c->reg); + c->div = divider + 2; + c->mul = 2; + return 0; + } + } else if (c->flags & DIV_U151) { + divider = clk_div151_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider >= 0) { + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; + val |= divider; + if (c->flags & DIV_U151_UART) { + if (divider) + val |= PERIPH_CLK_UART_DIV_ENB; + else + val &= ~PERIPH_CLK_UART_DIV_ENB; + } + clk_writel_delay(val, c->reg); + c->div = divider + 2; + c->mul = 2; + return 0; + } + } else if (c->flags & DIV_U16) { + divider = clk_div16_get_divider(parent_rate, rate); + if (divider >= 0) { + val = clk_readl(c->reg); + val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; + val |= divider; + clk_writel_delay(val, c->reg); + c->div = divider + 1; + c->mul = 1; + return 0; + } + } else if (parent_rate <= rate) { + c->div = 1; + c->mul = 1; + return 0; + } + return -EINVAL; +} + +static long tegra3_periph_clk_round_rate(struct clk *c, + unsigned long rate) +{ + int divider; + unsigned long parent_rate = clk_get_rate(c->parent); + pr_debug("%s: %s %lu\n", __func__, c->name, rate); + + if (c->flags & DIV_U71) { + divider = clk_div71_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider < 0) + return divider; + + return DIV_ROUND_UP(parent_rate * 2, divider + 2); + } else if (c->flags & DIV_U151) { + divider = clk_div151_get_divider( + parent_rate, rate, c->flags, ROUND_DIVIDER_UP); + if (divider < 0) + return divider; + + return DIV_ROUND_UP(parent_rate * 2, divider + 2); + } else if (c->flags & DIV_U16) { + divider = clk_div16_get_divider(parent_rate, rate); + if (divider < 0) + return divider; + return DIV_ROUND_UP(parent_rate, divider + 1); + } + return -EINVAL; +} + +static struct clk_ops tegra_periph_clk_ops = { + .init = &tegra3_periph_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_parent = &tegra3_periph_clk_set_parent, + .set_rate = &tegra3_periph_clk_set_rate, + .round_rate = &tegra3_periph_clk_round_rate, + .reset = &tegra3_periph_clk_reset, +}; + + +/* Periph extended clock configuration ops */ +static int +tegra3_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + if (p == TEGRA_CLK_VI_INP_SEL) { + u32 val = clk_readl(c->reg); + val &= ~PERIPH_CLK_VI_SEL_EX_MASK; + val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & + PERIPH_CLK_VI_SEL_EX_MASK; + clk_writel(val, c->reg); + return 0; + } + return -EINVAL; +} + +static struct clk_ops tegra_vi_clk_ops = { + .init = &tegra3_periph_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_parent = &tegra3_periph_clk_set_parent, + .set_rate = &tegra3_periph_clk_set_rate, + .round_rate = &tegra3_periph_clk_round_rate, + .clk_cfg_ex = &tegra3_vi_clk_cfg_ex, + .reset = &tegra3_periph_clk_reset, +}; + +static int +tegra3_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { + u32 val = clk_readl(c->reg); + if (setting) + val |= PERIPH_CLK_NAND_DIV_EX_ENB; + else + val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; + clk_writel(val, c->reg); + return 0; + } + return -EINVAL; +} + +static struct clk_ops tegra_nand_clk_ops = { + .init = &tegra3_periph_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_parent = &tegra3_periph_clk_set_parent, + .set_rate = &tegra3_periph_clk_set_rate, + .round_rate = &tegra3_periph_clk_round_rate, + .clk_cfg_ex = &tegra3_nand_clk_cfg_ex, + .reset = &tegra3_periph_clk_reset, +}; + + +static int +tegra3_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) +{ + if (p == TEGRA_CLK_DTV_INVERT) { + u32 val = clk_readl(c->reg); + if (setting) + val |= PERIPH_CLK_DTV_POLARITY_INV; + else + val &= ~PERIPH_CLK_DTV_POLARITY_INV; + clk_writel(val, c->reg); + return 0; + } + return -EINVAL; +} + +static struct clk_ops tegra_dtv_clk_ops = { + .init = &tegra3_periph_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_parent = &tegra3_periph_clk_set_parent, + .set_rate = &tegra3_periph_clk_set_rate, + .round_rate = &tegra3_periph_clk_round_rate, + .clk_cfg_ex = &tegra3_dtv_clk_cfg_ex, + .reset = &tegra3_periph_clk_reset, +}; + +static int tegra3_dsib_clk_set_parent(struct clk *c, struct clk *p) +{ + const struct clk_mux_sel *sel; + struct clk *d = tegra_get_clock_by_name("pll_d"); + + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + if (c->refcnt) + clk_enable(p); + + /* The DSIB parent selection bit is in PLLD base + register - can not do direct r-m-w, must be + protected by PLLD lock */ + tegra_clk_cfg_ex( + d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value); + + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + return 0; + } + } + + return -EINVAL; +} + +static struct clk_ops tegra_dsib_clk_ops = { + .init = &tegra3_periph_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_parent = &tegra3_dsib_clk_set_parent, + .set_rate = &tegra3_periph_clk_set_rate, + .round_rate = &tegra3_periph_clk_round_rate, + .reset = &tegra3_periph_clk_reset, +}; + +/* pciex clock support only reset function */ +static struct clk_ops tegra_pciex_clk_ops = { + .reset = tegra3_periph_clk_reset, +}; + +/* Output clock ops (non-atomic shared register access) */ + +static DEFINE_SPINLOCK(clk_out_lock); + +static void tegra3_clk_out_init(struct clk *c) +{ + const struct clk_mux_sel *mux = 0; + const struct clk_mux_sel *sel; + u32 val = pmc_readl(c->reg); + + c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; + c->mul = 1; + c->div = 1; + + for (sel = c->inputs; sel->input != NULL; sel++) { + if (((val & periph_clk_source_mask(c)) >> + periph_clk_source_shift(c)) == sel->value) + mux = sel; + } + BUG_ON(!mux); + c->parent = mux->input; +} + +static int tegra3_clk_out_enable(struct clk *c) +{ + u32 val; + unsigned long flags; + + pr_debug("%s on clock %s\n", __func__, c->name); + + spin_lock_irqsave(&clk_out_lock, flags); + val = pmc_readl(c->reg); + val |= (0x1 << c->u.periph.clk_num); + pmc_writel(val, c->reg); + spin_unlock_irqrestore(&clk_out_lock, flags); + + return 0; +} + +static void tegra3_clk_out_disable(struct clk *c) +{ + u32 val; + unsigned long flags; + + pr_debug("%s on clock %s\n", __func__, c->name); + + spin_lock_irqsave(&clk_out_lock, flags); + val = pmc_readl(c->reg); + val &= ~(0x1 << c->u.periph.clk_num); + pmc_writel(val, c->reg); + spin_unlock_irqrestore(&clk_out_lock, flags); +} + +static int tegra3_clk_out_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + unsigned long flags; + const struct clk_mux_sel *sel; + + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + if (c->refcnt) + clk_enable(p); + + spin_lock_irqsave(&clk_out_lock, flags); + val = pmc_readl(c->reg); + val &= ~periph_clk_source_mask(c); + val |= (sel->value << periph_clk_source_shift(c)); + pmc_writel(val, c->reg); + spin_unlock_irqrestore(&clk_out_lock, flags); + + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + return 0; + } + } + return -EINVAL; +} + +static struct clk_ops tegra_clk_out_ops = { + .init = &tegra3_clk_out_init, + .enable = &tegra3_clk_out_enable, + .disable = &tegra3_clk_out_disable, + .set_parent = &tegra3_clk_out_set_parent, +}; + + +/* External memory controller clock ops */ +static void tegra3_emc_clk_init(struct clk *c) +{ + tegra3_periph_clk_init(c); + tegra_emc_dram_type_init(c); + + /* On A01 limit EMC maximum rate to boot frequency; + starting with A02 full PLLM range should be supported */ + if (tegra_get_revision() == TEGRA_REVISION_A01) + c->max_rate = clk_get_rate_locked(c); + else + c->max_rate = clk_get_rate(c->parent); +} + +static long tegra3_emc_clk_round_rate(struct clk *c, unsigned long rate) +{ + long new_rate = max(rate, c->min_rate); + + new_rate = tegra_emc_round_rate(new_rate); + if (new_rate < 0) + new_rate = c->max_rate; + + return new_rate; +} + +static int tegra3_emc_clk_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + u32 div_value; + struct clk *p; + + /* The tegra3 memory controller has an interlock with the clock + * block that allows memory shadowed registers to be updated, + * and then transfer them to the main registers at the same + * time as the clock update without glitches. During clock change + * operation both clock parent and divider may change simultaneously + * to achieve requested rate. */ + p = tegra_emc_predict_parent(rate, &div_value); + div_value += 2; /* emc has fractional DIV_U71 divider */ + + /* No matching rate in emc dfs table */ + if (IS_ERR(p)) + return PTR_ERR(p); + + /* Table rate found, but need to relock source pll */ + if (!p) + return tegra3_emc_relock_set_rate(c, clk_get_rate_locked(c), + rate, rate * (div_value / 2)); + + if (p == c->parent) { + if (div_value == c->div) + return 0; + } else if (c->refcnt) + clk_enable(p); + + ret = tegra_emc_set_rate(rate); + if (ret < 0) + return ret; + + if (p != c->parent) { + if(c->refcnt && c->parent) + clk_disable(c->parent); + clk_reparent(c, p); + } + c->div = div_value; + c->mul = 2; + return 0; +} + +static struct clk_ops tegra_emc_clk_ops = { + .init = &tegra3_emc_clk_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_rate = &tegra3_emc_clk_set_rate, + .round_rate = &tegra3_emc_clk_round_rate, + .reset = &tegra3_periph_clk_reset, + .shared_bus_update = &tegra3_clk_shared_bus_update, +}; + +/* Clock doubler ops (non-atomic shared register access) */ +static DEFINE_SPINLOCK(doubler_lock); + +static void tegra3_clk_double_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; + c->div = 1; + c->state = ON; + if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) + c->state = OFF; +}; + +static int tegra3_clk_double_set_rate(struct clk *c, unsigned long rate) +{ + u32 val; + unsigned long parent_rate = clk_get_rate(c->parent); + unsigned long flags; + + if (rate == parent_rate) { + spin_lock_irqsave(&doubler_lock, flags); + val = clk_readl(c->reg) | (0x1 << c->reg_shift); + clk_writel(val, c->reg); + c->mul = 1; + c->div = 1; + spin_unlock_irqrestore(&doubler_lock, flags); + return 0; + } else if (rate == 2 * parent_rate) { + spin_lock_irqsave(&doubler_lock, flags); + val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); + clk_writel(val, c->reg); + c->mul = 2; + c->div = 1; + spin_unlock_irqrestore(&doubler_lock, flags); + return 0; + } + return -EINVAL; +} + +static struct clk_ops tegra_clk_double_ops = { + .init = &tegra3_clk_double_init, + .enable = &tegra3_periph_clk_enable, + .disable = &tegra3_periph_clk_disable, + .set_rate = &tegra3_clk_double_set_rate, +}; + +/* Audio sync clock ops */ +static int tegra3_sync_source_set_rate(struct clk *c, unsigned long rate) +{ + c->rate = rate; + return 0; +} + +static struct clk_ops tegra_sync_source_ops = { + .set_rate = &tegra3_sync_source_set_rate, +}; + +static void tegra3_audio_sync_clk_init(struct clk *c) +{ + int source; + const struct clk_mux_sel *sel; + u32 val = clk_readl(c->reg); + c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; + source = val & AUDIO_SYNC_SOURCE_MASK; + for (sel = c->inputs; sel->input != NULL; sel++) + if (sel->value == source) + break; + BUG_ON(sel->input == NULL); + c->parent = sel->input; +} + +static int tegra3_audio_sync_clk_enable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); + return 0; +} + +static void tegra3_audio_sync_clk_disable(struct clk *c) +{ + u32 val = clk_readl(c->reg); + clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); +} + +static int tegra3_audio_sync_clk_set_parent(struct clk *c, struct clk *p) +{ + u32 val; + const struct clk_mux_sel *sel; + for (sel = c->inputs; sel->input != NULL; sel++) { + if (sel->input == p) { + val = clk_readl(c->reg); + val &= ~AUDIO_SYNC_SOURCE_MASK; + val |= sel->value; + + if (c->refcnt) + clk_enable(p); + + clk_writel(val, c->reg); + + if (c->refcnt && c->parent) + clk_disable(c->parent); + + clk_reparent(c, p); + return 0; + } + } + + return -EINVAL; +} + +static struct clk_ops tegra_audio_sync_clk_ops = { + .init = tegra3_audio_sync_clk_init, + .enable = tegra3_audio_sync_clk_enable, + .disable = tegra3_audio_sync_clk_disable, + .set_parent = tegra3_audio_sync_clk_set_parent, +}; + +/* cml0 (pcie), and cml1 (sata) clock ops (non-atomic shared register access) */ +static DEFINE_SPINLOCK(cml_lock); + +static void tegra3_cml_clk_init(struct clk *c) +{ + u32 val = clk_readl(c->reg); + c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; +} + +static int tegra3_cml_clk_enable(struct clk *c) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&cml_lock, flags); + val = clk_readl(c->reg); + val |= (0x1 << c->u.periph.clk_num); + clk_writel(val, c->reg); + spin_unlock_irqrestore(&cml_lock, flags); + return 0; +} + +static void tegra3_cml_clk_disable(struct clk *c) +{ + u32 val; + unsigned long flags; + + spin_lock_irqsave(&cml_lock, flags); + val = clk_readl(c->reg); + val &= ~(0x1 << c->u.periph.clk_num); + clk_writel(val, c->reg); + spin_unlock_irqrestore(&cml_lock, flags); +} + +static struct clk_ops tegra_cml_clk_ops = { + .init = &tegra3_cml_clk_init, + .enable = &tegra3_cml_clk_enable, + .disable = &tegra3_cml_clk_disable, +}; + + +/* cbus ops */ +/* + * Some clocks require dynamic re-locking of source PLL in order to + * achieve frequency scaling granularity that matches characterized + * core voltage steps. The cbus clock creates a shared bus that + * provides a virtual root for such clocks to hide and synchronize + * parent PLL re-locking as well as backup operations. +*/ + +static void tegra3_clk_cbus_init(struct clk *c) +{ + c->state = OFF; + c->set = true; + c->shared_bus_backup.bus_rate = + clk_get_rate(c->shared_bus_backup.input) / + c->shared_bus_backup.value; +} + +static int tegra3_clk_cbus_enable(struct clk *c) +{ + return 0; +} + +static long tegra3_clk_cbus_round_rate(struct clk *c, unsigned long rate) +{ + int i; + + if (!c->dvfs) + return rate; + + /* update min now, since no dvfs table was available during init + (skip placeholder entries set to 1 kHz) */ + if (!c->min_rate) { + for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { + if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) { + c->min_rate = c->dvfs->freqs[i]; + break; + } + } + BUG_ON(!c->min_rate); + } + rate = max(rate, c->min_rate); + + for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { + unsigned long f = c->dvfs->freqs[i]; + if (f >= rate) + break; + } + return c->dvfs->freqs[i]; +} + +static int cbus_switch_one(struct clk *c, struct clk *p, u32 div, bool abort) +{ + int ret = 0; + + /* set new divider if it is bigger than the current one */ + if (c->div < c->mul * div) { + ret = clk_set_div(c, div); + if (ret) { + pr_err("%s: failed to set %s clock divider %u: %d\n", + __func__, c->name, div, ret); + if (abort) + return ret; + } + } + + ret = clk_set_parent(c, p); + if (ret) { + pr_err("%s: failed to set %s clock parent %s: %d\n", + __func__, c->name, p->name, ret); + if (abort) + return ret; + } + + /* set new divider if it is smaller than the current one */ + if (c->div > c->mul * div) { + ret = clk_set_div(c, div); + if (ret) + pr_err("%s: failed to set %s clock divider %u: %d\n", + __func__, c->name, div, ret); + } + + return ret; +} + +static int cbus_backup(struct clk *c) +{ + int ret; + struct clk *user; + + list_for_each_entry(user, &c->shared_bus_list, + u.shared_bus_user.node) { + bool enabled = user->u.shared_bus_user.client && + (user->u.shared_bus_user.enabled || + user->u.shared_bus_user.client->refcnt); + if (enabled) { + ret = cbus_switch_one(user->u.shared_bus_user.client, + c->shared_bus_backup.input, + c->shared_bus_backup.value * + user->div, true); + if (ret) + return ret; + } + } + return 0; +} + +static void cbus_restore(struct clk *c) +{ + struct clk *user; + + list_for_each_entry(user, &c->shared_bus_list, + u.shared_bus_user.node) { + bool back = user->u.shared_bus_user.client && (c->parent != + user->u.shared_bus_user.client->parent); + if (back) + cbus_switch_one(user->u.shared_bus_user.client, + c->parent, c->div * user->div, false); + } +} + +static int tegra3_clk_cbus_set_rate(struct clk *c, unsigned long rate) +{ + int ret; + + if (rate == 0) + return 0; + + ret = clk_enable(c->parent); + if (ret) { + pr_err("%s: failed to enable %s clock: %d\n", + __func__, c->name, ret); + return ret; + } + + ret = cbus_backup(c); + if (ret) + goto out; + + ret = clk_set_rate(c->parent, rate * c->div); + if (ret) { + pr_err("%s: failed to set %s clock rate %lu: %d\n", + __func__, c->name, rate, ret); + goto out; + } + + cbus_restore(c); + +out: + clk_disable(c->parent); + return ret; +} + +static struct clk_ops tegra_clk_cbus_ops = { + .init = tegra3_clk_cbus_init, + .enable = tegra3_clk_cbus_enable, + .set_rate = tegra3_clk_cbus_set_rate, + .round_rate = tegra3_clk_cbus_round_rate, + .shared_bus_update = tegra3_clk_shared_bus_update, +}; + +/* shared bus ops */ +/* + * Some clocks may have multiple downstream users that need to request a + * higher clock rate. Shared bus clocks provide a unique shared_bus_user + * clock to each user. The frequency of the bus is set to the highest + * enabled shared_bus_user clock, with a minimum value set by the + * shared bus. + */ + +static noinline int shared_bus_set_rate(struct clk *bus, unsigned long rate, + unsigned long old_rate) +{ + int ret, mv, old_mv; + unsigned long bridge_rate = emc_bridge->u.shared_bus_user.rate; + + /* If bridge is not needed (LPDDR2) just set bus rate */ + if (tegra_emc_get_dram_type() == DRAM_TYPE_LPDDR2) + return clk_set_rate_locked(bus, rate); + + mv = tegra_dvfs_predict_millivolts(bus, rate); + old_mv = tegra_dvfs_predict_millivolts(bus, old_rate); + if (IS_ERR_VALUE(mv) || IS_ERR_VALUE(old_mv)) { + pr_err("%s: Failed to predict %s voltage for %lu => %lu\n", + __func__, bus->name, old_rate, rate); + return -EINVAL; + } + + /* emc bus: set bridge rate as intermediate step when crossing + * bridge threshold in any direction + */ + if (bus->flags & PERIPH_EMC_ENB) { + if (((mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && + (old_rate < bridge_rate)) || + ((old_mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && + (rate < bridge_rate))) { + ret = clk_set_rate_locked(bus, bridge_rate); + if (ret) { + pr_err("%s: Failed to set emc bridge rate %lu\n", + __func__, bridge_rate); + return ret; + } + } + return clk_set_rate_locked(bus, rate); + } + + /* sbus and cbus: enable/disable emc bridge user when crossing voltage + * threshold up/down respectively; hence, emc rate is kept above the + * bridge rate as long as any sbus or cbus user requires high voltage + */ + if ((mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN) && + (old_mv <= TEGRA_EMC_BRIDGE_MVOLTS_MIN)) { + ret = clk_enable(emc_bridge); + if (ret) { + pr_err("%s: Failed to enable emc bridge\n", __func__); + return ret; + } + } + + ret = clk_set_rate_locked(bus, rate); + if (ret) + return ret; + + if ((mv <= TEGRA_EMC_BRIDGE_MVOLTS_MIN) && + (old_mv > TEGRA_EMC_BRIDGE_MVOLTS_MIN)) + clk_disable(emc_bridge); + + return 0; +} + +static int tegra3_clk_shared_bus_update(struct clk *bus) +{ + struct clk *c; + unsigned long old_rate; + unsigned long rate = bus->min_rate; + unsigned long bw = 0; + unsigned long ceiling = bus->max_rate; + u8 emc_bw_efficiency = tegra_emc_bw_efficiency_boost; + + if (detach_shared_bus) + return 0; + + list_for_each_entry(c, &bus->shared_bus_list, + u.shared_bus_user.node) { + /* Ignore requests from disabled floor and bw users, and from + * auto-users riding the bus. Always honor ceiling users, even + * if they are disabled - we do not want to keep enabled parent + * bus just because ceiling is set. + */ + if (c->u.shared_bus_user.enabled || + (c->u.shared_bus_user.mode == SHARED_CEILING)) { + if (!strcmp(c->name, "3d.emc")) + emc_bw_efficiency = tegra_emc_bw_efficiency; + + switch (c->u.shared_bus_user.mode) { + case SHARED_BW: + if (bw < bus->max_rate) + bw += c->u.shared_bus_user.rate; + break; + case SHARED_CEILING: + ceiling = min(c->u.shared_bus_user.rate, + ceiling); + break; + case SHARED_AUTO: + case SHARED_FLOOR: + default: + rate = max(c->u.shared_bus_user.rate, rate); + } + } + } + + if (bw) { + if (bus->flags & PERIPH_EMC_ENB) { + bw = emc_bw_efficiency ? + (bw / emc_bw_efficiency) : bus->max_rate; + bw = (bw < bus->max_rate / 100) ? + (bw * 100) : bus->max_rate; + } + bw = clk_round_rate_locked(bus, bw); + } + rate = min(max(rate, bw), ceiling); + + old_rate = clk_get_rate_locked(bus); + if (rate == old_rate) + return 0; + + return shared_bus_set_rate(bus, rate, old_rate); +}; + +static void tegra_clk_shared_bus_init(struct clk *c) +{ + c->max_rate = c->parent->max_rate; + c->u.shared_bus_user.rate = c->parent->max_rate; + c->state = OFF; + c->set = true; + + if (c->u.shared_bus_user.client_id) { + c->u.shared_bus_user.client = + tegra_get_clock_by_name(c->u.shared_bus_user.client_id); + if (!c->u.shared_bus_user.client) { + pr_err("%s: could not find clk %s\n", __func__, + c->u.shared_bus_user.client_id); + return; + } + c->u.shared_bus_user.client->flags |= + c->parent->flags & PERIPH_ON_CBUS; + c->flags |= c->parent->flags & PERIPH_ON_CBUS; + c->div = c->u.shared_bus_user.client_div ? : 1; + c->mul = 1; + } + + list_add_tail(&c->u.shared_bus_user.node, + &c->parent->shared_bus_list); +} + +static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) +{ + c->u.shared_bus_user.rate = rate; + tegra_clk_shared_bus_update(c->parent); + return 0; +} + +static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate) +{ + /* auto user follow others, by itself it run at minimum bus rate */ + if (c->u.shared_bus_user.mode == SHARED_AUTO) + rate = 0; + + /* BW users should not be rounded until aggregated */ + if (c->u.shared_bus_user.mode == SHARED_BW) + return rate; + + return clk_round_rate(c->parent, rate); +} + +static int tegra_clk_shared_bus_enable(struct clk *c) +{ + c->u.shared_bus_user.enabled = true; + tegra_clk_shared_bus_update(c->parent); + if (c->u.shared_bus_user.client) { + return clk_enable(c->u.shared_bus_user.client); + } + return 0; +} + +static void tegra_clk_shared_bus_disable(struct clk *c) +{ + if (c->u.shared_bus_user.client) + clk_disable(c->u.shared_bus_user.client); + c->u.shared_bus_user.enabled = false; + tegra_clk_shared_bus_update(c->parent); +} + +static void tegra_clk_shared_bus_reset(struct clk *c, bool assert) +{ + if (c->u.shared_bus_user.client) { + if (c->u.shared_bus_user.client->ops && + c->u.shared_bus_user.client->ops->reset) + c->u.shared_bus_user.client->ops->reset( + c->u.shared_bus_user.client, assert); + } +} + +static struct clk_ops tegra_clk_shared_bus_ops = { + .init = tegra_clk_shared_bus_init, + .enable = tegra_clk_shared_bus_enable, + .disable = tegra_clk_shared_bus_disable, + .set_rate = tegra_clk_shared_bus_set_rate, + .round_rate = tegra_clk_shared_bus_round_rate, + .reset = tegra_clk_shared_bus_reset, +}; + +/* emc bridge ops */ +/* On Tegra3 platforms emc configurations for DDR3 low rates can not work + * at high core voltage; the intermediate step (bridge) is mandatory whenever + * core voltage is crossing the threshold: TEGRA_EMC_BRIDGE_MVOLTS_MIN (fixed + * for the entire Tegra3 arch); also emc must run above the bridge rate if any + * other than emc clock requires high voltage. LP CPU, memory, sbus and cbus + * together include all clocks that may require core voltage above threshold + * (other peripherals can reach their maximum rates below threshold). LP CPU + * dependency is taken care of via tegra_emc_to_cpu_ratio() api. Memory clock + * transitions are forced to step through bridge rate; sbus and cbus control + * emc bridge to set emc clock floor as necessary. + * + * EMC bridge is implemented as a special emc shared bus user: initialized at + * minimum rate until updated once by emc dvfs setup; then it is only enabled + * or disabled when sbus and/or cbus voltage is crossing the threshold. + */ +static void tegra3_clk_emc_bridge_init(struct clk *c) +{ + tegra_clk_shared_bus_init(c); + c->u.shared_bus_user.rate = 0; +} + +static int tegra3_clk_emc_bridge_set_rate(struct clk *c, unsigned long rate) +{ + if (c->u.shared_bus_user.rate == 0) + c->u.shared_bus_user.rate = rate; + return 0; +} + +static struct clk_ops tegra_clk_emc_bridge_ops = { + .init = tegra3_clk_emc_bridge_init, + .enable = tegra_clk_shared_bus_enable, + .disable = tegra_clk_shared_bus_disable, + .set_rate = tegra3_clk_emc_bridge_set_rate, + .round_rate = tegra_clk_shared_bus_round_rate, +}; + +/* Clock definitions */ +static struct clk tegra_clk_32k = { + .name = "clk_32k", + .rate = 32768, + .ops = NULL, + .max_rate = 32768, +}; + +static struct clk tegra_clk_m = { + .name = "clk_m", + .flags = ENABLE_ON_INIT, + .ops = &tegra_clk_m_ops, + .reg = 0x1fc, + .reg_shift = 28, + .max_rate = 48000000, +}; + +static struct clk tegra_clk_m_div2 = { + .name = "clk_m_div2", + .ops = &tegra_clk_m_div_ops, + .parent = &tegra_clk_m, + .mul = 1, + .div = 2, + .state = ON, + .max_rate = 24000000, +}; + +static struct clk tegra_clk_m_div4 = { + .name = "clk_m_div4", + .ops = &tegra_clk_m_div_ops, + .parent = &tegra_clk_m, + .mul = 1, + .div = 4, + .state = ON, + .max_rate = 12000000, +}; + +static struct clk tegra_pll_ref = { + .name = "pll_ref", + .flags = ENABLE_ON_INIT, + .ops = &tegra_pll_ref_ops, + .parent = &tegra_clk_m, + .max_rate = 26000000, +}; + +static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { + { 12000000, 1200000000, 600, 6, 1, 8}, + { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ + { 16800000, 1200000000, 500, 7, 1, 8}, + { 19200000, 1200000000, 500, 8, 1, 8}, + { 26000000, 1200000000, 600, 13, 1, 8}, + + { 12000000, 1040000000, 520, 6, 1, 8}, + { 13000000, 1040000000, 480, 6, 1, 8}, + { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */ + { 19200000, 1040000000, 325, 6, 1, 6}, + { 26000000, 1040000000, 520, 13, 1, 8}, + + { 12000000, 832000000, 416, 6, 1, 8}, + { 13000000, 832000000, 832, 13, 1, 8}, + { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */ + { 19200000, 832000000, 260, 6, 1, 8}, + { 26000000, 832000000, 416, 13, 1, 8}, + + { 12000000, 624000000, 624, 12, 1, 8}, + { 13000000, 624000000, 624, 13, 1, 8}, + { 16800000, 624000000, 520, 14, 1, 8}, + { 19200000, 624000000, 520, 16, 1, 8}, + { 26000000, 624000000, 624, 26, 1, 8}, + + { 12000000, 600000000, 600, 12, 1, 8}, + { 13000000, 600000000, 600, 13, 1, 8}, + { 16800000, 600000000, 500, 14, 1, 8}, + { 19200000, 600000000, 375, 12, 1, 6}, + { 26000000, 600000000, 600, 26, 1, 8}, + + { 12000000, 520000000, 520, 12, 1, 8}, + { 13000000, 520000000, 520, 13, 1, 8}, + { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */ + { 19200000, 520000000, 325, 12, 1, 6}, + { 26000000, 520000000, 520, 26, 1, 8}, + + { 12000000, 416000000, 416, 12, 1, 8}, + { 13000000, 416000000, 416, 13, 1, 8}, + { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */ + { 19200000, 416000000, 260, 12, 1, 6}, + { 26000000, 416000000, 416, 26, 1, 8}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_c = { + .name = "pll_c", + .flags = PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0x80, + .parent = &tegra_pll_ref, + .max_rate = 1400000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_c_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk tegra_pll_c_out1 = { + .name = "pll_c_out1", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71 | PERIPH_ON_CBUS, + .parent = &tegra_pll_c, + .reg = 0x84, + .reg_shift = 0, + .max_rate = 700000000, +}; + +static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { + { 12000000, 666000000, 666, 12, 1, 8}, + { 13000000, 666000000, 666, 13, 1, 8}, + { 16800000, 666000000, 555, 14, 1, 8}, + { 19200000, 666000000, 555, 16, 1, 8}, + { 26000000, 666000000, 666, 26, 1, 8}, + { 12000000, 600000000, 600, 12, 1, 8}, + { 13000000, 600000000, 600, 13, 1, 8}, + { 16800000, 600000000, 500, 14, 1, 8}, + { 19200000, 600000000, 375, 12, 1, 6}, + { 26000000, 600000000, 600, 26, 1, 8}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_m = { + .name = "pll_m", + .flags = PLL_HAS_CPCON | PLLM, + .ops = &tegra_pll_ops, + .reg = 0x90, + .parent = &tegra_pll_ref, + .max_rate = 900000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1200000000, + .freq_table = tegra_pll_m_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk tegra_pll_m_out1 = { + .name = "pll_m_out1", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71, + .parent = &tegra_pll_m, + .reg = 0x94, + .reg_shift = 0, + .max_rate = 600000000, +}; + +static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { + { 12000000, 216000000, 432, 12, 2, 8}, + { 13000000, 216000000, 432, 13, 2, 8}, + { 16800000, 216000000, 360, 14, 2, 8}, + { 19200000, 216000000, 360, 16, 2, 8}, + { 26000000, 216000000, 432, 26, 2, 8}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_p = { + .name = "pll_p", + .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, + .ops = &tegra_pllp_ops, + .reg = 0xa0, + .parent = &tegra_pll_ref, + .max_rate = 432000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_p_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk tegra_pll_p_out1 = { + .name = "pll_p_out1", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa4, + .reg_shift = 0, + .max_rate = 432000000, +}; + +static struct clk tegra_pll_p_out2 = { + .name = "pll_p_out2", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa4, + .reg_shift = 16, + .max_rate = 432000000, +}; + +static struct clk tegra_pll_p_out3 = { + .name = "pll_p_out3", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa8, + .reg_shift = 0, + .max_rate = 432000000, +}; + +static struct clk tegra_pll_p_out4 = { + .name = "pll_p_out4", + .ops = &tegra_pll_div_ops, + .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, + .parent = &tegra_pll_p, + .reg = 0xa8, + .reg_shift = 16, + .max_rate = 432000000, +}; + +static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { + { 9600000, 564480000, 294, 5, 1, 4}, + { 9600000, 552960000, 288, 5, 1, 4}, + { 9600000, 24000000, 5, 2, 1, 1}, + + { 28800000, 56448000, 49, 25, 1, 1}, + { 28800000, 73728000, 64, 25, 1, 1}, + { 28800000, 24000000, 5, 6, 1, 1}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_a = { + .name = "pll_a", + .flags = PLL_HAS_CPCON, + .ops = &tegra_pll_ops, + .reg = 0xb0, + .parent = &tegra_pll_p_out1, + .max_rate = 700000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1400000000, + .freq_table = tegra_pll_a_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk tegra_pll_a_out0 = { + .name = "pll_a_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_U71, + .parent = &tegra_pll_a, + .reg = 0xb4, + .reg_shift = 0, + .max_rate = 100000000, +}; + +static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { + { 12000000, 216000000, 216, 12, 1, 4}, + { 13000000, 216000000, 216, 13, 1, 4}, + { 16800000, 216000000, 180, 14, 1, 4}, + { 19200000, 216000000, 180, 16, 1, 4}, + { 26000000, 216000000, 216, 26, 1, 4}, + + { 12000000, 594000000, 594, 12, 1, 8}, + { 13000000, 594000000, 594, 13, 1, 8}, + { 16800000, 594000000, 495, 14, 1, 8}, + { 19200000, 594000000, 495, 16, 1, 8}, + { 26000000, 594000000, 594, 26, 1, 8}, + + { 12000000, 1000000000, 1000, 12, 1, 12}, + { 13000000, 1000000000, 1000, 13, 1, 12}, + { 19200000, 1000000000, 625, 12, 1, 8}, + { 26000000, 1000000000, 1000, 26, 1, 12}, + + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_d = { + .name = "pll_d", + .flags = PLL_HAS_CPCON | PLLD, + .ops = &tegra_plld_ops, + .reg = 0xd0, + .parent = &tegra_pll_ref, + .max_rate = 1000000000, + .u.pll = { + .input_min = 2000000, + .input_max = 40000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 40000000, + .vco_max = 1000000000, + .freq_table = tegra_pll_d_freq_table, + .lock_delay = 1000, + }, +}; + +static struct clk tegra_pll_d_out0 = { + .name = "pll_d_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_2 | PLLD, + .parent = &tegra_pll_d, + .max_rate = 500000000, +}; + +static struct clk tegra_pll_d2 = { + .name = "pll_d2", + .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, + .ops = &tegra_plld_ops, + .reg = 0x4b8, + .parent = &tegra_pll_ref, + .max_rate = 1000000000, + .u.pll = { + .input_min = 2000000, + .input_max = 40000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 40000000, + .vco_max = 1000000000, + .freq_table = tegra_pll_d_freq_table, + .lock_delay = 1000, + }, +}; + +static struct clk tegra_pll_d2_out0 = { + .name = "pll_d2_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_2 | PLLD, + .parent = &tegra_pll_d2, + .max_rate = 500000000, +}; + +static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { + { 12000000, 480000000, 960, 12, 2, 12}, + { 13000000, 480000000, 960, 13, 2, 12}, + { 16800000, 480000000, 400, 7, 2, 5}, + { 19200000, 480000000, 200, 4, 2, 3}, + { 26000000, 480000000, 960, 26, 2, 12}, + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_u = { + .name = "pll_u", + .flags = PLL_HAS_CPCON | PLLU, + .ops = &tegra_pll_ops, + .reg = 0xc0, + .parent = &tegra_pll_ref, + .max_rate = 480000000, + .u.pll = { + .input_min = 2000000, + .input_max = 40000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 480000000, + .vco_max = 960000000, + .freq_table = tegra_pll_u_freq_table, + .lock_delay = 1000, + }, +}; + +static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { + /* 1.7 GHz */ + { 12000000, 1700000000, 850, 6, 1, 8}, + { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */ + { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */ + { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */ + { 26000000, 1700000000, 850, 13, 1, 8}, + + /* 1.6 GHz */ + { 12000000, 1600000000, 800, 6, 1, 8}, + { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */ + { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */ + { 19200000, 1600000000, 500, 6, 1, 8}, + { 26000000, 1600000000, 800, 13, 1, 8}, + + /* 1.5 GHz */ + { 12000000, 1500000000, 750, 6, 1, 8}, + { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */ + { 16800000, 1500000000, 625, 7, 1, 8}, + { 19200000, 1500000000, 625, 8, 1, 8}, + { 26000000, 1500000000, 750, 13, 1, 8}, + + /* 1.4 GHz */ + { 12000000, 1400000000, 700, 6, 1, 8}, + { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */ + { 16800000, 1400000000, 1000, 12, 1, 8}, + { 19200000, 1400000000, 875, 12, 1, 8}, + { 26000000, 1400000000, 700, 13, 1, 8}, + + /* 1.3 GHz */ + { 12000000, 1300000000, 975, 9, 1, 8}, + { 13000000, 1300000000, 1000, 10, 1, 8}, + { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */ + { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */ + { 26000000, 1300000000, 650, 13, 1, 8}, + + /* 1.2 GHz */ + { 12000000, 1200000000, 1000, 10, 1, 8}, + { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */ + { 16800000, 1200000000, 1000, 14, 1, 8}, + { 19200000, 1200000000, 1000, 16, 1, 8}, + { 26000000, 1200000000, 600, 13, 1, 8}, + + /* 1.1 GHz */ + { 12000000, 1100000000, 825, 9, 1, 8}, + { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */ + { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */ + { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */ + { 26000000, 1100000000, 550, 13, 1, 8}, + + /* 1 GHz */ + { 12000000, 1000000000, 1000, 12, 1, 8}, + { 13000000, 1000000000, 1000, 13, 1, 8}, + { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */ + { 19200000, 1000000000, 625, 12, 1, 8}, + { 26000000, 1000000000, 1000, 26, 1, 8}, + + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_x = { + .name = "pll_x", + .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, + .ops = &tegra_pll_ops, + .reg = 0xe0, + .parent = &tegra_pll_ref, + .max_rate = 1700000000, + .u.pll = { + .input_min = 2000000, + .input_max = 31000000, + .cf_min = 1000000, + .cf_max = 6000000, + .vco_min = 20000000, + .vco_max = 1700000000, + .freq_table = tegra_pll_x_freq_table, + .lock_delay = 300, + }, +}; + +static struct clk tegra_pll_x_out0 = { + .name = "pll_x_out0", + .ops = &tegra_pll_div_ops, + .flags = DIV_2 | PLLX, + .parent = &tegra_pll_x, + .max_rate = 850000000, +}; + + +static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { + /* PLLE special case: use cpcon field to store cml divider value */ + { 12000000, 100000000, 150, 1, 18, 11}, + { 216000000, 100000000, 200, 18, 24, 13}, +#ifndef CONFIG_TEGRA_SILICON_PLATFORM + { 13000000, 100000000, 200, 1, 26, 13}, +#endif + { 0, 0, 0, 0, 0, 0 }, +}; + +static struct clk tegra_pll_e = { + .name = "pll_e", + .flags = PLL_ALT_MISC_REG, + .ops = &tegra_plle_ops, + .reg = 0xe8, + .max_rate = 100000000, + .u.pll = { + .input_min = 12000000, + .input_max = 216000000, + .cf_min = 12000000, + .cf_max = 12000000, + .vco_min = 1200000000, + .vco_max = 2400000000U, + .freq_table = tegra_pll_e_freq_table, + .lock_delay = 300, + .fixed_rate = 100000000, + }, +}; + +static struct clk tegra_cml0_clk = { + .name = "cml0", + .parent = &tegra_pll_e, + .ops = &tegra_cml_clk_ops, + .reg = PLLE_AUX, + .max_rate = 100000000, + .u.periph = { + .clk_num = 0, + }, +}; + +static struct clk tegra_cml1_clk = { + .name = "cml1", + .parent = &tegra_pll_e, + .ops = &tegra_cml_clk_ops, + .reg = PLLE_AUX, + .max_rate = 100000000, + .u.periph = { + .clk_num = 1, + }, +}; + +static struct clk tegra_pciex_clk = { + .name = "pciex", + .parent = &tegra_pll_e, + .ops = &tegra_pciex_clk_ops, + .max_rate = 100000000, + .u.periph = { + .clk_num = 74, + }, +}; + +/* Audio sync clocks */ +#define SYNC_SOURCE(_id, _dev) \ + { \ + .name = #_id "_sync", \ + .lookup = { \ + .dev_id = #_dev , \ + .con_id = "ext_audio_sync", \ + }, \ + .rate = 24000000, \ + .max_rate = 24000000, \ + .ops = &tegra_sync_source_ops \ + } +static struct clk tegra_sync_source_list[] = { + SYNC_SOURCE(spdif_in, tegra30-spdif), + SYNC_SOURCE(i2s0, tegra30-i2s.0), + SYNC_SOURCE(i2s1, tegra30-i2s.1), + SYNC_SOURCE(i2s2, tegra30-i2s.2), + SYNC_SOURCE(i2s3, tegra30-i2s.3), + SYNC_SOURCE(i2s4, tegra30-i2s.4), + SYNC_SOURCE(vimclk, vimclk), +}; + +static struct clk_mux_sel mux_audio_sync_clk[] = +{ + { .input = &tegra_sync_source_list[0], .value = 0}, + { .input = &tegra_sync_source_list[1], .value = 1}, + { .input = &tegra_sync_source_list[2], .value = 2}, + { .input = &tegra_sync_source_list[3], .value = 3}, + { .input = &tegra_sync_source_list[4], .value = 4}, + { .input = &tegra_sync_source_list[5], .value = 5}, + { .input = &tegra_pll_a_out0, .value = 6}, + { .input = &tegra_sync_source_list[6], .value = 7}, + { 0, 0 } +}; + +#define AUDIO_SYNC_CLK(_id, _dev, _index) \ + { \ + .name = #_id, \ + .lookup = { \ + .dev_id = #_dev, \ + .con_id = "audio_sync", \ + }, \ + .inputs = mux_audio_sync_clk, \ + .reg = 0x4A0 + (_index) * 4, \ + .max_rate = 24000000, \ + .ops = &tegra_audio_sync_clk_ops \ + } +static struct clk tegra_clk_audio_list[] = { + AUDIO_SYNC_CLK(audio0, tegra30-i2s.0, 0), + AUDIO_SYNC_CLK(audio1, tegra30-i2s.1, 1), + AUDIO_SYNC_CLK(audio2, tegra30-i2s.2, 2), + AUDIO_SYNC_CLK(audio3, tegra30-i2s.3, 3), + AUDIO_SYNC_CLK(audio4, tegra30-i2s.4, 4), + AUDIO_SYNC_CLK(audio, tegra30-spdif, 5), +}; + +#define AUDIO_SYNC_2X_CLK(_id, _dev, _index) \ + { \ + .name = #_id "_2x", \ + .lookup = { \ + .dev_id = #_dev, \ + .con_id = "audio_sync_2x" \ + }, \ + .flags = PERIPH_NO_RESET, \ + .max_rate = 48000000, \ + .ops = &tegra_clk_double_ops, \ + .reg = 0x49C, \ + .reg_shift = 24 + (_index), \ + .parent = &tegra_clk_audio_list[(_index)], \ + .u.periph = { \ + .clk_num = 113 + (_index), \ + }, \ + } +static struct clk tegra_clk_audio_2x_list[] = { + AUDIO_SYNC_2X_CLK(audio0, tegra30-i2s.0, 0), + AUDIO_SYNC_2X_CLK(audio1, tegra30-i2s.1, 1), + AUDIO_SYNC_2X_CLK(audio2, tegra30-i2s.2, 2), + AUDIO_SYNC_2X_CLK(audio3, tegra30-i2s.3, 3), + AUDIO_SYNC_2X_CLK(audio4, tegra30-i2s.4, 4), + AUDIO_SYNC_2X_CLK(audio, tegra30-spdif, 5), +}; + +#define MUX_I2S_SPDIF(_id, _index) \ +static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \ + {.input = &tegra_pll_a_out0, .value = 0}, \ + {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \ + {.input = &tegra_pll_p, .value = 2}, \ + {.input = &tegra_clk_m, .value = 3}, \ + { 0, 0}, \ +} +MUX_I2S_SPDIF(audio0, 0); +MUX_I2S_SPDIF(audio1, 1); +MUX_I2S_SPDIF(audio2, 2); +MUX_I2S_SPDIF(audio3, 3); +MUX_I2S_SPDIF(audio4, 4); +MUX_I2S_SPDIF(audio, 5); /* SPDIF */ + +/* External clock outputs (through PMC) */ +#define MUX_EXTERN_OUT(_id) \ +static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \ + {.input = &tegra_clk_m, .value = 0}, \ + {.input = &tegra_clk_m_div2, .value = 1}, \ + {.input = &tegra_clk_m_div4, .value = 2}, \ + {.input = NULL, .value = 3}, /* placeholder */ \ + { 0, 0}, \ +} +MUX_EXTERN_OUT(1); +MUX_EXTERN_OUT(2); +MUX_EXTERN_OUT(3); + +static struct clk_mux_sel *mux_extern_out_list[] = { + mux_clkm_clkm2_clkm4_extern1, + mux_clkm_clkm2_clkm4_extern2, + mux_clkm_clkm2_clkm4_extern3, +}; + +#define CLK_OUT_CLK(_id) \ + { \ + .name = "clk_out_" #_id, \ + .lookup = { \ + .dev_id = "clk_out_" #_id, \ + .con_id = "extern" #_id, \ + }, \ + .ops = &tegra_clk_out_ops, \ + .reg = 0x1a8, \ + .inputs = mux_clkm_clkm2_clkm4_extern##_id, \ + .flags = MUX_CLK_OUT, \ + .max_rate = 216000000, \ + .u.periph = { \ + .clk_num = (_id - 1) * 8 + 2, \ + }, \ + } +static struct clk tegra_clk_out_list[] = { + CLK_OUT_CLK(1), + CLK_OUT_CLK(2), + CLK_OUT_CLK(3), +}; + +/* called after peripheral external clocks are initialized */ +static void init_clk_out_mux(void) +{ + int i; + struct clk *c; + + /* output clock con_id is the name of peripheral + external clock connected to input 3 of the output mux */ + for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) { + c = tegra_get_clock_by_name( + tegra_clk_out_list[i].lookup.con_id); + if (!c) + pr_err("%s: could not find clk %s\n", __func__, + tegra_clk_out_list[i].lookup.con_id); + mux_extern_out_list[i][3].input = c; + } +} + +/* Peripheral muxes */ +static struct clk_mux_sel mux_cclk_g[] = { + { .input = &tegra_clk_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_clk_32k, .value = 2}, + { .input = &tegra_pll_m, .value = 3}, + { .input = &tegra_pll_p, .value = 4}, + { .input = &tegra_pll_p_out4, .value = 5}, + { .input = &tegra_pll_p_out3, .value = 6}, + /* { .input = &tegra_clk_d, .value = 7}, - no use on tegra3 */ + { .input = &tegra_pll_x, .value = 8}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_cclk_lp[] = { + { .input = &tegra_clk_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_clk_32k, .value = 2}, + { .input = &tegra_pll_m, .value = 3}, + { .input = &tegra_pll_p, .value = 4}, + { .input = &tegra_pll_p_out4, .value = 5}, + { .input = &tegra_pll_p_out3, .value = 6}, + /* { .input = &tegra_clk_d, .value = 7}, - no use on tegra3 */ + { .input = &tegra_pll_x_out0, .value = 8}, + { .input = &tegra_pll_x, .value = 8 | SUPER_LP_DIV2_BYPASS}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_sclk[] = { + { .input = &tegra_clk_m, .value = 0}, + { .input = &tegra_pll_c_out1, .value = 1}, + { .input = &tegra_pll_p_out4, .value = 2}, + { .input = &tegra_pll_p_out3, .value = 3}, + { .input = &tegra_pll_p_out2, .value = 4}, + /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra3 */ + { .input = &tegra_clk_32k, .value = 6}, + { .input = &tegra_pll_m_out1, .value = 7}, + { 0, 0}, +}; + +static struct clk tegra_clk_cclk_g = { + .name = "cclk_g", + .flags = DIV_U71 | DIV_U71_INT, + .inputs = mux_cclk_g, + .reg = 0x368, + .ops = &tegra_super_ops, + .max_rate = 1700000000, +}; + +static struct clk tegra_clk_cclk_lp = { + .name = "cclk_lp", + .flags = DIV_2 | DIV_U71 | DIV_U71_INT, + .inputs = mux_cclk_lp, + .reg = 0x370, + .ops = &tegra_super_ops, + .max_rate = 620000000, +}; + +static struct clk tegra_clk_sclk = { + .name = "sclk", + .inputs = mux_sclk, + .reg = 0x28, + .ops = &tegra_super_ops, + .max_rate = 378000000, + .min_rate = 12000000, +}; + +static struct clk tegra_clk_virtual_cpu_g = { + .name = "cpu_g", + .parent = &tegra_clk_cclk_g, + .ops = &tegra_cpu_ops, + .max_rate = 1700000000, + .u.cpu = { + .main = &tegra_pll_x, + .backup = &tegra_pll_p, + .mode = MODE_G, + }, +}; + +static struct clk tegra_clk_virtual_cpu_lp = { + .name = "cpu_lp", + .parent = &tegra_clk_cclk_lp, + .ops = &tegra_cpu_ops, + .max_rate = 620000000, + .u.cpu = { + .main = &tegra_pll_x, + .backup = &tegra_pll_p, + .mode = MODE_LP, + }, +}; + +static struct clk_mux_sel mux_cpu_cmplx[] = { + { .input = &tegra_clk_virtual_cpu_g, .value = 0}, + { .input = &tegra_clk_virtual_cpu_lp, .value = 1}, + { 0, 0}, +}; + +static struct clk tegra_clk_cpu_cmplx = { + .name = "cpu", + .inputs = mux_cpu_cmplx, + .ops = &tegra_cpu_cmplx_ops, + .max_rate = 1700000000, +}; + +static struct clk tegra_clk_cop = { + .name = "cop", + .parent = &tegra_clk_sclk, + .ops = &tegra_cop_ops, + .max_rate = 378000000, +}; + +static struct clk tegra_clk_hclk = { + .name = "hclk", + .flags = DIV_BUS, + .parent = &tegra_clk_sclk, + .reg = 0x30, + .reg_shift = 4, + .ops = &tegra_bus_ops, + .max_rate = 378000000, + .min_rate = 12000000, +}; + +static struct clk tegra_clk_pclk = { + .name = "pclk", + .flags = DIV_BUS, + .parent = &tegra_clk_hclk, + .reg = 0x30, + .reg_shift = 0, + .ops = &tegra_bus_ops, + .max_rate = 167000000, + .min_rate = 12000000, +}; + +static struct raw_notifier_head sbus_rate_change_nh; + +static struct clk tegra_clk_sbus_cmplx = { + .name = "sbus", + .parent = &tegra_clk_sclk, + .ops = &tegra_sbus_cmplx_ops, + .u.system = { + .pclk = &tegra_clk_pclk, + .hclk = &tegra_clk_hclk, + .sclk_low = &tegra_pll_p_out4, + .sclk_high = &tegra_pll_m_out1, + }, + .rate_change_nh = &sbus_rate_change_nh, +}; + +static struct clk tegra_clk_blink = { + .name = "blink", + .parent = &tegra_clk_32k, + .reg = 0x40, + .ops = &tegra_blink_clk_ops, + .max_rate = 32768, +}; + +static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { + { .input = &tegra_pll_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_pll_a_out0, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { + { .input = &tegra_pll_m, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { + { .input = &tegra_pll_p, .value = 0}, + { .input = &tegra_pll_c, .value = 1}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + { .input = &tegra_pll_m, .value = 2}, +#endif + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_clkm[] = { + { .input = &tegra_pll_p, .value = 0}, + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_d_out0, .value = 1}, + {.input = &tegra_pll_c, .value = 2}, + {.input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = { + {.input = &tegra_pll_p, .value = 0}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + {.input = &tegra_pll_m, .value = 1}, +#endif + {.input = &tegra_pll_d_out0, .value = 2}, + {.input = &tegra_pll_a_out0, .value = 3}, + {.input = &tegra_pll_c, .value = 4}, + {.input = &tegra_pll_d2_out0, .value = 5}, + {.input = &tegra_clk_m, .value = 6}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = { + { .input = &tegra_pll_a_out0, .value = 0}, + /* { .input = &tegra_pll_c, .value = 1}, no use on tegra3 */ + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_c, .value = 1}, + {.input = &tegra_clk_32k, .value = 2}, + {.input = &tegra_clk_m, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_c, .value = 1}, + {.input = &tegra_clk_m, .value = 2}, + {.input = &tegra_clk_32k, .value = 3}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_pllc_pllm[] = { + {.input = &tegra_pll_p, .value = 0}, + {.input = &tegra_pll_c, .value = 1}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + {.input = &tegra_pll_m, .value = 2}, +#endif + { 0, 0}, +}; + +static struct clk_mux_sel mux_clk_m[] = { + { .input = &tegra_clk_m, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_pllp_out3[] = { + { .input = &tegra_pll_p_out3, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plld_out0[] = { + { .input = &tegra_pll_d_out0, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plld_out0_plld2_out0[] = { + { .input = &tegra_pll_d_out0, .value = 0}, + { .input = &tegra_pll_d2_out0, .value = 1}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_clk_32k[] = { + { .input = &tegra_clk_32k, .value = 0}, + { 0, 0}, +}; + +static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = { + { .input = &tegra_pll_a_out0, .value = 0}, + { .input = &tegra_clk_32k, .value = 1}, + { .input = &tegra_pll_p, .value = 2}, + { .input = &tegra_clk_m, .value = 3}, + { .input = &tegra_pll_e, .value = 4}, + { 0, 0}, +}; + +static struct raw_notifier_head emc_rate_change_nh; + +static struct clk tegra_clk_emc = { + .name = "emc", + .ops = &tegra_emc_clk_ops, + .reg = 0x19c, + .max_rate = 900000000, + .min_rate = 12000000, + .inputs = mux_pllm_pllc_pllp_clkm, + .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, + .u.periph = { + .clk_num = 57, + }, + .shared_bus_backup = { + .input = &tegra_pll_c, + }, + .rate_change_nh = &emc_rate_change_nh, +}; + +static struct clk tegra_clk_emc_bridge = { + .name = "bridge.emc", + .ops = &tegra_clk_emc_bridge_ops, + .parent = &tegra_clk_emc, +}; + +static struct clk tegra_clk_cbus = { + .name = "cbus", + .parent = &tegra_pll_c, + .ops = &tegra_clk_cbus_ops, + .max_rate = 700000000, + .mul = 1, + .div = CONFIG_TEGRA_CBUS_CLOCK_DIVIDER, + .flags = PERIPH_ON_CBUS, + .shared_bus_backup = { + .input = &tegra_pll_p, + .value = 2, + } +}; + +#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + .ops = &tegra_periph_clk_ops, \ + .reg = _reg, \ + .inputs = _inputs, \ + .flags = _flags, \ + .max_rate = _max, \ + .u.periph = { \ + .clk_num = _clk_num, \ + }, \ + } + +#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \ + _flags, _ops) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + .ops = _ops, \ + .reg = _reg, \ + .inputs = _inputs, \ + .flags = _flags, \ + .max_rate = _max, \ + .u.periph = { \ + .clk_num = _clk_num, \ + }, \ + } + +#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + .ops = &tegra_clk_shared_bus_ops, \ + .parent = _parent, \ + .u.shared_bus_user = { \ + .client_id = _id, \ + .client_div = _div, \ + .mode = _mode, \ + }, \ + } +struct clk tegra_list_clks[] = { + PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 26000000, mux_clk_m, 0), + PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), + PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), + PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), + PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("i2s0", "tegra30-i2s.0", "i2s", 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("i2s1", "tegra30-i2s.1", "i2s", 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("i2s2", "tegra30-i2s.2", "i2s", 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("i2s3", "tegra30-i2s.3", "i2s", 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("i2s4", "tegra30-i2s.4", "i2s", 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 26000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 408000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("sbc1", "spi_tegra.0", "spi", 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc2", "spi_tegra.1", "spi", 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc3", "spi_tegra.2", "spi", 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc4", "spi_tegra.3", "spi", 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc5", "spi_tegra.4", "spi", 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sbc6", "spi_tegra.5", "spi", 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB, &tegra_nand_clk_ops), + PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 50000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 102000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ + PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("cec", "tegra_cec", NULL, 136, 0, 26000000, mux_clk_m, PERIPH_ON_APB), + PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 600000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT), + PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* max rate ??? */ + PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("nor", "tegra-nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */ + PERIPH_CLK("i2c1", "tegra-i2c.0", "i2c-div", 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c2", "tegra-i2c.1", "i2c-div", 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c3", "tegra-i2c.2", "i2c-div", 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c4", "tegra-i2c.3", "i2c-div", 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c5", "tegra-i2c.4", "i2c-div", 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), + PERIPH_CLK("i2c1-fast", "tegra-i2c.0", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c2-fast", "tegra-i2c.1", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c3-fast", "tegra-i2c.2", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c4-fast", "tegra-i2c.3", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("i2c5-fast", "tegra-i2c.4", "i2c-fast", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartd", "tegra_uart.3", NULL, 65, 0x1c0, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uarte", "tegra_uart.4", NULL, 66, 0x1c4, 900000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uarta_dbg", "serial8250.0", "uarta", 6, 0x178, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartb_dbg", "serial8250.0", "uartb", 7, 0x17c, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartc_dbg", "serial8250.0", "uartc", 55, 0x1a0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uartd_dbg", "serial8250.0", "uartd", 65, 0x1c0, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK("uarte_dbg", "serial8250.0", "uarte", 66, 0x1c4, 900000000, mux_pllp_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), + PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 470000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops), + PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), + PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), + PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET), + PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE), + PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), + PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 600000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), + PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT), + PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, PERIPH_ON_APB, &tegra_dtv_clk_ops), + PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71), + PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ + PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), + PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8), + PERIPH_CLK("usbd", "tegra-udc.0", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ + PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0), + PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops), + PERIPH_CLK("dsi1-fixed", "tegradc.0", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("dsi2-fixed", "tegradc.1", "dsi-fixed", 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), + PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0), + PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ + PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), + + PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71), + PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), + PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), + PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71), + PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0), + PERIPH_CLK("se", "se", NULL, 127, 0x42c, 625000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT | PERIPH_ON_APB), + PERIPH_CLK("mselect", "mselect", NULL, 99, 0x3b4, 108000000, mux_pllp_clkm, MUX | DIV_U71), + + SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("usbd.sclk", "tegra-udc.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("usb1.sclk", "tegra-ehci.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("usb2.sclk", "tegra-ehci.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("usb3.sclk", "tegra-ehci.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("wake.sclk", "wake_sclk", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("cpu_mode.sclk","cpu_mode", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("mon.avp", "tegra_actmon", "avp", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("cap.sclk", "cap_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, SHARED_CEILING), + SHARED_CLK("floor.sclk", "floor_sclk", NULL, &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc1.sclk", "spi_tegra.0", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc2.sclk", "spi_tegra.1", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc3.sclk", "spi_tegra.2", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc4.sclk", "spi_tegra.3", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc5.sclk", "spi_tegra.4", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + SHARED_CLK("sbc6.sclk", "spi_tegra.5", "sclk", &tegra_clk_sbus_cmplx, NULL, 0, 0), + + SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), + SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), + SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("usbd.emc", "tegra-udc.0", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("mon.emc", "tegra_actmon", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING), + SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("mpe.emc", "tegra_mpe", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), + SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0), + + SHARED_CLK("host1x.cbus", "tegra_host1x", "host1x", &tegra_clk_cbus, "host1x", 2, SHARED_AUTO), + SHARED_CLK("3d.cbus", "tegra_gr3d", "gr3d", &tegra_clk_cbus, "3d", 0, 0), + SHARED_CLK("3d2.cbus", "tegra_gr3d", "gr3d2", &tegra_clk_cbus, "3d2", 0, 0), + SHARED_CLK("2d.cbus", "tegra_gr2d", "gr2d", &tegra_clk_cbus, "2d", 0, 0), + SHARED_CLK("epp.cbus", "tegra_gr2d", "epp", &tegra_clk_cbus, "epp", 0, 0), + SHARED_CLK("mpe.cbus", "tegra_mpe", "mpe", &tegra_clk_cbus, "mpe", 0, 0), + SHARED_CLK("vde.cbus", "tegra-avp", "vde", &tegra_clk_cbus, "vde", 0, 0), +#ifdef CONFIG_TEGRA_SE_ON_CBUS + SHARED_CLK("se.cbus", "tegra-se", NULL, &tegra_clk_cbus, "se", 0, 0), +#endif + SHARED_CLK("cap.cbus", "cap.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), + SHARED_CLK("cap.profile.cbus", "profile.cbus", NULL, &tegra_clk_cbus, NULL, 0, SHARED_CEILING), + SHARED_CLK("floor.cbus", "floor.cbus", NULL, &tegra_clk_cbus, NULL, 0, 0), +}; + +#define CLK_DUPLICATE(_name, _dev, _con) \ + { \ + .name = _name, \ + .lookup = { \ + .dev_id = _dev, \ + .con_id = _con, \ + }, \ + } + +/* Some clocks may be used by different drivers depending on the board + * configuration. List those here to register them twice in the clock lookup + * table under two names. + */ +struct clk_duplicate tegra_clk_duplicates[] = { + CLK_DUPLICATE("usbd", "utmip-pad", NULL), + CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), + CLK_DUPLICATE("usbd", "tegra-otg", NULL), + CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), + CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), + CLK_DUPLICATE("dsib", "tegradc.0", "dsib"), + CLK_DUPLICATE("dsia", "tegradc.1", "dsia"), + CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), + CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL), + CLK_DUPLICATE("cop", "tegra-avp", "cop"), + CLK_DUPLICATE("bsev", "tegra-avp", "bsev"), + CLK_DUPLICATE("cop", "nvavp", "cop"), + CLK_DUPLICATE("bsev", "nvavp", "bsev"), + CLK_DUPLICATE("vde", "tegra-aes", "vde"), + CLK_DUPLICATE("bsea", "tegra-aes", "bsea"), + CLK_DUPLICATE("bsea", "nvavp", "bsea"), + CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL), + CLK_DUPLICATE("cml0", "tegra_pcie", "cml"), + CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"), + CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL), + CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL), + CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL), + CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL), + CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL), + CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL), + CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL), + CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL), + CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL), + CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL), + CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), + CLK_DUPLICATE("twd", "smp_twd", NULL), + CLK_DUPLICATE("vcp", "nvavp", "vcp"), + CLK_DUPLICATE("avp.sclk", "nvavp", "sclk"), + CLK_DUPLICATE("avp.emc", "nvavp", "emc"), + CLK_DUPLICATE("vde.cbus", "nvavp", "vde"), + CLK_DUPLICATE("epp.cbus", "tegra_isp", "epp"), +}; + +struct clk *tegra_ptr_clks[] = { + &tegra_clk_32k, + &tegra_clk_m, + &tegra_clk_m_div2, + &tegra_clk_m_div4, + &tegra_pll_ref, + &tegra_pll_m, + &tegra_pll_m_out1, + &tegra_pll_c, + &tegra_pll_c_out1, + &tegra_pll_p, + &tegra_pll_p_out1, + &tegra_pll_p_out2, + &tegra_pll_p_out3, + &tegra_pll_p_out4, + &tegra_pll_a, + &tegra_pll_a_out0, + &tegra_pll_d, + &tegra_pll_d_out0, + &tegra_pll_d2, + &tegra_pll_d2_out0, + &tegra_pll_u, + &tegra_pll_x, + &tegra_pll_x_out0, + &tegra_pll_e, + &tegra_cml0_clk, + &tegra_cml1_clk, + &tegra_pciex_clk, + &tegra_clk_cclk_g, + &tegra_clk_cclk_lp, + &tegra_clk_sclk, + &tegra_clk_hclk, + &tegra_clk_pclk, + &tegra_clk_virtual_cpu_g, + &tegra_clk_virtual_cpu_lp, + &tegra_clk_cpu_cmplx, + &tegra_clk_blink, + &tegra_clk_cop, + &tegra_clk_sbus_cmplx, + &tegra_clk_emc, + &tegra3_clk_twd, + &tegra_clk_emc_bridge, + &tegra_clk_cbus, +}; + +static int tegra3_emc_relock_set_rate(struct clk *emc, unsigned long old_rate, + unsigned long new_rate, unsigned long new_pll_rate) +{ + int ret; + + struct clk *sbus = &tegra_clk_sbus_cmplx; + struct clk *cbus = &tegra_clk_cbus; + struct clk *pll_m = &tegra_pll_m; + unsigned long backup_rate = emc->shared_bus_backup.bus_rate; + unsigned long flags; + + bool on_pllm = emc->parent == pll_m; + + /* + * Relock procedure pre-conditions: + * - LPDDR2 only + * - EMC clock is enabled, and EMC backup rate is found in DFS table + * - All 3 shared buses: emc, sbus, cbus can sleep + */ + if ((tegra_emc_get_dram_type() != DRAM_TYPE_LPDDR2) || !emc->refcnt || + !backup_rate || (cbus->parent != emc->shared_bus_backup.input) || + !clk_cansleep(emc) || !clk_cansleep(cbus) || !clk_cansleep(sbus)) + return -ENOSYS; + + /* Move sbus from PLLM by setting it at low rate threshold level */ + clk_lock_save(sbus, &flags); + if (clk_get_rate_locked(sbus) > sbus->u.system.threshold) { + ret = clk_set_rate_locked(sbus, sbus->u.system.threshold); + if (ret) + goto _sbus_out; + } + + /* If PLLM is current EMC parent set cbus to backup rate, and move EMC + to backup PLLC */ + if (on_pllm) { + clk_lock_save(cbus, &flags); + clk_enable(cbus->parent); + ret = clk_set_rate_locked(cbus, backup_rate); + if (ret) { + clk_disable(cbus->parent); + goto _cbus_out; + } + + ret = tegra_emc_backup(backup_rate); + if (ret) { + clk_disable(cbus->parent); + goto _cbus_out; + } + clk_disable(emc->parent); + clk_reparent(emc, cbus->parent); + } + + /* + * Re-lock PLLM and switch EMC to it; relocking error indicates that + * PLLM has some other than EMC or sbus client. In this case PLLM has + * not been changed, and we still can safely switch back. Recursive + * tegra3_emc_clk_set_rate() call below will be resolved, since PLLM + * is now matching target rate. + */ + ret = clk_set_rate(pll_m, new_pll_rate); + if (ret) { + if (on_pllm) + tegra3_emc_clk_set_rate(emc, old_rate); + } else + ret = tegra3_emc_clk_set_rate(emc, new_rate); + + +_cbus_out: + if (on_pllm) { + tegra3_clk_shared_bus_update(cbus); + clk_unlock_restore(cbus, &flags); + } + +_sbus_out: + tegra3_clk_shared_bus_update(sbus); + clk_unlock_restore(sbus, &flags); + + return ret; +} + +/* + * Backup rate targets for each CPU mode is selected below Fmax(Vmin), and + * high enough to avoid voltage droop when CPU clock is switched between + * backup and main clock sources. Actual backup rates will be rounded based + * on backup source fixed frequency. Maximum stay-on-backup rate will be set + * as a minimum of G and LP backup rates to be supported in both modes. + * + * Sbus threshold must be exact factor of pll_p rate. + */ +#define CPU_G_BACKUP_RATE_TARGET 440000000 +#define CPU_LP_BACKUP_RATE_TARGET 220000000 + +static void tegra3_pllp_init_dependencies(unsigned long pllp_rate) +{ + u32 div; + unsigned long backup_rate; + + switch (pllp_rate) { + case 216000000: + tegra_pll_p_out1.u.pll_div.default_rate = 28800000; + tegra_pll_p_out3.u.pll_div.default_rate = 72000000; + tegra_clk_sbus_cmplx.u.system.threshold = 108000000; + break; + case 408000000: + tegra_pll_p_out1.u.pll_div.default_rate = 9600000; + tegra_pll_p_out3.u.pll_div.default_rate = 102000000; + tegra_clk_sbus_cmplx.u.system.threshold = 204000000; + break; + case 204000000: + tegra_pll_p_out1.u.pll_div.default_rate = 4800000; + tegra_pll_p_out3.u.pll_div.default_rate = 102000000; + tegra_clk_sbus_cmplx.u.system.threshold = 204000000; + break; + default: + pr_err("tegra: PLLP rate: %lu is not supported\n", pllp_rate); + BUG(); + } + pr_info("tegra: PLLP fixed rate: %lu\n", pllp_rate); + + div = DIV_ROUND_UP(pllp_rate, CPU_G_BACKUP_RATE_TARGET); + backup_rate = pllp_rate / div; + tegra_clk_cclk_g.u.cclk.div71 = 2 * div - 2; + tegra_clk_virtual_cpu_g.u.cpu.backup_rate = backup_rate; + cpu_stay_on_backup_max = backup_rate; + + div = DIV_ROUND_UP(pllp_rate, CPU_LP_BACKUP_RATE_TARGET); + backup_rate = pllp_rate / div; + tegra_clk_cclk_lp.u.cclk.div71 = 2 * div - 2; + tegra_clk_virtual_cpu_lp.u.cpu.backup_rate = backup_rate; + cpu_stay_on_backup_max = min(cpu_stay_on_backup_max, backup_rate); +} + +bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p) +{ + if (c->flags & PERIPH_ON_CBUS) + return p != &tegra_pll_m; + else + return p != &tegra_pll_c; + + return true; +} + +static void tegra3_init_one_clock(struct clk *c) +{ + clk_init(c); + INIT_LIST_HEAD(&c->shared_bus_list); + if (!c->lookup.dev_id && !c->lookup.con_id) + c->lookup.con_id = c->name; + c->lookup.clk = c; + clkdev_add(&c->lookup); +} + +/* + * Emergency throttle of G-CPU by setting G-super clock skipper underneath + * clock framework, dvfs, and cpufreq driver s/w layers. Can be called in + * ISR context for EDP events. When releasing throttle, LP-divider is cleared + * just in case it was set as a result of save/restore operations across + * cluster switch (should not happen) + */ +void tegra_edp_throttle_cpu_now(u8 factor) +{ + if (factor > 1) { + if (!is_lp_cluster()) + tegra3_super_clk_skipper_update( + &tegra_clk_cclk_g, 1, factor); + } else if (factor == 0) { + tegra3_super_clk_skipper_update(&tegra_clk_cclk_g, 0, 0); + tegra3_super_clk_skipper_update(&tegra_clk_cclk_lp, 0, 0); + } +} + +#ifdef CONFIG_CPU_FREQ + +/* + * Frequency table index must be sequential starting at 0 and frequencies + * must be ascending. Re-configurable PLLX is used as a source for rates + * above 204MHz. Rates 204MHz and below are divided down from fixed frequency + * PLLP that may run either at 408MHz or at 204MHz on Tegra3 silicon platforms + * (on FPGA platform PLLP output is reported as 216MHz, but no respective + * tables are provided, since there is no clock scaling on FPGA at all). + */ + +static struct cpufreq_frequency_table freq_table_300MHz[] = { + { 0, 204000 }, + { 1, 300000 }, + { 2, CPUFREQ_TABLE_END }, +}; + +static struct cpufreq_frequency_table freq_table_1p0GHz[] = { + { 0, 51000 }, + { 1, 102000 }, + { 2, 204000 }, + { 3, 312000 }, + { 4, 456000 }, + { 5, 608000 }, + { 6, 760000 }, + { 7, 816000 }, + { 8, 912000 }, + { 9, 1000000 }, + {10, CPUFREQ_TABLE_END }, +}; + +static struct cpufreq_frequency_table freq_table_1p3GHz[] = { + { 0, 51000 }, + { 1, 102000 }, + { 2, 204000 }, + { 3, 340000 }, + { 4, 475000 }, + { 5, 640000 }, + { 6, 760000 }, + { 7, 860000 }, + { 8, 1000000 }, + { 9, 1100000 }, + {10, 1200000 }, + {11, 1300000 }, + {12, CPUFREQ_TABLE_END }, +}; + +static struct cpufreq_frequency_table freq_table_1p4GHz[] = { + { 0, 51000 }, + { 1, 102000 }, + { 2, 204000 }, + { 3, 370000 }, + { 4, 475000 }, + { 5, 620000 }, + { 6, 760000 }, + { 7, 860000 }, + { 8, 1000000 }, + { 9, 1100000 }, + {10, 1200000 }, + {11, 1300000 }, + {12, 1400000 }, + {13, CPUFREQ_TABLE_END }, +}; + +static struct cpufreq_frequency_table freq_table_1p5GHz[] = { + { 0, 51000 }, + { 1, 102000 }, + { 2, 204000 }, + { 3, 340000 }, + { 4, 475000 }, + { 5, 640000 }, + { 6, 760000 }, + { 7, 860000 }, + { 8, 1000000 }, + { 9, 1100000 }, + {10, 1200000 }, + {11, 1300000 }, + {12, 1400000 }, + {13, 1500000 }, + {14, CPUFREQ_TABLE_END }, +}; + +static struct cpufreq_frequency_table freq_table_1p7GHz[] = { + { 0, 51000 }, + { 1, 102000 }, + { 2, 204000 }, + { 3, 370000 }, + { 4, 475000 }, + { 5, 620000 }, + { 6, 760000 }, + { 7, 910000 }, + { 8, 1000000 }, + { 9, 1150000 }, + {10, 1300000 }, + {11, 1400000 }, + {12, 1500000 }, + {13, 1600000 }, + {14, 1700000 }, + {15, CPUFREQ_TABLE_END }, +}; + +static struct tegra_cpufreq_table_data cpufreq_tables[] = { + { freq_table_300MHz, 0, 1 }, + { freq_table_1p0GHz, 2, 8 }, + { freq_table_1p3GHz, 2, 10 }, + { freq_table_1p4GHz, 2, 11 }, + { freq_table_1p5GHz, 2, 12 }, + { freq_table_1p7GHz, 2, 12 }, +}; + +static int clip_cpu_rate_limits( + struct tegra_cpufreq_table_data *data, + struct cpufreq_policy *policy, + struct clk *cpu_clk_g, + struct clk *cpu_clk_lp) +{ + int idx, ret; + struct cpufreq_frequency_table *freq_table = data->freq_table; + + /* clip CPU G mode maximum frequency to table entry */ + ret = cpufreq_frequency_table_target(policy, freq_table, + cpu_clk_g->max_rate / 1000, CPUFREQ_RELATION_H, &idx); + if (ret) { + pr_err("%s: G CPU max rate %lu outside of cpufreq table", + __func__, cpu_clk_g->max_rate); + return ret; + } + cpu_clk_g->max_rate = freq_table[idx].frequency * 1000; + if (cpu_clk_g->max_rate < cpu_clk_lp->max_rate) { + pr_err("%s: G CPU max rate %lu is below LP CPU max rate %lu", + __func__, cpu_clk_g->max_rate, cpu_clk_lp->max_rate); + return -EINVAL; + } + + /* clip CPU LP mode maximum frequency to table entry, and + set CPU G mode minimum frequency one table step below */ + ret = cpufreq_frequency_table_target(policy, freq_table, + cpu_clk_lp->max_rate / 1000, CPUFREQ_RELATION_H, &idx); + if (ret || !idx) { + pr_err("%s: LP CPU max rate %lu %s of cpufreq table", __func__, + cpu_clk_lp->max_rate, ret ? "outside" : "at the bottom"); + return ret; + } + cpu_clk_lp->max_rate = freq_table[idx].frequency * 1000; + cpu_clk_g->min_rate = freq_table[idx-1].frequency * 1000; + data->suspend_index = idx; + return 0; +} + +struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) +{ + int i, ret; + unsigned long selection_rate; + struct clk *cpu_clk_g = tegra_get_clock_by_name("cpu_g"); + struct clk *cpu_clk_lp = tegra_get_clock_by_name("cpu_lp"); + + /* For table selection use top cpu_g rate in dvfs ladder; selection + rate may exceed cpu max_rate (e.g., because of edp limitations on + cpu voltage) - in any case max_rate will be clipped to the table */ + if (cpu_clk_g->dvfs && cpu_clk_g->dvfs->num_freqs) + selection_rate = + cpu_clk_g->dvfs->freqs[cpu_clk_g->dvfs->num_freqs - 1]; + else + selection_rate = cpu_clk_g->max_rate; + + for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) { + struct cpufreq_policy policy; + policy.cpu = 0; /* any on-line cpu */ + ret = cpufreq_frequency_table_cpuinfo( + &policy, cpufreq_tables[i].freq_table); + if (!ret) { + if ((policy.max * 1000) == selection_rate) { + ret = clip_cpu_rate_limits( + &cpufreq_tables[i], + &policy, cpu_clk_g, cpu_clk_lp); + if (!ret) + return &cpufreq_tables[i]; + } + } + } + WARN(1, "%s: No cpufreq table matching G & LP cpu ranges", __func__); + return NULL; +} + +/* On DDR3 platforms there is an implicit dependency in this mapping: when cpu + * exceeds max dvfs level for LP CPU clock at TEGRA_EMC_BRIDGE_MVOLTS_MIN, the + * respective emc rate should be above TEGRA_EMC_BRIDGE_RATE_MIN + */ +/* FIXME: explicitly check this dependency */ +unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) +{ + static unsigned long emc_max_rate = 0; + + if (emc_max_rate == 0) + emc_max_rate = clk_round_rate( + tegra_get_clock_by_name("emc"), ULONG_MAX); + + /* Vote on memory bus frequency based on cpu frequency; + cpu rate is in kHz, emc rate is in Hz */ + if (cpu_rate >= 925000) + return emc_max_rate; /* cpu >= 925 MHz, emc max */ + else if (cpu_rate >= 450000) + return emc_max_rate/2; /* cpu >= 450 MHz, emc max/2 */ + else if (cpu_rate >= 250000) + return 100000000; /* cpu >= 250 MHz, emc 100 MHz */ + else + return 0; /* emc min */ +} + +int tegra_update_mselect_rate(unsigned long cpu_rate) +{ + static struct clk *mselect = NULL; + + unsigned long mselect_rate; + + if (!mselect) { + mselect = tegra_get_clock_by_name("mselect"); + if (!mselect) + return -ENODEV; + } + + /* Vote on mselect frequency based on cpu frequency: + keep mselect at half of cpu rate up to 102 MHz; + cpu rate is in kHz, mselect rate is in Hz */ + mselect_rate = DIV_ROUND_UP(cpu_rate, 2) * 1000; + mselect_rate = min(mselect_rate, 102000000UL); + + if (mselect_rate != clk_get_rate(mselect)) + return clk_set_rate(mselect, mselect_rate); + + return 0; +} +#endif + +#ifdef CONFIG_PM_SLEEP +static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + + PERIPH_CLK_SOURCE_NUM + 24]; + +static int tegra_clk_suspend(void) +{ + unsigned long off; + u32 *ctx = clk_rst_suspend; + + *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; + *ctx++ = clk_readl(CPU_SOFTRST_CTRL); + + *ctx++ = clk_readl(tegra_pll_p_out1.reg); + *ctx++ = clk_readl(tegra_pll_p_out3.reg); + + *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); + *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_BASE); + *ctx++ = clk_readl(tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); + + *ctx++ = clk_readl(tegra_pll_m_out1.reg); + *ctx++ = clk_readl(tegra_pll_a_out0.reg); + *ctx++ = clk_readl(tegra_pll_c_out1.reg); + + *ctx++ = clk_readl(tegra_clk_cclk_g.reg); + *ctx++ = clk_readl(tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); + *ctx++ = clk_readl(tegra_clk_cclk_lp.reg); + *ctx++ = clk_readl(tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); + + *ctx++ = clk_readl(tegra_clk_sclk.reg); + *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); + *ctx++ = clk_readl(tegra_clk_pclk.reg); + + for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; + off += 4) { + if (off == PERIPH_CLK_SOURCE_EMC) + continue; + *ctx++ = clk_readl(off); + } + for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; + off+=4) { + *ctx++ = clk_readl(off); + } + for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { + *ctx++ = clk_readl(off); + } + + *ctx++ = clk_readl(RST_DEVICES_L); + *ctx++ = clk_readl(RST_DEVICES_H); + *ctx++ = clk_readl(RST_DEVICES_U); + *ctx++ = clk_readl(RST_DEVICES_V); + *ctx++ = clk_readl(RST_DEVICES_W); + + *ctx++ = clk_readl(CLK_OUT_ENB_L); + *ctx++ = clk_readl(CLK_OUT_ENB_H); + *ctx++ = clk_readl(CLK_OUT_ENB_U); + *ctx++ = clk_readl(CLK_OUT_ENB_V); + *ctx++ = clk_readl(CLK_OUT_ENB_W); + + *ctx++ = clk_readl(MISC_CLK_ENB); + *ctx++ = clk_readl(CLK_MASK_ARM); + + return 0; +} + +static void tegra_clk_resume(void) +{ + unsigned long off; + const u32 *ctx = clk_rst_suspend; + u32 val; + u32 pllc_base; + u32 plla_base; + u32 plld_base; + u32 plld2_base; + u32 pll_p_out12, pll_p_out34; + u32 pll_a_out0, pll_m_out1, pll_c_out1; + struct clk *p; + + val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; + val |= *ctx++; + clk_writel(val, OSC_CTRL); + clk_writel(*ctx++, CPU_SOFTRST_CTRL); + + /* Since we are going to reset devices and switch clock sources in this + * function, plls and secondary dividers is required to be enabled. The + * actual value will be restored back later. Note that boot plls: pllm, + * pllp, and pllu are already configured and enabled. + */ + val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; + val |= val << 16; + pll_p_out12 = *ctx++; + clk_writel(pll_p_out12 | val, tegra_pll_p_out1.reg); + pll_p_out34 = *ctx++; + clk_writel(pll_p_out34 | val, tegra_pll_p_out3.reg); + + pllc_base = *ctx++; + clk_writel(pllc_base | PLL_BASE_ENABLE, tegra_pll_c.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); + + plla_base = *ctx++; + clk_writel(plla_base | PLL_BASE_ENABLE, tegra_pll_a.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); + + plld_base = *ctx++; + clk_writel(plld_base | PLL_BASE_ENABLE, tegra_pll_d.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); + + plld2_base = *ctx++; + clk_writel(plld2_base | PLL_BASE_ENABLE, tegra_pll_d2.reg + PLL_BASE); + clk_writel(*ctx++, tegra_pll_d2.reg + PLL_MISC(&tegra_pll_d2)); + + udelay(1000); + + val = PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; + pll_m_out1 = *ctx++; + clk_writel(pll_m_out1 | val, tegra_pll_m_out1.reg); + pll_a_out0 = *ctx++; + clk_writel(pll_a_out0 | val, tegra_pll_a_out0.reg); + pll_c_out1 = *ctx++; + clk_writel(pll_c_out1 | val, tegra_pll_c_out1.reg); + + clk_writel(*ctx++, tegra_clk_cclk_g.reg); + clk_writel(*ctx++, tegra_clk_cclk_g.reg + SUPER_CLK_DIVIDER); + clk_writel(*ctx++, tegra_clk_cclk_lp.reg); + clk_writel(*ctx++, tegra_clk_cclk_lp.reg + SUPER_CLK_DIVIDER); + + clk_writel(*ctx++, tegra_clk_sclk.reg); + clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); + clk_writel(*ctx++, tegra_clk_pclk.reg); + + /* enable all clocks before configuring clock sources */ + clk_writel(0xfdfffff1ul, CLK_OUT_ENB_L); + clk_writel(0xfefff7f7ul, CLK_OUT_ENB_H); + clk_writel(0x75f79bfful, CLK_OUT_ENB_U); + clk_writel(0xfffffffful, CLK_OUT_ENB_V); + clk_writel(0x00003ffful, CLK_OUT_ENB_W); + wmb(); + + for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; + off += 4) { + if (off == PERIPH_CLK_SOURCE_EMC) + continue; + clk_writel(*ctx++, off); + } + for (off = PERIPH_CLK_SOURCE_G3D2; off <= PERIPH_CLK_SOURCE_SE; + off += 4) { + clk_writel(*ctx++, off); + } + for (off = AUDIO_DLY_CLK; off <= AUDIO_SYNC_CLK_SPDIF; off+=4) { + clk_writel(*ctx++, off); + } + wmb(); + + clk_writel(*ctx++, RST_DEVICES_L); + clk_writel(*ctx++, RST_DEVICES_H); + clk_writel(*ctx++, RST_DEVICES_U); + + /* For LP0 resume, don't reset lpcpu, since we are running from it */ + val = *ctx++; + val &= ~RST_DEVICES_V_SWR_CPULP_RST_DIS; + clk_writel(val, RST_DEVICES_V); + + clk_writel(*ctx++, RST_DEVICES_W); + wmb(); + + clk_writel(*ctx++, CLK_OUT_ENB_L); + clk_writel(*ctx++, CLK_OUT_ENB_H); + clk_writel(*ctx++, CLK_OUT_ENB_U); + + /* For LP0 resume, clk to lpcpu is required to be on */ + val = *ctx++; + val |= CLK_OUT_ENB_V_CLK_ENB_CPULP_EN; + clk_writel(val, CLK_OUT_ENB_V); + + clk_writel(*ctx++, CLK_OUT_ENB_W); + wmb(); + + clk_writel(*ctx++, MISC_CLK_ENB); + clk_writel(*ctx++, CLK_MASK_ARM); + + /* Restore back the actual pll and secondary divider values */ + /* FIXME: need to root cause why pllc is required to be on + * clk_writel(pllc_base, tegra_pll_c.reg + PLL_BASE); + */ + clk_writel(pll_p_out12, tegra_pll_p_out1.reg); + clk_writel(pll_p_out34, tegra_pll_p_out3.reg); + + clk_writel(plla_base, tegra_pll_a.reg + PLL_BASE); + clk_writel(plld_base, tegra_pll_d.reg + PLL_BASE); + clk_writel(plld2_base, tegra_pll_d2.reg + PLL_BASE); + + clk_writel(pll_m_out1, tegra_pll_m_out1.reg); + clk_writel(pll_a_out0, tegra_pll_a_out0.reg); + clk_writel(pll_c_out1, tegra_pll_c_out1.reg); + + /* Since EMC clock is not restored, and may not preserve parent across + suspend, update current state, and mark EMC DFS as out of sync */ + tegra3_pll_m_override_update(&tegra_pll_m, false); + p = tegra_clk_emc.parent; + tegra3_periph_clk_init(&tegra_clk_emc); + + if (p != tegra_clk_emc.parent) { + /* FIXME: old parent is left enabled here even if EMC was its + only child before suspend (never happens on Tegra3) */ + pr_debug("EMC parent(refcount) across suspend: %s(%d) : %s(%d)", + p->name, p->refcnt, tegra_clk_emc.parent->name, + tegra_clk_emc.parent->refcnt); + + BUG_ON(!p->refcnt); + p->refcnt--; + + /* the new parent is enabled by low level code, but ref count + need to be updated up to the root */ + p = tegra_clk_emc.parent; + while (p && ((p->refcnt++) == 0)) + p = p->parent; + } + tegra_emc_timing_invalidate(); + + tegra3_pll_clk_init(&tegra_pll_u); /* Re-init utmi parameters */ + tegra3_pllp_clk_resume(&tegra_pll_p); /* Fire a bug if not restored */ +} +#else +#define tegra_clk_suspend NULL +#define tegra_clk_resume NULL +#endif + +static struct syscore_ops tegra_clk_syscore_ops = { + .suspend = tegra_clk_suspend, + .resume = tegra_clk_resume, +}; + +#ifdef CONFIG_TEGRA_PREINIT_CLOCKS + +#define CLK_RSTENB_DEV_V_0_DAM2_BIT (1 << 14) +#define CLK_RSTENB_DEV_V_0_DAM1_BIT (1 << 13) +#define CLK_RSTENB_DEV_V_0_DAM0_BIT (1 << 12) +#define CLK_RSTENB_DEV_V_0_AUDIO_BIT (1 << 10) +#define CLK_RSTENB_DEV_V_0_3D2_BIT (1 << 2) + +#define CLK_RSTENB_DEV_L_0_HOST1X_BIT (1 << 28) +#define CLK_RSTENB_DEV_L_0_DISP1_BIT (1 << 27) +#define CLK_RSTENB_DEV_L_0_3D_BIT (1 << 24) +#define CLK_RSTENB_DEV_L_0_2D_BIT (1 << 21) +#define CLK_RSTENB_DEV_L_0_VI_BIT (1 << 20) +#define CLK_RSTENB_DEV_L_0_EPP_BIT (1 << 19) + +#define CLK_RSTENB_DEV_H_0_VDE_BIT (1 << 29) +#define CLK_RSTENB_DEV_H_0_MPE_BIT (1 << 28) + +#define DISP1_CLK_REG_OFFSET 0x138 +#define DISP1_CLK_SRC_SHIFT 29 +#define DISP1_CLK_SRC_MASK (0x7 << DISP1_CLK_SRC_SHIFT) +#define DISP1_CLK_SRC_PLLP_OUT0 0 +#define DISP1_CLK_SRC_PLLM_OUT0 1 +#define DISP1_CLK_SRC_PLLD_OUT0 2 +#define DISP1_CLK_SRC_PLLA_OUT0 3 +#define DISP1_CLK_SRC_PLLC_OUT0 4 +#define DISP1_CLK_SRC_PLLD2_OUT0 5 +#define DISP1_CLK_SRC_CLKM 6 +#define DISP1_CLK_SRC_DEFAULT (DISP1_CLK_SRC_PLLP_OUT0 << DISP1_CLK_SRC_SHIFT) + +#define HOST1X_CLK_REG_OFFSET 0x180 +#define HOST1X_CLK_SRC_SHIFT 30 +#define HOST1X_CLK_SRC_MASK (0x3 << HOST1X_CLK_SRC_SHIFT) +#define HOST1X_CLK_SRC_PLLM_OUT0 0 +#define HOST1X_CLK_SRC_PLLC_OUT0 1 +#define HOST1X_CLK_SRC_PLLP_OUT0 2 +#define HOST1X_CLK_SRC_PLLA_OUT0 3 +#define HOST1X_CLK_SRC_DEFAULT (\ + HOST1X_CLK_SRC_PLLP_OUT0 << HOST1X_CLK_SRC_SHIFT) +#define HOST1X_CLK_IDLE_DIV_SHIFT 8 +#define HOST1X_CLK_IDLE_DIV_MASK (0xff << HOST1X_CLK_IDLE_DIV_SHIFT) +#define HOST1X_CLK_IDLE_DIV_DEFAULT (0 << HOST1X_CLK_IDLE_DIV_SHIFT) +#define HOST1X_CLK_DIV_SHIFT 0 +#define HOST1X_CLK_DIV_MASK (0xff << HOST1X_CLK_DIV_SHIFT) +#define HOST1X_CLK_DIV_DEFAULT (3 << HOST1X_CLK_DIV_SHIFT) + +#define AUDIO_CLK_REG_OFFSET 0x3d0 +#define DAM0_CLK_REG_OFFSET 0x3d8 +#define DAM1_CLK_REG_OFFSET 0x3dc +#define DAM2_CLK_REG_OFFSET 0x3e0 +#define AUDIO_CLK_SRC_SHIFT 28 +#define AUDIO_CLK_SRC_MASK (0x0f << AUDIO_CLK_SRC_SHIFT) +#define AUDIO_CLK_SRC_PLLA_OUT0 0x01 +#define AUDIO_CLK_SRC_PLLC_OUT0 0x05 +#define AUDIO_CLK_SRC_PLLP_OUT0 0x09 +#define AUDIO_CLK_SRC_CLKM 0x0d +#define AUDIO_CLK_SRC_DEFAULT (\ + AUDIO_CLK_SRC_CLKM << AUDIO_CLK_SRC_SHIFT) +#define AUDIO_CLK_DIV_SHIFT 0 +#define AUDIO_CLK_DIV_MASK (0xff << AUDIO_CLK_DIV_SHIFT) +#define AUDIO_CLK_DIV_DEFAULT (\ + (0 << AUDIO_CLK_DIV_SHIFT)) + +#define VCLK_SRC_SHIFT 30 +#define VCLK_SRC_MASK (0x3 << VCLK_SRC_SHIFT) +#define VCLK_SRC_PLLM_OUT0 0 +#define VCLK_SRC_PLLC_OUT0 1 +#define VCLK_SRC_PLLP_OUT0 2 +#define VCLK_SRC_PLLA_OUT0 3 +#define VCLK_SRC_DEFAULT (VCLK_SRC_PLLM_OUT0 << VCLK_SRC_SHIFT) +#define VCLK_IDLE_DIV_SHIFT 8 +#define VCLK_IDLE_DIV_MASK (0xff << VCLK_IDLE_DIV_SHIFT) +#define VCLK_IDLE_DIV_DEFAULT (0 << VCLK_IDLE_DIV_SHIFT) +#define VCLK_DIV_SHIFT 0 +#define VCLK_DIV_MASK (0xff << VCLK_DIV_SHIFT) +#define VCLK_DIV_DEFAULT (0xa << VCLK_DIV_SHIFT) + +#define VI_CLK_REG_OFFSET 0x148 +#define VI_CLK_SEL_VI_SENSOR_CLK (1 << 25) +#define VI_CLK_SEL_EXTERNAL_CLK (1 << 24) +#define VI_SENSOR_CLK_REG_OFFSET 0x1a8 +#define G3D_CLK_REG_OFFSET 0x158 +#define G2D_CLK_REG_OFFSET 0x15c +#define EPP_CLK_REG_OFFSET 0x16c +#define MPE_CLK_REG_OFFSET 0x170 +#define VDE_CLK_REG_OFFSET 0x170 +#define G3D2_CLK_REG_OFFSET 0x3b0 + +static void __init clk_setbit(u32 reg, u32 bit) +{ + u32 val = clk_readl(reg); + + if ((val & bit) == bit) + return; + val |= bit; + clk_writel(val, reg); + udelay(2); +} + +static void __init clk_clrbit(u32 reg, u32 bit) +{ + u32 val = clk_readl(reg); + + if ((val & bit) == 0) + return; + val &= ~bit; + clk_writel(val, reg); + udelay(2); +} + +static void __init clk_setbits(u32 reg, u32 bits, u32 mask) +{ + u32 val = clk_readl(reg); + + if ((val & mask) == bits) + return; + val &= ~mask; + val |= bits; + clk_writel(val, reg); + udelay(2); +} + +static void __init vclk_init(int tag, u32 src, u32 rebit) +{ + u32 rst, enb; + + switch (tag) { + case 'L': + rst = RST_DEVICES_L; + enb = CLK_OUT_ENB_L; + break; + case 'H': + rst = RST_DEVICES_H; + enb = CLK_OUT_ENB_H; + break; + case 'U': + rst = RST_DEVICES_U; + enb = CLK_OUT_ENB_U; + break; + case 'V': + rst = RST_DEVICES_V; + enb = CLK_OUT_ENB_V; + break; + case 'W': + rst = RST_DEVICES_W; + enb = CLK_OUT_ENB_W; + break; + default: + /* Quietly ignore. */ + return; + } + + clk_setbit(rst, rebit); + clk_clrbit(enb, rebit); + clk_setbits(src, VCLK_SRC_DEFAULT, VCLK_SRC_MASK); + clk_setbits(src, VCLK_DIV_DEFAULT, VCLK_DIV_MASK); + clk_clrbit(rst, rebit); +} + +static int __init tegra_soc_preinit_clocks(void) +{ + /* + * Make sure host1x clock configuration has: + * HOST1X_CLK_SRC : PLLP_OUT0. + * HOST1X_CLK_DIVISOR: >2 to start from safe enough frequency. + */ + clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); + clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); + clk_setbits(HOST1X_CLK_REG_OFFSET, + HOST1X_CLK_DIV_DEFAULT, HOST1X_CLK_DIV_MASK); + clk_setbits(HOST1X_CLK_REG_OFFSET, + HOST1X_CLK_IDLE_DIV_DEFAULT, HOST1X_CLK_IDLE_DIV_MASK); + clk_setbits(HOST1X_CLK_REG_OFFSET, + HOST1X_CLK_SRC_DEFAULT, HOST1X_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_HOST1X_BIT); + + /* + * Make sure disp1 clock configuration ha: + * DISP1_CLK_SRC: DISP1_CLK_SRC_PLLP_OUT0 + */ + clk_setbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); + clk_setbit(CLK_OUT_ENB_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); + clk_setbits(DISP1_CLK_REG_OFFSET, + DISP1_CLK_SRC_DEFAULT, DISP1_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_L, CLK_RSTENB_DEV_L_0_DISP1_BIT); + + /* + * Make sure dam2 clock configuration has: + * DAM2_CLK_SRC: AUDIO_CLK_SRC_CLKM + */ + clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); + clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); + clk_setbits(DAM2_CLK_REG_OFFSET, + AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); + clk_setbits(DAM2_CLK_REG_OFFSET, + AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM2_BIT); + + /* + * Make sure dam1 clock configuration has: + * DAM1_CLK_SRC: AUDIO_CLK_SRC_CLKM + */ + clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); + clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); + clk_setbits(DAM1_CLK_REG_OFFSET, + AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); + clk_setbits(DAM1_CLK_REG_OFFSET, + AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM1_BIT); + + /* + * Make sure dam0 clock configuration has: + * DAM0_CLK_SRC: AUDIO_CLK_SRC_CLKM + */ + clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); + clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); + clk_setbits(DAM0_CLK_REG_OFFSET, + AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); + clk_setbits(DAM0_CLK_REG_OFFSET, + AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_DAM0_BIT); + + /* + * Make sure d_audio clock configuration has: + * AUDIO_CLK_SRC: AUDIO_CLK_SRC_CLKM + */ + clk_setbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); + clk_setbit(CLK_OUT_ENB_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); + clk_setbits(AUDIO_CLK_REG_OFFSET, + AUDIO_CLK_DIV_DEFAULT, AUDIO_CLK_DIV_MASK); + clk_setbits(AUDIO_CLK_REG_OFFSET, + AUDIO_CLK_SRC_DEFAULT, AUDIO_CLK_SRC_MASK); + clk_clrbit(RST_DEVICES_V, CLK_RSTENB_DEV_V_0_AUDIO_BIT); + + /* Pre-initialize Video clocks. */ + vclk_init('L', G3D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_3D_BIT); + vclk_init('L', G2D_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_2D_BIT); + vclk_init('L', VI_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_VI_BIT); + vclk_init('L', EPP_CLK_REG_OFFSET, CLK_RSTENB_DEV_L_0_EPP_BIT); + vclk_init('H', VDE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_VDE_BIT); + vclk_init('H', MPE_CLK_REG_OFFSET, CLK_RSTENB_DEV_H_0_MPE_BIT); + vclk_init('V', G3D2_CLK_REG_OFFSET, CLK_RSTENB_DEV_V_0_3D2_BIT); + + return 0; +} +#endif /* CONFIG_TEGRA_PREINIT_CLOCKS */ + +void __init tegra_soc_init_clocks(void) +{ + int i; + struct clk *c; + +#ifdef CONFIG_TEGRA_PREINIT_CLOCKS + tegra_soc_preinit_clocks(); +#endif /* CONFIG_TEGRA_PREINIT_CLOCKS */ + + for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) + tegra3_init_one_clock(tegra_ptr_clks[i]); + + for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) + tegra3_init_one_clock(&tegra_list_clks[i]); + + for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { + c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); + if (!c) { + pr_err("%s: Unknown duplicate clock %s\n", __func__, + tegra_clk_duplicates[i].name); + continue; + } + + tegra_clk_duplicates[i].lookup.clk = c; + clkdev_add(&tegra_clk_duplicates[i].lookup); + } + + for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++) + tegra3_init_one_clock(&tegra_sync_source_list[i]); + for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++) + tegra3_init_one_clock(&tegra_clk_audio_list[i]); + for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++) + tegra3_init_one_clock(&tegra_clk_audio_2x_list[i]); + + init_clk_out_mux(); + for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) + tegra3_init_one_clock(&tegra_clk_out_list[i]); + + emc_bridge = &tegra_clk_emc_bridge; + cpu_mode_sclk = tegra_get_clock_by_name("cpu_mode.sclk"); + + /* Initialize to default */ + tegra_init_cpu_edp_limits(0); + + register_syscore_ops(&tegra_clk_syscore_ops); +} diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 8479c14b685e..16356835055d 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -21,6 +21,7 @@ #include <linux/clk.h> #include <linux/kobject.h> #include <linux/err.h> +#include <linux/time.h> #include "clock.h" #include "dvfs.h" @@ -28,12 +29,16 @@ #include "board.h" #include "tegra3_emc.h" +#define CPU_MILLIVOLTS {\ + 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; + static bool tegra_dvfs_cpu_disabled; static bool tegra_dvfs_core_disabled; static struct dvfs *cpu_dvfs; -static const int cpu_millivolts[MAX_DVFS_FREQS] = { - 750, 762, 775, 787, 800, 825, 837, 850, 862, 875, 887, 900, 912, 916, 925, 937, 950, 962, 975, 987, 1000, 1007, 1012, 1025, 1037, 1050, 1062, 1075, 1087, 1100, 1112, 1125, 1137, 1150, 1162, 1175, 1187, 1200, 1212, 1237}; +static int cpu_millivolts[MAX_DVFS_FREQS] = CPU_MILLIVOLTS; + +static const int cpu_millivolts_aged[MAX_DVFS_FREQS] = CPU_MILLIVOLTS; static const unsigned int cpu_cold_offs_mhz[MAX_DVFS_FREQS] = { 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50}; @@ -54,7 +59,7 @@ static int cpu_below_core = VDD_CPU_BELOW_VDD_CORE; static struct dvfs_rail tegra3_dvfs_rail_vdd_cpu = { .reg_id = "vdd_cpu", .max_millivolts = 1250, - .min_millivolts = 750, + .min_millivolts = 725, .step = VDD_SAFE_STEP, .jmp_to_zero = true, }; @@ -632,6 +637,41 @@ static int __init get_core_nominal_mv_index(int speedo_id) return (i - 1); } +static void tegra_adjust_cpu_mvs(int mvs) +{ + int i; + + BUG_ON(ARRAY_SIZE(cpu_millivolts) != ARRAY_SIZE(cpu_millivolts_aged)); + + for (i = 0; i < ARRAY_SIZE(cpu_millivolts); i++) + cpu_millivolts[i] = cpu_millivolts_aged[i] - mvs; +} + +/** + * Adjust VDD_CPU to offset aging. + * 25mV for 1st year + * 12mV for 2nd and 3rd year + * 0mV for 4th year onwards + */ +void tegra_dvfs_age_cpu(int cur_linear_age) +{ + int chip_linear_age; + int chip_life; + chip_linear_age = tegra_get_age(); + chip_life = cur_linear_age - chip_linear_age; + + /*For T37 and AP37*/ + if (tegra_cpu_speedo_id() == 12 || tegra_cpu_speedo_id() == 13) { + if (chip_linear_age <= 0) { + return; + } else if (chip_life <= 12) { + tegra_adjust_cpu_mvs(25); + } else if (chip_life <= 36) { + tegra_adjust_cpu_mvs(13); + } + } +} + void __init tegra3_init_dvfs(void) { int cpu_speedo_id = tegra_cpu_speedo_id(); diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index 3c7fb4acd649..c0c46861c623 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/tegra3_speedo.c * - * Copyright (c) 2011, NVIDIA Corporation. + * Copyright (c) 2011-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,6 +26,8 @@ #include <mach/iomap.h> #include <mach/tegra_fuse.h> #include <mach/hardware.h> +#include <linux/module.h> +#include <linux/moduleparam.h> #include "fuse.h" @@ -131,6 +133,11 @@ static int core_process_id; static int cpu_speedo_id; static int soc_speedo_id; static int package_id; +/* + * Only AP37 supports App Profile + * This informs user space of support without exposing cpu id's + */ +static int enable_app_profiles; static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp) { @@ -270,6 +277,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) cpu_speedo_id = 12; soc_speedo_id = 2; threshold_index = 9; + enable_app_profiles = 1; break; default: pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", @@ -562,3 +570,15 @@ int tegra_core_speedo_mv(void) BUG(); } } + +static int get_enable_app_profiles(char *val, const struct kernel_param *kp) +{ + return param_get_uint(val, kp); +} + +static struct kernel_param_ops tegra_profiles_ops = { + .get = get_enable_app_profiles, +}; + +module_param_cb(tegra_enable_app_profiles, + &tegra_profiles_ops, &enable_app_profiles, 0444); diff --git a/arch/arm/mach-tegra/tegra3_usb_phy.c b/arch/arm/mach-tegra/tegra3_usb_phy.c index 3169c5b33b40..e6097201b67f 100644 --- a/arch/arm/mach-tegra/tegra3_usb_phy.c +++ b/arch/arm/mach-tegra/tegra3_usb_phy.c @@ -474,6 +474,11 @@ #define PHY_DBG(stuff...) do {} while (0) #endif +/* define HSIC phy params */ +#define HSIC_SYNC_START_DELAY 9 +#define HSIC_IDLE_WAIT_DELAY 17 +#define HSIC_ELASTIC_UNDERRUN_LIMIT 16 +#define HSIC_ELASTIC_OVERRUN_LIMIT 16 static u32 utmip_rctrl_val, utmip_tctrl_val; static DEFINE_SPINLOCK(utmip_pad_lock); @@ -743,6 +748,7 @@ static void utmip_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val = readl(pmc_base + PMC_TRIGGERS); val |= UTMIP_CLR_WALK_PTR(inst); + val |= UTMIP_CLR_WAKE_ALARM(inst); writel(val, pmc_base + PMC_TRIGGERS); phy->remote_wakeup = false; @@ -989,7 +995,8 @@ static int usb_phy_bringup_host_controller(struct tegra_usb_phy *phy) /* Program the field PTC based on the saved speed mode */ val = readl(base + USB_PORTSC); val &= ~USB_PORTSC_PTC(~0); - if (phy->port_speed == USB_PHY_PORT_SPEED_HIGH) + if ((phy->port_speed == USB_PHY_PORT_SPEED_HIGH) || + (phy->pdata->phy_intf == TEGRA_USB_PHY_INTF_HSIC)) val |= USB_PORTSC_PTC(5); else if (phy->port_speed == USB_PHY_PORT_SPEED_FULL) val |= USB_PORTSC_PTC(6); @@ -1821,6 +1828,31 @@ static void uhsic_powerup_pmc_wake_detect(struct tegra_usb_phy *phy) mdelay(1); } +static void uhsic_powerdown_pmc_wake_detect(struct tegra_usb_phy *phy) +{ + unsigned long val; + void __iomem *pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); + + DBG("%s:%d\n", __func__, __LINE__); + + /* turn off pad detectors for HSIC*/ + val = readl(pmc_base + PMC_USB_AO); + val |= (HSIC_RESERVED_P0 | STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); + writel(val, pmc_base + PMC_USB_AO); + + /* enable pull downs on HSIC PMC */ + val = UHSIC_STROBE_RPD_A | UHSIC_DATA_RPD_A | UHSIC_STROBE_RPD_B | + UHSIC_DATA_RPD_B | UHSIC_STROBE_RPD_C | UHSIC_DATA_RPD_C | + UHSIC_STROBE_RPD_D | UHSIC_DATA_RPD_D; + writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); + + /* Turn over pad configuration to PMC */ + val = readl(pmc_base + PMC_SLEEP_CFG); + val &= ~UHSIC_WAKE_VAL_P0(~0); + val |= UHSIC_WAKE_VAL_P0(WAKE_VAL_NONE) | UHSIC_MASTER_ENABLE_P0; + writel(val, pmc_base + PMC_SLEEP_CFG); +} + static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) { unsigned long val; @@ -1855,6 +1887,30 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_PWR; writel(val, pmc_base + PMC_UTMIP_MASTER_CONFIG); + /* Make sure nothing is happening on the line with respect to PMC */ + val = readl(pmc_base + PMC_UTMIP_UHSIC_FAKE); + val &= ~UHSIC_STROBE_VAL; + val &= ~UHSIC_DATA_VAL; + writel(val, pmc_base + PMC_UTMIP_UHSIC_FAKE); + + /* Clear walk enable */ + val = readl(pmc_base + PMC_SLEEPWALK_CFG); + val &= ~UHSIC_LINEVAL_WALK_EN; + writel(val, pmc_base + PMC_SLEEPWALK_CFG); + + /* Make sure wake value for line is none */ + val = readl(pmc_base + PMC_SLEEP_CFG); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); + val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); + writel(val, pmc_base + PMC_SLEEP_CFG); + + /* turn on pad detectors */ + val = readl(pmc_base + PMC_USB_AO); + val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); + writel(val, pmc_base + PMC_USB_AO); + + /* Add small delay before usb detectors provide stable line values */ + udelay(1); /* Enable which type of event can trigger a walk, * in this case usb_line_wake */ @@ -1871,19 +1927,16 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_DATA_RPD_A; val &= ~UHSIC_STROBE_RPD_A; val |= UHSIC_STROBE_RPU_A; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_B; val |= UHSIC_DATA_RPU_B; val &= ~UHSIC_STROBE_RPU_B; val |= UHSIC_STROBE_RPD_B; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_C; val |= UHSIC_DATA_RPU_C; val &= ~UHSIC_STROBE_RPU_C; val |= UHSIC_STROBE_RPD_C; - writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); val &= ~UHSIC_DATA_RPD_D; val |= UHSIC_DATA_RPU_D; @@ -1891,19 +1944,21 @@ static void uhsic_setup_pmc_wake_detect(struct tegra_usb_phy *phy) val |= UHSIC_STROBE_RPD_D; writel(val, pmc_base + PMC_SLEEPWALK_UHSIC); - /* turn on pad detectors */ - val = readl(pmc_base + PMC_USB_AO); - val &= ~(STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); - writel(val, pmc_base + PMC_USB_AO); - /* Add small delay before usb detectors provide stable line values */ - udelay(1); - phy->remote_wakeup = false; - /* Turn over pad configuration to PMC for line wake events*/ + /* Setting Wake event*/ val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(~0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_SD10); + writel(val, pmc_base + PMC_SLEEP_CFG); + + /* Clear the walk pointers and wake alarm */ + val = readl(pmc_base + PMC_TRIGGERS); + val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; + writel(val, pmc_base + PMC_TRIGGERS); + + /* Turn over pad configuration to PMC for line wake events*/ + val = readl(pmc_base + PMC_SLEEP_CFG); val |= UHSIC_MASTER_ENABLE; writel(val, pmc_base + PMC_SLEEP_CFG); @@ -1922,14 +1977,10 @@ static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) DBG("%s (%d)\n", __func__, __LINE__); val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(0x0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); writel(val, pmc_base + PMC_SLEEP_CFG); - val = readl(pmc_base + PMC_TRIGGERS); - val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; - writel(val, pmc_base + PMC_TRIGGERS); - val = readl(base + UHSIC_PMC_WAKEUP0); val &= ~EVENT_INT_ENB; writel(val, base + UHSIC_PMC_WAKEUP0); @@ -1944,6 +1995,10 @@ static void uhsic_phy_disable_pmc_bus_ctrl(struct tegra_usb_phy *phy) val |= (STROBE_VAL_PD_P0 | DATA_VAL_PD_P0); writel(val, pmc_base + PMC_USB_AO); + val = readl(pmc_base + PMC_TRIGGERS); + val |= (UHSIC_CLR_WALK_PTR_P0 | UHSIC_CLR_WAKE_ALARM_P0); + writel(val, pmc_base + PMC_TRIGGERS); + phy->remote_wakeup = false; } @@ -1958,12 +2013,12 @@ static bool uhsic_phy_remotewake_detected(struct tegra_usb_phy *phy) val = readl(pmc_base + UTMIP_UHSIC_STATUS); if (UHSIC_WAKE_ALARM & val) { val = readl(pmc_base + PMC_SLEEP_CFG); - val &= ~UHSIC_WAKE_VAL(0x0); + val &= ~UHSIC_WAKE_VAL(WAKE_VAL_ANY); val |= UHSIC_WAKE_VAL(WAKE_VAL_NONE); writel(val, pmc_base + PMC_SLEEP_CFG); val = readl(pmc_base + PMC_TRIGGERS); - val |= UHSIC_CLR_WAKE_ALARM_P0 | UHSIC_CLR_WALK_PTR_P0; + val |= UHSIC_CLR_WAKE_ALARM_P0; writel(val, pmc_base + PMC_TRIGGERS); val = readl(base + UHSIC_PMC_WAKEUP0); @@ -2031,7 +2086,7 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) unsigned long val; void __iomem *base = phy->regs; - int wait_time_us = 3000; /* FPR should be set by this time */ + int wait_time_us = 25000; /* FPR should be set by this time */ DBG("%s(%d)\n", __func__, __LINE__); @@ -2047,7 +2102,8 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) return; } wait_time_us--; - } while (!(val & USB_PORTSC_RESUME)); + } while (val & (USB_PORTSC_RESUME | USB_PORTSC_SUSP)); + /* wait for 25 ms to port resume complete */ msleep(25); /* disable PMC master control */ @@ -2077,10 +2133,58 @@ static void uhsic_phy_restore_end(struct tegra_usb_phy *phy) } } +static int hsic_rail_enable(struct tegra_usb_phy *phy) +{ + int ret; + + if (phy->hsic_reg == NULL) { + phy->hsic_reg = regulator_get(NULL, "avdd_hsic"); + if (IS_ERR_OR_NULL(phy->hsic_reg)) { + pr_err("HSIC: Could not get regulator avdd_hsic\n"); + phy->hsic_reg = NULL; + return PTR_ERR(phy->hsic_reg); + } + } + + ret = regulator_enable(phy->hsic_reg); + if (ret < 0) { + pr_err("%s avdd_hsic could not be enabled\n", __func__); + return ret; + } + + return 0; +} + +static int hsic_rail_disable(struct tegra_usb_phy *phy) +{ + int ret; + + if (phy->hsic_reg == NULL) { + pr_warn("%s: unbalanced disable\n", __func__); + return -EIO; + } + + ret = regulator_disable(phy->hsic_reg); + if (ret < 0) { + pr_err("HSIC regulator avdd_hsic cannot be disabled\n"); + return ret; + } + + return 0; +} + static int uhsic_phy_open(struct tegra_usb_phy *phy) { unsigned long parent_rate; int i; + int ret; + + phy->hsic_reg = NULL; + ret = hsic_rail_enable(phy); + if (ret < 0) { + pr_err("%s avdd_hsic could not be enabled\n", __func__); + return ret; + } DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); parent_rate = clk_get_rate(clk_get_parent(phy->pllu_clk)); @@ -2100,6 +2204,18 @@ static int uhsic_phy_open(struct tegra_usb_phy *phy) return 0; } +static void uhsic_phy_close(struct tegra_usb_phy *phy) +{ + int ret; + + DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); + uhsic_powerdown_pmc_wake_detect(phy); + + ret = hsic_rail_disable(phy); + if (ret < 0) + pr_err("%s avdd_hsic could not be disabled\n", __func__); +} + static int uhsic_phy_irq(struct tegra_usb_phy *phy) { usb_phy_fence_read(phy); @@ -2113,7 +2229,6 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) { unsigned long val; void __iomem *base = phy->regs; - struct tegra_hsic_config *config = &phy->pdata->u_cfg.hsic; DBG("%s(%d) inst:[%d]\n", __func__, __LINE__, phy->inst); @@ -2139,13 +2254,13 @@ static int uhsic_phy_power_on(struct tegra_usb_phy *phy) writel(val, base + USB_SUSP_CTRL); val = readl(base + UHSIC_HSRX_CFG0); - val |= UHSIC_IDLE_WAIT(config->idle_wait_delay); - val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_underrun_limit); - val |= UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_overrun_limit); + val |= UHSIC_IDLE_WAIT(HSIC_IDLE_WAIT_DELAY); + val |= UHSIC_ELASTIC_UNDERRUN_LIMIT(HSIC_ELASTIC_UNDERRUN_LIMIT); + val |= UHSIC_ELASTIC_OVERRUN_LIMIT(HSIC_ELASTIC_OVERRUN_LIMIT); writel(val, base + UHSIC_HSRX_CFG0); val = readl(base + UHSIC_HSRX_CFG1); - val |= UHSIC_HS_SYNC_START_DLY(config->sync_start_delay); + val |= UHSIC_HS_SYNC_START_DLY(HSIC_SYNC_START_DELAY); writel(val, base + UHSIC_HSRX_CFG1); /* WAR HSIC TX */ @@ -2875,6 +2990,7 @@ static struct tegra_usb_phy_ops utmi_phy_ops = { static struct tegra_usb_phy_ops uhsic_phy_ops = { .open = uhsic_phy_open, + .close = uhsic_phy_close, .irq = uhsic_phy_irq, .power_on = uhsic_phy_power_on, .power_off = uhsic_phy_power_off, diff --git a/arch/arm/mach-tegra/tegra_odm_fuses.c b/arch/arm/mach-tegra/tegra_odm_fuses.c index d4a68d117ab5..11bc3ef79ef9 100644 --- a/arch/arm/mach-tegra/tegra_odm_fuses.c +++ b/arch/arm/mach-tegra/tegra_odm_fuses.c @@ -54,6 +54,7 @@ #define NFUSES 64 #define STATE_IDLE (0x4 << 16) +#define SENSE_DONE (0x1 << 30) /* since fuse burning is irreversible, use this for testing */ #define ENABLE_FUSE_BURNING 1 @@ -608,6 +609,17 @@ static void fuse_program_array(int pgm_cycles) } fuse_power_disable(); + + /* + * Wait until done (polling) + * this one needs to use fuse_sense done, the FSM follows a periodic + * sequence that includes idle + */ + do { + udelay(1); + reg = tegra_fuse_readl(FUSE_CTRL); + } while ((reg & (0x1 << 30)) != SENSE_DONE); + } static int fuse_set(enum fuse_io_param io_param, u32 *param, int size) diff --git a/arch/arm/mach-tegra/tegra_usb_modem_power.c b/arch/arm/mach-tegra/tegra_usb_modem_power.c index 00c806364706..106f083c2455 100644 --- a/arch/arm/mach-tegra/tegra_usb_modem_power.c +++ b/arch/arm/mach-tegra/tegra_usb_modem_power.c @@ -308,8 +308,6 @@ static int mdm_request_wakeable_irq(struct tegra_usb_modem *modem, if (ret) return ret; - tegra_gpio_enable(irq_gpio); - /* enable IRQ for GPIO */ *irq = gpio_to_irq(irq_gpio); @@ -401,7 +399,8 @@ static ssize_t load_unload_usb_host(struct device *dev, return count; } -static DEVICE_ATTR(load_host, 0666, show_usb_host, load_unload_usb_host); +static DEVICE_ATTR(load_host, S_IRUSR | S_IWUSR, show_usb_host, + load_unload_usb_host); static int mdm_init(struct tegra_usb_modem *modem, struct platform_device *pdev) { diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 491a325c8d64..aacba98c3f7b 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -80,6 +80,7 @@ struct tegra_usb_phy { struct clk *emc_clk; struct clk *sys_clk; struct regulator *vdd_reg; + struct regulator *hsic_reg; struct regulator *vbus_reg; struct tegra_usb_phy_ops *ops; struct tegra_xtal_freq *freq; @@ -97,6 +98,7 @@ struct tegra_usb_phy { bool ulpi_clk_padout_ena; bool pmc_sleepwalk; bool bus_reseting; + bool linkphy_init; }; int usb_phy_reg_status_wait(void __iomem *reg, u32 mask, diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c index 58deb1b8d351..2f1d565789fe 100644 --- a/arch/arm/mach-tegra/timer.c +++ b/arch/arm/mach-tegra/timer.c @@ -31,6 +31,7 @@ #include <linux/io.h> #include <linux/syscore_ops.h> #include <linux/cpu_pm.h> +#include <linux/rtc.h> #include <asm/mach/time.h> #include <asm/arch_timer.h> @@ -552,6 +553,96 @@ static inline int tegra_init_arch_timer(void) { return -ENODEV; } static inline int tegra_init_late_arch_timer(void) { return -ENODEV; } #endif +#ifdef CONFIG_RTC_CLASS +/** + * has_readtime - check rtc device has readtime ability + * @dev: current device + * @name_ptr: name to be returned + * + * This helper function checks to see if the rtc device can be + * used for reading time + */ +static int has_readtime(struct device *dev, void *name_ptr) +{ + struct rtc_device *candidate = to_rtc_device(dev); + + if (!candidate->ops->read_time) + return 0; + + return 1; +} + +/** + * tegra_get_linear_age - helper function to return linear age + * from Jan 2012. + * + * @return + * 1 - Jan 2012, + * 2 - Feb 2012, + * ..... + * 13 - Jan 2013 + */ +int tegra_get_linear_age(void) +{ + struct rtc_time tm; + int year, month, linear_age; + struct rtc_device *rtc_dev = NULL; + const char *name = NULL; + int ret; + struct device *dev = NULL; + + linear_age = -1; + year = month = 0; + dev = class_find_device(rtc_class, NULL, &name, has_readtime); + + if (!dev) { + pr_err("DVFS: No device with readtime capability\n"); + goto done; + } + + name = dev_name(dev); + + pr_info("DVFS: Got RTC device name:%s\n", name); + + if (name) + rtc_dev = rtc_class_open((char *)name); + + if (!rtc_dev) { + pr_err("DVFS: No RTC device\n"); + goto error_dev; + } + + ret = rtc_read_time(rtc_dev, &tm); + + if (ret < 0) { + pr_err("DVFS: Can't read RTC time\n"); + goto error_rtc; + } + + year = tm.tm_year; + /*Normalize it to 2012*/ + year -= 112; + month = tm.tm_mon + 1; + + if (year >= 0) + linear_age = year * 12 + month; + +error_rtc: + rtc_class_close(rtc_dev); +error_dev: + put_device(dev); +done: + return linear_age; + +} + +#else +int tegra_get_linear_age() +{ + return -1; +} +#endif + void __init tegra_init_timer(void) { struct clk *clk; diff --git a/arch/arm/mach-tegra/timer.h b/arch/arm/mach-tegra/timer.h index 77edfbfd466b..ecb669b7f0b0 100644 --- a/arch/arm/mach-tegra/timer.h +++ b/arch/arm/mach-tegra/timer.h @@ -53,11 +53,14 @@ void __init tegra_cpu_timer_init(void); int tegra_twd_get_state(struct tegra_twd_context *context); void tegra_twd_suspend(struct tegra_twd_context *context); void tegra_twd_resume(struct tegra_twd_context *context); +int tegra_get_linear_age(void); #else static inline int tegra_twd_get_state(struct tegra_twd_context *context) { return -ENODEV; } static inline void tegra_twd_suspend(struct tegra_twd_context *context) {} static inline void tegra_twd_resume(struct tegra_twd_context *context) {} +static inline int tegra_get_linear_age() +{ return -1; } #endif #ifdef CONFIG_ARM_ARCH_TIMER diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 20694dc2102a..c3060b7734bc 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -145,7 +145,7 @@ static irqreturn_t usb_phy_dev_vbus_pmu_irq_thr(int irq, void *pdata) if (phy->vdd_reg && !phy->vdd_reg_on) { regulator_enable(phy->vdd_reg); - phy->vdd_reg_on = 1; + phy->vdd_reg_on = true; /* * Optimal time to get the regulator turned on * before detecting vbus interrupt. @@ -182,7 +182,8 @@ static int tegra_usb_phy_get_clocks(struct tegra_usb_phy *phy) phy->pllu_clk = clk_get_sys(NULL, "pll_u"); if (IS_ERR(phy->pllu_clk)) { ERR("inst:[%d] Can't get pllu_clk clock\n", phy->inst); - return PTR_ERR(phy->pllu_clk); + err = PTR_ERR(phy->pllu_clk); + goto fail_pll; } clk_enable(phy->pllu_clk); @@ -230,6 +231,7 @@ fail_ctrlr_clk: clk_disable(phy->pllu_clk); clk_put(phy->pllu_clk); +fail_pll: return err; } @@ -246,20 +248,23 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) if (!pdata) { dev_err(&pdev->dev, "inst:[%d] Platform data missing\n", pdev->id); - return ERR_PTR(-EINVAL); + err = -EINVAL; + goto fail_inval; } phy = devm_kzalloc(&pdev->dev, sizeof(struct tegra_usb_phy), GFP_KERNEL); if (!phy) { ERR("inst:[%d] malloc usb phy failed\n", pdev->id); - return ERR_PTR(-ENOMEM); + err = -ENOMEM; + goto fail_nomem; } phy->pdata = devm_kzalloc(&pdev->dev, plat_data_size, GFP_KERNEL); if (!phy->pdata) { ERR("inst:[%d] malloc usb phy pdata failed\n", pdev->id); - kfree(phy); - return ERR_PTR(-ENOMEM); + devm_kfree(&pdev->dev, phy); + err = -ENOMEM; + goto fail_nomem; } memcpy(phy->pdata, pdata, plat_data_size); @@ -272,20 +277,24 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { ERR("inst:[%d] failed to get I/O memory\n", phy->inst); - return ERR_PTR(-ENXIO); + err = -ENXIO; + goto fail_io; } phy->regs = ioremap(res->start, resource_size(res)); if (!phy->regs) { ERR("inst:[%d] Failed to remap I/O memory\n", phy->inst); - return ERR_PTR(-ENOMEM); + err = -ENOMEM; + goto fail_io; } - phy->vdd_reg = regulator_get(NULL, "avdd_usb"); + phy->vdd_reg = regulator_get(&pdev->dev, "avdd_usb"); if (IS_ERR_OR_NULL(phy->vdd_reg)) { ERR("inst:[%d] couldn't get regulator avdd_usb: %ld\n", phy->inst, PTR_ERR(phy->vdd_reg)); phy->vdd_reg = NULL; + err = PTR_ERR(phy->vdd_reg); + goto fail_io; } err = tegra_usb_phy_get_clocks(phy); @@ -327,8 +336,6 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) req failed\n", phy->inst); goto fail_init; } - if (gpio < TEGRA_NR_GPIOS) - tegra_gpio_enable(gpio); if (gpio_direction_output(gpio, 1) < 0) { ERR("inst:[%d] host vbus gpio \ dir failed\n", phy->inst); @@ -381,6 +388,12 @@ fail_init: fail_clk: regulator_put(phy->vdd_reg); iounmap(phy->regs); +fail_io: + devm_kfree(&pdev->dev, phy->pdata); + devm_kfree(&pdev->dev, phy); + +fail_nomem: +fail_inval: return ERR_PTR(err); } EXPORT_SYMBOL_GPL(tegra_usb_phy_open); @@ -420,8 +433,10 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) regulator_put(phy->vdd_reg); } - tegra_usb_phy_release_clocks(phy); + + devm_kfree(&phy->pdev->dev, phy->pdata); + devm_kfree(&phy->pdev->dev, phy); } EXPORT_SYMBOL_GPL(tegra_usb_phy_close); @@ -473,26 +488,30 @@ int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) clk_disable(phy->sys_clk); if (phy->pdata->op_mode == TEGRA_USB_OPMODE_HOST) { if (!phy->pdata->u_data.host.hot_plug && - !phy->pdata->u_data.host.remote_wakeup_supported) + !phy->pdata->u_data.host.remote_wakeup_supported) { clk_disable(phy->ctrlr_clk); + phy->ctrl_clk_on = false; + if (phy->vdd_reg && phy->vdd_reg_on) { + regulator_disable(phy->vdd_reg); + phy->vdd_reg_on = false; + } + } } else { - /* In device mode clock is turned on by pmu irq handler - * if pmu irq is not available clocks will not be turned off/on + /* In device mode clock regulator/clocks will be turned off + * only if pmu interrupt is present on the board and host mode + * support through OTG is supported on the board. */ - if (phy->pdata->u_data.dev.vbus_pmu_irq) { + if (phy->pdata->u_data.dev.vbus_pmu_irq && + phy->pdata->builtin_host_disabled) { clk_disable(phy->ctrlr_clk); phy->ctrl_clk_on = false; + if (phy->vdd_reg && phy->vdd_reg_on) { + regulator_disable(phy->vdd_reg); + phy->vdd_reg_on = false; + } } } -#ifndef CONFIG_ARCH_TEGRA_2x_SOC - if (phy->vdd_reg && phy->vdd_reg_on) - if (phy->pdata->has_hostpc || phy->pdata->builtin_host_disabled) { - regulator_disable(phy->vdd_reg); - phy->vdd_reg_on = false; - } -#endif - phy->phy_power_on = false; return err; diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index ba61f7dabccc..b43248a00ca7 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_ATA) += libata.o # non-SFF interface obj-$(CONFIG_SATA_AHCI) += ahci.o libahci.o +CFLAGS_ahci-tegra.o = -Werror obj-$(CONFIG_SATA_AHCI_TEGRA) += ahci-tegra.o libahci.o obj-$(CONFIG_SATA_ACARD_AHCI) += acard-ahci.o libahci.o obj-$(CONFIG_SATA_AHCI_PLATFORM) += ahci_platform.o libahci.o diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c index 236b09b51062..a99a6dc69468 100644 --- a/drivers/cpufreq/cpufreq_interactive.c +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -44,6 +44,7 @@ struct cpufreq_interactive_cpuinfo { u64 freq_change_time; u64 freq_change_time_in_idle; u64 freq_change_time_in_iowait; + u64 last_high_freq_time; struct cpufreq_policy *policy; struct cpufreq_frequency_table *freq_table; unsigned int target_freq; @@ -88,6 +89,24 @@ static unsigned long min_sample_time; #define DEFAULT_TIMER_RATE 20000; static unsigned long timer_rate; +/* + * The minimum delay before frequency is allowed to raise over normal rate. + * Since it must remain at high frequency for a minimum of MIN_SAMPLE_TIME + * once it rises, setting this delay to a multiple of MIN_SAMPLE_TIME + * becomes the best way to enforce a square wave. + * e.g. 5*MIN_SAMPLE_TIME = 20% high freq duty cycle + */ +#define DEFAULT_HIGH_FREQ_MIN_DELAY 5*DEFAULT_MIN_SAMPLE_TIME +static unsigned long high_freq_min_delay; + +/* + * The maximum frequency CPUs are allowed to run normally + * 0 if disabled + */ +#define DEFAULT_MAX_NORMAL_FREQ 0 +static unsigned long max_normal_freq; + + /* Defines to control mid-range frequencies */ #define DEFAULT_MID_RANGE_GO_MAXSPEED_LOAD 95 @@ -493,7 +512,9 @@ DECL_CPUFREQ_INTERACTIVE_ATTR(max_boost) DECL_CPUFREQ_INTERACTIVE_ATTR(midrange_max_boost) DECL_CPUFREQ_INTERACTIVE_ATTR(sustain_load) DECL_CPUFREQ_INTERACTIVE_ATTR(min_sample_time) -DECL_CPUFREQ_INTERACTIVE_ATTR(timer_rate); +DECL_CPUFREQ_INTERACTIVE_ATTR(timer_rate) +DECL_CPUFREQ_INTERACTIVE_ATTR(high_freq_min_delay) +DECL_CPUFREQ_INTERACTIVE_ATTR(max_normal_freq) #undef DECL_CPUFREQ_INTERACTIVE_ATTR @@ -508,6 +529,8 @@ static struct attribute *interactive_attributes[] = { &sustain_load_attr.attr, &min_sample_time_attr.attr, &timer_rate_attr.attr, + &high_freq_min_delay_attr.attr, + &max_normal_freq_attr.attr, NULL, }; @@ -565,7 +588,8 @@ static int cpufreq_governor_interactive(struct cpufreq_policy *policy, pcpu->freq_change_time_in_iowait = get_cpu_iowait_time(j, NULL); pcpu->time_in_iowait = pcpu->freq_change_time_in_iowait; - + if (!pcpu->last_high_freq_time) + pcpu->last_high_freq_time = pcpu->freq_change_time; pcpu->timer_idlecancel = 1; pcpu->governor_enabled = 1; smp_wmb(); @@ -636,6 +660,8 @@ static int __init cpufreq_interactive_init(void) midrange_go_maxspeed_load = DEFAULT_MID_RANGE_GO_MAXSPEED_LOAD; min_sample_time = DEFAULT_MIN_SAMPLE_TIME; timer_rate = DEFAULT_TIMER_RATE; + high_freq_min_delay = DEFAULT_HIGH_FREQ_MIN_DELAY; + max_normal_freq = DEFAULT_MAX_NORMAL_FREQ; /* Initalize per-cpu timers */ for_each_possible_cpu(i) { diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index e244cfcdd505..7ab59856d755 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -15,5 +15,7 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o +CFLAGS_tegra-aes.o = -Werror obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o +CFLAGS_tegra-se.o = -Werror obj-$(CONFIG_CRYPTO_DEV_TEGRA_SE) += tegra-se.o diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3b7579647446..236854f91b52 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o +CFLAGS_gpio-tegra.o = -Werror obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o obj-$(CONFIG_ARCH_DAVINCI_TNETV107X) += gpio-tnetv107x.o diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index 02e2dca5762e..2089712759fd 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c @@ -309,6 +309,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) spin_unlock_irqrestore(&bank->lvl_lock[port], flags); + tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); + tegra_gpio_enable(gpio); + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) __irq_set_handler_locked(d->irq, handle_level_irq); else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 30655656888e..a0f4a22bc143 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -129,6 +129,7 @@ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o obj-$(CONFIG_SENSORS_INA219) += ina219.o obj-$(CONFIG_SENSORS_INA230) += ina230.o +CFLAGS_tegra-tsensor.o = -Werror obj-$(CONFIG_SENSORS_TEGRA_TSENSOR) += tegra-tsensor.o obj-$(CONFIG_PMBUS) += pmbus/ diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 707e447ae1c3..2cbfd854a1d1 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -67,7 +67,9 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o obj-$(CONFIG_I2C_STU300) += i2c-stu300.o +CFLAGS_i2c-tegra.o = -Werror obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o +CFLAGS_i2c-slave-tegra.o = -Werror obj-$(CONFIG_I2C_SLAVE_TEGRA) += i2c-slave-tegra.o obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c index 4cb034197549..c85cf42e206a 100644 --- a/drivers/input/touchscreen/atmel_mxt_ts.c +++ b/drivers/input/touchscreen/atmel_mxt_ts.c @@ -3,7 +3,7 @@ * * Copyright (C) 2010 Samsung Electronics Co.Ltd * Copyright (C) 2011 Atmel Corporation - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012 NVIDIA Corporation * Author: Joonyoung Shim <jy0922.shim@samsung.com> * * This program is free software; you can redistribute it and/or modify it @@ -705,6 +705,7 @@ static void mxt_input_touchevent(struct mxt_data *data, finger[id].area = area; finger[id].pressure = pressure; + trace_nvevent_irq_data_submit("mxt_input_touchevent"); mxt_input_report(data, id); } @@ -717,11 +718,15 @@ static irqreturn_t mxt_interrupt(int irq, void *dev_id) int touchid; u8 reportid; + trace_nvevent_irq_data_read_start_series("mxt_input_interrupt"); do { + trace_nvevent_irq_data_read_start_single("mxt_input_interrupt"); if (mxt_read_message(data, &message)) { dev_err(dev, "Failed to read message\n"); goto end; } + trace_nvevent_irq_data_read_finish_single( + "mxt_input_interrupt"); reportid = message.reportid; @@ -740,6 +745,7 @@ static irqreturn_t mxt_interrupt(int irq, void *dev_id) } else if (reportid != MXT_RPTID_NOMSG) mxt_dump_message(dev, &message); } while (reportid != MXT_RPTID_NOMSG); + trace_nvevent_irq_data_read_finish_series("mxt_input_interrupt"); end: return IRQ_HANDLED; diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile index 7ad7a3bc1242..ed59619d1af8 100644 --- a/drivers/iommu/Makefile +++ b/drivers/iommu/Makefile @@ -8,5 +8,7 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o +CFLAGS_tegra-gart.o = -Werror obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o +CFLAGS_tegra-smmu.o = -Werror obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index f956f6e19b80..6975dae99310 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -353,8 +353,15 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, val = smmu_read(smmu, offs); if (on) { #if !defined(SKIP_SWGRP_CHECK) - if (WARN_ON(val & mask)) - goto err_hw_busy; + if (WARN_ON(val & mask)) { + for_each_set_bit(i, &map, HWGRP_COUNT) { + offs = HWGRP_ASID_REG(i); + val = smmu_read(smmu, offs); + val &= ~mask; + smmu_write(smmu, val, offs); + } + return -EBUSY; + } #endif val |= mask; } else { @@ -369,14 +376,6 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, c->hwgrp = map; return 0; -err_hw_busy: - for_each_set_bit(i, &map, HWGRP_COUNT) { - offs = HWGRP_ASID_REG(i); - val = smmu_read(smmu, offs); - val &= ~mask; - smmu_write(smmu, val, offs); - } - return -EBUSY; } static int smmu_client_set_hwgrp(struct smmu_client *c, u32 map, int on) diff --git a/drivers/media/video/tegra/ad5816.c b/drivers/media/video/tegra/ad5816.c index fd1468f677f6..e5ec9545918c 100644 --- a/drivers/media/video/tegra/ad5816.c +++ b/drivers/media/video/tegra/ad5816.c @@ -97,12 +97,14 @@ #define AD5816_ID 0x04 #define AD5816_FOCAL_LENGTH (4.570f) #define AD5816_FNUMBER (2.8f) -#define AD5816_ACTUATOR_RANGE 680 -#define AD5816_SETTLETIME 110 +#define AD5816_SLEW_RATE 1 +#define AD5816_ACTUATOR_RANGE 1023 +#define AD5816_SETTLETIME 50 #define AD5816_FOCUS_MACRO 810 #define AD5816_FOCUS_INFINITY 50 /* Exact value needs to be decided */ -#define AD5816_POS_LOW_DEFAULT 220 -#define AD5816_POS_HIGH_DEFAULT 900 +#define AD5816_POS_LOW_DEFAULT 0 +#define AD5816_POS_HIGH_DEFAULT 1023 +#define AD5816_POS_CLAMP 0x03ff /* Need to decide exact value of VCM_THRESHOLD and its use */ /* define AD5816_VCM_THRESHOLD 20 */ @@ -141,6 +143,7 @@ struct ad5816_info { struct ad5816_info *s_info; struct nvc_focus_nvc nvc; struct nvc_focus_cap cap; + struct nv_focuser_config nv_config; struct ad5816_pdata_info config; }; @@ -155,10 +158,12 @@ static struct ad5816_pdata_info ad5816_default_info = { static struct nvc_focus_cap ad5816_default_cap = { .version = NVC_FOCUS_CAP_VER2, + .slew_rate = AD5816_SLEW_RATE, .actuator_range = AD5816_ACTUATOR_RANGE, .settle_time = AD5816_SETTLETIME, .focus_macro = AD5816_FOCUS_MACRO, .focus_infinity = AD5816_FOCUS_INFINITY, + .focus_hyper = AD5816_FOCUS_INFINITY, }; static struct nvc_focus_nvc ad5816_default_nvc = { @@ -640,28 +645,76 @@ static int ad5816_position_rd(struct ad5816_info *info, unsigned *position) int err = 0; err = ad5816_i2c_rd8(info, 0, VCM_CODE_MSB, &t1); - pos = t1 & 0x03; + pos = t1; err = ad5816_i2c_rd8(info, 0, VCM_CODE_LSB, &t1); pos = (pos << 8) | t1; - if(pos) - *position = pos - info->config.pos_low; - else - *position = info->config.pos_low; - return 0; + if (pos < info->config.pos_low) + pos = info->config.pos_low; + else if (pos > info->config.pos_high) + pos = info->config.pos_high; + + *position = pos; + + return err; } -static int ad5816_position_wr(struct ad5816_info *info, unsigned position) +static int ad5816_position_wr(struct ad5816_info *info, s32 position) { - u16 data; + s16 data; - position = position + info->config.pos_low; - if(position > info->config.pos_high) - position = info->config.pos_high; + ad5816_set_arc_mode(info); - data = position & 0x03ff; + if (position > info->config.pos_high) + return -EINVAL; + data = position & AD5816_POS_CLAMP; return ad5816_i2c_wr16(info, VCM_CODE_MSB, data); + +} + +static void ad5816_get_focuser_capabilities(struct ad5816_info *info) +{ + memset(&info->nv_config, 0, sizeof(info->nv_config)); + + info->nv_config.focal_length = info->nvc.focal_length; + info->nv_config.fnumber = info->nvc.fnumber; + info->nv_config.max_aperture = info->nvc.fnumber; + info->nv_config.range_ends_reversed = 0; + info->nv_config.settle_time = info->cap.settle_time; + + info->nv_config.pos_working_low = AF_POS_INVALID_VALUE; + info->nv_config.pos_working_high = AF_POS_INVALID_VALUE; + + info->nv_config.pos_actual_low = info->config.pos_low; + info->nv_config.pos_actual_high = info->config.pos_high; + + info->nv_config.slew_rate = info->cap.slew_rate; + info->nv_config.circle_of_confusion = -1; + info->nv_config.num_focuser_sets = 1; + info->nv_config.focuser_set[0].macro = info->cap.focus_macro; + info->nv_config.focuser_set[0].hyper = info->cap.focus_hyper; + info->nv_config.focuser_set[0].inf = info->cap.focus_infinity; + info->nv_config.focuser_set[0].settle_time = info->cap.settle_time; +} + +static int ad5816_set_focuser_capabilities(struct ad5816_info *info, + struct nvc_param *params) +{ + if (copy_from_user(&info->nv_config, (const void __user *)params->p_value, + sizeof(struct nv_focuser_config))) { + dev_err(&info->i2c_client->dev, "%s Error: copy_from_user bytes %d\n", + __func__, sizeof(struct nv_focuser_config)); + return -EFAULT; + } + + /* set pre-set value, as currently ODM sets incorrect value */ + info->cap.settle_time = AD5816_SETTLETIME; + + dev_dbg(&info->i2c_client->dev, "%s: copy_from_user bytes %d info->cap.settle_time %d\n", + __func__, sizeof(struct nv_focuser_config), info->cap.settle_time); + + return 0; } static int ad5816_param_rd(struct ad5816_info *info, unsigned long arg) @@ -709,13 +762,10 @@ static int ad5816_param_rd(struct ad5816_info *info, unsigned long arg) __func__, info->nvc.fnumber); break; case NVC_PARAM_CAPS: - data_ptr = &info->cap; - /* there are different sizes depending on the version */ /* send back just what's requested or our max size */ - if (params.sizeofvalue < sizeof(info->cap)) - data_size = params.sizeofvalue; - else - data_size = sizeof(info->cap); + ad5816_get_focuser_capabilities(info); + data_ptr = &info->nv_config; + data_size = sizeof(info->nv_config); dev_err(&info->i2c_client->dev, "%s CAPS\n", __func__); break; case NVC_PARAM_STS: @@ -748,17 +798,17 @@ static int ad5816_param_rd(struct ad5816_info *info, unsigned long arg) } static int ad5816_param_wr_s(struct ad5816_info *info, - struct nvc_param *params, u32 u32val) + struct nvc_param *params, s32 s32val) { int err = 0; switch (params->param) { case NVC_PARAM_LOCUS: - dev_dbg(&info->i2c_client->dev, "%s LOCUS: %u\n", __func__, u32val); - err = ad5816_position_wr(info, u32val); + dev_dbg(&info->i2c_client->dev, "%s LOCUS: %d\n", __func__, s32val); + err = ad5816_position_wr(info, s32val); return err; case NVC_PARAM_RESET: - err = ad5816_reset(info, u32val); + err = ad5816_reset(info, s32val); dev_dbg(&info->i2c_client->dev, "%s RESET: %d\n", __func__, err); return err; case NVC_PARAM_SELF_TEST: @@ -777,7 +827,7 @@ static int ad5816_param_wr(struct ad5816_info *info, unsigned long arg) { struct nvc_param params; u8 u8val; - u32 u32val; + s32 s32val; int err = 0; if (copy_from_user(¶ms, (const void __user *)arg, sizeof(struct nvc_param))) { @@ -785,11 +835,11 @@ static int ad5816_param_wr(struct ad5816_info *info, unsigned long arg) __func__, __LINE__); return -EFAULT; } - if (copy_from_user(&u32val, (const void __user *)params.p_value, sizeof(u32val))) { + if (copy_from_user(&s32val, (const void __user *)params.p_value, sizeof(s32val))) { dev_err(&info->i2c_client->dev, "%s %d copy_from_user err\n", __func__, __LINE__); return -EFAULT; } - u8val = (u8)u32val; + u8val = (u8)s32val; /* parameters independent of sync mode */ switch (params.param) { case NVC_PARAM_STEREO: @@ -837,7 +887,7 @@ static int ad5816_param_wr(struct ad5816_info *info, unsigned long arg) /* sync power */ info->s_info->pwr_api = info->pwr_api; /* move slave lens to master position */ - err = ad5816_position_wr(info->s_info, info->pos); + err = ad5816_position_wr(info->s_info, (s32)info->pos); if (!err) { info->s_mode = u8val; info->s_info->s_mode = u8val; @@ -858,20 +908,29 @@ static int ad5816_param_wr(struct ad5816_info *info, unsigned long arg) if (info->pdata->cfg & NVC_CFG_NOERR) return 0; return err; + + case NVC_PARAM_CAPS: + if (ad5816_set_focuser_capabilities(info, ¶ms)) { + dev_err(&info->i2c_client->dev, "%s: Error: copy_from_user bytes %d\n", + __func__, params.sizeofvalue); + return -EFAULT; + } + return 0; + default: /* parameters dependent on sync mode */ switch (info->s_mode) { case NVC_SYNC_OFF: case NVC_SYNC_MASTER: - return ad5816_param_wr_s(info, ¶ms, u32val); + return ad5816_param_wr_s(info, ¶ms, s32val); case NVC_SYNC_SLAVE: - return ad5816_param_wr_s(info->s_info, ¶ms, u32val); + return ad5816_param_wr_s(info->s_info, ¶ms, s32val); case NVC_SYNC_STEREO: - err = ad5816_param_wr_s(info, ¶ms, u32val); + err = ad5816_param_wr_s(info, ¶ms, s32val); if (!(info->pdata->cfg & NVC_CFG_SYNC_I2C_MUX)) err |= ad5816_param_wr_s(info->s_info, ¶ms, - u32val); + s32val); return err; default: dev_err(&info->i2c_client->dev, "%s %d internal err\n", @@ -890,10 +949,14 @@ static long ad5816_ioctl(struct file *file, int err = 0; switch (cmd) { case NVC_IOCTL_PARAM_WR: + ad5816_pm_dev_wr(info, NVC_PWR_ON); err = ad5816_param_wr(info, arg); + ad5816_pm_dev_wr(info, NVC_PWR_OFF); return err; case NVC_IOCTL_PARAM_RD: + ad5816_pm_dev_wr(info, NVC_PWR_ON); err = ad5816_param_rd(info, arg); + ad5816_pm_dev_wr(info, NVC_PWR_OFF); return err; case NVC_IOCTL_PWR_WR: /* This is a Guaranteed Level of Service (GLOS) call */ @@ -1036,8 +1099,8 @@ static int ad5816_open(struct inode *inode, struct file *file) } file->private_data = info; ad5816_pm_dev_wr(info, NVC_PWR_ON); - /* set ARC Mode to ensure faster focus */ - ad5816_set_arc_mode(info); + ad5816_position_wr(info, info->cap.focus_infinity); + ad5816_pm_dev_wr(info, NVC_PWR_OFF); dev_dbg(&info->i2c_client->dev, "%s\n", __func__); return 0; diff --git a/drivers/media/video/tegra/nvavp/nvavp_dev.c b/drivers/media/video/tegra/nvavp/nvavp_dev.c index ab9a351de79d..78e7b0a0b2bb 100644 --- a/drivers/media/video/tegra/nvavp/nvavp_dev.c +++ b/drivers/media/video/tegra/nvavp/nvavp_dev.c @@ -1,7 +1,7 @@ /* * drivers/media/video/tegra/nvavp/nvavp_dev.c * - * Copyright (C) 2011-2012 NVIDIA Corp. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -102,6 +102,10 @@ struct nvavp_info { struct clk *bsev_clk; struct clk *vde_clk; struct clk *cop_clk; +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + struct clk *bsea_clk; + struct clk *vcp_clk; +#endif /* used for dvfs */ struct clk *sclk; @@ -116,6 +120,7 @@ struct nvavp_info { int video_initialized; #if defined(CONFIG_TEGRA_NVAVP_AUDIO) int audio_initialized; + struct work_struct app_notify_work; #endif struct work_struct clock_disable_work; @@ -263,14 +268,26 @@ static void nvavp_clks_disable(struct nvavp_info *nvavp) } } -static u32 nvavp_check_idle(struct nvavp_info *nvavp) +static u32 nvavp_check_idle(struct nvavp_info *nvavp, int channel_id) { - struct nvavp_channel *channel_info = nvavp_get_channel_info(nvavp, NVAVP_VIDEO_CHANNEL); + struct nvavp_channel *channel_info = nvavp_get_channel_info(nvavp, channel_id); struct nv_e276_control *control = channel_info->os_control; return (control->put == control->get) ? 1 : 0; } +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) +static void app_notify_handler(struct work_struct *work) +{ + struct nvavp_info *nvavp; + + nvavp = container_of(work, struct nvavp_info, + app_notify_work); + + kobject_uevent(&nvavp->nvhost_dev->dev.kobj, KOBJ_CHANGE); +} +#endif + static void clock_disable_handler(struct work_struct *work) { struct nvavp_info *nvavp; @@ -282,7 +299,7 @@ static void clock_disable_handler(struct work_struct *work) channel_info = nvavp_get_channel_info(nvavp, NVAVP_VIDEO_CHANNEL); mutex_lock(&channel_info->pushbuffer_lock); mutex_lock(&nvavp->open_lock); - if (nvavp_check_idle(nvavp) && nvavp->pending) { + if (nvavp_check_idle(nvavp, NVAVP_VIDEO_CHANNEL) && nvavp->pending) { nvavp->pending = false; nvavp_clks_disable(nvavp); } @@ -328,6 +345,13 @@ static int nvavp_service(struct nvavp_info *nvavp) dev_err(&nvavp->nvhost_dev->dev, "AVP timeout\n"); writel(inbox & NVAVP_INBOX_VALID, NVAVP_OS_INBOX); +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + if (inbox & NVE276_OS_INTERRUPT_APP_NOTIFY) { + pr_debug("nvavp_service NVE276_OS_INTERRUPT_APP_NOTIFY\n"); + schedule_work(&nvavp->app_notify_work); + } +#endif + return 0; } @@ -968,18 +992,14 @@ static void nvavp_uninit(struct nvavp_info *nvavp) if (video_initialized) { pr_debug("nvavp_uninit nvavp->video_initialized\n"); cancel_work_sync(&nvavp->clock_disable_work); - nvavp_halt_vde(nvavp); - - clk_disable(nvavp->sclk); - clk_disable(nvavp->emc_clk); - nvavp_set_video_init_status(nvavp, 0); video_initialized = 0; } #if defined(CONFIG_TEGRA_NVAVP_AUDIO) if (audio_initialized) { + cancel_work_sync(&nvavp->app_notify_work); nvavp_set_audio_init_status(nvavp, 0); audio_initialized = 0; } @@ -988,6 +1008,9 @@ static void nvavp_uninit(struct nvavp_info *nvavp) /* Video and Audio both becomes uninitialized */ if (video_initialized == audio_initialized) { pr_debug("nvavp_uninit both channels unitialized\n"); + + clk_disable(nvavp->sclk); + clk_disable(nvavp->emc_clk); disable_irq(nvavp->mbox_from_avp_pend_irq); nvavp_pushbuffer_deinit(nvavp); nvavp_halt_avp(nvavp); @@ -1248,6 +1271,62 @@ static int nvavp_force_clock_stay_on_ioctl(struct file *filp, unsigned int cmd, return 0; } +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) +static int nvavp_enable_audio_clocks(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct nvavp_clientctx *clientctx = filp->private_data; + struct nvavp_info *nvavp = clientctx->nvavp; + struct nvavp_clock_args config; + + if (copy_from_user(&config, (void __user *)arg, sizeof(struct nvavp_clock_args))) + return -EFAULT; + + dev_dbg(&nvavp->nvhost_dev->dev, "%s: clk_id=%d\n", + __func__, config.id); + + if (config.id == NVAVP_MODULE_ID_VCP) + clk_enable(nvavp->vcp_clk); + else if (config.id == NVAVP_MODULE_ID_BSEA) + clk_enable(nvavp->bsea_clk); + + return 0; +} + +static int nvavp_disable_audio_clocks(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct nvavp_clientctx *clientctx = filp->private_data; + struct nvavp_info *nvavp = clientctx->nvavp; + struct nvavp_clock_args config; + + if (copy_from_user(&config, (void __user *)arg, sizeof(struct nvavp_clock_args))) + return -EFAULT; + + dev_dbg(&nvavp->nvhost_dev->dev, "%s: clk_id=%d\n", + __func__, config.id); + + if (config.id == NVAVP_MODULE_ID_VCP) + clk_disable(nvavp->vcp_clk); + else if (config.id == NVAVP_MODULE_ID_BSEA) + clk_disable(nvavp->bsea_clk); + + return 0; +} +#else +static int nvavp_enable_audio_clocks(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static int nvavp_disable_audio_clocks(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + return 0; +} +#endif + static int tegra_nvavp_open(struct inode *inode, struct file *filp, int channel_id) { struct miscdevice *miscdev = filp->private_data; @@ -1365,6 +1444,12 @@ static long tegra_nvavp_ioctl(struct file *filp, unsigned int cmd, case NVAVP_IOCTL_FORCE_CLOCK_STAY_ON: ret = nvavp_force_clock_stay_on_ioctl(filp, cmd, arg); break; + case NVAVP_IOCTL_ENABLE_AUDIO_CLOCKS: + ret = nvavp_enable_audio_clocks(filp, cmd, arg); + break; + case NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS: + ret = nvavp_disable_audio_clocks(filp, cmd, arg); + break; default: ret = -EINVAL; break; @@ -1538,6 +1623,22 @@ static int tegra_nvavp_probe(struct nvhost_device *ndev, goto err_get_emc_clk; } +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + nvavp->bsea_clk = clk_get(&ndev->dev, "bsea"); + if (IS_ERR(nvavp->bsea_clk)) { + dev_err(&ndev->dev, "cannot get bsea clock\n"); + ret = -ENOENT; + goto err_get_bsea_clk; + } + + nvavp->vcp_clk = clk_get(&ndev->dev, "vcp"); + if (IS_ERR(nvavp->vcp_clk)) { + dev_err(&ndev->dev, "cannot get vcp clock\n"); + ret = -ENOENT; + goto err_get_vcp_clk; + } +#endif + nvavp->clk_enabled = 0; nvavp_halt_avp(nvavp); @@ -1556,6 +1657,7 @@ static int tegra_nvavp_probe(struct nvhost_device *ndev, } #if defined(CONFIG_TEGRA_NVAVP_AUDIO) + INIT_WORK(&nvavp->app_notify_work, app_notify_handler); nvavp->audio_misc_dev.minor = MISC_DYNAMIC_MINOR; nvavp->audio_misc_dev.name = "tegra_audio_avpchannel"; nvavp->audio_misc_dev.fops = &tegra_audio_nvavp_fops; @@ -1589,6 +1691,12 @@ err_audio_misc_reg: #endif misc_deregister(&nvavp->video_misc_dev); err_misc_reg: +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + clk_put(nvavp->vcp_clk); +err_get_vcp_clk: + clk_put(nvavp->bsea_clk); +err_get_bsea_clk: +#endif clk_put(nvavp->emc_clk); err_get_emc_clk: clk_put(nvavp->sclk); @@ -1637,6 +1745,8 @@ static int tegra_nvavp_remove(struct nvhost_device *ndev) #if defined(CONFIG_TEGRA_NVAVP_AUDIO) misc_deregister(&nvavp->audio_misc_dev); + clk_put(nvavp->vcp_clk); + clk_put(nvavp->bsea_clk); #endif clk_put(nvavp->bsev_clk); clk_put(nvavp->vde_clk); @@ -1660,14 +1770,22 @@ static int tegra_nvavp_suspend(struct nvhost_device *ndev, pm_message_t state) mutex_lock(&nvavp->open_lock); if (nvavp->refcount) { - if (!nvavp->clk_enabled) + if (!nvavp->clk_enabled) { +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + if (nvavp_check_idle(nvavp, NVAVP_AUDIO_CHANNEL)) + nvavp_uninit(nvavp); + else + ret = -EBUSY; +#else nvavp_uninit(nvavp); - else +#endif + } + else { ret = -EBUSY; + } } mutex_unlock(&nvavp->open_lock); - return ret; } @@ -1677,9 +1795,12 @@ static int tegra_nvavp_resume(struct nvhost_device *ndev) mutex_lock(&nvavp->open_lock); - if (nvavp->refcount) + if (nvavp->refcount) { nvavp_init(nvavp, NVAVP_VIDEO_CHANNEL); - +#if defined(CONFIG_TEGRA_NVAVP_AUDIO) + nvavp_init(nvavp, NVAVP_AUDIO_CHANNEL); +#endif + } mutex_unlock(&nvavp->open_lock); return 0; diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c index c5fce649ebca..09ad9e64ce12 100644 --- a/drivers/media/video/tegra/ov5650.c +++ b/drivers/media/video/tegra/ov5650.c @@ -641,6 +641,11 @@ static struct ov5650_reg mode_320x240[] = { {0x380f, 0x38}, + {0x3500, 0x00}, + {0x3501, 0x13}, + {0x3502, 0x80}, + {0x350b, 0x7f}, + {0x3815, 0x81}, {0x3824, 0x23}, {0x3825, 0x20}, diff --git a/drivers/media/video/tegra/ov9726.c b/drivers/media/video/tegra/ov9726.c index 27400516488d..52b3b075dd0e 100644 --- a/drivers/media/video/tegra/ov9726.c +++ b/drivers/media/video/tegra/ov9726.c @@ -38,6 +38,7 @@ struct ov9726_devinfo { struct ov9726_power_rail power_rail; atomic_t in_use; __u32 mode; + struct ov9726_reg grphold_temp[10]; }; static struct ov9726_reg mode_1280x720[] = { @@ -603,6 +604,46 @@ static int ov9726_set_gain(struct i2c_client *i2c_client, u16 gain) return ret; } +static int ov9726_set_group_hold(struct ov9726_devinfo *dev, + struct ov9726_ae *ae) +{ +#define OV9726_REG_PUSH8(p, a, v) \ + do { \ + (p)->addr = (a); \ + (p)->val = (v); \ + (p)++; \ + } while (0) + +#define OV9726_REG_PUSH16(ptr, addr, val) do { \ + OV9726_REG_PUSH8(ptr, (addr), (val) >> 8); \ + OV9726_REG_PUSH8(ptr, (addr) + 1, (val) & 0xff); \ + } while (0) + + struct ov9726_reg *gptr = &dev->grphold_temp[0]; + + if (!ae->gain_enable && + !ae->coarse_time_enable && + !ae->frame_length_enable) + return 0; + + OV9726_REG_PUSH8(gptr, 0x0104, 0x01); + if (ae->gain_enable) + OV9726_REG_PUSH16(gptr, + OV9726_REG_GAIN_HI, ae->gain); + if (ae->coarse_time_enable) + OV9726_REG_PUSH16(gptr, + OV9726_REG_COARSE_TIME_HI, ae->coarse_time); + if (ae->frame_length_enable) { + OV9726_REG_PUSH16(gptr, + OV9726_REG_FRAME_LENGTH_HI, ae->frame_length); + } + OV9726_REG_PUSH8(gptr, 0x0104, 0x00); + OV9726_REG_PUSH8(gptr, OV9726_TABLE_END, 0x00); + + return ov9726_write_table(dev->i2c_client, + dev->grphold_temp, NULL, 0); +} + static int ov9726_get_status(struct i2c_client *i2c_client, u8 *status) { int err; @@ -681,19 +722,26 @@ ov9726_ioctl(struct file *file, unsigned int cmd, unsigned long arg) break; } - case OV9726_IOCTL_SET_FRAME_LENGTH: err = ov9726_set_frame_length(i2c_client, (u32)arg); break; - case OV9726_IOCTL_SET_COARSE_TIME: err = ov9726_set_coarse_time(i2c_client, (u32)arg); break; - case OV9726_IOCTL_SET_GAIN: err = ov9726_set_gain(i2c_client, (u16)arg); break; - + case OV9726_IOCTL_SET_GROUP_HOLD: + { + struct ov9726_ae ae; + if (copy_from_user(&ae, + (const void __user *)arg, sizeof(struct ov9726_ae))) { + pr_info("%s %d\n", __func__, __LINE__); + return -EFAULT; + } + err = ov9726_set_group_hold(dev, &ae); + break; + } case OV9726_IOCTL_GET_STATUS: { u8 status; @@ -706,7 +754,6 @@ ov9726_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } break; } - default: err = -EINVAL; break; diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 3742523f3ce9..5d9c5b33fc4f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -896,18 +896,6 @@ config MFD_TPS6591X additional drivers must be enabled in order to use the functionality of the device. -config MFD_TPS65090 - bool "TPS65090 Power Management chips" - depends on I2C && GENERIC_HARDIRQS - select MFD_CORE - select REGMAP_I2C - help - If you say yes here you get support for the TPS65090 series of - Power Management chips. - This driver provides common support for accessing the device, - additional drivers must be enabled in order to use the - functionality of the device. - config MFD_RC5T583 bool "Ricoh RC5T583 Power Management system device" depends on I2C=y && GENERIC_HARDIRQS diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index d46c9fc6dc45..f9a47aeb8a73 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -116,7 +116,6 @@ obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o obj-$(CONFIG_MFD_S5M_CORE) += s5m-core.o s5m-irq.o obj-$(CONFIG_MFD_TPS6591X) += tps6591x.o -obj-$(CONFIG_MFD_TPS65090) += tps65090.o obj-$(CONFIG_MFD_TPS80031) += tps80031.o obj-$(CONFIG_GPADC_TPS80031) += tps8003x-gpadc.o obj-$(CONFIG_MFD_MAX8907C) += max8907c.o diff --git a/drivers/mfd/tps65090.c b/drivers/mfd/tps65090.c index 5d476c3da685..dea52e8301b4 100644 --- a/drivers/mfd/tps65090.c +++ b/drivers/mfd/tps65090.c @@ -17,7 +17,6 @@ */ #include <linux/interrupt.h> -#include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/mutex.h> @@ -160,7 +159,7 @@ static irqreturn_t tps65090_irq(int irq, void *data) { struct tps65090 *tps65090 = data; int ret = 0; - u8 status, mask; + u8 status = 0, mask = 0; unsigned long int acks = 0; int i; @@ -274,17 +273,15 @@ static int __devinit tps65090_i2c_probe(struct i2c_client *client, return -EINVAL; } - tps65090 = devm_kzalloc(&client->dev, sizeof(struct tps65090), - GFP_KERNEL); - if (tps65090 == NULL) + tps65090 = devm_kzalloc(&client->dev, sizeof(*tps65090), GFP_KERNEL); + if (!tps65090) { + dev_err(&client->dev, "mem alloc for tps65090 failed\n"); return -ENOMEM; + } - tps65090->client = client; tps65090->dev = &client->dev; i2c_set_clientdata(client, tps65090); - mutex_init(&tps65090->lock); - if (client->irq) { ret = tps65090_irq_init(tps65090, client->irq, pdata->irq_base); if (ret) { @@ -337,13 +334,15 @@ static int __devexit tps65090_i2c_remove(struct i2c_client *client) #ifdef CONFIG_PM static int tps65090_i2c_suspend(struct i2c_client *client, pm_message_t state) { + struct i2c_client *client = to_i2c_client(dev); if (client->irq) disable_irq(client->irq); return 0; } -static int tps65090_i2c_resume(struct i2c_client *client) +static int tps65090_resume(struct device *dev) { + struct i2c_client *client = to_i2c_client(dev); if (client->irq) enable_irq(client->irq); return 0; @@ -360,13 +359,10 @@ static struct i2c_driver tps65090_driver = { .driver = { .name = "tps65090", .owner = THIS_MODULE, + .pm = &tps65090_pm_ops, }, .probe = tps65090_i2c_probe, .remove = __devexit_p(tps65090_i2c_remove), -#ifdef CONFIG_PM - .suspend = tps65090_i2c_suspend, - .resume = tps65090_i2c_resume, -#endif .id_table = tps65090_id_table, }; @@ -384,4 +380,4 @@ module_exit(tps65090_exit); MODULE_DESCRIPTION("TPS65090 core driver"); MODULE_AUTHOR("Venu Byravarasu <vbyravarasu@nvidia.com>"); -MODULE_LICENSE("GPL v2");
\ No newline at end of file +MODULE_LICENSE("GPL v2"); diff --git a/drivers/mfd/tps80031.c b/drivers/mfd/tps80031.c index 691c9d2ee798..f524b2964068 100644 --- a/drivers/mfd/tps80031.c +++ b/drivers/mfd/tps80031.c @@ -132,7 +132,7 @@ #define TPS80031_ID2_PWM 0xBA ... 0xBE #define TPS80031_ID2_FUEL_GAUSE 0xC0 ... 0xCB #define TPS80031_ID2_INTERFACE_INTERRUPTS 0xD0 ... 0xD8 -#define TPS80031_ID2_CHARGER 0xE0 ... 0xF5 +#define TPS80031_ID2_CHARGER 0xDA ... 0xF5 #define TPS80031_ID3_TEST_LDO 0x00 ... 0x09 #define TPS80031_ID3_TEST_SMPS 0x10 ... 0x2B @@ -297,6 +297,14 @@ struct tps80031 { struct regmap *regmap[TPS_NUM_SLAVES]; }; +/* TPS80031 sub mfd devices */ +static struct mfd_cell tps80031_cell[] = { + { + .name = "tps80031-regulators", + }, +}; + + int tps80031_write(struct device *dev, int sid, int reg, uint8_t val) { struct tps80031 *tps80031 = dev_get_drvdata(dev); @@ -1226,6 +1234,8 @@ static int __devexit tps80031_i2c_remove(struct i2c_client *client) struct tps80031 *tps80031 = i2c_get_clientdata(client); int i; + mfd_remove_devices(tps80031->dev); + if (client->irq) free_irq(client->irq, tps80031); @@ -1303,7 +1313,7 @@ static int __devinit tps80031_i2c_probe(struct i2c_client *client, if (!tps->client) { dev_err(&client->dev, "can't attach client %d\n", i); ret = -ENOMEM; - goto fail; + goto fail_client_reg; } i2c_set_clientdata(tps->client, tps80031); mutex_init(&tps->lock); @@ -1314,7 +1324,7 @@ static int __devinit tps80031_i2c_probe(struct i2c_client *client, ret = PTR_ERR(tps80031->regmap[i]); dev_err(&client->dev, "regmap %d init failed, err %d\n", i, ret); - goto fail; + goto fail_client_reg; } } @@ -1323,7 +1333,7 @@ static int __devinit tps80031_i2c_probe(struct i2c_client *client, pdata->irq_base); if (ret) { dev_err(&client->dev, "IRQ init failed: %d\n", ret); - goto fail; + goto fail_client_reg; } } @@ -1331,10 +1341,17 @@ static int __devinit tps80031_i2c_probe(struct i2c_client *client, tps80031_init_ext_control(tps80031, pdata); + ret = mfd_add_devices(tps80031->dev, -1, + tps80031_cell, ARRAY_SIZE(tps80031_cell), NULL, 0); + if (ret < 0) { + dev_err(&client->dev, "mfd_add_devices failed: %d\n", ret); + goto fail_mfd_add; + } + ret = tps80031_add_subdevs(tps80031, pdata); if (ret) { dev_err(&client->dev, "add devices failed: %d\n", ret); - goto fail; + goto fail_add_subdev; } tps80031_gpio_init(tps80031, pdata); @@ -1352,8 +1369,20 @@ static int __devinit tps80031_i2c_probe(struct i2c_client *client, return 0; -fail: - tps80031_i2c_remove(client); +fail_add_subdev: + mfd_remove_devices(tps80031->dev); + +fail_mfd_add: + if (client->irq) + free_irq(client->irq, tps80031); +fail_client_reg: + for (i = 0; i < TPS_NUM_SLAVES; i++) { + struct tps80031_client *tps = &tps80031->tps_clients[i]; + if (tps->client && tps->client != client) + i2c_unregister_device(tps->client); + tps80031->tps_clients[i].client = NULL; + mutex_destroy(&tps->lock); + } return ret; } diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b9c48b27fd36..8a018eaa6ce1 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -572,6 +572,13 @@ config THERM_EST ---help--- Thermal driver which estimates temperature based of other sensors. +config TEGRA_THROUGHPUT + bool "Device node to set throughput target" + depends on TEGRA_DC && TEGRA_DC_EXTENSIONS + default y + ---help--- + Dev node /dev/tegra-throughput used to set a throughput target. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index f931c73e8d3c..89def1668c6e 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,9 +57,11 @@ obj-$(CONFIG_SENSORS_AK8975) += akm8975.o obj-$(CONFIG_SENSORS_NCT1008) += nct1008.o obj-$(CONFIG_BCM4329_RFKILL) += bcm4329_rfkill.o obj-$(CONFIG_INV_SENSORS) += inv_mpu/ +CFLAGS_tegra-cryptodev.o = -Werror obj-$(CONFIG_TEGRA_CRYPTO_DEV) += tegra-cryptodev.o obj-$(CONFIG_TEGRA_BB_SUPPORT) += tegra-baseband/ obj-$(CONFIG_TEGRA_CEC_SUPPORT) += tegra-cec/ obj-$(CONFIG_MAX1749_VIBRATOR) += max1749.o obj-$(CONFIG_APANIC) += apanic.o obj-$(CONFIG_THERM_EST) += therm_est.o +obj-$(CONFIG_TEGRA_THROUGHPUT) += tegra-throughput.o diff --git a/drivers/misc/inv_mpu/mpu6050/mldl_cfg.c b/drivers/misc/inv_mpu/mpu6050/mldl_cfg.c index 22af0c200985..920f4ae8a4b7 100644 --- a/drivers/misc/inv_mpu/mpu6050/mldl_cfg.c +++ b/drivers/misc/inv_mpu/mpu6050/mldl_cfg.c @@ -1786,6 +1786,16 @@ int inv_mpu_suspend(struct mldl_cfg *mldl_cfg, return result; } } + /* Disable irq when suspend all sensors */ + if (sensors == INV_ALL_SENSORS) { + result = inv_serial_single_write( + gyro_handle, mldl_cfg->mpu_chip_info->addr, + MPUREG_INT_ENABLE, 0); + if (result) { + LOG_RESULT_LOCATION(result); + return result; + } + } mldl_cfg->inv_mpu_cfg->requested_sensors = (~sensors) & INV_ALL_SENSORS; return result; diff --git a/drivers/misc/tegra-baseband/bb-power.c b/drivers/misc/tegra-baseband/bb-power.c index 4873bbde5238..0a8f406f1f45 100644 --- a/drivers/misc/tegra-baseband/bb-power.c +++ b/drivers/misc/tegra-baseband/bb-power.c @@ -72,9 +72,6 @@ static int tegra_bb_power_gpio_init(struct tegra_bb_power_gdata *gdata) else gpio_direction_output(gpio_id, (!gpio_flags ? 0 : 1)); - /* Enable the gpio */ - tegra_gpio_enable(gpio_id); - /* Create a sysfs node, if requested */ if (gpiolist->doexport) gpio_export(gpio_id, false); diff --git a/drivers/misc/tegra-cec/Makefile b/drivers/misc/tegra-cec/Makefile index ab380305c35f..8bac2a519046 100644 --- a/drivers/misc/tegra-cec/Makefile +++ b/drivers/misc/tegra-cec/Makefile @@ -2,4 +2,6 @@ # Makefile for tegra cec support. # +subdir-ccflags-y = -Werror + obj-$(CONFIG_TEGRA_CEC_T30) += tegra_cec.o diff --git a/drivers/misc/tegra-throughput.c b/drivers/misc/tegra-throughput.c new file mode 100644 index 000000000000..b2375d2913bf --- /dev/null +++ b/drivers/misc/tegra-throughput.c @@ -0,0 +1,233 @@ +/* + * drivers/misc/throughput.c + * + * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <linux/kthread.h> +#include <linux/ktime.h> +#include <linux/notifier.h> +#include <linux/miscdevice.h> +#include <linux/fs.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/throughput_ioctl.h> +#include <linux/nvhost.h> +#include <mach/dc.h> + +#define DEFAULT_SYNC_RATE 60000 /* 60 Hz */ + +static unsigned short target_frame_time; +static unsigned short last_frame_time; +static ktime_t last_flip; +static unsigned int multiple_app_disable; + +static spinlock_t lock; + +static int throughput_flip_notifier(struct notifier_block *nb, + unsigned long val, + void *data) +{ + /* only register flips when a single display is active */ + if (val != 1 || multiple_app_disable) + return NOTIFY_DONE; + else { + long timediff; + ktime_t now; + int throughput_hint; + + now = ktime_get(); + if (last_flip.tv64 != 0) { + timediff = (long) ktime_us_delta(now, last_flip); + if (timediff > (long) USHRT_MAX) + last_frame_time = USHRT_MAX; + else + last_frame_time = (unsigned short) timediff; + + throughput_hint = + ((int) target_frame_time * 100)/last_frame_time; + + /* notify throughput hint clients here */ + nvhost_scale3d_set_throughput_hint(throughput_hint); + } + last_flip = now; + } + + return NOTIFY_OK; +} + +static struct notifier_block throughput_flip_nb = { + .notifier_call = throughput_flip_notifier, +}; + +static int sync_rate; +static int throughput_active_app_count; + +static void reset_target_frame_time(void) +{ + if (sync_rate == 0) { + sync_rate = tegra_dc_get_panel_sync_rate(); + + if (sync_rate == 0) + sync_rate = DEFAULT_SYNC_RATE; + } + + target_frame_time = (unsigned short) (1000000000 / sync_rate); + + pr_debug("%s: panel sync rate %d, target frame time %u\n", + __func__, sync_rate, target_frame_time); +} + +static int notifier_initialized; + +static int throughput_open(struct inode *inode, struct file *file) +{ + if (!notifier_initialized) { + tegra_dc_register_flip_notifier(&throughput_flip_nb); + notifier_initialized = 1; + } + + spin_lock(&lock); + + throughput_active_app_count++; + if (throughput_active_app_count > 1) + multiple_app_disable = 1; + + spin_unlock(&lock); + + pr_debug("throughput_open node %p file %p\n", inode, file); + + return 0; +} + +static int throughput_release(struct inode *inode, struct file *file) +{ + spin_lock(&lock); + throughput_active_app_count--; + spin_unlock(&lock); + + if (throughput_active_app_count == 0) { + reset_target_frame_time(); + multiple_app_disable = 0; + tegra_dc_unregister_flip_notifier(&throughput_flip_nb); + notifier_initialized = 0; + } + + + pr_debug("throughput_release node %p file %p\n", inode, file); + + return 0; +} + +static int throughput_set_target_fps(unsigned long arg) +{ + int disable; + + pr_debug("%s: target fps %lu requested\n", __func__, arg); + + disable = multiple_app_disable; + + if (disable) { + pr_debug("%s: %d active apps, disabling fps usage\n", + __func__, throughput_active_app_count); + return 0; + } + + if (arg == 0) + reset_target_frame_time(); + else { + unsigned long frame_time = (1000000 / arg); + + if (frame_time > USHRT_MAX) + frame_time = USHRT_MAX; + + target_frame_time = (unsigned short) frame_time; + } + + return 0; +} + +static long +throughput_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + int err = 0; + + if ((_IOC_TYPE(cmd) != TEGRA_THROUGHPUT_MAGIC) || + (_IOC_NR(cmd) == 0) || + (_IOC_NR(cmd) > TEGRA_THROUGHPUT_IOCTL_MAXNR)) + return -EFAULT; + + switch (cmd) { + case TEGRA_THROUGHPUT_IOCTL_TARGET_FPS: + pr_debug("%s: TEGRA_THROUGHPUT_IOCTL_TARGET_FPS %lu\n", + __func__, arg); + err = throughput_set_target_fps(arg); + break; + + default: + err = -ENOTTY; + } + + return err; +} + +static const struct file_operations throughput_user_fops = { + .owner = THIS_MODULE, + .open = throughput_open, + .release = throughput_release, + .unlocked_ioctl = throughput_ioctl, +}; + +#define TEGRA_THROUGHPUT_MINOR 1 + +static struct miscdevice throughput_miscdev = { + .minor = TEGRA_THROUGHPUT_MINOR, + .name = "tegra-throughput", + .fops = &throughput_user_fops, + .mode = 0666, +}; + +int __init throughput_init_miscdev(void) +{ + int ret; + + pr_debug("%s: initializing\n", __func__); + + spin_lock_init(&lock); + + ret = misc_register(&throughput_miscdev); + if (ret) { + pr_err("can\'t reigster throughput miscdev" + " (minor %d err %d)\n", TEGRA_THROUGHPUT_MINOR, ret); + return ret; + } + + return 0; +} + +module_init(throughput_init_miscdev); + +void __exit throughput_exit_miscdev(void) +{ + pr_debug("%s: exiting\n", __func__); + + misc_deregister(&throughput_miscdev); +} + +module_exit(throughput_exit_miscdev); + diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 9bb8d4d4849e..8d39c5f110a1 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o +CFLAGS_sdhci-tegra.o = -Werror obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 25c4dbe2cba7..8c7b0efe86ec 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -494,7 +494,7 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci, sdhci->max_clk = 26000000; #endif } - +#ifdef CONFIG_ARCH_TEGRA_3x_SOC static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int clock) { int div; @@ -579,6 +579,7 @@ set_clk: out: sdhci->clock = clock; } +#endif /* #ifdef CONFIG_ARCH_TEGRA_3x_SOC */ static void tegra_sdhci_set_clock(struct sdhci_host *sdhci, unsigned int clock) { @@ -1160,7 +1161,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate power gpio\n"); goto err_power_req; } - tegra_gpio_enable(plat->power_gpio); gpio_direction_output(plat->power_gpio, 1); } @@ -1171,7 +1171,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate cd gpio\n"); goto err_cd_req; } - tegra_gpio_enable(plat->cd_gpio); gpio_direction_input(plat->cd_gpio); tegra_host->card_present = (gpio_get_value(plat->cd_gpio) == 0); @@ -1206,7 +1205,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) "failed to allocate wp gpio\n"); goto err_wp_req; } - tegra_gpio_enable(plat->wp_gpio); gpio_direction_input(plat->wp_gpio); } @@ -1349,23 +1347,17 @@ err_add_host: err_clk_put: clk_put(pltfm_host->clk); err_clk_get: - if (gpio_is_valid(plat->wp_gpio)) { - tegra_gpio_disable(plat->wp_gpio); + if (gpio_is_valid(plat->wp_gpio)) gpio_free(plat->wp_gpio); - } err_wp_req: if (gpio_is_valid(plat->cd_gpio)) free_irq(gpio_to_irq(plat->cd_gpio), host); err_cd_irq_req: - if (gpio_is_valid(plat->cd_gpio)) { - tegra_gpio_disable(plat->cd_gpio); + if (gpio_is_valid(plat->cd_gpio)) gpio_free(plat->cd_gpio); - } err_cd_req: - if (gpio_is_valid(plat->power_gpio)) { - tegra_gpio_disable(plat->power_gpio); + if (gpio_is_valid(plat->power_gpio)) gpio_free(plat->power_gpio); - } err_power_req: kfree(tegra_host); err_no_plat: @@ -1395,21 +1387,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev) regulator_put(tegra_host->vdd_io_reg); } - if (gpio_is_valid(plat->wp_gpio)) { - tegra_gpio_disable(plat->wp_gpio); + if (gpio_is_valid(plat->wp_gpio)) gpio_free(plat->wp_gpio); - } if (gpio_is_valid(plat->cd_gpio)) { free_irq(gpio_to_irq(plat->cd_gpio), host); - tegra_gpio_disable(plat->cd_gpio); gpio_free(plat->cd_gpio); } - if (gpio_is_valid(plat->power_gpio)) { - tegra_gpio_disable(plat->power_gpio); + if (gpio_is_valid(plat->power_gpio)) gpio_free(plat->power_gpio); - } if (tegra_host->clk_enabled) clk_disable(pltfm_host->clk); diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index de7cc6b7ade6..76499e01b282 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1979,19 +1979,13 @@ int sdhci_enable(struct mmc_host *mmc) struct sdhci_host *host = mmc_priv(mmc); u16 clk; - if (!mmc->card) + if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO) return 0; if (mmc->ios.clock) { - if (mmc->card->type != MMC_TYPE_SDIO) { - if (host->ops->set_clock) - host->ops->set_clock(host, mmc->ios.clock); - sdhci_set_clock(host, mmc->ios.clock); - } else { - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - clk |= SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - } + if (host->ops->set_clock) + host->ops->set_clock(host, mmc->ios.clock); + sdhci_set_clock(host, mmc->ios.clock); } return 0; @@ -2002,19 +1996,12 @@ int sdhci_disable(struct mmc_host *mmc, int lazy) struct sdhci_host *host = mmc_priv(mmc); u16 clk; - if (!mmc->card) + if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO) return 0; - /* For SDIO cards, only disable the card clock. */ - if (mmc->card->type != MMC_TYPE_SDIO) { - sdhci_set_clock(host, 0); - if (host->ops->set_clock) - host->ops->set_clock(host, 0); - } else { - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - clk &= ~SDHCI_CLOCK_CARD_EN; - sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - } + sdhci_set_clock(host, 0); + if (host->ops->set_clock) + host->ops->set_clock(host, 0); return 0; } @@ -2496,7 +2483,16 @@ int sdhci_suspend_host(struct sdhci_host *host) host->flags &= ~SDHCI_NEEDS_RETUNING; } - if (mmc->card) + if (mmc->card) { + /* + * If eMMC cards are put in sleep state, Vccq can be disabled + * but Vcc would still be powered on. In resume, we only restore + * the controller context. So, set MMC_PM_KEEP_POWER flag. + */ + if (mmc_card_can_sleep(mmc) && + !(mmc->caps & MMC_CAP2_NO_SLEEP_CMD)) + mmc->pm_flags = MMC_PM_KEEP_POWER; + ret = mmc_suspend_host(host->mmc); if (ret) { if (has_tuning_timer) { diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile index fd58b65804d4..0b3f4a3f7b2a 100644 --- a/drivers/mtd/devices/Makefile +++ b/drivers/mtd/devices/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o obj-$(CONFIG_MTD_M25P80) += m25p80.o obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o obj-$(CONFIG_MTD_SST25L) += sst25l.o +CFLAGS_tegra_nand.o = -Werror obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o CFLAGS_docg3.o += -I$(src) diff --git a/drivers/mtd/devices/tegra_nand.c b/drivers/mtd/devices/tegra_nand.c index c8a3e7090b90..38baa40746c6 100644 --- a/drivers/mtd/devices/tegra_nand.c +++ b/drivers/mtd/devices/tegra_nand.c @@ -1615,7 +1615,6 @@ static int __devinit tegra_nand_probe(struct platform_device *pdev) if (plat->wp_gpio) { gpio_request(plat->wp_gpio, "nand_wp"); - tegra_gpio_enable(plat->wp_gpio); gpio_direction_output(plat->wp_gpio, 1); } diff --git a/drivers/net/caif/Makefile b/drivers/net/caif/Makefile index f30752565b33..5f85fe79c595 100644 --- a/drivers/net/caif/Makefile +++ b/drivers/net/caif/Makefile @@ -15,5 +15,6 @@ obj-$(CONFIG_CAIF_SHM) += caif_shm.o obj-$(CONFIG_CAIF_HSI) += caif_hsi.o # Tegra specific SPI slave physical interfaces module +CFLAGS_tegra_caif_sspi.o = -Werror tegra_cfspi_slave-objs := tegra_caif_sspi.o obj-$(CONFIG_TEGRA_SPI_CAIF) += tegra_cfspi_slave.o diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c index e3c2de3af052..cc73c09e3c19 100644 --- a/drivers/net/usb/cdc_ether.c +++ b/drivers/net/usb/cdc_ether.c @@ -625,6 +625,14 @@ static const struct usb_device_id products [] = { USB_DEVICE(0x0489,0xE03A), .driver_info = (unsigned long)&rmnet_info, }, + +/* ZM5250 */ +{ + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + USB_DEVICE(0x19D2,0x1554), + .driver_info = (unsigned long)&rmnet_info, +}, /* * WHITELIST!!! * diff --git a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c index a2c49a631dc1..0fbd0042bdce 100644 --- a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c +++ b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc.c @@ -36,6 +36,7 @@ #include <linux/mmc/core.h> #include <linux/mmc/card.h> +#include <linux/mmc/host.h> #include <linux/mmc/sdio_func.h> #include <linux/mmc/sdio_ids.h> @@ -1356,7 +1357,7 @@ sdioh_start(sdioh_info_t *si, int stage) 2.6.27. The implementation prior to that is buggy, and needs broadcom's patch for it */ - if ((ret = sdio_reset_comm(gInstance->func[0]->card))) { + if ((ret = mmc_power_restore_host((gInstance->func[0])->card->host))) { sd_err(("%s Failed, error = %d\n", __FUNCTION__, ret)); return ret; } @@ -1441,6 +1442,8 @@ sdioh_stop(sdioh_info_t *si) #endif bcmsdh_oob_intr_set(FALSE); #endif /* !defined(OOB_INTR_ONLY) */ + if (mmc_power_save_host((gInstance->func[0])->card->host)) + sd_err(("%s card power save fail\n", __FUNCTION__)); } else sd_err(("%s Failed\n", __FUNCTION__)); diff --git a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c index a564671a242e..ad73d7f9fc56 100644 --- a/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c +++ b/drivers/net/wireless/bcmdhd/bcmsdh_sdmmc_linux.c @@ -34,6 +34,7 @@ #include <linux/mmc/core.h> #include <linux/mmc/card.h> +#include <linux/mmc/host.h> #include <linux/mmc/sdio_func.h> #include <linux/mmc/sdio_ids.h> @@ -127,9 +128,9 @@ static int bcmsdh_sdmmc_probe(struct sdio_func *func, gInstance->func[func->num] = func; if (func->num == 2) { - #ifdef WL_CFG80211 +#ifdef WL_CFG80211 wl_cfg80211_set_parent_dev(&func->dev); - #endif +#endif sd_trace(("F2 found, calling bcmsdh_probe...\n")); ret = bcmsdh_probe_bcmdhd(&func->dev); } diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 7ff99094d22f..00ddb9cb1ef9 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -48,5 +48,6 @@ obj-$(CONFIG_CHARGER_MANAGER) += charger-manager.o obj-$(CONFIG_CHARGER_MAX8997) += max8997_charger.o obj-$(CONFIG_CHARGER_MAX8998) += max8998_charger.o obj-$(CONFIG_MAX8907C_CHARGER) += max8907c-charger.o +CFLAGS_tegra_bpc_mgmt.o = -Werror obj-$(CONFIG_TEGRA_BPC_MGMT) += tegra_bpc_mgmt.o obj-$(CONFIG_CHARGER_SMB347) += smb347-charger.o diff --git a/drivers/power/tps80031-charger.c b/drivers/power/tps80031-charger.c index bd183971a839..484005a285f6 100644 --- a/drivers/power/tps80031-charger.c +++ b/drivers/power/tps80031-charger.c @@ -270,7 +270,8 @@ static int configure_charging_parameter(struct tps80031_charger *charger) } /* set Pre Charge current to 400mA */ - ret = tps80031_write(charger->dev->parent, SLAVE_ID2, 0xDE, 0x3); + ret = tps80031_write(charger->dev->parent, SLAVE_ID2, + CHARGERUSB_VICHRG_PC, 0x3); if (ret < 0) { dev_err(charger->dev, "%s(): Failed in writing register 0x%02x\n", __func__, 0xDD); diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index dd0283ec380c..3a4a0c42e297 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -450,12 +450,12 @@ config REGULATOR_TPS51632 The TPS52632 is 3-2-1 Phase D-Cap+ Step Down Driverless Controller with Serial VID control and DVFS. -config REGULATOR_WM8350 - tristate "Wolfson Microelectronics WM8350 AudioPlus PMIC" - depends on MFD_WM8350 +config REGULATOR_TPS65090 + tristate "TI TPS65090 Power regulator" + depends on MFD_TPS65090 help - This driver provides support for the voltage and current regulators - of the WM8350 AudioPlus PMIC. + This driver provides support for the voltage regulators on the + TI TPS65090 PMIC. config REGULATOR_TPS65910 tristate "TI TPS65910/TPS65911 Power Regulators" @@ -483,6 +483,13 @@ config REGULATOR_TPS6238X0 high-frequency synchronous step down dc-dc converter optimized for battery-powered portable applications. +config REGULATOR_WM8350 + tristate "Wolfson Microelectronics WM8350 AudioPlus PMIC" + depends on MFD_WM8350 + help + This driver provides support for the voltage and current regulators + of the WM8350 AudioPlus PMIC. + config REGULATOR_WM8400 tristate "Wolfson Microelectronics WM8400 AudioPlus PMIC" depends on MFD_WM8400 @@ -504,12 +511,6 @@ config REGULATOR_TPS6591X help This driver supports TPS6591X voltage regulator chips. -config REGULATOR_TPS65090 - tristate "TI TPS65090 Power regulators" - depends on MFD_TPS65090 - help - This driver supports TPS65090 voltage regulator chips. - config REGULATOR_TPS80031 tristate "TI TPS80031 Power regulators" depends on MFD_TPS80031 diff --git a/drivers/regulator/tps62360-regulator.c b/drivers/regulator/tps62360-regulator.c index dca2c88bd4fa..30f79e64dfaf 100644 --- a/drivers/regulator/tps62360-regulator.c +++ b/drivers/regulator/tps62360-regulator.c @@ -323,9 +323,15 @@ static int __devinit tps62360_init_dcdc(struct tps62360_chip *tps, return ret; } +static bool is_volatile_reg(struct device *dev, unsigned int reg) +{ + return false; +} + static const struct regmap_config tps62360_regmap_config = { .reg_bits = 8, .val_bits = 8, + .volatile_reg = is_volatile_reg, .max_register = REG_CHIPID, .cache_type = REGCACHE_RBTREE, }; diff --git a/drivers/regulator/tps65090-regulator.c b/drivers/regulator/tps65090-regulator.c index 8249a4b7ded2..aca2f56aa172 100644 --- a/drivers/regulator/tps65090-regulator.c +++ b/drivers/regulator/tps65090-regulator.c @@ -1,29 +1,25 @@ /* - * drivers/regulator/tps65090-regulator.c - * * Regulator driver for tps65090 power management chip. * - * Copyright (C) 2012 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/> */ #include <linux/module.h> #include <linux/delay.h> #include <linux/init.h> +#include <linux/gpio.h> #include <linux/slab.h> #include <linux/err.h> #include <linux/platform_device.h> @@ -32,7 +28,7 @@ #include <linux/mfd/tps65090.h> #include <linux/regulator/tps65090-regulator.h> -struct tps65090_regulator { +struct tps65090_regulator_info { int id; /* Regulator register address.*/ u8 reg_en_reg; @@ -40,30 +36,51 @@ struct tps65090_regulator { /* used by regulator core */ struct regulator_desc desc; - - /* Device */ - struct device *dev; }; +struct tps65090_regulator { + struct tps65090_regulator_info *rinfo; + struct device *dev; + struct regulator_dev *rdev; + bool enable_ext_control; + int gpio; + int gpio_state; +}; static inline struct device *to_tps65090_dev(struct regulator_dev *rdev) { return rdev_get_dev(rdev)->parent->parent; } + +static inline bool is_dcdc(int id) +{ + if ((id == TPS65090_REGULATOR_DCDC1) || + (id == TPS65090_REGULATOR_DCDC2) || + (id == TPS65090_REGULATOR_DCDC2)) + return true; + return false; +} + static int tps65090_reg_is_enabled(struct regulator_dev *rdev) { struct tps65090_regulator *ri = rdev_get_drvdata(rdev); struct device *parent = to_tps65090_dev(rdev); - uint8_t control; + uint8_t control = 0; int ret; - ret = tps65090_read(parent, ri->reg_en_reg, &control); + if (is_dcdc(ri->rinfo->desc.id) && ri->enable_ext_control) { + if (gpio_is_valid(ri->gpio)) + return ri->gpio_state; + return 1; + } + + ret = tps65090_read(parent, ri->rinfo->reg_en_reg, &control); if (ret < 0) { dev_err(&rdev->dev, "Error in reading reg 0x%x\n", - ri->reg_en_reg); + ri->rinfo->reg_en_reg); return ret; } - return (((control >> ri->en_bit) & 1) == 1); + return (((control >> ri->rinfo->en_bit) & 1) == 1); } static int tps65090_reg_enable(struct regulator_dev *rdev) @@ -72,10 +89,19 @@ static int tps65090_reg_enable(struct regulator_dev *rdev) struct device *parent = to_tps65090_dev(rdev); int ret; - ret = tps65090_set_bits(parent, ri->reg_en_reg, ri->en_bit); + if (is_dcdc(ri->rinfo->desc.id) && ri->enable_ext_control) { + if (gpio_is_valid(ri->gpio)) { + gpio_set_value(ri->gpio, 1); + ri->gpio_state = 1; + } + return 0; + } + + ret = tps65090_set_bits(parent, ri->rinfo->reg_en_reg, + ri->rinfo->en_bit); if (ret < 0) dev_err(&rdev->dev, "Error in updating reg 0x%x\n", - ri->reg_en_reg); + ri->rinfo->reg_en_reg); return ret; } @@ -85,10 +111,19 @@ static int tps65090_reg_disable(struct regulator_dev *rdev) struct device *parent = to_tps65090_dev(rdev); int ret; - ret = tps65090_clr_bits(parent, ri->reg_en_reg, ri->en_bit); + if (is_dcdc(ri->rinfo->desc.id) && ri->enable_ext_control) { + if (gpio_is_valid(ri->gpio)) { + gpio_set_value(ri->gpio, 0); + ri->gpio_state = 0; + } + return 0; + } + + ret = tps65090_clr_bits(parent, ri->rinfo->reg_en_reg, + ri->rinfo->en_bit); if (ret < 0) dev_err(&rdev->dev, "Error in updating reg 0x%x\n", - ri->reg_en_reg); + ri->rinfo->reg_en_reg); return ret; } @@ -99,84 +134,209 @@ static struct regulator_ops tps65090_ops = { .is_enabled = tps65090_reg_is_enabled, }; -#define tps65090_REG(_id, _en_reg, _en_bit, _ops) \ +static struct regulator_ops tps65090_ldo_ops = { +}; + +#define tps65090_REG(_id, _sname, _en_reg, _en_bit, _ops) \ { \ .reg_en_reg = _en_reg, \ .en_bit = _en_bit, \ - .id = TPS65090_ID_##_id, \ + .id = TPS65090_REGULATOR_##_id, \ .desc = { \ .name = tps65090_rails(_id), \ - .id = TPS65090_ID_##_id, \ + .supply_name = _sname, \ + .id = TPS65090_REGULATOR_##_id, \ .ops = &_ops, \ .type = REGULATOR_VOLTAGE, \ .owner = THIS_MODULE, \ }, \ } -static struct tps65090_regulator TPS65090_regulator[] = { - tps65090_REG(DCDC1, 12, 0, tps65090_ops), - tps65090_REG(DCDC2, 13, 0, tps65090_ops), - tps65090_REG(DCDC3, 14, 0, tps65090_ops), - tps65090_REG(FET1, 15, 0, tps65090_ops), - tps65090_REG(FET2, 16, 0, tps65090_ops), - tps65090_REG(FET3, 17, 0, tps65090_ops), - tps65090_REG(FET4, 18, 0, tps65090_ops), - tps65090_REG(FET5, 19, 0, tps65090_ops), - tps65090_REG(FET6, 20, 0, tps65090_ops), - tps65090_REG(FET7, 21, 0, tps65090_ops), +static struct tps65090_regulator_info TPS65090_regulator_info[] = { + tps65090_REG(DCDC1, "VSYS1", 12, 0, tps65090_ops), + tps65090_REG(DCDC2, "VSYS2", 13, 0, tps65090_ops), + tps65090_REG(DCDC3, "VSYS3", 14, 0, tps65090_ops), + tps65090_REG(LDO1, "VSYS_L1", 0, 0, tps65090_ldo_ops), + tps65090_REG(LDO2, "VSYS_L2", 0, 0, tps65090_ldo_ops), + tps65090_REG(FET1, "INFET1", 15, 0, tps65090_ops), + tps65090_REG(FET2, "INFET2", 16, 0, tps65090_ops), + tps65090_REG(FET3, "INFET3", 17, 0, tps65090_ops), + tps65090_REG(FET4, "INFET4", 18, 0, tps65090_ops), + tps65090_REG(FET5, "INFET5", 19, 0, tps65090_ops), + tps65090_REG(FET6, "INFET6", 20, 0, tps65090_ops), + tps65090_REG(FET7, "INFET7", 21, 0, tps65090_ops), }; -static inline struct tps65090_regulator *find_regulator_info(int id) + +static inline struct tps65090_regulator_info *find_regulator_info(int id) { - struct tps65090_regulator *ri; + struct tps65090_regulator_info *rinfo; int i; - for (i = 0; i < ARRAY_SIZE(TPS65090_regulator); i++) { - ri = &TPS65090_regulator[i]; - if (ri->desc.id == id) - return ri; + for (i = 0; i < ARRAY_SIZE(TPS65090_regulator_info); i++) { + rinfo = &TPS65090_regulator_info[i]; + if (rinfo->desc.id == id) + return rinfo; } return NULL; } + +static int __devinit tps65090_regulator_preinit(int id, + struct tps65090_regulator *ri, + struct tps65090_regulator_platform_data *tps_pdata) +{ + int ret = 0; + struct device *parent = ri->dev->parent; + + if (!tps_pdata->enable_ext_control) { + ret = tps65090_clr_bits(parent, + ri->rinfo->reg_en_reg, 1); + if (ret < 0) { + dev_err(ri->dev, "Error in clr reg 0x%x\n", + ri->rinfo->reg_en_reg); + return ret; + } + } + + if (gpio_is_valid(tps_pdata->gpio)) { + int gpio_flag = GPIOF_OUT_INIT_LOW; + const char *sname; + + sname = tps_pdata->reg_init_data->constraints.name; + if (!sname) + sname = ri->rinfo->desc.name; + ri->gpio_state = 0; + if (tps_pdata->reg_init_data->constraints.always_on || + tps_pdata->reg_init_data->constraints.boot_on) { + gpio_flag = GPIOF_OUT_INIT_HIGH; + ri->gpio_state = 1; + } + + ret = gpio_request_one(tps_pdata->gpio, gpio_flag, sname); + if (ret < 0) { + dev_err(ri->dev, "gpio request failed, e %d\n", ret); + return ret; + } + } + ret = tps65090_set_bits(parent, ri->rinfo->reg_en_reg, 1); + if (ret < 0) { + dev_err(ri->dev, "Error in setting reg 0x%x\n", + ri->rinfo->reg_en_reg); + return ret; + } + ri->enable_ext_control = true; + ri->gpio = tps_pdata->gpio; + return ret; +} + static int __devinit tps65090_regulator_probe(struct platform_device *pdev) { - struct tps65090_regulator *ri = NULL; + struct tps65090_regulator_info *rinfo = NULL; + struct tps65090_regulator *ri; + struct tps65090_regulator *pmic; struct regulator_dev *rdev; struct tps65090_regulator_platform_data *tps_pdata; - int id = pdev->id; + struct tps65090_platform_data *tps65090_pdata; + int id; + int num; + int ret; - dev_dbg(&pdev->dev, "Probing regulator %d\n", id); + dev_dbg(&pdev->dev, "Probing regulator\n"); - ri = find_regulator_info(id); - if (ri == NULL) { - dev_err(&pdev->dev, "invalid regulator ID specified\n"); + tps65090_pdata = dev_get_platdata(pdev->dev.parent); + if (!tps65090_pdata || !tps65090_pdata->num_reg_pdata) { + dev_err(&pdev->dev, "Proper platform data missing\n"); return -EINVAL; } - tps_pdata = pdev->dev.platform_data; - ri->dev = &pdev->dev; - - rdev = regulator_register(&ri->desc, &pdev->dev, - &tps_pdata->regulator, ri); - if (IS_ERR_OR_NULL(rdev)) { - dev_err(&pdev->dev, "failed to register regulator %s\n", - ri->desc.name); - return PTR_ERR(rdev); + + pmic = devm_kzalloc(&pdev->dev, + tps65090_pdata->num_reg_pdata * sizeof(*pmic), + GFP_KERNEL); + if (!pmic) { + dev_err(&pdev->dev, "mem alloc for pmic failed\n"); + return -ENOMEM; + } + + for (num = 0; num < tps65090_pdata->num_reg_pdata; ++num) { + tps_pdata = tps65090_pdata->reg_pdata[num]; + if (!tps_pdata || !tps_pdata->reg_init_data) { + dev_err(&pdev->dev, + "Null platform data for regultor %d\n", num); + ret = -EINVAL; + goto scrub; + } + + id = tps_pdata->id; + rinfo = find_regulator_info(id); + if (!rinfo) { + dev_err(&pdev->dev, + "invalid regulator ID %d specified\n", id); + ret = -EINVAL; + goto scrub; + } + + ri = &pmic[num]; + ri->dev = &pdev->dev; + ri->rinfo = rinfo; + + if (is_dcdc(id)) { + ret = tps65090_regulator_preinit(id, ri, tps_pdata); + if (ret < 0) { + dev_err(&pdev->dev, + "failed to preinit regulator %d\n", id); + goto scrub; + } + } + rdev = regulator_register(&ri->rinfo->desc, &pdev->dev, + tps_pdata->reg_init_data, ri); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register regulator %s\n", + ri->rinfo->desc.name); + ret = PTR_ERR(rdev); + goto scrub; + } + ri->rdev = rdev; } - platform_set_drvdata(pdev, rdev); + platform_set_drvdata(pdev, pmic); return 0; + +scrub: + while (--num >= 0) { + ri = &pmic[num]; + regulator_unregister(ri->rdev); + if (is_dcdc(ri->rinfo->desc.id) && (ri->enable_ext_control)) { + if (gpio_is_valid(ri->gpio)) + gpio_free(ri->gpio); + } + } + return ret; } static int __devexit tps65090_regulator_remove(struct platform_device *pdev) { - struct regulator_dev *rdev = platform_get_drvdata(pdev); + struct tps65090_regulator *pmic = platform_get_drvdata(pdev); + struct tps65090_platform_data *tps65090_pdata; + struct tps65090_regulator *ri; + int num; + + tps65090_pdata = dev_get_platdata(pdev->dev.parent); + if (!tps65090_pdata || !tps65090_pdata->num_reg_pdata) + return 0; - regulator_unregister(rdev); + for (num = 0; num < tps65090_pdata->num_reg_pdata; ++num) { + ri = &pmic[num]; + regulator_unregister(ri->rdev); + if (is_dcdc(ri->rinfo->desc.id) && (ri->enable_ext_control)) { + if (gpio_is_valid(ri->gpio)) + gpio_free(ri->gpio); + } + } return 0; } static struct platform_driver tps65090_regulator_driver = { .driver = { - .name = "tps65090-regulator", + .name = "tps65090-pmic", .owner = THIS_MODULE, }, .probe = tps65090_regulator_probe, @@ -196,5 +356,5 @@ static void __exit tps65090_regulator_exit(void) module_exit(tps65090_regulator_exit); MODULE_DESCRIPTION("tps65090 regulator driver"); -MODULE_ALIAS("platform:tps65090-regulator"); -MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Venu Byravarasu <vbyravarasu@nvidia.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/regulator/tps80031-regulator.c b/drivers/regulator/tps80031-regulator.c index e2ab5bfe0e4b..b778e3d8da7a 100644 --- a/drivers/regulator/tps80031-regulator.c +++ b/drivers/regulator/tps80031-regulator.c @@ -82,44 +82,48 @@ #define EXT_PWR_REQ (PWR_REQ_INPUT_PREQ1 | PWR_REQ_INPUT_PREQ2 | \ PWR_REQ_INPUT_PREQ3) -struct tps80031_regulator { - +struct tps80031_regulator_info { /* Regulator register address.*/ u8 trans_reg; u8 state_reg; u8 force_reg; u8 volt_reg; u8 volt_id; - uint8_t trans_reg_cache; - uint8_t state_reg_cache; - uint8_t force_reg_cache; - uint8_t volt_reg_cache; - - /* twl resource ID, for resource control state machine */ - u8 id; /* chip constraints on regulator behavior */ u16 min_mV; u16 max_mV; - unsigned int tolerance_uv; - /* regulator specific turn-on delay */ + /* regulator specific turn-on delay as per datasheet*/ int delay; - u8 flags; - unsigned int platform_flags; - unsigned int ext_ctrl_flag; - /* used by regulator core */ struct regulator_desc desc; - /* Device */ - struct device *dev; - /*Power request bits */ int preq_bit; }; +struct tps80031_regulator { + struct device *dev; + struct regulator_dev *rdev; + struct tps80031_regulator_info *rinfo; + unsigned int tolerance_uv; + + /* Regulator specific turn-on delay if board file provided */ + int delay; + + u8 flags; + unsigned int platform_flags; + unsigned int ext_ctrl_flag; + + /* Cached register */ + uint8_t trans_reg_cache; + uint8_t state_reg_cache; + uint8_t force_reg_cache; + uint8_t volt_reg_cache; +}; + static inline struct device *to_tps80031_dev(struct regulator_dev *rdev) { return rdev_get_dev(rdev)->parent->parent; @@ -179,7 +183,7 @@ static int tps80031_reg_enable(struct regulator_dev *rdev) reg_val = (ri->state_reg_cache & ~STATE_MASK) | (STATE_ON & STATE_MASK); - ret = tps80031_write(parent, SLAVE_ID1, ri->state_reg, reg_val); + ret = tps80031_write(parent, SLAVE_ID1, ri->rinfo->state_reg, reg_val); if (ret < 0) { dev_err(&rdev->dev, "Error in writing the STATE register\n"); return ret; @@ -201,7 +205,7 @@ static int tps80031_reg_disable(struct regulator_dev *rdev) reg_val = (ri->state_reg_cache & ~STATE_MASK) | (STATE_OFF & STATE_MASK); - ret = tps80031_write(parent, SLAVE_ID1, ri->state_reg, reg_val); + ret = tps80031_write(parent, SLAVE_ID1, ri->rinfo->state_reg, reg_val); if (ret < 0) dev_err(&rdev->dev, "Error in writing the STATE register\n"); else @@ -389,10 +393,10 @@ static int __tps80031_dcdc_set_voltage(struct device *parent, if (selector) *selector = vsel; - if (ri->force_reg) { + if (ri->rinfo->force_reg) { if (((ri->force_reg_cache >> 6) & 0x3) == 0) { - ret = tps80031_write(parent, ri->volt_id, - ri->force_reg, vsel); + ret = tps80031_write(parent, ri->rinfo->volt_id, + ri->rinfo->force_reg, vsel); if (ret < 0) dev_err(ri->dev, "Error in writing the " "force register\n"); @@ -401,7 +405,8 @@ static int __tps80031_dcdc_set_voltage(struct device *parent, return ret; } } - ret = tps80031_write(parent, ri->volt_id, ri->volt_reg, vsel); + ret = tps80031_write(parent, ri->rinfo->volt_id, + ri->rinfo->volt_reg, vsel); if (ret < 0) dev_err(ri->dev, "Error in writing the Voltage register\n"); else @@ -424,7 +429,7 @@ static int tps80031dcdc_get_voltage(struct regulator_dev *rdev) uint8_t vsel = 0; int voltage = 0; - if (ri->force_reg) { + if (ri->rinfo->force_reg) { vsel = ri->force_reg_cache; if ((vsel & SMPS_CMD_MASK) == 0) goto decode; @@ -515,11 +520,11 @@ static int tps80031ldo_list_voltage(struct regulator_dev *rdev, unsigned index) if (index == 0) return 0; - if ((ri->desc.id == TPS80031_ID_LDO2) && + if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) && (ri->flags & TRACK_MODE_ENABLE)) - return (ri->min_mV + (((index - 1) * 125))/10) * 1000; + return (ri->rinfo->min_mV + (((index - 1) * 125))/10) * 1000; - return (ri->min_mV + ((index - 1) * 100)) * 1000; + return (ri->rinfo->min_mV + ((index - 1) * 100)) * 1000; } static int __tps80031_ldo2_set_voltage_track_mode(struct device *parent, @@ -553,7 +558,8 @@ static int __tps80031_ldo2_set_voltage_track_mode(struct device *parent, } } - ret = tps80031_write(parent, ri->volt_id, ri->volt_reg, vsel); + ret = tps80031_write(parent, ri->rinfo->volt_id, + ri->rinfo->volt_reg, vsel); if (ret < 0) dev_err(ri->dev, "Error in writing the Voltage register\n"); else @@ -570,10 +576,11 @@ static int __tps80031_ldo_set_voltage(struct device *parent, int vsel; int ret; - if ((min_uV/1000 < ri->min_mV) || (max_uV/1000 > ri->max_mV)) + if ((min_uV/1000 < ri->rinfo->min_mV) || + (max_uV/1000 > ri->rinfo->max_mV)) return -EDOM; - if ((ri->desc.id == TPS80031_ID_LDO2) && + if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) && (ri->flags & TRACK_MODE_ENABLE)) return __tps80031_ldo2_set_voltage_track_mode(parent, ri, min_uV, max_uV); @@ -585,7 +592,8 @@ static int __tps80031_ldo_set_voltage(struct device *parent, vsel = (min_uV/1000 - 1000)/100 + 1; if (selector) *selector = vsel; - ret = tps80031_write(parent, ri->volt_id, ri->volt_reg, vsel); + ret = tps80031_write(parent, ri->rinfo->volt_id, + ri->rinfo->volt_reg, vsel); if (ret < 0) dev_err(ri->dev, "Error in writing the Voltage register\n"); else @@ -609,10 +617,10 @@ static int tps80031ldo_get_voltage(struct regulator_dev *rdev) uint8_t vsel; - if ((ri->desc.id == TPS80031_ID_LDO2) && + if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) && (ri->flags & TRACK_MODE_ENABLE)) { vsel = ri->volt_reg_cache & 0x3F; - return (ri->min_mV + (((vsel - 1) * 125))/10) * 1000; + return (ri->rinfo->min_mV + (((vsel - 1) * 125))/10) * 1000; } vsel = ri->volt_reg_cache & LDO_VSEL_MASK; @@ -720,6 +728,22 @@ static int tps80031vbus_get_voltage(struct regulator_dev *rdev) return ret; } +static int tps80031_extreg_enable_time(struct regulator_dev *rdev) +{ + struct tps80031_regulator *ri = rdev_get_drvdata(rdev); + return ri->delay; +} + +static int tps80031_extreg_get_voltage(struct regulator_dev *rdev) +{ + struct tps80031_regulator *ri = rdev_get_drvdata(rdev); + int ret; + ret = tps80031_reg_is_enabled(rdev); + if (ret > 0) + return ri->rinfo->max_mV * 1000; + return 0; +} + static struct regulator_ops tps80031dcdc_ops = { .list_voltage = tps80031dcdc_list_voltage, .set_voltage = tps80031dcdc_set_voltage, @@ -748,6 +772,16 @@ static struct regulator_ops tps80031vbus_ops = { .enable_time = tps80031_vbus_enable_time, }; +static struct regulator_ops tps80031_ext_reg_ops = { + .enable = tps80031_reg_enable, + .disable = tps80031_reg_disable, + .is_enabled = tps80031_reg_is_enabled, + .enable_time = tps80031_extreg_enable_time, + .get_voltage = tps80031_extreg_get_voltage, +}; + + + #define TPS80031_REG(_id, _trans_reg, _state_reg, _force_reg, _volt_reg, \ _volt_id, min_mVolts, max_mVolts, _ops, _n_volt, _delay, \ _preq_bit) \ @@ -757,12 +791,11 @@ static struct regulator_ops tps80031vbus_ops = { .force_reg = _force_reg, \ .volt_reg = _volt_reg, \ .volt_id = _volt_id, \ - .id = TPS80031_ID_##_id, \ .min_mV = min_mVolts, \ .max_mV = max_mVolts, \ .desc = { \ .name = tps80031_rails(_id), \ - .id = TPS80031_ID_##_id, \ + .id = TPS80031_REGULATOR_##_id, \ .n_voltages = _n_volt, \ .ops = &_ops, \ .type = REGULATOR_VOLTAGE, \ @@ -772,7 +805,7 @@ static struct regulator_ops tps80031vbus_ops = { .preq_bit = _preq_bit, \ } -static struct tps80031_regulator tps80031_regulator[] = { +static struct tps80031_regulator_info tps80031_regulator_info[] = { TPS80031_REG(VIO, 0x47, 0x48, 0x49, 0x4A, SLAVE_ID0, 600, 2100, tps80031dcdc_ops, 63, 500, 4), TPS80031_REG(SMPS1, 0x53, 0x54, 0x55, 0x56, SLAVE_ID0, 600, 2100, @@ -806,6 +839,12 @@ static struct tps80031_regulator tps80031_regulator[] = { tps80031ldo_ops, 25, 500, -1), TPS80031_REG(VBUS, 0x0, 0x0, 0x00, 0x0, SLAVE_ID1, 0, 5000, tps80031vbus_ops, 2, 200000, -1), + TPS80031_REG(REGEN1, 0xAE, 0xAF, 0x00, 0x0, SLAVE_ID1, 0, 3300, + tps80031_ext_reg_ops, 2, 500, 16), + TPS80031_REG(REGEN2, 0xB1, 0xB2, 0x00, 0x0, SLAVE_ID1, 0, 3300, + tps80031_ext_reg_ops, 2, 500, 17), + TPS80031_REG(SYSEN, 0xB4, 0xB5, 0x00, 0x0, SLAVE_ID1, 0, 3300, + tps80031_ext_reg_ops, 2, 500, 18), }; static int tps80031_power_req_config(struct device *parent, @@ -815,17 +854,18 @@ static int tps80031_power_req_config(struct device *parent, int ret = 0; uint8_t reg_val; - if (ri->preq_bit < 0) + if (ri->rinfo->preq_bit < 0) goto skip_pwr_req_config; ret = tps80031_ext_power_req_config(parent, ri->ext_ctrl_flag, - ri->preq_bit, ri->state_reg, ri->trans_reg); + ri->rinfo->preq_bit, ri->rinfo->state_reg, + ri->rinfo->trans_reg); if (!ret) - ret = tps80031_read(parent, SLAVE_ID1, ri->trans_reg, + ret = tps80031_read(parent, SLAVE_ID1, ri->rinfo->trans_reg, &ri->trans_reg_cache); - if (!ret && ri->state_reg) - ret = tps80031_read(parent, SLAVE_ID1, ri->state_reg, + if (!ret && ri->rinfo->state_reg) + ret = tps80031_read(parent, SLAVE_ID1, ri->rinfo->state_reg, &ri->state_reg_cache); if (ret < 0) { dev_err(ri->dev, "%s() fails\n", __func__); @@ -839,11 +879,11 @@ skip_pwr_req_config: if (tps80031_pdata->ext_ctrl_flag & PWR_ON_ON_SLEEP) reg_val |= 0x4; - ret = tps80031_write(parent, SLAVE_ID1, ri->trans_reg, + ret = tps80031_write(parent, SLAVE_ID1, ri->rinfo->trans_reg, reg_val); if (ret < 0) dev_err(ri->dev, "Not able to write reg 0x%02x\n", - ri->trans_reg); + ri->rinfo->trans_reg); else ri->trans_reg_cache = reg_val; } @@ -857,7 +897,7 @@ static int tps80031_regulator_preinit(struct device *parent, int ret = 0; uint8_t reg_val; - if (ri->desc.id == TPS80031_ID_LDOUSB) { + if (ri->rinfo->desc.id == TPS80031_REGULATOR_LDOUSB) { if (ri->platform_flags & USBLDO_INPUT_VSYS) ret = tps80031_update(parent, SLAVE_ID1, TPS80031_MISC2_ADD, @@ -873,7 +913,7 @@ static int tps80031_regulator_preinit(struct device *parent, } } - if (ri->desc.id == TPS80031_ID_LDO3) { + if (ri->rinfo->desc.id == TPS80031_REGULATOR_LDO3) { if (ri->platform_flags & LDO3_OUTPUT_VIB) ret = tps80031_update(parent, SLAVE_ID1, TPS80031_MISC2_ADD, @@ -886,31 +926,59 @@ static int tps80031_regulator_preinit(struct device *parent, } } + switch (ri->rinfo->desc.id) { + case TPS80031_REGULATOR_REGEN1: + case TPS80031_REGULATOR_REGEN2: + case TPS80031_REGULATOR_SYSEN: + if (tps80031_pdata->reg_init_data->constraints.always_on || + tps80031_pdata->reg_init_data->constraints.boot_on) + ret = tps80031_update(parent, SLAVE_ID1, + ri->rinfo->state_reg, STATE_ON, STATE_MASK); + else + ret = tps80031_update(parent, SLAVE_ID1, + ri->rinfo->state_reg, STATE_OFF, STATE_MASK); + if (ret < 0) { + dev_err(ri->dev, + "state reg update failed, e %d\n", ret); + return ret; + } + ret = tps80031_update(parent, SLAVE_ID1, + ri->rinfo->trans_reg, 1, 0x3); + if (ret < 0) { + dev_err(ri->dev, + "trans reg update failed, e %d\n", ret); + return ret; + } + break; + default: + break; + } + if (!tps80031_pdata->init_apply) return 0; if (tps80031_pdata->init_uV >= 0) { - switch (ri->desc.id) { - case TPS80031_ID_VIO: - case TPS80031_ID_SMPS1: - case TPS80031_ID_SMPS2: - case TPS80031_ID_SMPS3: - case TPS80031_ID_SMPS4: + switch (ri->rinfo->desc.id) { + case TPS80031_REGULATOR_VIO: + case TPS80031_REGULATOR_SMPS1: + case TPS80031_REGULATOR_SMPS2: + case TPS80031_REGULATOR_SMPS3: + case TPS80031_REGULATOR_SMPS4: ret = __tps80031_dcdc_set_voltage(parent, ri, tps80031_pdata->init_uV, tps80031_pdata->init_uV, 0); break; - case TPS80031_ID_LDO1: - case TPS80031_ID_LDO2: - case TPS80031_ID_LDO3: - case TPS80031_ID_LDO4: - case TPS80031_ID_LDO5: - case TPS80031_ID_LDO6: - case TPS80031_ID_LDO7: - case TPS80031_ID_LDOUSB: - case TPS80031_ID_LDOLN: - case TPS80031_ID_VANA: + case TPS80031_REGULATOR_LDO1: + case TPS80031_REGULATOR_LDO2: + case TPS80031_REGULATOR_LDO3: + case TPS80031_REGULATOR_LDO4: + case TPS80031_REGULATOR_LDO5: + case TPS80031_REGULATOR_LDO6: + case TPS80031_REGULATOR_LDO7: + case TPS80031_REGULATOR_LDOUSB: + case TPS80031_REGULATOR_LDOLN: + case TPS80031_REGULATOR_VANA: ret = __tps80031_ldo_set_voltage(parent, ri, tps80031_pdata->init_uV, tps80031_pdata->init_uV, 0); @@ -923,7 +991,7 @@ static int tps80031_regulator_preinit(struct device *parent, if (ret < 0) { dev_err(ri->dev, "Not able to initialize voltage %d " "for rail %d err %d\n", tps80031_pdata->init_uV, - ri->desc.id, ret); + ri->rinfo->desc.id, ret); return ret; } } @@ -935,25 +1003,25 @@ static int tps80031_regulator_preinit(struct device *parent, reg_val = (ri->state_reg_cache & ~STATE_MASK) | (STATE_OFF & STATE_MASK); - ret = tps80031_write(parent, SLAVE_ID1, ri->state_reg, reg_val); + ret = tps80031_write(parent, SLAVE_ID1, ri->rinfo->state_reg, reg_val); if (ret < 0) dev_err(ri->dev, "Not able to %s rail %d err %d\n", (tps80031_pdata->init_enable) ? "enable" : "disable", - ri->desc.id, ret); + ri->rinfo->desc.id, ret); else ri->state_reg_cache = reg_val; return ret; } -static inline struct tps80031_regulator *find_regulator_info(int id) +static inline struct tps80031_regulator_info *find_regulator_info(int id) { - struct tps80031_regulator *ri; + struct tps80031_regulator_info *rinfo; int i; - for (i = 0; i < ARRAY_SIZE(tps80031_regulator); i++) { - ri = &tps80031_regulator[i]; - if (ri->desc.id == id) - return ri; + for (i = 0; i < ARRAY_SIZE(tps80031_regulator_info); i++) { + rinfo = &tps80031_regulator_info[i]; + if (rinfo->desc.id == id) + return rinfo; } return NULL; } @@ -961,30 +1029,30 @@ static void check_smps_mode_mult(struct device *parent, struct tps80031_regulator *ri) { int mult_offset; - switch (ri->desc.id) { - case TPS80031_ID_VIO: + switch (ri->rinfo->desc.id) { + case TPS80031_REGULATOR_VIO: mult_offset = SMPS_MULTOFFSET_VIO; break; - case TPS80031_ID_SMPS1: + case TPS80031_REGULATOR_SMPS1: mult_offset = SMPS_MULTOFFSET_SMPS1; break; - case TPS80031_ID_SMPS2: + case TPS80031_REGULATOR_SMPS2: mult_offset = SMPS_MULTOFFSET_SMPS2; break; - case TPS80031_ID_SMPS3: + case TPS80031_REGULATOR_SMPS3: mult_offset = SMPS_MULTOFFSET_SMPS3; break; - case TPS80031_ID_SMPS4: + case TPS80031_REGULATOR_SMPS4: mult_offset = SMPS_MULTOFFSET_SMPS4; break; - case TPS80031_ID_LDO2: + case TPS80031_REGULATOR_LDO2: ri->flags = (tps80031_get_smps_mult(parent) & (1 << 5)) ? TRACK_MODE_ENABLE : 0; /* TRACK mode the ldo2 varies from 600mV to 1300mV */ if (ri->flags & TRACK_MODE_ENABLE) { - ri->min_mV = 600; - ri->max_mV = 1300; - ri->desc.n_voltages = 57; + ri->rinfo->min_mV = 600; + ri->rinfo->max_mV = 1300; + ri->rinfo->desc.n_voltages = 57; } return; default: @@ -1003,33 +1071,34 @@ static inline int tps80031_cache_regulator_register(struct device *parent, { int ret; - ret = tps80031_read(parent, SLAVE_ID1, ri->trans_reg, + ret = tps80031_read(parent, SLAVE_ID1, ri->rinfo->trans_reg, &ri->trans_reg_cache); - if (!ret && ri->state_reg) - ret = tps80031_read(parent, SLAVE_ID1, ri->state_reg, + if (!ret && ri->rinfo->state_reg) + ret = tps80031_read(parent, SLAVE_ID1, ri->rinfo->state_reg, &ri->state_reg_cache); - if (!ret && ri->force_reg) - ret = tps80031_read(parent, ri->volt_id, ri->force_reg, - &ri->force_reg_cache); - if (!ret && ri->volt_reg) - ret = tps80031_read(parent, ri->volt_id, ri->volt_reg, - &ri->volt_reg_cache); + if (!ret && ri->rinfo->force_reg) + ret = tps80031_read(parent, ri->rinfo->volt_id, + ri->rinfo->force_reg, &ri->force_reg_cache); + if (!ret && ri->rinfo->volt_reg) + ret = tps80031_read(parent, ri->rinfo->volt_id, + ri->rinfo->volt_reg, &ri->volt_reg_cache); return ret; } static int __devinit tps80031_regulator_probe(struct platform_device *pdev) { - struct tps80031_regulator *ri = NULL; - struct regulator_dev *rdev; + struct tps80031_platform_data *pdata = dev_get_platdata(pdev->dev.parent); struct tps80031_regulator_platform_data *tps_pdata; - int id = pdev->id; - int err; - - dev_dbg(&pdev->dev, "Probing reulator %d\n", id); + struct tps80031_regulator_info *rinfo; + struct tps80031_regulator *ri; + struct tps80031_regulator *pmic; + struct regulator_dev *rdev; + int id; + int ret; + int num; - ri = find_regulator_info(id); - if (ri == NULL) { - dev_err(&pdev->dev, "invalid regulator ID specified\n"); + if (!pdata || !pdata->num_regulator_pdata) { + dev_err(&pdev->dev, "Number of regulator is 0\n"); return -EINVAL; } tps_pdata = pdev->dev.platform_data; @@ -1063,22 +1132,105 @@ static int __devinit tps80031_regulator_probe(struct platform_device *pdev) return PTR_ERR(rdev); } - platform_set_drvdata(pdev, rdev); + pmic = devm_kzalloc(&pdev->dev, + pdata->num_regulator_pdata * sizeof(*pmic), GFP_KERNEL); + if (!pmic) { + dev_err(&pdev->dev, "mem alloc for pmic failed\n"); + return -ENOMEM; + } + for (num = 0; num < pdata->num_regulator_pdata; ++num) { + tps_pdata = pdata->regulator_pdata[num]; + if (!tps_pdata->reg_init_data) { + dev_err(&pdev->dev, + "No regulator init data for index %d\n", num); + ret = -EINVAL; + goto fail; + } + + id = tps_pdata->regulator_id; + rinfo = find_regulator_info(id); + if (!rinfo) { + dev_err(&pdev->dev, "invalid regulator ID specified\n"); + ret = -EINVAL; + goto fail; + } + + ri = &pmic[num]; + ri->rinfo = rinfo; + ri->dev = &pdev->dev; + if (tps_pdata->delay_us) + ri->delay = tps_pdata->delay_us; + else + ri->delay = rinfo->delay; + ri->tolerance_uv = tps_pdata->tolerance_uv; + + check_smps_mode_mult(pdev->dev.parent, ri); + ri->platform_flags = tps_pdata->flags; + ri->ext_ctrl_flag = tps_pdata->ext_ctrl_flag; + + ret = tps80031_cache_regulator_register(pdev->dev.parent, ri); + if (ret < 0) { + dev_err(&pdev->dev, + "Register cache failed, err %d\n", ret); + goto fail; + } + ret = tps80031_regulator_preinit(pdev->dev.parent, ri, tps_pdata); + if (ret < 0) { + dev_err(&pdev->dev, + "regulator preinit failed, err %d\n", ret); + goto fail; + } + + ret = tps80031_power_req_config(pdev->dev.parent, ri, tps_pdata); + if (ret < 0) { + dev_err(&pdev->dev, + "power req config failed, err %d\n", ret); + goto fail; + } + + rdev = regulator_register(&ri->rinfo->desc, &pdev->dev, + tps_pdata->reg_init_data, ri); + if (IS_ERR_OR_NULL(rdev)) { + dev_err(&pdev->dev, + "register regulator failed %s\n", + ri->rinfo->desc.name); + ret = PTR_ERR(rdev); + goto fail; + } + ri->rdev = rdev; + } + + platform_set_drvdata(pdev, pmic); return 0; +fail: + while(--num >= 0) { + ri = &pmic[num]; + regulator_unregister(ri->rdev); + } + return ret; } static int __devexit tps80031_regulator_remove(struct platform_device *pdev) { - struct regulator_dev *rdev = platform_get_drvdata(pdev); + struct tps80031_platform_data *pdata = pdev->dev.parent->platform_data; + struct tps80031_regulator *pmic = platform_get_drvdata(pdev); + struct tps80031_regulator *ri = NULL; + int num; - regulator_unregister(rdev); + if (!pdata || !pdata->num_regulator_pdata) + return 0; + + for (num = 0; num < pdata->num_regulator_pdata; ++num) { + ri = &pmic[num]; + regulator_unregister(ri->rdev); + } return 0; } static struct platform_driver tps80031_regulator_driver = { .driver = { - .name = "tps80031-regulator", + .name = "tps80031-regulators", .owner = THIS_MODULE, }, .probe = tps80031_regulator_probe, diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 54ce1d2b0de4..3abf7bd2bddd 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -102,6 +102,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) += rtc-starfire.o obj-$(CONFIG_RTC_DRV_STK17TA8) += rtc-stk17ta8.o obj-$(CONFIG_RTC_DRV_STMP) += rtc-stmp3xxx.o obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o +CFLAGS_rtc-tegra.o = -Werror obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 6b18fc269b3e..1a9679d8aa90 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -57,8 +57,10 @@ obj-$(CONFIG_SPI_SH_MSIOF) += spi-sh-msiof.o obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o obj-$(CONFIG_SPI_SIRF) += spi-sirf.o obj-$(CONFIG_SPI_STMP3XXX) += spi-stmp.o +CFLAGS_spi-tegra.o = -Werror obj-$(CONFIG_SPI_TEGRA) += spi-tegra.o obj-$(CONFIG_SPI_TEGRA) += spi-tegra11.o +CFLAGS_spi_slave_tegra.o = -Werror obj-$(CONFIG_SPI_SLAVE_TEGRA) += spi_slave_tegra.o obj-$(CONFIG_SPI_TI_SSP) += spi-ti-ssp.o obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c index 5568cc7cd84d..1d08b7f20c93 100644 --- a/drivers/spi/spi-tegra.c +++ b/drivers/spi/spi-tegra.c @@ -1488,33 +1488,33 @@ skip_dma_alloc: if (tspi->is_clkon_always) spi_pm_runtime_get_sync(&pdev->dev); - master->dev.of_node = pdev->dev.of_node; - ret = spi_register_master(master); - if (ret < 0) { - dev_err(&pdev->dev, "can not register to master err %d\n", ret); - goto exit_pm_suspend; - } - - /* create the workqueue for the kbc path */ + /* create the workqueue for the spi transfer */ snprintf(spi_wq_name, sizeof(spi_wq_name), "spi_tegra-%d", pdev->id); tspi->spi_workqueue = create_singlethread_workqueue(spi_wq_name); if (!tspi->spi_workqueue) { dev_err(&pdev->dev, "Failed to create work queue\n"); ret = -ENODEV; - goto exit_master_unregister; + goto exit_fail_wq; } INIT_WORK(&tspi->spi_transfer_work, tegra_spi_transfer_work); + master->dev.of_node = pdev->dev.of_node; + ret = spi_register_master(master); + if (ret < 0) { + dev_err(&pdev->dev, "can not register to master err %d\n", ret); + goto exit_destry_wq; + } + return ret; -exit_master_unregister: - spi_unregister_master(master); +exit_destry_wq: + destroy_workqueue(tspi->spi_workqueue); +exit_fail_wq: if (tspi->is_clkon_always) spi_pm_runtime_put_sync(&pdev->dev); -exit_pm_suspend: if (!spi_pm_runtime_status_suspended(&pdev->dev)) tegra_spi_runtime_idle(&pdev->dev); diff --git a/drivers/spi/spi_slave_tegra.c b/drivers/spi/spi_slave_tegra.c index 1f46a4a199da..7c2eb6b30966 100644 --- a/drivers/spi/spi_slave_tegra.c +++ b/drivers/spi/spi_slave_tegra.c @@ -418,7 +418,7 @@ static unsigned int spi_tegra_read_rx_fifo_to_client_rxbuf( u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; unsigned i, count; unsigned long x; - unsigned int read_words; + unsigned int read_words = 0; unsigned len; fifo_status = spi_tegra_readl(tspi, SLINK_STATUS2); diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c index 3c60088871e0..5b89cac4753e 100644 --- a/drivers/staging/nvec/nvec.c +++ b/drivers/staging/nvec/nvec.c @@ -802,6 +802,8 @@ static int __devinit tegra_nvec_probe(struct platform_device *pdev) dev_err(nvec->dev, "couldn't request gpio\n"); goto failed; } + gpio_direction_output(nvec->gpio, 1); + gpio_set_value(nvec->gpio, 1); err = request_irq(nvec->irq, nvec_interrupt, 0, "nvec", nvec); if (err) { diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index b7f5d52b3388..f041a2e7dfa5 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o obj-$(CONFIG_SERIAL_BFIN) += bfin_uart.o obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o +CFLAGS_tegra_hsuart.o = -Werror obj-$(CONFIG_SERIAL_TEGRA) += tegra_hsuart.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_MAX3107) += max3107.o diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 9478a1bdaaca..b0e593b2a2a3 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_USB_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_FSL_USB2) += fsl_usb2_udc.o fsl_usb2_udc-y := fsl_udc_core.o fsl_usb2_udc-$(CONFIG_ARCH_MXC) += fsl_mxc_udc.o +CFLAGS_tegra_udc.o = -Werror obj-$(CONFIG_USB_TEGRA) += tegra_udc.o obj-$(CONFIG_USB_M66592) += m66592-udc.o obj-$(CONFIG_USB_R8A66597) += r8a66597-udc.o diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile index 39600f2d008a..e2f49cb9ae7b 100644 --- a/drivers/usb/otg/Makefile +++ b/drivers/usb/otg/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_USB_OTG_WAKELOCK) += otg-wakelock.o # transceiver drivers obj-$(CONFIG_USB_GPIO_VBUS) += gpio_vbus.o +CFLAGS_tegra-otg.o = -Werror obj-$(CONFIG_USB_TEGRA_OTG) += tegra-otg.o obj-$(CONFIG_ISP1301_OMAP) += isp1301_omap.o obj-$(CONFIG_TWL4030_USB) += twl4030-usb.o diff --git a/drivers/usb/otg/tegra-otg.c b/drivers/usb/otg/tegra-otg.c index 7a4d18cac257..a2c6477cdbc9 100644 --- a/drivers/usb/otg/tegra-otg.c +++ b/drivers/usb/otg/tegra-otg.c @@ -64,7 +64,7 @@ struct tegra_otg_data { bool clk_enabled; bool interrupt_mode; bool builtin_host; - bool suspended + bool suspended; }; static struct tegra_otg_data *tegra_clone; @@ -107,7 +107,7 @@ static unsigned long enable_interrupt(struct tegra_otg_data *tegra, bool en) if (tegra->builtin_host) val |= USB_INT_EN; else - val = USB_VBUS_INT_EN | USB_VBUS_WAKEUP_EN | USB_ID_PIN_WAKEUP_EN; + val |= USB_VBUS_INT_EN | USB_VBUS_WAKEUP_EN | USB_ID_PIN_WAKEUP_EN; } else val &= ~USB_INT_EN; @@ -339,7 +339,7 @@ static ssize_t store_host_en(struct device *dev, struct device_attribute *attr, { struct platform_device *pdev = to_platform_device(dev); struct tegra_otg_data *tegra = platform_get_drvdata(pdev); - unsigned long host; + unsigned int host; if (sscanf(buf, "%d", &host) != 1 || host < 0 || host > 1) return -EINVAL; diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile index 867ace0010d8..f28843e11cb1 100644 --- a/drivers/video/backlight/Makefile +++ b/drivers/video/backlight/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_BACKLIGHT_PANDORA) += pandora_bl.o obj-$(CONFIG_BACKLIGHT_PROGEAR) += progear_bl.o obj-$(CONFIG_BACKLIGHT_CARILLO_RANCH) += cr_bllcd.o obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o +CFLAGS_tegra_pwm_bl.o = -Werror obj-$(CONFIG_BACKLIGHT_TEGRA_PWM) += tegra_pwm_bl.o obj-$(CONFIG_BACKLIGHT_DA903X) += da903x_bl.o obj-$(CONFIG_BACKLIGHT_DA9052) += da9052_bl.o diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 0498774d5225..ce7224e2d0eb 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -1280,9 +1280,9 @@ static void tegra_dc_underflow_handler(struct tegra_dc *dc) #endif #ifdef CONFIG_ARCH_TEGRA_3x_SOC if (dc->windows[i].underflows > 4) { - printk("%s:dc in underflow state." + trace_printk("%s:window %c in underflow state." " enable UF_LINE_FLUSH to clear up\n", - __func__); + dc->ndev->name, (65 + i)); tegra_dc_writel(dc, UF_LINE_FLUSH, DC_DISP_DISP_MISC_CONTROL); tegra_dc_writel(dc, GENERAL_UPDATE, @@ -1597,14 +1597,18 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc) tegra_dc_clk_enable(dc); /* do not accept interrupts during initialization */ - tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE); tegra_dc_writel(dc, 0, DC_CMD_INT_MASK); enable_dc_irq(dc->irq); failed_init = tegra_dc_init(dc); if (failed_init) { - _tegra_dc_controller_disable(dc); + tegra_dc_writel(dc, 0, DC_CMD_INT_MASK); + disable_irq(dc->irq); + tegra_dc_clear_bandwidth(dc); + tegra_dc_clk_disable(dc); + if (dc->out && dc->out->disable) + dc->out->disable(); return false; } @@ -1725,7 +1729,11 @@ static bool _tegra_dc_enable(struct tegra_dc *dc) tegra_dc_io_start(dc); - return _tegra_dc_controller_enable(dc); + if (!_tegra_dc_controller_enable(dc)) { + tegra_dc_io_end(dc); + return false; + } + return true; } void tegra_dc_enable(struct tegra_dc *dc) diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h index e79d1ec44afc..209bd7fa136d 100644 --- a/drivers/video/tegra/dc/dc_priv.h +++ b/drivers/video/tegra/dc/dc_priv.h @@ -375,7 +375,7 @@ void tegra_dc_disable_crc(struct tegra_dc *dc); void tegra_dc_set_out_pin_polars(struct tegra_dc *dc, const struct tegra_dc_out_pin *pins, const unsigned int n_pins); -/* defined in dc.c, used in bandwidth.c */ +/* defined in dc.c, used in bandwidth.c and ext/dev.c */ unsigned int tegra_dc_has_multiple_dc(void); /* defined in dc.c, used in dsi.c */ diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index 1d01f68ccb63..cf1f6970001c 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -306,6 +306,7 @@ static int dbg_dsi_show(struct seq_file *s, void *unused) DUMP_REG(DSI_CTXSW); DUMP_REG(DSI_POWER_CONTROL); DUMP_REG(DSI_INT_ENABLE); + DUMP_REG(DSI_HOST_DSI_CONTROL); DUMP_REG(DSI_CONTROL); DUMP_REG(DSI_SOL_DELAY); DUMP_REG(DSI_MAX_THRESHOLD); @@ -1520,6 +1521,31 @@ static void tegra_dsi_reset_underflow_overflow } } +static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi) +{ + u32 trigger; + + tegra_dsi_writel(dsi, + DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE), + DSI_POWER_CONTROL); + /* stabilization delay */ + udelay(300); + + tegra_dsi_writel(dsi, + DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE), + DSI_POWER_CONTROL); + /* stabilization delay */ + udelay(300); + + /* dsi HW does not clear host trigger bit automatically + * on dsi interface disable if host fifo is empty or in mid + * of host transmission + */ + trigger = tegra_dsi_readl(dsi, DSI_TRIGGER); + if (trigger) + tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER); +} + static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi) { @@ -1538,13 +1564,13 @@ static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, long timeout; u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate); - /* stop dc */ - tegra_dsi_stop_dc_stream(dc, dsi); + INIT_COMPLETION(dc->frame_end_complete); - /* enable frame end interrupt */ + /* unmask frame end interrupt */ val = tegra_dc_readl(dc, DC_CMD_INT_MASK); - val |= FRAME_END_INT; - tegra_dc_writel(dc, val, DC_CMD_INT_MASK); + tegra_dc_writel(dc, val | FRAME_END_INT, DC_CMD_INT_MASK); + + tegra_dsi_stop_dc_stream(dc, dsi); /* wait for frame_end completion. * timeout is 2 frame duration to accomodate for @@ -1554,9 +1580,14 @@ static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc, &dc->frame_end_complete, msecs_to_jiffies(2 * frame_period)); - /* disable frame end interrupt */ - val = tegra_dc_readl(dc, DC_CMD_INT_MASK); - val &= ~FRAME_END_INT; + /* give 2 line time to dsi HW to catch up + * with pixels sent by dc + */ + udelay(50); + + tegra_dsi_soft_reset(dsi); + + /* reinstate interrupt mask */ tegra_dc_writel(dc, val, DC_CMD_INT_MASK); if (timeout == 0) @@ -1740,7 +1771,8 @@ static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi) dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT; } -static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi) +static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi, + u8 driven_mode) { u32 dsi_control; u32 host_dsi_control; @@ -1752,7 +1784,7 @@ static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi) max_threshold = 0; dcs_cmd = 0; - if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) { + if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) { dsi_control |= DSI_CTRL_HOST_DRIVEN; host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN; max_threshold = @@ -1764,17 +1796,19 @@ static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi) max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH); dsi->status.driven = DSI_DRIVEN_MODE_DC; - } - - if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) { - dsi_control |= DSI_CTRL_CMD_MODE; - dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(DSI_WRITE_MEMORY_START)| - DSI_DCS_CMDS_LT3_DCS_CMD(DSI_WRITE_MEMORY_CONTINUE); - dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE; - } else { - dsi_control |= DSI_CTRL_VIDEO_MODE; - dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE; + if (dsi->info.video_data_type == + TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) { + dsi_control |= DSI_CTRL_CMD_MODE; + dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD( + DSI_WRITE_MEMORY_START)| + DSI_DCS_CMDS_LT3_DCS_CMD( + DSI_WRITE_MEMORY_CONTINUE); + dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE; + } else { + dsi_control |= DSI_CTRL_VIDEO_MODE; + dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE; + } } tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD); @@ -1987,6 +2021,7 @@ static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc, dsi->status.lphs = DSI_LPHS_IN_LP_MODE; dsi->status.lp_op = lp_op; + dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST; success: err = 0; fail: @@ -2038,7 +2073,8 @@ static void tegra_dsi_ganged(struct tegra_dc *dc, } static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc, - struct tegra_dc_dsi_data *dsi) + struct tegra_dc_dsi_data *dsi, + u8 driven_mode) { int err; @@ -2047,9 +2083,12 @@ static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc, goto fail; } - if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) + if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE && + dsi->driven_mode == driven_mode) goto success; + dsi->driven_mode = driven_mode; + if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); @@ -2064,14 +2103,14 @@ static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc, tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE); - if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_DC) { + if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) { tegra_dsi_set_pkt_seq(dc, dsi); tegra_dsi_set_pkt_length(dc, dsi); tegra_dsi_set_sol_delay(dc, dsi); tegra_dsi_set_dc_clk(dc, dsi); } - tegra_dsi_set_control_reg_hs(dsi); + tegra_dsi_set_control_reg_hs(dsi, driven_mode); if (dsi->info.ganged_type) tegra_dsi_ganged(dc, dsi); @@ -2145,35 +2184,6 @@ fail: return (err < 0 ? true : false); } -static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi) -{ - u32 trigger; - u32 status; - - tegra_dsi_writel(dsi, - DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE), - DSI_POWER_CONTROL); - /* stabilization delay */ - udelay(300); - - tegra_dsi_writel(dsi, - DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE), - DSI_POWER_CONTROL); - /* stabilization delay */ - udelay(300); - - /* dsi HW does not clear host trigger bit automatically - * on dsi interface disable if host fifo is empty - */ - trigger = tegra_dsi_readl(dsi, DSI_TRIGGER); - status = tegra_dsi_readl(dsi, DSI_STATUS); - if (trigger & DSI_TRIGGER_HOST_TRIGGER(0x1) && - status & DSI_STATUS_IDLE(0x1)) { - trigger &= ~(DSI_TRIGGER_HOST_TRIGGER(0x1)); - tegra_dsi_writel(dsi, trigger, DSI_TRIGGER); - } -} - static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi) { u32 val; @@ -2192,49 +2202,42 @@ static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode( struct tegra_dc *dc, u8 lp_op) { - struct dsi_status *init_status; + struct dsi_status *init_status = NULL; int err; + if (dsi->status.init != DSI_MODULE_INIT || + dsi->status.lphs == DSI_LPHS_NOT_INIT) { + err = -EPERM; + goto fail; + } + init_status = kzalloc(sizeof(*init_status), GFP_KERNEL); if (!init_status) return ERR_PTR(-ENOMEM); *init_status = dsi->status; - if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) { - if (dsi->status.driven == DSI_DRIVEN_MODE_DC) { - if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) - tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); - dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST; - if (dsi->info.hs_cmd_mode_supported) { - err = tegra_dsi_set_to_hs_mode(dc, dsi); - if (err < 0) { - dev_err(&dc->ndev->dev, - "Switch to HS host mode failed\n"); - goto fail; - } - } - } - if (!dsi->info.hs_cmd_mode_supported) { - err = - tegra_dsi_set_to_lp_mode(dc, dsi, lp_op); - if (err < 0) { - dev_err(&dc->ndev->dev, - "DSI failed to go to LP mode\n"); - goto fail; - } - } - } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) { - if (dsi->status.lp_op != lp_op) { - err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op); - if (err < 0) { - dev_err(&dc->ndev->dev, - "DSI failed to go to LP mode\n"); - goto fail; - } + if (dsi->info.hs_cmd_mode_supported) { + err = tegra_dsi_set_to_hs_mode(dc, dsi, + TEGRA_DSI_DRIVEN_BY_HOST); + if (err < 0) { + dev_err(&dc->ndev->dev, + "Switch to HS host mode failed\n"); + goto fail; } + + goto success; } + if (dsi->status.lp_op != lp_op) { + err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op); + if (err < 0) { + dev_err(&dc->ndev->dev, + "DSI failed to go to LP mode\n"); + goto fail; + } + } +success: return init_status; fail: kfree(init_status); @@ -2248,6 +2251,7 @@ static struct dsi_status *tegra_dsi_prepare_host_transmission( { int err = 0; struct dsi_status *init_status; + bool restart_dc_stream = false; if (dsi->status.init != DSI_MODULE_INIT || dsi->ulpm) { @@ -2255,12 +2259,13 @@ static struct dsi_status *tegra_dsi_prepare_host_transmission( goto fail; } + if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) { + restart_dc_stream = true; + tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); + } + if (tegra_dsi_host_busy(dsi)) { tegra_dsi_soft_reset(dsi); - - /* WAR to stop host write in middle */ - tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_TRIGGER); - if (tegra_dsi_host_busy(dsi)) { err = -EBUSY; dev_err(&dc->ndev->dev, "DSI host busy\n"); @@ -2287,6 +2292,9 @@ static struct dsi_status *tegra_dsi_prepare_host_transmission( goto fail; } + if (restart_dc_stream) + init_status->dc_stream = DSI_DC_STREAM_ENABLE; + return init_status; fail: return ERR_PTR(err); @@ -2296,50 +2304,30 @@ static int tegra_dsi_restore_state(struct tegra_dc *dc, struct tegra_dc_dsi_data *dsi, struct dsi_status *init_status) { - bool switch_back_to_dc_mode = false; - bool switch_back_to_hs_mode = false; - bool restart_dc_stream; int err = 0; - switch_back_to_dc_mode = (dsi->status.driven == - DSI_DRIVEN_MODE_HOST && - init_status->driven == - DSI_DRIVEN_MODE_DC); - switch_back_to_hs_mode = (dsi->status.lphs == - DSI_LPHS_IN_LP_MODE && - init_status->lphs == - DSI_LPHS_IN_HS_MODE); - restart_dc_stream = (dsi->status.dc_stream == - DSI_DC_STREAM_DISABLE && - init_status->dc_stream == - DSI_DC_STREAM_ENABLE); - - if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE && - init_status->lphs == DSI_LPHS_IN_LP_MODE) { - if (dsi->status.lp_op != init_status->lp_op) { - err = - tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op); - if (err < 0) { - dev_err(&dc->ndev->dev, - "Failed to config LP mode\n"); - goto fail; - } + if (init_status->lphs == DSI_LPHS_IN_LP_MODE) { + err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op); + if (err < 0) { + dev_err(&dc->ndev->dev, + "Failed to config LP mode\n"); + goto fail; } goto success; } - if (switch_back_to_dc_mode) - dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC; - if (switch_back_to_dc_mode || switch_back_to_hs_mode) { - err = tegra_dsi_set_to_hs_mode(dc, dsi); + if (init_status->lphs == DSI_LPHS_IN_HS_MODE) { + u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ? + TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST; + err = tegra_dsi_set_to_hs_mode(dc, dsi, driven); if (err < 0) { dev_err(&dc->ndev->dev, "Failed to config HS mode\n"); goto fail; } } - if (restart_dc_stream) - tegra_dsi_start_dc_stream(dc, dsi); + if (init_status->dc_stream == DSI_DC_STREAM_ENABLE) + tegra_dsi_start_dc_stream(dc, dsi); success: fail: kfree(init_status); @@ -2844,6 +2832,7 @@ int tegra_dsi_read_data(struct tegra_dc *dc, int err = 0; struct dsi_status *init_status; + mutex_lock(&dsi->lock); tegra_dc_io_start(dc); init_status = tegra_dsi_prepare_host_transmission( @@ -2902,6 +2891,7 @@ fail: if (err < 0) dev_err(&dc->ndev->dev, "Failed to restore prev state\n"); tegra_dc_io_end(dc); + mutex_unlock(&dsi->lock); return err; } EXPORT_SYMBOL(tegra_dsi_read_data); @@ -3040,7 +3030,8 @@ static void tegra_dsi_send_dc_frames(struct tegra_dc *dc, bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE); if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) { - err = tegra_dsi_set_to_hs_mode(dc, dsi); + err = tegra_dsi_set_to_hs_mode(dc, dsi, + TEGRA_DSI_DRIVEN_BY_DC); if (err < 0) { dev_err(&dc->ndev->dev, "Switch to HS host mode failed\n"); @@ -3173,7 +3164,8 @@ static void _tegra_dc_dsi_enable(struct tegra_dc *dc) goto fail; } - err = tegra_dsi_set_to_hs_mode(dc, dsi); + err = tegra_dsi_set_to_hs_mode(dc, dsi, + TEGRA_DSI_DRIVEN_BY_DC); if (err < 0) { dev_err(&dc->ndev->dev, "dsi: not able to set to hs mode\n"); @@ -3756,7 +3748,6 @@ static void tegra_dc_dsi_disable(struct tegra_dc *dc) } } } - fail: mutex_unlock(&dsi->lock); tegra_dc_io_end(dc); diff --git a/drivers/video/tegra/dc/ext/dev.c b/drivers/video/tegra/dc/ext/dev.c index d8dab844655d..966dbe1b5853 100644 --- a/drivers/video/tegra/dc/ext/dev.c +++ b/drivers/video/tegra/dc/ext/dev.c @@ -275,6 +275,32 @@ static int tegra_dc_ext_set_windowattr(struct tegra_dc_ext *ext, return 0; } +static struct srcu_notifier_head tegra_dc_flip_notifier_list; +static bool init_tegra_dc_flip_notifier_list_called; +static int __init init_tegra_dc_flip_notifier_list(void) +{ + srcu_init_notifier_head(&tegra_dc_flip_notifier_list); + init_tegra_dc_flip_notifier_list_called = true; + return 0; +} + +pure_initcall(init_tegra_dc_flip_notifier_list); + +int tegra_dc_register_flip_notifier(struct notifier_block *nb) +{ + WARN_ON(!init_tegra_dc_flip_notifier_list_called); + + return srcu_notifier_chain_register( + &tegra_dc_flip_notifier_list, nb); +} +EXPORT_SYMBOL(tegra_dc_register_flip_notifier); + +int tegra_dc_unregister_flip_notifier(struct notifier_block *nb) +{ + return srcu_notifier_chain_unregister(&tegra_dc_flip_notifier_list, nb); +} +EXPORT_SYMBOL(tegra_dc_unregister_flip_notifier); + static void tegra_dc_ext_flip_worker(struct work_struct *work) { struct tegra_dc_ext_flip_data *data = @@ -328,6 +354,9 @@ static void tegra_dc_ext_flip_worker(struct work_struct *work) tegra_dc_update_windows(wins, nr_win); /* TODO: implement swapinterval here */ tegra_dc_sync_windows(wins, nr_win); + if (!tegra_dc_has_multiple_dc()) + srcu_notifier_call_chain(&tegra_dc_flip_notifier_list, + 1UL, NULL); } for (i = 0; i < DC_N_WINDOWS; i++) { diff --git a/drivers/video/tegra/dc/mode.c b/drivers/video/tegra/dc/mode.c index 49cc5f5abd53..be909691b957 100644 --- a/drivers/video/tegra/dc/mode.c +++ b/drivers/video/tegra/dc/mode.c @@ -247,10 +247,23 @@ int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode) return 0; } +static int panel_sync_rate; + +int tegra_dc_get_panel_sync_rate(void) +{ + return panel_sync_rate; +} +EXPORT_SYMBOL(tegra_dc_get_panel_sync_rate); + int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode) { memcpy(&dc->mode, mode, sizeof(dc->mode)); + if (dc->out->type == TEGRA_DC_OUT_RGB) + panel_sync_rate = tegra_dc_calc_refresh(mode); + else if (dc->out->type == TEGRA_DC_OUT_DSI) + panel_sync_rate = dc->out->dsi->rated_refresh_rate * 1000; + print_mode(dc, mode, __func__); return 0; diff --git a/drivers/video/tegra/host/bus.c b/drivers/video/tegra/host/bus.c index b84865d0d8c7..9baa7a51c0d1 100644 --- a/drivers/video/tegra/host/bus.c +++ b/drivers/video/tegra/host/bus.c @@ -98,7 +98,7 @@ static int nvhost_bus_match(struct device *_dev, struct device_driver *drv) if (ndrv->id_table) return nvhost_bus_match_id(dev, ndrv->id_table) != NULL; else /* driver does not support id_table */ - return !strncmp(dev->name, drv->name, strlen(drv->name)); + return !strcmp(dev->name, drv->name); } static int nvhost_drv_probe(struct device *_dev) diff --git a/drivers/video/tegra/host/gr3d/scale3d.c b/drivers/video/tegra/host/gr3d/scale3d.c index 5922b55a836a..9a6a8e73b513 100644 --- a/drivers/video/tegra/host/gr3d/scale3d.c +++ b/drivers/video/tegra/host/gr3d/scale3d.c @@ -85,9 +85,14 @@ struct scale3d_info_rec { long emc_dip_offset; long emc_xmid; unsigned long min_rate_3d; + ktime_t last_throughput_hint; struct work_struct work; struct delayed_work idle_timer; unsigned int scale; + unsigned int p_use_throughput_hint; + unsigned int p_throughput_lo_limit; + unsigned int p_throughput_hi_limit; + unsigned int p_scale_step; unsigned int p_period; unsigned int period; unsigned int p_idle_min; @@ -382,6 +387,13 @@ void nvhost_scale3d_notify_idle(struct nvhost_device *dev) if (!scale3d.enable) return; + /* if throughput hint enabled, and last hint is recent enough, return */ + if (scale3d.p_use_throughput_hint) { + t = ktime_get(); + if (ktime_us_delta(t, scale3d.last_throughput_hint) < 1000000) + return; + } + mutex_lock(&scale3d.lock); t = ktime_get(); @@ -416,6 +428,13 @@ void nvhost_scale3d_notify_busy(struct nvhost_device *dev) if (!scale3d.enable) return; + /* if throughput hint enabled, and last hint is recent enough, return */ + if (scale3d.p_use_throughput_hint) { + t = ktime_get(); + if (ktime_us_delta(t, scale3d.last_throughput_hint) < 1000000) + return; + } + mutex_lock(&scale3d.lock); cancel_delayed_work(&scale3d.idle_timer); @@ -437,6 +456,66 @@ void nvhost_scale3d_notify_busy(struct nvhost_device *dev) mutex_unlock(&scale3d.lock); } +static void do_scale(int diff) +{ + unsigned long hz, curr; + + if (!tegra_is_clk_enabled(scale3d.clk_3d)) + return; + + if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) + if (!tegra_is_clk_enabled(scale3d.clk_3d2)) + return; + + curr = clk_get_rate(scale3d.clk_3d); + hz = curr + diff; + + if (hz < scale3d.min_rate_3d) + hz = scale3d.min_rate_3d; + + if (hz > scale3d.max_rate_3d) + hz = scale3d.max_rate_3d; + + if (hz == curr) return; + + if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA3) + clk_set_rate(scale3d.clk_3d2, 0); + clk_set_rate(scale3d.clk_3d, hz); + + if (scale3d.p_scale_emc) { + long after = (long) clk_get_rate(scale3d.clk_3d); + hz = after * scale3d.emc_slope + scale3d.emc_offset; + if (scale3d.p_emc_dip) + hz -= + (scale3d.emc_dip_slope * + POW2(after / 1000 - scale3d.emc_xmid) + + scale3d.emc_dip_offset); + clk_set_rate(scale3d.clk_3d_emc, hz); + } +} + +#define scale_up() do_scale(scale3d.p_scale_step) +#define scale_down() do_scale(-scale3d.p_scale_step) + +void nvhost_scale3d_set_throughput_hint(int hint) +{ + if (!scale3d.enable) + return; + + if (!scale3d.p_use_throughput_hint) + return; + + scale3d.last_throughput_hint = ktime_get(); + + if (scale3d.p_use_throughput_hint) { + if (hint >= scale3d.p_throughput_hi_limit) + scale_down(); + else if (hint <= scale3d.p_throughput_lo_limit) + scale_up(); + } +} +EXPORT_SYMBOL(nvhost_scale3d_set_throughput_hint); + static void scale3d_idle_handler(struct work_struct *work) { int notify_idle = 0; @@ -502,6 +581,10 @@ void nvhost_scale3d_debug_init(struct dentry *de) CREATE_SCALE3D_FILE(adjust); CREATE_SCALE3D_FILE(scale_emc); CREATE_SCALE3D_FILE(emc_dip); + CREATE_SCALE3D_FILE(use_throughput_hint); + CREATE_SCALE3D_FILE(throughput_hi_limit); + CREATE_SCALE3D_FILE(throughput_lo_limit); + CREATE_SCALE3D_FILE(scale_step); CREATE_SCALE3D_FILE(verbosity); #undef CREATE_SCALE3D_FILE } @@ -642,6 +725,10 @@ void nvhost_scale3d_init(struct nvhost_device *d) scale3d.p_emc_dip = 1; scale3d.p_verbosity = 0; scale3d.p_adjust = 1; + scale3d.p_use_throughput_hint = 1; + scale3d.p_throughput_lo_limit = 95; + scale3d.p_throughput_hi_limit = 100; + scale3d.p_scale_step = 60000000; error = device_create_file(&d->dev, &dev_attr_enable_3d_scaling); diff --git a/drivers/video/tegra/nvmap/nvmap_ioctl.c b/drivers/video/tegra/nvmap/nvmap_ioctl.c index 44f00d2951a0..5bfbbf60f8ff 100644 --- a/drivers/video/tegra/nvmap/nvmap_ioctl.c +++ b/drivers/video/tegra/nvmap/nvmap_ioctl.c @@ -65,10 +65,10 @@ int nvmap_ioctl_pinop(struct file *filp, bool is_pin, void __user *arg) return -EINVAL; if (op.count > 1) { - size_t bytes = op.count * sizeof(unsigned long *); + size_t bytes = op.count * sizeof(*refs); /* kcalloc below will catch overflow. */ if (op.count > ARRAY_SIZE(on_stack)) - refs = kmalloc(op.count * sizeof(*refs), GFP_KERNEL); + refs = kcalloc(op.count, sizeof(*refs), GFP_KERNEL); else refs = on_stack; @@ -251,7 +251,7 @@ int nvmap_map_into_caller_ptr(struct file *filp, void __user *arg) goto out; } - if ((op.offset + op.length) > h->size) { + if (op.offset > h->size || (op.offset + op.length) > h->size) { err = -EADDRNOTAVAIL; goto out; } diff --git a/drivers/w1/masters/Makefile b/drivers/w1/masters/Makefile index 96499dce0b94..1f05328a7013 100644 --- a/drivers/w1/masters/Makefile +++ b/drivers/w1/masters/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_W1_MASTER_MXC) += mxc_w1.o obj-$(CONFIG_W1_MASTER_DS1WM) += ds1wm.o obj-$(CONFIG_W1_MASTER_GPIO) += w1-gpio.o obj-$(CONFIG_HDQ_MASTER_OMAP) += omap_hdq.o +CFLAGS_tegra_w1.o = -Werror obj-$(CONFIG_W1_MASTER_TEGRA) += tegra_w1.o diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 105cd0fb6784..a8030d225db9 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o obj-$(CONFIG_DW_WATCHDOG) += dw_wdt.o obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o +CFLAGS_tegra_wdt.o = -Werror obj-$(CONFIG_TEGRA_WATCHDOG) += tegra_wdt.o obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o diff --git a/drivers/watchdog/tegra_wdt.c b/drivers/watchdog/tegra_wdt.c index 0d8373efd3f1..1bcd726ebbd6 100644 --- a/drivers/watchdog/tegra_wdt.c +++ b/drivers/watchdog/tegra_wdt.c @@ -330,11 +330,11 @@ static const struct file_operations tegra_wdt_fops = { static int tegra_wdt_probe(struct platform_device *pdev) { - struct resource *res_src, *res_wdt, *res_irq, *res_int_base; + struct resource *res_src, *res_wdt, *res_irq; + struct resource *res_int_base = NULL; struct tegra_wdt *wdt; u32 src; int ret = 0; - u32 val = 0; if (pdev->id < -1 && pdev->id > 3) { dev_err(&pdev->dev, "only IDs 3:0 supported\n"); @@ -469,6 +469,7 @@ static int tegra_wdt_probe(struct platform_device *pdev) #ifdef CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE /* Init and enable watchdog on WDT0 with timer 8 during probe */ if (!(pdev->id)) { + u32 val = 0; wdt->status = WDT_ENABLED | WDT_ENABLED_AT_PROBE; wdt->timeout = heartbeat; tegra_wdt_enable(wdt); diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h index 5f001db4eea8..7ae86b956710 100644 --- a/include/linux/mfd/tps65090.h +++ b/include/linux/mfd/tps65090.h @@ -22,31 +22,60 @@ #ifndef __LINUX_MFD_TPS65090_H #define __LINUX_MFD_TPS65090_H -#include <linux/rtc.h> +#include <linux/irq.h> +#include <linux/regmap.h> -struct tps65090_subdev_info { - int id; - const char *name; - void *platform_data; +struct tps65090 { + struct device *dev; + struct regmap *rmap; + struct irq_chip irq_chip; + struct mutex irq_lock; + int irq_base; }; struct tps65090_platform_data { int irq_base; - int num_subdevs; - struct tps65090_subdev_info *subdevs; + struct tps65090_regulator_platform_data **reg_pdata; + int num_reg_pdata; }; /* * NOTE: the functions below are not intended for use outside * of the TPS65090 sub-device drivers */ -extern int tps65090_write(struct device *dev, int reg, uint8_t val); -extern int tps65090_writes(struct device *dev, int reg, int len, uint8_t *val); -extern int tps65090_read(struct device *dev, int reg, uint8_t *val); -extern int tps65090_reads(struct device *dev, int reg, int len, uint8_t *val); -extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num); -extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num); -extern int tps65090_update(struct device *dev, int reg, uint8_t val, - uint8_t bit_num); +static inline int tps65090_write(struct device *dev, int reg, uint8_t val) +{ + struct tps65090 *tps = dev_get_drvdata(dev); + + return regmap_write(tps->rmap, reg, val); +} + +static inline int tps65090_read(struct device *dev, int reg, uint8_t *val) +{ + struct tps65090 *tps = dev_get_drvdata(dev); + unsigned int temp_val; + int ret; + + ret = regmap_read(tps->rmap, reg, &temp_val); + if (!ret) + *val = temp_val; + return ret; +} + +static inline int tps65090_set_bits(struct device *dev, int reg, + uint8_t bit_num) +{ + struct tps65090 *tps = dev_get_drvdata(dev); + + return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u); +} + +static inline int tps65090_clr_bits(struct device *dev, int reg, + uint8_t bit_num) +{ + struct tps65090 *tps = dev_get_drvdata(dev); + + return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u); +} #endif /*__LINUX_MFD_TPS65090_H */ diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h index b3b9480ce596..974fc0db0ff2 100644 --- a/include/linux/mfd/tps80031.h +++ b/include/linux/mfd/tps80031.h @@ -197,6 +197,8 @@ struct tps80031_platform_data { bool use_power_off; struct tps80031_pupd_init_data *pupd_init_data; int pupd_init_data_size; + struct tps80031_regulator_platform_data **regulator_pdata; + int num_regulator_pdata; }; struct tps80031_bg_platform_data { diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index dd458b3d202b..05de12d85114 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -241,6 +241,13 @@ struct mmc_host { #define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */ #define MMC_CAP2_BKOPS (1 << 10) /* Host supports BKOPS */ + unsigned int caps2; /* More host capabilities */ +#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ +#define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ +#define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */ +#define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */ +#define MMC_CAP2_NO_SLEEP_CMD (1 << 4) /* Don't allow sleep command */ + mmc_pm_flag_t pm_caps; /* supported pm features */ unsigned int power_notify_type; #define MMC_HOST_PW_NOTIFY_NONE 0 diff --git a/include/linux/nvhost.h b/include/linux/nvhost.h index f71d64885efe..83cd02a8bf19 100644 --- a/include/linux/nvhost.h +++ b/include/linux/nvhost.h @@ -211,4 +211,6 @@ u32 nvhost_syncpt_read_ext(struct nvhost_device *dev, u32 id); int nvhost_syncpt_wait_timeout_ext(struct nvhost_device *dev, u32 id, u32 thresh, u32 timeout, u32 *value); +void nvhost_scale3d_set_throughput_hint(int hint); + #endif diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h index 4a3286dc96d0..597c2f3a15c9 100644 --- a/include/linux/platform_data/tegra_usb.h +++ b/include/linux/platform_data/tegra_usb.h @@ -65,17 +65,6 @@ struct tegra_ulpi_config { }; /** - * configuration structure for setting up hsic phy - */ -struct tegra_hsic_config { - u8 sync_start_delay; - u8 idle_wait_delay; - u8 term_range_adj; - u8 elastic_underrun_limit; - u8 elastic_overrun_limit; -}; - -/** * Platform specific operations that will be controlled * during the phy operations. */ @@ -134,7 +123,6 @@ struct tegra_usb_platform_data { union { struct tegra_utmi_config utmi; struct tegra_ulpi_config ulpi; - struct tegra_hsic_config hsic; } u_cfg; struct tegra_usb_phy_platform_ops *ops; diff --git a/include/linux/regulator/tps65090-regulator.h b/include/linux/regulator/tps65090-regulator.h index 341d53ec994a..785ca84efa8b 100644 --- a/include/linux/regulator/tps65090-regulator.h +++ b/include/linux/regulator/tps65090-regulator.h @@ -1,24 +1,19 @@ /* - * include/linux/regulator/tps65090-regulator.h + * Regulator driver interface for TI TPS65090 PMIC family * - * Interface for regulator driver for TI TPS65090 PMIC family - * - * Copyright (C) 2012 NVIDIA Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #ifndef __REGULATOR_TPS65090_H @@ -29,32 +24,36 @@ #define tps65090_rails(_name) "tps65090_"#_name enum { - TPS65090_ID_DCDC1, - TPS65090_ID_DCDC2, - TPS65090_ID_DCDC3, - TPS65090_ID_FET1, - TPS65090_ID_FET2, - TPS65090_ID_FET3, - TPS65090_ID_FET4, - TPS65090_ID_FET5, - TPS65090_ID_FET6, - TPS65090_ID_FET7, + TPS65090_REGULATOR_DCDC1, + TPS65090_REGULATOR_DCDC2, + TPS65090_REGULATOR_DCDC3, + TPS65090_REGULATOR_LDO1, + TPS65090_REGULATOR_LDO2, + TPS65090_REGULATOR_FET1, + TPS65090_REGULATOR_FET2, + TPS65090_REGULATOR_FET3, + TPS65090_REGULATOR_FET4, + TPS65090_REGULATOR_FET5, + TPS65090_REGULATOR_FET6, + TPS65090_REGULATOR_FET7, }; /* * struct tps65090_regulator_platform_data * - * @regulator: The regulator init data. - * @init_uV: initial micro volts which need to be set. - * @init_enable: Enable or do not enable the rails during initialization. - * @init_apply: Init parameter applied or not. - * @slew_rate_uV_per_us: Slew rate microvolt per microsec. + * @reg_init_data: The regulator init data. + * @id: Regulator ID. + * @enable_ext_control: Enable extrenal control or not. Only available for + * DCDC1, DCDC2 and DCDC3. + * @gpio: Gpio number if external control is enabled and controlled through + * gpio. */ struct tps65090_regulator_platform_data { - struct regulator_init_data regulator; - int slew_rate_uV_per_us; - unsigned int flags; + int id; + bool enable_ext_control; + int gpio; + struct regulator_init_data *reg_init_data; }; #endif /* __REGULATOR_TPS65090_H */ diff --git a/include/linux/regulator/tps80031-regulator.h b/include/linux/regulator/tps80031-regulator.h index 4dfdf7950918..f51fd24feff8 100644 --- a/include/linux/regulator/tps80031-regulator.h +++ b/include/linux/regulator/tps80031-regulator.h @@ -29,23 +29,26 @@ #define tps80031_rails(_name) "tps80031_"#_name enum { - TPS80031_ID_VIO, - TPS80031_ID_SMPS1, - TPS80031_ID_SMPS2, - TPS80031_ID_SMPS3, - TPS80031_ID_SMPS4, - TPS80031_ID_VANA, - TPS80031_ID_LDO1, - TPS80031_ID_LDO2, - TPS80031_ID_LDO3, - TPS80031_ID_LDO4, - TPS80031_ID_LDO5, - TPS80031_ID_LDO6, - TPS80031_ID_LDO7, - TPS80031_ID_LDOLN, - TPS80031_ID_LDOUSB, - TPS80031_ID_VBUS, - TPS80031_ID_CHARGER, + TPS80031_REGULATOR_VIO, + TPS80031_REGULATOR_SMPS1, + TPS80031_REGULATOR_SMPS2, + TPS80031_REGULATOR_SMPS3, + TPS80031_REGULATOR_SMPS4, + TPS80031_REGULATOR_VANA, + TPS80031_REGULATOR_LDO1, + TPS80031_REGULATOR_LDO2, + TPS80031_REGULATOR_LDO3, + TPS80031_REGULATOR_LDO4, + TPS80031_REGULATOR_LDO5, + TPS80031_REGULATOR_LDO6, + TPS80031_REGULATOR_LDO7, + TPS80031_REGULATOR_LDOLN, + TPS80031_REGULATOR_LDOUSB, + TPS80031_REGULATOR_VBUS, + TPS80031_REGULATOR_REGEN1, + TPS80031_REGULATOR_REGEN2, + TPS80031_REGULATOR_SYSEN, + TPS80031_REGULATOR_CHARGER, }; @@ -66,7 +69,8 @@ enum { /* * struct tps80031_regulator_platform_data - tps80031 regulator platform data. * - * @regulator: The regulator init data. + * @regulator_id" Regulator ID. + * @reg_init_data: The regulator init data. * @init_uV: initial micro volts which need to be set. * @init_enable: Enable or do not enable the rails during initialization. * @init_apply: Init parameter applied or not. @@ -80,7 +84,8 @@ enum { */ struct tps80031_regulator_platform_data { - struct regulator_init_data regulator; + int regulator_id; + struct regulator_init_data *reg_init_data; int init_uV; unsigned init_enable:1; unsigned init_apply:1; diff --git a/include/linux/tegra_nvavp.h b/include/linux/tegra_nvavp.h index 6774d0eaa7ef..250eee379de9 100644 --- a/include/linux/tegra_nvavp.h +++ b/include/linux/tegra_nvavp.h @@ -1,7 +1,7 @@ /* * include/linux/tegra_nvavp.h * - * Copyright (C) 2011 NVIDIA Corp. + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any @@ -89,8 +89,12 @@ struct nvavp_clock_stay_on_state_args { __u32) #define NVAVP_IOCTL_FORCE_CLOCK_STAY_ON _IOW(NVAVP_IOCTL_MAGIC, 0x67, \ struct nvavp_clock_stay_on_state_args) +#define NVAVP_IOCTL_ENABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x68, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x69, \ + struct nvavp_clock_args) #define NVAVP_IOCTL_MIN_NR _IOC_NR(NVAVP_IOCTL_SET_NVMAP_FD) -#define NVAVP_IOCTL_MAX_NR _IOC_NR(NVAVP_IOCTL_FORCE_CLOCK_STAY_ON) +#define NVAVP_IOCTL_MAX_NR _IOC_NR(NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS) #endif /* __LINUX_TEGRA_NVAVP_H */ diff --git a/include/linux/throughput_ioctl.h b/include/linux/throughput_ioctl.h new file mode 100644 index 000000000000..96e57399b2e9 --- /dev/null +++ b/include/linux/throughput_ioctl.h @@ -0,0 +1,39 @@ +/* + * include/linux/throughput_ioctl.h + * + * ioctl declarations for throughput miscdev + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __TEGRA_THROUGHPUT_IOCTL_H +#define __TEGRA_THROUGHPUT_IOCTL_H + +#include <linux/ioctl.h> + +#define TEGRA_THROUGHPUT_MAGIC 'g' + +struct tegra_throughput_target_fps_args { + __u32 target_fps; +}; + +#define TEGRA_THROUGHPUT_IOCTL_TARGET_FPS \ + _IOW(TEGRA_THROUGHPUT_MAGIC, 1, struct tegra_throughput_target_fps_args) +#define TEGRA_THROUGHPUT_IOCTL_MAXNR \ + (_IOC_NR(TEGRA_THROUGHPUT_IOCTL_TARGET_FPS)) + +#endif /* !defined(__TEGRA_THROUGHPUT_IOCTL_H) */ + diff --git a/include/media/ov9726.h b/include/media/ov9726.h index b1e759ba583c..fb9995b4a8de 100644 --- a/include/media/ov9726.h +++ b/include/media/ov9726.h @@ -19,7 +19,8 @@ #define OV9726_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) #define OV9726_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) #define OV9726_IOCTL_SET_GAIN _IOW('o', 4, __u16) -#define OV9726_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV9726_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV9726_IOCTL_SET_GROUP_HOLD _IOW('o', 6, struct ov9726_ae) struct ov9726_mode { int mode_id; @@ -30,6 +31,15 @@ struct ov9726_mode { __u16 gain; }; +struct ov9726_ae { + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + __u8 frame_length_enable; + __u8 coarse_time_enable; + __u8 gain_enable; +}; + struct ov9726_reg { __u16 addr; __u16 val; diff --git a/include/trace/events/nvevent.h b/include/trace/events/nvevent.h new file mode 100644 index 000000000000..30987129deaf --- /dev/null +++ b/include/trace/events/nvevent.h @@ -0,0 +1,100 @@ +/* + * include/trace/events/nvevent.h + * + * Input event logging to ftrace. + * + * Copyright (c) 2012, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM nvevent + +#if !defined(_TRACE_NVEVENT_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_NVEVENT_H + +#include <linux/ktime.h> +#include <linux/tracepoint.h> + +TRACE_EVENT(nvevent_irq_data_read_start_series, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name; + ), + TP_printk("name=%s", + __entry->name) +); + +TRACE_EVENT(nvevent_irq_data_read_finish_series, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name; + ), + TP_printk("name=%s", + __entry->name) +); + +TRACE_EVENT(nvevent_irq_data_read_start_single, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name; + ), + TP_printk("name=%s", + __entry->name) +); + +TRACE_EVENT(nvevent_irq_data_read_finish_single, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name; + ), + TP_printk("name=%s", + __entry->name) +); + +TRACE_EVENT(nvevent_irq_data_submit, + TP_PROTO(const char *name), + TP_ARGS(name), + TP_STRUCT__entry( + __field(const char *, name) + ), + TP_fast_assign( + __entry->name = name; + ), + TP_printk("name=%s", + __entry->name) +); + +#endif /* _TRACE_NVEVENT_H */ + +/* This part must be outside protection */ +#include <trace/define_trace.h> diff --git a/kernel/kthread.c b/kernel/kthread.c index 3d3de633702e..b68236b45ba9 100644 --- a/kernel/kthread.c +++ b/kernel/kthread.c @@ -16,6 +16,7 @@ #include <linux/mutex.h> #include <linux/slab.h> #include <linux/freezer.h> +#include <linux/preempt.h> #include <trace/events/sched.h> static DEFINE_SPINLOCK(kthread_create_lock); @@ -113,7 +114,17 @@ static int kthread(void *_create) /* OK, tell user we're spawned, wait for stop or wakeup */ __set_current_state(TASK_UNINTERRUPTIBLE); create->result = current; + + /* + * Disable preemption so we enter TASK_UNINTERRUPTIBLE after + * complete() instead of possibly being preempted. This speeds + * up clients that do a kthread_bind() directly after + * creation. + */ + preempt_disable(); complete(&create->done); + preempt_enable_no_resched(); + schedule(); ret = -EINTR; diff --git a/sound/pci/hda/hda_codec.c b/sound/pci/hda/hda_codec.c index 6f3a85740e59..e525a32f1f53 100644 --- a/sound/pci/hda/hda_codec.c +++ b/sound/pci/hda/hda_codec.c @@ -3018,6 +3018,16 @@ static int snd_hda_spdif_out_switch_put(struct snd_kcontrol *kcontrol, return change; } +int snd_hda_max_pcm_ch_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 0xFFFFFFFF; + return 0; +} + int snd_hda_hdmi_decode_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) { @@ -3028,6 +3038,15 @@ int snd_hda_hdmi_decode_info(struct snd_kcontrol *kcontrol, return 0; } +static int snd_hda_max_pcm_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct hda_codec *codec = snd_kcontrol_chip(kcontrol); + + ucontrol->value.integer.value[0] = codec->max_pcm_channels; + return 0; +} + static int snd_hda_hdmi_decode_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -3072,6 +3091,12 @@ static struct snd_kcontrol_new dig_mixes[] = { .info = snd_hda_hdmi_decode_info, .get = snd_hda_hdmi_decode_get, }, + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "HDA Maximum PCM Channels", + .info = snd_hda_max_pcm_ch_info, + .get = snd_hda_max_pcm_ch_get, + }, { } /* end */ }; diff --git a/sound/pci/hda/hda_codec.h b/sound/pci/hda/hda_codec.h index 7b336ee44951..0910bc2d6e47 100644 --- a/sound/pci/hda/hda_codec.h +++ b/sound/pci/hda/hda_codec.h @@ -873,6 +873,7 @@ struct hda_codec { #endif unsigned int recv_dec_cap; + unsigned int max_pcm_channels; /* codec-specific additional proc output */ void (*proc_widget_hook)(struct snd_info_buffer *buffer, struct hda_codec *codec, hda_nid_t nid); diff --git a/sound/pci/hda/hda_eld.c b/sound/pci/hda/hda_eld.c index 92ba18687dff..cc15d09e8d99 100644 --- a/sound/pci/hda/hda_eld.c +++ b/sound/pci/hda/hda_eld.c @@ -443,6 +443,10 @@ int snd_hdmi_get_eld(struct hdmi_eld *eld, codec->recv_dec_cap |= (1 << AUDIO_CODING_TYPE_AC3); } else if (eld->sad[i].format == AUDIO_CODING_TYPE_DTS) { codec->recv_dec_cap |= (1 << AUDIO_CODING_TYPE_DTS); + } else if (eld->sad[i].format == AUDIO_CODING_TYPE_LPCM) { + codec->max_pcm_channels = + eld->sad[i].channels > codec->max_pcm_channels ? + eld->sad[i].channels : codec->max_pcm_channels; } } diff --git a/sound/soc/codecs/max98088.c b/sound/soc/codecs/max98088.c index e29e728f4e25..1be92feb1215 100644 --- a/sound/soc/codecs/max98088.c +++ b/sound/soc/codecs/max98088.c @@ -387,7 +387,7 @@ static struct { { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ { 0xFF, 0xFF, 0 }, /* 2D SPK control */ { 0xFF, 0xFF, 0 }, /* 2E sidetone */ - { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ + { 0xFF, 0xFF, 1 }, /* 2F DAI1 playback level */ { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c index 573fbe71f3c4..ea7eb766d73f 100644 --- a/sound/soc/tegra/tegra30_i2s.c +++ b/sound/soc/tegra/tegra30_i2s.c @@ -568,6 +568,13 @@ static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream, return ret; } + ret = clk_set_parent(clk_get_parent(i2s->clk_audio_2x), + i2s->clk_i2s_sync); + if (ret) { + dev_err(dev, "Can't set parent of audio2x clock\n"); + return ret; + } + ret = clk_set_rate(i2s->clk_audio_2x, i2sclock); if (ret) { dev_err(dev, "Can't set I2S sync clock rate\n"); diff --git a/sound/soc/tegra/tegra_max98095.c b/sound/soc/tegra/tegra_max98095.c index 0503a973b81f..35f8342a9d35 100644 --- a/sound/soc/tegra/tegra_max98095.c +++ b/sound/soc/tegra/tegra_max98095.c @@ -154,6 +154,31 @@ static int tegra_max98095_hw_params(struct snd_pcm_substream *substream, break; } + i2s_daifmt = SND_SOC_DAIFMT_NB_NF; + i2s_daifmt |= pdata->i2s_param[HIFI_CODEC].is_i2s_master ? + SND_SOC_DAIFMT_CBS_CFS : SND_SOC_DAIFMT_CBM_CFM; + + switch (pdata->i2s_param[HIFI_CODEC].i2s_mode) { + case TEGRA_DAIFMT_I2S : + i2s_daifmt |= SND_SOC_DAIFMT_I2S; + break; + case TEGRA_DAIFMT_DSP_A : + i2s_daifmt |= SND_SOC_DAIFMT_DSP_A; + break; + case TEGRA_DAIFMT_DSP_B : + i2s_daifmt |= SND_SOC_DAIFMT_DSP_B; + break; + case TEGRA_DAIFMT_LEFT_J : + i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J; + break; + case TEGRA_DAIFMT_RIGHT_J : + i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J; + break; + default : + dev_err(card->dev, "Can't configure i2s format\n"); + return -EINVAL; + } + err = tegra_asoc_utils_set_rate(&machine->util_data, srate, mclk); if (err < 0) { if (!(machine->util_data.set_mclk % mclk)) diff --git a/sound/usb/card.c b/sound/usb/card.c index 4a7be7b98331..223e4fe8e284 100644 --- a/sound/usb/card.c +++ b/sound/usb/card.c @@ -35,7 +35,6 @@ * indeed an AC3 stream packed in SPDIF frames (i.e. no real AC3 stream). */ - #include <linux/bitops.h> #include <linux/init.h> #include <linux/list.h> @@ -48,6 +47,9 @@ #include <linux/usb/audio.h> #include <linux/usb/audio-v2.h> #include <linux/module.h> +#ifdef CONFIG_SWITCH +#include <linux/switch.h> +#endif #include <sound/control.h> #include <sound/core.h> @@ -116,6 +118,18 @@ static DEFINE_MUTEX(register_mutex); static struct snd_usb_audio *usb_chip[SNDRV_CARDS]; static struct usb_driver usb_audio_driver; +#ifdef CONFIG_SWITCH +enum switch_state { + STATE_CONNECTED_UNKNOWN = -1, + STATE_DISCONNECTED = 0, + STATE_CONNECTED = 1 +}; + +static struct switch_dev usb_switch_dev = { + .name = "usb_audio", +}; +#endif + /* * disconnect streams * called from snd_usb_audio_disconnect() @@ -524,10 +538,15 @@ snd_usb_audio_probe(struct usb_device *dev, goto __error; } +#ifdef CONFIG_SWITCH + switch_set_state(&usb_switch_dev, STATE_CONNECTED); +#endif + usb_chip[chip->index] = chip; chip->num_interfaces++; chip->probing = 0; mutex_unlock(®ister_mutex); + return chip; __error: @@ -538,6 +557,7 @@ snd_usb_audio_probe(struct usb_device *dev, } mutex_unlock(®ister_mutex); __err_val: + return NULL; } @@ -559,6 +579,11 @@ static void snd_usb_audio_disconnect(struct usb_device *dev, mutex_lock(&chip->shutdown_mutex); chip->shutdown = 1; chip->num_interfaces--; + +#ifdef CONFIG_SWITCH + switch_set_state(&usb_switch_dev, STATE_DISCONNECTED); +#endif + if (chip->num_interfaces <= 0) { snd_card_disconnect(card); /* release the pcm resources */ @@ -713,15 +738,37 @@ static struct usb_driver usb_audio_driver = { static int __init snd_usb_audio_init(void) { + int err = 0; + if (nrpacks < 1 || nrpacks > MAX_PACKS) { printk(KERN_WARNING "invalid nrpacks value.\n"); return -EINVAL; } - return usb_register(&usb_audio_driver); + +#ifdef CONFIG_SWITCH + /* Add usb_audio swith class support */ + err = switch_dev_register(&usb_switch_dev); + if (err < 0){ + printk(KERN_ERR "failed to register switch device"); + return -EINVAL; + } +#endif + + err = usb_register(&usb_audio_driver); + if (err) { +#ifdef CONFIG_SWITCH + switch_dev_unregister(&usb_switch_dev); +#endif + } + + return err; } static void __exit snd_usb_audio_cleanup(void) { +#ifdef CONFIG_SWITCH + switch_dev_unregister(&usb_switch_dev); +#endif usb_deregister(&usb_audio_driver); } |