diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2016-08-31 13:34:14 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2016-09-12 10:42:34 +0800 |
| commit | d2b10f0c41e4b1def4d35b26d0d179111ff73406 (patch) | |
| tree | f6850b8a7c87cf7c47b1f13808bca956a1ae60da | |
| parent | cde006010b2d436891817982144fba9927a72a61 (diff) | |
MLK-13186-3 arm: clk: configure pcie ext osc clk
When the external oscillator is used as pcie ref clk.
the below configurations should done.
- set the lvds_clk1 as input
- set the source of the pll6_bypass to be lvds_clk1
- set the pll6 to be bypass mode.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit c45c230b7f488dcf18b715129852d27c24c849e6)
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index dbdddeea324e..ad0897ac5832 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -869,8 +869,21 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); /* All existing boards with PCIe use LVDS1 */ - if (IS_ENABLED(CONFIG_PCI_IMX6)) + if (IS_ENABLED(CONFIG_PCI_IMX6)) { imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); + np = of_find_compatible_node(NULL, NULL, "snps,dw-pcie"); + /* external oscillator is used or not. */ + if (of_property_read_u32(np, "ext_osc", &val) < 0) + val = 0; + /* + * imx6qp sabresd revb board has the external osc used by pcie + * - pll6 should be set bypass mode later in driver. + * - lvds_clk1 should be selected as pll6 bypass src, set here. + */ + if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_2_0 + && (val == 1)) + imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS_SRC], clk[IMX6QDL_CLK_LVDS1_IN]); + } /* * Enable clocks only after both parent and rate are all initialized |