MLK-19186: mtd: fsl-flexspi: enable flexspi octal ddr read for QXP

Enabled the FlexSPI Octal DDR read for QXP, since all parameters for
this mode cannot be read from SFDP table, set the related parameters in
spi_nor_init_params.

Signed-off-by: Han Xu <han.xu@nxp.com>

3 files changed, 20 insertions, 15 deletions

diff --git a/drivers/mtd/spi-nor/fsl-flexspi.c b/drivers/mtd/spi-nor/fsl-flexspi.c
index 9b114cb54c3e..1deb0e551530 100644
--- a/drivers/mtd/spi-nor/fsl-flexspi.c
+++ b/drivers/mtd/spi-nor/fsl-flexspi.c
@@ -525,7 +525,7 @@ static void fsl_flexspi_init_lut(struct fsl_flexspi *flex)
 	dm = nor->read_dummy;
 
 	/* Normal Read */
-	if (op == SPINOR_OP_READ) {
+	if (op == SPINOR_OP_READ || op == 0) {
 		writel(LUT0(CMD, PAD1, op) |
 		       LUT1(ADDR, PAD1, addrlen),
 		       base + FLEXSPI_LUT(lut_base));
@@ -533,9 +533,9 @@ static void fsl_flexspi_init_lut(struct fsl_flexspi *flex)
 		writel(LUT0(FSL_READ, PAD1, 0),
 		       base + FLEXSPI_LUT(lut_base + 1));
 	/* Octal DDR Read */
-	} else if (op == SPINOR_OP_READ_1_1_8_D) {
+	} else if (op == SPINOR_OP_READ_1_8_8_DTR_4B) {
 		writel(LUT0(CMD, PAD1, op) |
-		       LUT1(ADDR_DDR, PAD8, addrlen),
+		       LUT1(ADDR_DDR, PAD1, addrlen),
 		       base + FLEXSPI_LUT(lut_base));
 
 		writel(LUT0(DUMMY_DDR, PAD8, dm * 2)
@@ -551,7 +551,7 @@ static void fsl_flexspi_init_lut(struct fsl_flexspi *flex)
 		       LUT1(FSL_READ, PAD4, 0),
 		       base + FLEXSPI_LUT(lut_base + 1));
 	/* DDR Quad I/O Read 	 */
-	} else if (op == SPINOR_OP_READ_1_4_4_D || op == SPINOR_OP_READ_1_4_4_D_4B) {
+	} else if (op == SPINOR_OP_READ_1_4_4_DTR || op == SPINOR_OP_READ_1_4_4_DTR_4B) {
 		/* read mode : 1-4-4, such as Spansion s25fl128s. */
 		writel(LUT0(CMD_DDR, PAD1, op) |
 		       LUT1(ADDR_DDR, PAD4, addrlen),
@@ -565,7 +565,7 @@ static void fsl_flexspi_init_lut(struct fsl_flexspi *flex)
 		       LUT1(JMP_ON_CS, PAD1, 0),
 		       base + FLEXSPI_LUT(lut_base + 2));
 	/* DDR Quad Fast Read 	 */
-	} else if (op == SPINOR_OP_READ_1_1_4_D) {
+	} else if (op == SPINOR_OP_READ_1_1_4_DTR) {
 		/* read mode : 1-1-4, such as Micron N25Q256A. */
 		writel(LUT0(CMD, PAD1, op) |
 		       LUT1(ADDR_DDR, PAD1, addrlen),
@@ -648,10 +648,10 @@ static int fsl_flexspi_get_seqid(struct fsl_flexspi *flex, u8 cmd)
 {
 
 	switch (cmd) {
-	case SPINOR_OP_READ_1_1_4_D:
-	case SPINOR_OP_READ_1_1_8_D:
-	case SPINOR_OP_READ_1_4_4_D:
-	case SPINOR_OP_READ_1_4_4_D_4B:
+	case SPINOR_OP_READ_1_1_4_DTR:
+	case SPINOR_OP_READ_1_8_8_DTR_4B:
+	case SPINOR_OP_READ_1_4_4_DTR:
+	case SPINOR_OP_READ_1_4_4_DTR_4B:
 	case SPINOR_OP_READ_1_1_4_4B:
 	case SPINOR_OP_READ_1_1_4:
 	case SPINOR_OP_READ_4B:
@@ -1314,7 +1314,7 @@ static int fsl_flexspi_probe(struct platform_device *pdev)
 					&dummy);
 		if (!ret && dummy > 0)
 			hwcaps.mask |= fsl_flexspi_quad_only(flex) ?
-				    SNOR_HWCAPS_READ_1_1_4 :SNOR_HWCAPS_READ_1_8_8;
+				    SNOR_HWCAPS_READ : SNOR_HWCAPS_READ_1_8_8_DTR;
 		else
 			hwcaps.mask |= SNOR_HWCAPS_READ;
 
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8fa307f97dc2..591e091c740d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1065,7 +1065,7 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
 	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
 	{ "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
-	{"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ) },
+	{"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_SKIP_SFDP) },
 
 	/* PMC */
 	{ "pm25lv512",   INFO(0,        0, 32 * 1024,    2, SECT_4K_PMC) },
@@ -2448,6 +2448,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
 					  SNOR_PROTO_1_1_4);
 	}
 
+	if (info->flags & SPI_NOR_OCTAL_READ) {
+		params->hwcaps.mask |= SNOR_HWCAPS_READ_1_8_8_DTR;
+		spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_1_8_8_DTR],
+					  0, 8, SPINOR_OP_READ_1_8_8_DTR_4B,
+					  SNOR_PROTO_1_8_8_DTR);
+	}
+
 	/* Page Program settings. */
 	params->hwcaps.mask |= SNOR_HWCAPS_PP;
 	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 900a5ef24c87..9c9401c7e1a5 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,10 +50,6 @@
 #define SPINOR_OP_READ_1_2_2	0xbb	/* Read data bytes (Dual I/O SPI) */
 #define SPINOR_OP_READ_1_1_4	0x6b	/* Read data bytes (Quad Output SPI) */
 #define SPINOR_OP_READ_1_4_4	0xeb	/* Read data bytes (Quad I/O SPI) */
-#define SPINOR_OP_READ_1_1_4_D  0x6d    /* Read data bytes (DDR Quad SPI) */
-#define SPINOR_OP_READ_1_4_4_D  0xed    /* Read data bytes (DDR Quad SPI) */
-#define SPINOR_OP_READ_1_1_8_D	0x9d	/* Read data bytes (Octal Output SPI) */
-#define SPINOR_OP_READ_1_8_8_D	0xfd	/* Read data bytes (DDR Octal I/O SPI) */
 #define SPINOR_OP_PP		0x02	/* Page program (up to 256 bytes) */
 #define SPINOR_OP_PP_1_1_4	0x32	/* Quad page program */
 #define SPINOR_OP_PP_1_4_4	0x38	/* Quad page program */
@@ -85,11 +81,13 @@
 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
 #define SPINOR_OP_READ_1_1_1_DTR	0x0d
 #define SPINOR_OP_READ_1_2_2_DTR	0xbd
+#define SPINOR_OP_READ_1_1_4_DTR	0x6d
 #define SPINOR_OP_READ_1_4_4_DTR	0xed
 
 #define SPINOR_OP_READ_1_1_1_DTR_4B	0x0e
 #define SPINOR_OP_READ_1_2_2_DTR_4B	0xbe
 #define SPINOR_OP_READ_1_4_4_DTR_4B	0xee
+#define SPINOR_OP_READ_1_8_8_DTR_4B	0x9d
 
 /* Used for SST flashes only. */
 #define SPINOR_OP_BP		0x02	/* Byte program */