diff options
| author | Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | 2014-09-25 17:40:14 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2014-10-21 00:12:42 +0900 |
| commit | e540920cf21c2764047b8a6ddaeaa0683624e46e (patch) | |
| tree | 13065a1cdc961163734569049326095de63c908d | |
| parent | 752d3a23d1f68de87e3cb6e0a9652143f1ea0a1a (diff) | |
ARM: dts: add CPU nodes for Exynos4 SoCs
Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
when topology is read from DT") fixed GIC driver to filter cluster ID
from values returned by cpu_logical_map() for SoCs having registers
mapped without per-CPU banking making it is possible to add CPU nodes
for Exynos4 SoCs. In case of Exynos SoCs these CPU nodes are also
required by future changes adding initialization of cpuidle states in
Exynos cpuidle driver through DT.
Tested on Origen board (Exynos4210 SoC) and Trats2 (Exynos4412 SoC).
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/boot/dts/exynos4210.dtsi | 17 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos4212.dtsi | 17 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos4412.dtsi | 29 |
3 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 807bb5bf91fc..bcc9e63c8070 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,23 @@ pinctrl2 = &pinctrl_2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x900>; + }; + + cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x901>; + }; + }; + pmu_system_controller: system-controller@10020000 { clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 3c00e6ec9302..dd0a43ec56da 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,23 @@ / { compatible = "samsung,exynos4212", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <18>; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d8bc059e172f..0f6ec93bb1d8 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,35 @@ / { compatible = "samsung,exynos4412", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + + cpu@A02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA02>; + }; + + cpu@A03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA03>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; }; |