diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2014-04-16 12:09:14 +0530 |
|---|---|---|
| committer | Seema Khowala <seemaj@nvidia.com> | 2014-04-23 14:05:09 -0700 |
| commit | e9a1d6c3fbe677ce2f2fb163766bca859b1b4514 (patch) | |
| tree | 0fe14e27d0c103fcf61f838b6e1762dc75b5457b | |
| parent | 3b0cc2dfdfc555ecbcb1a9d8b69662a3f68bf200 (diff) | |
ARM: tegra: remove T114 specific board files.
Remove T114 specific board files as these are not supported
on build/latest releases.
The platform's board files which are removed are:
- Dalmore
- Pluto
- Macallan
- Pismo
- Roth
Change-Id: Ie532fa8b326cef1aeda98d63215d7ecad26fb1ab
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/396859
Reviewed-by: Automatic_Commit_Validation_User
42 files changed, 0 insertions, 38744 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index ca7a87c1dd1e..994863896811 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -182,44 +182,6 @@ obj-y += panel-p-wuxga-10-1.o obj-y += panel-lgd-wxga-7-0.o obj-y += panel-s-wqxga-10-1.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-memory.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-power.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-sdhci.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-panel.o -obj-${CONFIG_MACH_DALMORE} += board-roth-panel.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-kbc.o -obj-${CONFIG_MACH_DALMORE} += board-dalmore-sensors.o -obj-${CONFIG_MACH_DALMORE} += panel-a-1080p-11-6.o -obj-${CONFIG_MACH_DALMORE} += panel-s-wqxga-10-1.o - -obj-${CONFIG_MACH_PISMO} += board-pismo.o -obj-${CONFIG_MACH_PISMO} += board-pismo-memory.o -obj-${CONFIG_MACH_PISMO} += board-pismo-power.o -obj-${CONFIG_MACH_PISMO} += board-pismo-sdhci.o -obj-${CONFIG_MACH_PISMO} += board-pismo-panel.o -obj-${CONFIG_MACH_PISMO} += board-pismo-sensors.o - -obj-${CONFIG_MACH_MACALLAN} += board-macallan.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-memory.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-power.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-sdhci.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-panel.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-kbc.o -obj-${CONFIG_MACH_MACALLAN} += board-macallan-sensors.o - - -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-memory.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-power.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-sdhci.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-panel.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-kbc.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += board-pluto-sensors.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += panel-l-720p-5.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += panel-j-720p-4-7.o -obj-${CONFIG_MACH_TEGRA_PLUTO} += panel-s-1080p-5.o - obj-${CONFIG_MACH_ARDBEG} += board-ardbeg.o obj-${CONFIG_MACH_ARDBEG} += board-ardbeg-sdhci.o obj-${CONFIG_MACH_ARDBEG} += board-ardbeg-sensors.o @@ -288,13 +250,3 @@ obj-$(CONFIG_TEGRA_BBC_THERMAL) += tegra_bbc_thermal.o obj-${CONFIG_TEGRA_ISOMGR} += isomgr.o obj-${CONFIG_TEGRA_NVDUMPER} += nvdumper.o - -obj-${CONFIG_MACH_ROTH} += board-roth.o -obj-${CONFIG_MACH_ROTH} += board-roth-memory.o -obj-${CONFIG_MACH_ROTH} += board-roth-power.o -obj-${CONFIG_MACH_ROTH} += board-roth-sdhci.o -obj-${CONFIG_MACH_ROTH} += board-roth-panel.o -obj-${CONFIG_MACH_ROTH} += board-roth-kbc.o -obj-${CONFIG_MACH_ROTH} += board-roth-sensors.o -obj-${CONFIG_MACH_ROTH} += board-roth-fan.o -obj-${CONFIG_MACH_ROTH} += board-roth-leds.o diff --git a/arch/arm/mach-tegra/board-dalmore-kbc.c b/arch/arm/mach-tegra/board-dalmore-kbc.c deleted file mode 100644 index b9c9ea42b6c7..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-kbc.c +++ /dev/null @@ -1,209 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore-kbc.c - * Keys configuration for Nvidia tegra3 dalmore platform. - * - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/input/tegra_kbc.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/mfd/palmas.h> - -#include "tegra-board-id.h" -#include "board.h" -#include "board-dalmore.h" -#include "devices.h" -#include "iomap.h" -#include "wakeups-t11x.h" - -#define DALMORE_ROW_COUNT 3 -#define DALMORE_COL_COUNT 3 - -static int dalmore_wakeup_key(void) -{ - int wakeup_key; - u64 status = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS) - | (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE) - + PMC_WAKE2_STATUS) << 32; - - if (status & (1ULL << TEGRA_WAKE_GPIO_PQ0)) - wakeup_key = KEY_POWER; - else if (status & (1ULL << TEGRA_WAKE_GPIO_PS0)) - wakeup_key = SW_LID; - else - wakeup_key = KEY_RESERVED; - - return wakeup_key; -} - -static const u32 kbd_keymap[] = { - KEY(0, 0, KEY_POWER), - KEY(0, 1, KEY_HOME), - - KEY(1, 0, KEY_RESERVED), - KEY(1, 1, KEY_VOLUMEDOWN), - - KEY(2, 0, KEY_CAMERA), - KEY(2, 1, KEY_VOLUMEUP), - KEY(2, 2, KEY_2), -}; - -static const struct matrix_keymap_data keymap_data = { - .keymap = kbd_keymap, - .keymap_size = ARRAY_SIZE(kbd_keymap), -}; - -static struct tegra_kbc_wake_key dalmore_wake_cfg[] = { - [0] = { - .row = 0, - .col = 0, - }, -}; - -static struct tegra_kbc_platform_data dalmore_kbc_platform_data = { - .debounce_cnt = 20 * 32, /* 20 ms debaunce time */ - .repeat_cnt = 1, - .scan_count = 30, - .wakeup = true, - .keymap_data = &keymap_data, - .wake_cnt = 1, - .wake_cfg = &dalmore_wake_cfg[0], - .wakeup_key = KEY_POWER, -#ifdef CONFIG_ANDROID - .disable_ev_rep = true, -#endif -}; - -#define GPIO_KCODE(_kcode, _kev, _gpio, _irq, _iswake, _deb) \ - { \ - .code = _kcode, \ - .gpio = TEGRA_GPIO_##_gpio, \ - .irq = _irq, \ - .active_low = 1, \ - .desc = #_kcode, \ - .type = _kev, \ - .wakeup = _iswake, \ - .debounce_interval = _deb, \ - } - -#define GPIO_KEY(_id, _gpio, _iswake) \ - GPIO_KCODE(_id, EV_KEY, _gpio, 0, _iswake, 10) - -#define GPIO_IKEY(_id, _irq, _iswake, _deb) \ - GPIO_KCODE(_id, EV_KEY, INVALID, _irq, _iswake, _deb) - -static struct gpio_keys_button dalmore_int_keys[] = { - [0] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + - MAX77663_IRQ_ONOFF_EN0_FALLING, 0, 100), - [1] = GPIO_IKEY(KEY_POWER, MAX77663_IRQ_BASE + - MAX77663_IRQ_ONOFF_EN0_1SEC, 0, 3000), -}; - -static struct gpio_keys_button dalmore_e1611_1001_keys[] = { - [0] = GPIO_KEY(KEY_POWER, PQ0, 1), - [1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0), - [2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0), - [3] = GPIO_KEY(KEY_HOME, PI5, 0), - [4] = GPIO_KCODE(SW_ROTATE_LOCK, EV_SW, PQ1, 0, 0, 10), -}; - -static struct gpio_keys_button dalmore_e1611_1000_keys[] = { - [0] = GPIO_KCODE(SW_ROTATE_LOCK, EV_SW, PI5, 0, 0, 10), -}; - -static struct gpio_keys_platform_data dalmore_int_keys_pdata = { - .buttons = dalmore_int_keys, - .nbuttons = ARRAY_SIZE(dalmore_int_keys), -}; - -static struct gpio_keys_platform_data dalmore_e1611_1001_keys_pdata = { - .buttons = dalmore_e1611_1001_keys, - .nbuttons = ARRAY_SIZE(dalmore_e1611_1001_keys), - .wakeup_key = dalmore_wakeup_key, -}; - -static struct gpio_keys_platform_data dalmore_e1611_1000_keys_pdata = { - .buttons = dalmore_e1611_1000_keys, - .nbuttons = ARRAY_SIZE(dalmore_e1611_1000_keys), -}; - -static struct platform_device dalmore_gpio_keys_device = { - .name = "gpio-keys", - .id = 0, - .dev = { - .platform_data = &dalmore_int_keys_pdata, - }, -}; - -static void __init dalmore_register_kbc(void) -{ - struct tegra_kbc_platform_data *data = &dalmore_kbc_platform_data; - int i; - - tegra_kbc_device.dev.platform_data = &dalmore_kbc_platform_data; - - for (i = 0; i < DALMORE_ROW_COUNT; i++) { - data->pin_cfg[i].num = i; - data->pin_cfg[i].type = PIN_CFG_ROW; - } - for (i = 0; i < DALMORE_COL_COUNT; i++) { - data->pin_cfg[i + KBC_PIN_GPIO_11].num = i; - data->pin_cfg[i + KBC_PIN_GPIO_11].type = PIN_CFG_COL; - } - - platform_device_register(&tegra_kbc_device); -} - -int __init dalmore_kbc_init(void) -{ - struct board_info board_info; - - tegra_get_board_info(&board_info); - pr_info("Boardid:SKU = 0x%04x:0x%04x\n", board_info.board_id, board_info.sku); - - if (board_info.board_id == BOARD_E1613) { - dalmore_register_kbc(); - goto gpio_keys; - } - - if ((board_info.board_id == BOARD_E1611) && (board_info.sku == 1000)) { - dalmore_register_kbc(); - dalmore_gpio_keys_device.dev.platform_data = - &dalmore_e1611_1000_keys_pdata; - } else { - int ret; - - ret = gpio_request(TEGRA_GPIO_PR0, "row0"); - if (ret < 0) { - pr_err("gpio_request for PR0 failed: %d\n", ret); - } else { - gpio_direction_output(TEGRA_GPIO_PR0, 0); - } - - dalmore_gpio_keys_device.dev.platform_data = - &dalmore_e1611_1001_keys_pdata; - } - -gpio_keys: - platform_device_register(&dalmore_gpio_keys_device); - return 0; -} diff --git a/arch/arm/mach-tegra/board-dalmore-memory.c b/arch/arm/mach-tegra/board-dalmore-memory.c deleted file mode 100644 index 3fe210e28104..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-memory.c +++ /dev/null @@ -1,8730 +0,0 @@ -/* - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include "board.h" -#include "board-dalmore.h" - -#include "tegra-board-id.h" -#include "tegra11_emc.h" -#include "devices.h" -#include "common.h" - -static struct tegra11_emc_table e1611_h5tc4g63afr_rda_T40S_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000e, /* EMC_RC */ - 0x00000050, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000009, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x00000009, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004d, /* EMC_AR2PDEN */ - 0x0000000e, /* EMC_RW2PDEN */ - 0x00000055, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000d, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000986, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ - 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x5320000e, /* EMC_CFG */ - 0x80000321, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00018000, /* EMC_DLL_XFORM_DQS4 */ - 0x00018000, /* EMC_DLL_XFORM_DQS5 */ - 0x00018000, /* EMC_DLL_XFORM_DQS6 */ - 0x00018000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00018000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000005, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS1 */ - 0x00018000, /* EMC_DLL_XFORM_DQS2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ1 */ - 0x00020001, /* EMC_DLL_XFORM_DQ2 */ - 0x00020001, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00018000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000005, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS1 */ - 0x00018000, /* EMC_DLL_XFORM_DQS2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ1 */ - 0x00020001, /* EMC_DLL_XFORM_DQ2 */ - 0x00020001, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 528000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000088, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000010, /* EMC_RAS */ - 0x00000006, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000006, /* EMC_RD_RCD */ - 0x00000006, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000009, /* EMC_IBDLY */ - 0x00090007, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ - 0x00000fd8, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000b, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000085, /* EMC_AR2PDEN */ - 0x00000012, /* EMC_RW2PDEN */ - 0x0000008f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000016, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000005, /* EMC_TCLKSTABLE */ - 0x00000006, /* EMC_TCLKSTOP */ - 0x00001019, /* EMC_TREFBW */ - 0x00000008, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0120091, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0139000f, /* EMC_MRS_WAIT_CNT */ - 0x0139000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80002066, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0f000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000010e, /* MC_PTSA_GRANT_DECREMENT */ - 0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73100004, /* EMC_CFG */ - 0x80000941, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001d, /* EMC_RC */ - 0x000000a1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000014, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x00000010, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x0000000a, /* EMC_IBDLY */ - 0x000c000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x000012c4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000d, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000009c, /* EMC_AR2PDEN */ - 0x00000015, /* EMC_RW2PDEN */ - 0x000000a9, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000019, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000006, /* EMC_TCLKSTABLE */ - 0x00000007, /* EMC_TCLKSTOP */ - 0x00001305, /* EMC_TREFBW */ - 0x00000009, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf00d0191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS4 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS5 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS6 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR1 */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR1 */ - 0x007f400e, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00b, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000b61, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200010, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000024, /* EMC_RC */ - 0x000000cd, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000019, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x00000009, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x000d000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000017e4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000012, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000c6, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x000000d6, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x00001825, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f508, /* EMC_XM2COMPPADCTRL */ - 0x07077704, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80003018, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73000000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200218, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1611_h5tc4g63afr_rda_T40T_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000e, /* EMC_RC */ - 0x00000050, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000009, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x00000009, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004d, /* EMC_AR2PDEN */ - 0x0000000e, /* EMC_RW2PDEN */ - 0x00000055, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000d, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000986, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ - 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x5320000e, /* EMC_CFG */ - 0x80000321, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00028000, /* EMC_DLL_XFORM_DQS4 */ - 0x00028000, /* EMC_DLL_XFORM_DQS5 */ - 0x00028000, /* EMC_DLL_XFORM_DQS6 */ - 0x00028000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00028000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS1 */ - 0x00028000, /* EMC_DLL_XFORM_DQS2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00028000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS1 */ - 0x00028000, /* EMC_DLL_XFORM_DQS2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001d, /* EMC_RC */ - 0x000000a1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000014, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x00000010, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x000c000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x000012c4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000d, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000009c, /* EMC_AR2PDEN */ - 0x00000015, /* EMC_RW2PDEN */ - 0x000000a9, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000019, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000006, /* EMC_TCLKSTABLE */ - 0x00000007, /* EMC_TCLKSTOP */ - 0x00001305, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf00d0191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS4 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS5 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS6 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000b61, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200010, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000024, /* EMC_RC */ - 0x000000cd, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000019, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x00000009, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x000d000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000017e4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000012, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000c6, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x000000d6, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x00001825, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008, /* EMC_DLL_XFORM_DQS4 */ - 0x00000008, /* EMC_DLL_XFORM_DQS5 */ - 0x00000008, /* EMC_DLL_XFORM_DQS6 */ - 0x00000008, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f508, /* EMC_XM2COMPPADCTRL */ - 0x07076604, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80003018, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200418, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 924000, /* SDRAM frequency */ - 1170, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000002b, /* EMC_RC */ - 0x000000f1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001e, /* EMC_RAS */ - 0x0000000b, /* EMC_RP */ - 0x00000009, /* EMC_R2W */ - 0x0000000f, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x00000018, /* EMC_W2P */ - 0x0000000b, /* EMC_RD_RCD */ - 0x0000000b, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000007, /* EMC_WDV */ - 0x00000007, /* EMC_WDV_MASK */ - 0x0000000d, /* EMC_IBDLY */ - 0x000f000c, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x0000000a, /* EMC_QRST */ - 0x00000016, /* EMC_RDV_MASK */ - 0x00001c39, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000070e, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000015, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000e8, /* EMC_AR2PDEN */ - 0x0000001d, /* EMC_RW2PDEN */ - 0x000000fd, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000006, /* EMC_TCKE */ - 0x00000006, /* EMC_TCKESR */ - 0x00000006, /* EMC_TPD */ - 0x00000026, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000009, /* EMC_TCLKSTABLE */ - 0x0000000a, /* EMC_TCLKSTOP */ - 0x00001c7a, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0030191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000007, /* EMC_DLL_XFORM_DQS4 */ - 0x00000007, /* EMC_DLL_XFORM_DQS5 */ - 0x00000007, /* EMC_DLL_XFORM_DQS6 */ - 0x00000007, /* EMC_DLL_XFORM_DQS7 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE4 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE5 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE6 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f508, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000801, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000128, /* EMC_ZCAL_WAIT_CNT */ - 0x00cb000f, /* EMC_MRS_WAIT_CNT */ - 0x00cb000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000004, /* EMC_CTT */ - 0x00000004, /* EMC_CTT_DURATION */ - 0x8000388a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0000000e, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000016, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ - 0x09060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x001b1016, /* MC_EMEM_ARB_DA_COVERS */ - 0x734f2b17, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000c, /* EMC_QUSE */ - 0x0000000a, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000007, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00004007, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000f0f, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS1 */ - 0x00000007, /* EMC_DLL_XFORM_DQS2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS3 */ - 0x00004007, /* EMC_DLL_XFORM_DQ1 */ - 0x00004007, /* EMC_DLL_XFORM_DQ2 */ - 0x00004007, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE1 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE2 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000c, /* EMC_QUSE */ - 0x0000000a, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000007, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00004007, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS1 */ - 0x00000007, /* EMC_DLL_XFORM_DQS2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS3 */ - 0x00004007, /* EMC_DLL_XFORM_DQ1 */ - 0x00004007, /* EMC_DLL_XFORM_DQ2 */ - 0x00004007, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE1 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE2 */ - 0x0002800c, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000001d9, /* MC_PTSA_GRANT_DECREMENT */ - 0x00070007, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00070008, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x000d000a, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000000d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x000d000d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x005d002c, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x005d005d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000004d, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000000, /* EMC_CFG */ - 0x80000115, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200420, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1180, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_T40S_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000e, /* EMC_RC */ - 0x00000050, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000009, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x00000009, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004d, /* EMC_AR2PDEN */ - 0x0000000e, /* EMC_RW2PDEN */ - 0x00000055, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000d, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000986, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ - 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x5320000e, /* EMC_CFG */ - 0x80000321, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00080006, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00018000, /* EMC_DLL_XFORM_DQS4 */ - 0x00018000, /* EMC_DLL_XFORM_DQS5 */ - 0x00018000, /* EMC_DLL_XFORM_DQS6 */ - 0x00018000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00018000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000005, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS1 */ - 0x00018000, /* EMC_DLL_XFORM_DQS2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ1 */ - 0x00020001, /* EMC_DLL_XFORM_DQ2 */ - 0x00020001, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00018000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000005, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000005, /* EMC_DLL_XFORM_ADDR2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS1 */ - 0x00018000, /* EMC_DLL_XFORM_DQS2 */ - 0x00018000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020001, /* EMC_DLL_XFORM_DQ1 */ - 0x00020001, /* EMC_DLL_XFORM_DQ2 */ - 0x00020001, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 528000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000088, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000010, /* EMC_RAS */ - 0x00000006, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000006, /* EMC_RD_RCD */ - 0x00000006, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000009, /* EMC_IBDLY */ - 0x00090007, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ - 0x00000fd8, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000003f6, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000b, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000085, /* EMC_AR2PDEN */ - 0x00000012, /* EMC_RW2PDEN */ - 0x0000008f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000016, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000005, /* EMC_TCLKSTABLE */ - 0x00000006, /* EMC_TCLKSTOP */ - 0x00001019, /* EMC_TREFBW */ - 0x00000008, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0120091, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0139000f, /* EMC_MRS_WAIT_CNT */ - 0x0139000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80002066, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0f000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000010e, /* MC_PTSA_GRANT_DECREMENT */ - 0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73100004, /* EMC_CFG */ - 0x80000941, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001d, /* EMC_RC */ - 0x000000a1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000014, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x00000010, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x0000000a, /* EMC_IBDLY */ - 0x000c000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x000012c4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004b1, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000d, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000009c, /* EMC_AR2PDEN */ - 0x00000015, /* EMC_RW2PDEN */ - 0x000000a9, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000019, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000006, /* EMC_TCLKSTABLE */ - 0x00000007, /* EMC_TCLKSTOP */ - 0x00001305, /* EMC_TREFBW */ - 0x00000009, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf00d0191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007f800b, /* EMC_DLL_XFORM_DQS4 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS5 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS6 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000261a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007f800b, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS1 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS2 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007f800b, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS1 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS2 */ - 0x007f800b, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000b61, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200010, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000024, /* EMC_RC */ - 0x000000cd, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000019, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x00000009, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x000d000a, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000017e4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005f9, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000012, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000c6, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x000000d6, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x00001825, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x80000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008, /* EMC_DLL_XFORM_DQS4 */ - 0x00000008, /* EMC_DLL_XFORM_DQS5 */ - 0x00000008, /* EMC_DLL_XFORM_DQS6 */ - 0x00000008, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f508, /* EMC_XM2COMPPADCTRL */ - 0x07076604, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80003018, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR1 */ - 0x007fc00d, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73000000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200218, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x07070707, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000404, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ1 */ - 0x00018000, /* EMC_DLL_XFORM_DQ2 */ - 0x00018000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ1 */ - 0x00018000, /* EMC_DLL_XFORM_DQ2 */ - 0x00018000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 480000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000017, /* EMC_RC */ - 0x00000082, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000010, /* EMC_RAS */ - 0x00000005, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000005, /* EMC_RD_RCD */ - 0x00000005, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000f23, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000003c8, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000b, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000007f, /* EMC_AR2PDEN */ - 0x00000012, /* EMC_RW2PDEN */ - 0x00000089, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000015, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000005, /* EMC_TCLKSTABLE */ - 0x00000006, /* EMC_TCLKSTOP */ - 0x00000f64, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0140091, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077704, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x013f000c, /* EMC_MRS_WAIT_CNT */ - 0x013f000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000808, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001f05, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x09000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000f080c, /* MC_EMEM_ARB_DA_COVERS */ - 0x7448170d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000f6, /* MC_PTSA_GRANT_DECREMENT */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000f0010, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00120014, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001a0014, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001a, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001a001a, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00b40055, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00b400b4, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73200006, /* EMC_CFG */ - 0x80000931, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1613_h9ccnnn8jtmlar_ntm_table[] = { - { - 0x40, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000c, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000008, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000003, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000001d, /* EMC_TXSR */ - 0x0000001d, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000b, /* EMC_TFAW */ - 0x00000005, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000351, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000000, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00014286, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00038000, /* EMC_DLL_XFORM_DQS4 */ - 0x00038000, /* EMC_DLL_XFORM_DQS5 */ - 0x00038000, /* EMC_DLL_XFORM_DQS6 */ - 0x00038000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000004a, /* EMC_ZCAL_WAIT_CNT */ - 0x00100010, /* EMC_MRS_WAIT_CNT */ - 0x00100010, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */ - 0x71e40a07, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00038000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00030000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00030000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00038000, /* EMC_DLL_XFORM_DQS1 */ - 0x00038000, /* EMC_DLL_XFORM_DQS2 */ - 0x00038000, /* EMC_DLL_XFORM_DQS3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ1 */ - 0x00034000, /* EMC_DLL_XFORM_DQ2 */ - 0x00034000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00038000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00030000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00030000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00038000, /* EMC_DLL_XFORM_DQS1 */ - 0x00038000, /* EMC_DLL_XFORM_DQS2 */ - 0x00038000, /* EMC_DLL_XFORM_DQS3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ1 */ - 0x00034000, /* EMC_DLL_XFORM_DQ2 */ - 0x00034000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - }, - { - 0x40, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000011, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x0000000b, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000008, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000005, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000003, /* EMC_PDEX2RD */ - 0x00000007, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000003a, /* EMC_TXSR */ - 0x0000003a, /* EMC_TXSRDLL */ - 0x00000007, /* EMC_TCKE */ - 0x00000007, /* EMC_TCKESR */ - 0x00000007, /* EMC_TPD */ - 0x00000015, /* EMC_TFAW */ - 0x00000009, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000006a2, /* EMC_TREFBW */ - 0x00000008, /* EMC_QUSE_EXTRA */ - 0x80000722, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x00580088, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00020000, /* EMC_DLL_XFORM_DQS4 */ - 0x00020000, /* EMC_DLL_XFORM_DQS5 */ - 0x00020000, /* EMC_DLL_XFORM_DQS6 */ - 0x00020000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003023d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000093, /* EMC_ZCAL_WAIT_CNT */ - 0x00120012, /* EMC_MRS_WAIT_CNT */ - 0x00120012, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06070102, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c7130d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10606, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10606, /* EMC_AUTO_CAL_CONFIG */ - 0x00010000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00010000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0001c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200006, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x000100c3, /* Mode Register 1 */ - 0x00020006, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - }, - { - 0x40, /* Rev 4.0.3 */ - 600000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000023, /* EMC_RC */ - 0x0000004d, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000019, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x0000000b, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x0000000f, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000005, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000a, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000006, /* EMC_QRST */ - 0x00000015, /* EMC_RDV_MASK */ - 0x000008e4, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000239, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000004, /* EMC_PDEX2RD */ - 0x0000000a, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000013, /* EMC_RW2PDEN */ - 0x00000054, /* EMC_TXSR */ - 0x00000054, /* EMC_TXSRDLL */ - 0x00000009, /* EMC_TCKE */ - 0x00000009, /* EMC_TCKESR */ - 0x00000009, /* EMC_TPD */ - 0x0000001e, /* EMC_TFAW */ - 0x0000000d, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000009c0, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0xf00e0199, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000c, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc005, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x000000d8, /* EMC_ZCAL_WAIT_CNT */ - 0x00130013, /* EMC_MRS_WAIT_CNT */ - 0x00130013, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800012d7, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07070103, /* MC_EMEM_ARB_DA_TURNS */ - 0x00140d12, /* MC_EMEM_ARB_DA_COVERS */ - 0x71a91b13, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000d, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000c, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000f, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000013, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000e, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f11f1f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000010, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000e, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000e, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000d, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000c, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000f, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000013, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f11f1f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000010, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000133, /* MC_PTSA_GRANT_DECREMENT */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000c000d, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e0010, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00150010, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00150015, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00900044, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00900090, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000003a, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xd3200000, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x000100e3, /* Mode Register 1 */ - 0x00020007, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - }, -}; - -static struct tegra11_emc_pdata e1613_h9ccnnn8jtmlar_ntm_pdata = { - .description = "e1613_h9ccnnn8jtmlar_ntm", - .tables = e1613_h9ccnnn8jtmlar_ntm_table, - .num_tables = ARRAY_SIZE(e1613_h9ccnnn8jtmlar_ntm_table), -}; - -static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_pdata = { - .description = "e1611_h5tc4g63mfr_pba", - .tables = e1611_h5tc4g63mfr_pba_table, - .num_tables = ARRAY_SIZE(e1611_h5tc4g63mfr_pba_table), -}; - -static struct tegra11_emc_pdata e1611_h5tc4g63afr_rda_T40T_pdata = { - .description = "e1611_h5tc4g63afr_rda_T40T", - .tables = e1611_h5tc4g63afr_rda_T40T_table, - .num_tables = ARRAY_SIZE(e1611_h5tc4g63afr_rda_T40T_table), -}; - -static struct tegra11_emc_pdata e1611_h5tc4g63afr_rda_T40S_pdata = { - .description = "e1611_h5tc4g63afr_rda_T40S", - .tables = e1611_h5tc4g63afr_rda_T40S_table, - .num_tables = ARRAY_SIZE(e1611_h5tc4g63afr_rda_T40S_table), -}; - -static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_T40S_pdata = { - .description = "e1611_h5tc4g63mfr_pba_T40S", - .tables = e1611_h5tc4g63mfr_pba_T40S_table, - .num_tables = ARRAY_SIZE(e1611_h5tc4g63mfr_pba_T40S_table), -}; - -static struct tegra11_emc_pdata *dalmore_get_emc_data(void) -{ - struct board_info board_info; - u32 tegra_sku_id; - - tegra_sku_id = tegra_get_sku_id(); - tegra_get_board_info(&board_info); - - /* load T40T/T40X Table */ - if (board_info.board_id == BOARD_E1611 && - (tegra_sku_id == 0x3 || tegra_sku_id == 0x4)) - return &e1611_h5tc4g63afr_rda_T40T_pdata; - /* load T40S Table */ - else if (board_info.board_id == BOARD_E1611 && - (tegra_sku_id == 0x5 || tegra_sku_id == 0x20)) { - if (tegra_get_memory_type()) - return &e1611_h5tc4g63afr_rda_T40S_pdata; - else - return &e1611_h5tc4g63mfr_pba_T40S_pdata; - } - else if (board_info.board_id == BOARD_E1611 || - board_info.board_id == BOARD_P2454) - return &e1611_h5tc4g63mfr_pba_pdata; - else - return &e1613_h9ccnnn8jtmlar_ntm_pdata; -} - -int __init dalmore_emc_init(void) -{ - tegra_emc_device.dev.platform_data = dalmore_get_emc_data(); - platform_device_register(&tegra_emc_device); - tegra11_emc_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-dalmore-panel.c b/arch/arm/mach-tegra/board-dalmore-panel.c deleted file mode 100644 index a90f9d9810dd..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-panel.c +++ /dev/null @@ -1,521 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore-panel.c - * - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ -#include <linux/ioport.h> -#include <linux/fb.h> -#include <linux/nvmap.h> -#include <linux/nvhost.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/of.h> - -#include <mach/irqs.h> -#include <mach/dc.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> - -#include "board.h" -#include "devices.h" -#include "gpio-names.h" -#include "board-panel.h" -#include "common.h" -#include "iomap.h" -#include "tegra11_host1x_devices.h" - -#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH3 -#define DSI_PANEL_BL_PWM_GPIO TEGRA_GPIO_PH1 - -struct platform_device * __init dalmore_host1x_init(void) -{ - struct platform_device *pdev = NULL; - -#ifdef CONFIG_TEGRA_GRHOST - if (!of_have_populated_dt()) - pdev = tegra11_register_host1x_devices(); - else - pdev = to_platform_device(bus_find_device_by_name( - &platform_bus_type, NULL, "host1x")); -#endif - return pdev; -} - -/* HDMI Hotplug detection pin */ -#define dalmore_hdmi_hpd TEGRA_GPIO_PN7 - -static struct regulator *dalmore_hdmi_reg; -static struct regulator *dalmore_hdmi_pll; -static struct regulator *dalmore_hdmi_vddio; - -static struct resource dalmore_disp1_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_GENERAL, - .end = INT_DISPLAY_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY_BASE, - .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by dalmore_panel_init() */ - .end = 0, /* Filled in by dalmore_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsia_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsib_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "dsi_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "mipi_cal", - .start = TEGRA_MIPI_CAL_BASE, - .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource dalmore_disp2_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_B_GENERAL, - .end = INT_DISPLAY_B_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY2_BASE, - .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by dalmore_panel_init() */ - .end = 0, /* Filled in by dalmore_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "hdmi_regs", - .start = TEGRA_HDMI_BASE, - .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - - -static struct tegra_dc_sd_settings sd_settings; - -static struct tegra_dc_out dalmore_disp1_out = { - .type = TEGRA_DC_OUT_DSI, - .sd_settings = &sd_settings, -}; - -static int dalmore_hdmi_enable(struct device *dev) -{ - int ret; - if (!dalmore_hdmi_reg) { - dalmore_hdmi_reg = regulator_get(dev, "avdd_hdmi"); - if (IS_ERR(dalmore_hdmi_reg)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); - dalmore_hdmi_reg = NULL; - return PTR_ERR(dalmore_hdmi_reg); - } - } - ret = regulator_enable(dalmore_hdmi_reg); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); - return ret; - } - if (!dalmore_hdmi_pll) { - dalmore_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll"); - if (IS_ERR(dalmore_hdmi_pll)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); - dalmore_hdmi_pll = NULL; - regulator_put(dalmore_hdmi_reg); - dalmore_hdmi_reg = NULL; - return PTR_ERR(dalmore_hdmi_pll); - } - } - ret = regulator_enable(dalmore_hdmi_pll); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); - return ret; - } - return 0; -} - -static int dalmore_hdmi_disable(void) -{ - if (dalmore_hdmi_reg) { - regulator_disable(dalmore_hdmi_reg); - regulator_put(dalmore_hdmi_reg); - dalmore_hdmi_reg = NULL; - } - - if (dalmore_hdmi_pll) { - regulator_disable(dalmore_hdmi_pll); - regulator_put(dalmore_hdmi_pll); - dalmore_hdmi_pll = NULL; - } - - return 0; -} - -static int dalmore_hdmi_postsuspend(void) -{ - if (dalmore_hdmi_vddio) { - regulator_disable(dalmore_hdmi_vddio); - regulator_put(dalmore_hdmi_vddio); - dalmore_hdmi_vddio = NULL; - } - return 0; -} - -static int dalmore_hdmi_hotplug_init(struct device *dev) -{ - int e = 0; - - if (!dalmore_hdmi_vddio) { - dalmore_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0"); - if (WARN_ON(IS_ERR(dalmore_hdmi_vddio))) { - e = PTR_ERR(dalmore_hdmi_vddio); - pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %d\n", - __func__, e); - dalmore_hdmi_vddio = NULL; - } else { - e = regulator_enable(dalmore_hdmi_vddio); - } - } - - return e; -} - -static void dalmore_hdmi_hotplug_report(bool state) -{ - if (state) { - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA, - TEGRA_PUPD_PULL_DOWN); - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL, - TEGRA_PUPD_PULL_DOWN); - } else { - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA, - TEGRA_PUPD_NORMAL); - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL, - TEGRA_PUPD_NORMAL); - } -} - -/* Electrical characteristics for HDMI, all modes must be declared here */ -struct tmds_config dalmore_tmds_config[] = { - { /* 480p : 27 MHz and below */ - .pclk = 27000000, - .pll0 = 0x01003010, - .pll1 = 0x00301b00, - .drive_current = 0x23232323, - .pe_current = 0x00000000, - .peak_current = 0x00000000, - }, - { /* 720p : 74.25MHz modes */ - .pclk = 74250000, - .pll0 = 0x01003110, - .pll1 = 0x00301b00, - .drive_current = 0x25252525, - .pe_current = 0x00000000, - .peak_current = 0x03030303, - }, - { /* 1080p : 148.5MHz modes */ - .pclk = 148500000, - .pll0 = 0x01003310, - .pll1 = 0x00301b00, - .drive_current = 0x27272727, - .pe_current = 0x00000000, - .peak_current = 0x03030303, - }, - { /* 4K : 297MHz modes */ - .pclk = INT_MAX, - .pll0 = 0x01003f10, - .pll1 = 0x00300f00, - .drive_current = 0x303f3f3f, - .pe_current = 0x00000000, - .peak_current = 0x040f0f0f, - }, -}; - -struct tegra_hdmi_out dalmore_hdmi_out = { - .tmds_config = dalmore_tmds_config, - .n_tmds_config = ARRAY_SIZE(dalmore_tmds_config), -}; - -static struct tegra_dc_out dalmore_disp2_out = { - .type = TEGRA_DC_OUT_HDMI, - .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, - .parent_clk = "pll_d2_out0", - - .ddc_bus = 3, - .hotplug_gpio = dalmore_hdmi_hpd, - .hdmi_out = &dalmore_hdmi_out, - - .max_pixclock = KHZ2PICOS(297000), - - .align = TEGRA_DC_ALIGN_MSB, - .order = TEGRA_DC_ORDER_RED_BLUE, - - .enable = dalmore_hdmi_enable, - .disable = dalmore_hdmi_disable, - .postsuspend = dalmore_hdmi_postsuspend, - .hotplug_init = dalmore_hdmi_hotplug_init, - .hotplug_report = dalmore_hdmi_hotplug_report, -}; - -static struct tegra_fb_data dalmore_disp1_fb_data = { - .win = 0, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data dalmore_disp1_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &dalmore_disp1_out, - .fb = &dalmore_disp1_fb_data, - .emc_clk_rate = 204000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct tegra_fb_data dalmore_disp2_fb_data = { - .win = 0, - .xres = 1280, - .yres = 720, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data dalmore_disp2_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &dalmore_disp2_out, - .fb = &dalmore_disp2_fb_data, - .emc_clk_rate = 300000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct platform_device dalmore_disp2_device = { - .name = "tegradc", - .id = 1, - .resource = dalmore_disp2_resources, - .num_resources = ARRAY_SIZE(dalmore_disp2_resources), - .dev = { - .platform_data = &dalmore_disp2_pdata, - }, -}; - -static struct platform_device dalmore_disp1_device = { - .name = "tegradc", - .id = 0, - .resource = dalmore_disp1_resources, - .num_resources = ARRAY_SIZE(dalmore_disp1_resources), - .dev = { - .platform_data = &dalmore_disp1_pdata, - }, -}; - -static struct nvmap_platform_carveout dalmore_carveouts[] = { - [0] = { - .name = "iram", - .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, - .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, - .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, - }, - [1] = { - .name = "generic-0", - .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, - .base = 0, /* Filled in by dalmore_panel_init() */ - .size = 0, /* Filled in by dalmore_panel_init() */ - }, - [2] = { - .name = "vpr", - .usage_mask = NVMAP_HEAP_CARVEOUT_VPR, - .base = 0, /* Filled in by dalmore_panel_init() */ - .size = 0, /* Filled in by dalmore_panel_init() */ - }, -}; - -static struct nvmap_platform_data dalmore_nvmap_data = { - .carveouts = dalmore_carveouts, - .nr_carveouts = ARRAY_SIZE(dalmore_carveouts), -}; -static struct platform_device dalmore_nvmap_device = { - .name = "tegra-nvmap", - .id = -1, - .dev = { - .platform_data = &dalmore_nvmap_data, - }, -}; - -static void dalmore_panel_select(void) -{ - struct tegra_panel *panel = NULL; - struct board_info board; - u8 dsi_instance; - - tegra_get_display_board_info(&board); - - switch (board.board_id) { - case BOARD_E1639: - panel = &dsi_s_wqxga_10_1; - /* FIXME: panel used ganged mode,need to check if - * the dsi_instance is useful in this case - */ - dsi_instance = DSI_INSTANCE_0; - break; - case BOARD_E1631: - panel = &dsi_a_1080p_11_6; - dsi_instance = DSI_INSTANCE_0; - break; - case BOARD_E1627: - /* fall through */ - default: - panel = &dsi_p_wuxga_10_1; - dsi_instance = DSI_INSTANCE_0; - break; - } - if (panel) { - if (panel->init_sd_settings) - panel->init_sd_settings(&sd_settings); - - if (panel->init_dc_out) { - panel->init_dc_out(&dalmore_disp1_out); - dalmore_disp1_out.dsi->dsi_instance = dsi_instance; - dalmore_disp1_out.dsi->dsi_panel_rst_gpio = - DSI_PANEL_RST_GPIO; - dalmore_disp1_out.dsi->dsi_panel_bl_pwm_gpio = - DSI_PANEL_BL_PWM_GPIO; - } - - if (panel->init_fb_data) - panel->init_fb_data(&dalmore_disp1_fb_data); - - if (panel->init_cmu_data) - panel->init_cmu_data(&dalmore_disp1_pdata); - - if (panel->set_disp_device) - panel->set_disp_device(&dalmore_disp1_device); - - tegra_dsi_resources_init(dsi_instance, dalmore_disp1_resources, - ARRAY_SIZE(dalmore_disp1_resources)); - - if (panel->register_bl_dev) - panel->register_bl_dev(); - - if (panel->register_i2c_bridge) - panel->register_i2c_bridge(); - } - -} -int __init dalmore_panel_init(void) -{ - int err = 0; - struct resource __maybe_unused *res; - struct platform_device *phost1x = NULL; - - dalmore_panel_select(); - -#ifdef CONFIG_TEGRA_NVMAP - dalmore_carveouts[1].base = tegra_carveout_start; - dalmore_carveouts[1].size = tegra_carveout_size; - dalmore_carveouts[2].base = tegra_vpr_start; - dalmore_carveouts[2].size = tegra_vpr_size; -#ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT - dalmore_carveouts[1].cma_dev = &tegra_generic_cma_dev; - dalmore_carveouts[1].resize = false; - dalmore_carveouts[2].cma_dev = &tegra_vpr_cma_dev; - dalmore_carveouts[2].resize = true; - dalmore_carveouts[2].cma_chunk_size = SZ_32M; -#endif - - err = platform_device_register(&dalmore_nvmap_device); - if (err) { - pr_err("nvmap device registration failed\n"); - return err; - } -#endif - - phost1x = dalmore_host1x_init(); - if (!phost1x) { - pr_err("host1x devices registration failed\n"); - return -EINVAL; - } - - res = platform_get_resource_byname(&dalmore_disp1_device, - IORESOURCE_MEM, "fbmem"); - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; - - /* Copy the bootloader fb to the fb. */ - if (tegra_bootloader_fb_size) - __tegra_move_framebuffer(&dalmore_nvmap_device, - tegra_fb_start, tegra_bootloader_fb_start, - min(tegra_fb_size, tegra_bootloader_fb_size)); - else - __tegra_clear_framebuffer(&dalmore_nvmap_device, - tegra_fb_start, tegra_fb_size); - - dalmore_disp1_device.dev.parent = &phost1x->dev; - err = platform_device_register(&dalmore_disp1_device); - if (err) { - pr_err("disp1 device registration failed\n"); - return err; - } - - err = tegra_init_hdmi(&dalmore_disp2_device, phost1x); - if (err) - return err; - -#ifdef CONFIG_TEGRA_NVAVP - if (!of_have_populated_dt()) { - nvavp_device.dev.parent = &phost1x->dev; - err = platform_device_register(&nvavp_device); - if (err) { - pr_err("nvavp device registration failed\n"); - return err; - } - } -#endif - return err; -} diff --git a/arch/arm/mach-tegra/board-dalmore-power.c b/arch/arm/mach-tegra/board-dalmore-power.c deleted file mode 100644 index 8bab8e0da739..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-power.c +++ /dev/null @@ -1,1454 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore-power.c - * - * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/pda_power.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/io.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/driver.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/max77663-core.h> -#include <linux/mfd/palmas.h> -#include <linux/mfd/tps65090.h> -#include <linux/regulator/max77663-regulator.h> -#include <linux/regulator/tps51632-regulator.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/regulator/userspace-consumer.h> -#include <linux/pid_thermal_gov.h> -#include <linux/tegra-soc.h> -#include <linux/tegra-pmc.h> - -#include <asm/mach-types.h> -#include <linux/power/sbs-battery.h> - -#include <mach/irqs.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> - -#include "cpu-tegra.h" -#include "pm.h" -#include "tegra-board-id.h" -#include "board-pmu-defines.h" -#include "board.h" -#include "gpio-names.h" -#include "board-common.h" -#include "board-dalmore.h" -#include "tegra_cl_dvfs.h" -#include "devices.h" -#include "tegra11_soctherm.h" -#include "iomap.h" - -#define PMC_CTRL 0x0 -#define PMC_CTRL_INTR_LOW (1 << 17) -#define TPS65090_CHARGER_INT TEGRA_GPIO_PJ0 -#define POWER_CONFIG2 0x02 - -/*TPS65090 consumer rails */ -static struct regulator_consumer_supply tps65090_dcdc1_supply[] = { - REGULATOR_SUPPLY("vdd_sys_5v0", NULL), - REGULATOR_SUPPLY("vdd_spk", NULL), - REGULATOR_SUPPLY("vdd_sys_modem_5v0", NULL), - REGULATOR_SUPPLY("vdd_sys_cam_5v0", NULL), -}; - -static struct regulator_consumer_supply tps65090_dcdc2_supply[] = { - REGULATOR_SUPPLY("vdd_sys_3v3", NULL), - REGULATOR_SUPPLY("vddio_hv", "tegradc.1"), - REGULATOR_SUPPLY("pwrdet_hv", NULL), - REGULATOR_SUPPLY("vdd_sys_ds_3v3", NULL), - REGULATOR_SUPPLY("avdd", "0-0028"), - REGULATOR_SUPPLY("vdd_sys_cam_3v3", NULL), - REGULATOR_SUPPLY("vdd_sys_sensor_3v3", NULL), - REGULATOR_SUPPLY("vdd_sys_audio_3v3", NULL), - REGULATOR_SUPPLY("vdd_sys_dtv_3v3", NULL), - REGULATOR_SUPPLY("vcc", "0-007c"), - REGULATOR_SUPPLY("vcc", "0-0030"), - REGULATOR_SUPPLY("vin", "2-0030"), -}; - -static struct regulator_consumer_supply tps65090_dcdc3_supply[] = { - REGULATOR_SUPPLY("vdd_ao", NULL), -}; - -static struct regulator_consumer_supply tps65090_ldo1_supply[] = { - REGULATOR_SUPPLY("vdd_sby_5v0", NULL), -}; - -static struct regulator_consumer_supply tps65090_ldo2_supply[] = { - REGULATOR_SUPPLY("vdd_sby_3v3", NULL), -}; - -static struct regulator_consumer_supply tps65090_fet1_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_bl", NULL), -}; - -static struct regulator_consumer_supply tps65090_fet3_supply[] = { - REGULATOR_SUPPLY("vdd_modem_3v3", NULL), -}; - -static struct regulator_consumer_supply tps65090_fet4_supply[] = { - REGULATOR_SUPPLY("avdd_lcd", NULL), - REGULATOR_SUPPLY("avdd", "spi3.2"), -}; - -static struct regulator_consumer_supply tps65090_fet5_supply[] = { - REGULATOR_SUPPLY("vdd_lvds", NULL), -}; - -static struct regulator_consumer_supply tps65090_fet6_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"), -}; - -static struct regulator_consumer_supply tps65090_fet7_supply[] = { - REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"), - REGULATOR_SUPPLY("avdd", "reg-userspace-consumer.2"), - REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"), -}; - -#define tps65090_rails(id) "tps65090-"#id -#define TPS65090_PDATA_INIT(_id, _name, _supply_reg, \ - _always_on, _boot_on, _apply_uV, _en_ext_ctrl, _gpio, _wait_to) \ -static struct regulator_init_data ri_data_##_name = \ -{ \ - .supply_regulator = _supply_reg, \ - .constraints = { \ - .name = tps65090_rails(_id), \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - .apply_uV = _apply_uV, \ - }, \ - .num_consumer_supplies = \ - ARRAY_SIZE(tps65090_##_name##_supply), \ - .consumer_supplies = tps65090_##_name##_supply, \ -}; \ -static struct tps65090_regulator_plat_data \ - tps65090_regulator_pdata_##_name = \ -{ \ - .enable_ext_control = _en_ext_ctrl, \ - .gpio = _gpio, \ - .reg_init_data = &ri_data_##_name , \ - .wait_timeout_us = _wait_to, \ -} - -TPS65090_PDATA_INIT(DCDC1, dcdc1, NULL, 1, 1, 0, true, -1, -1); -TPS65090_PDATA_INIT(DCDC2, dcdc2, NULL, 1, 1, 0, true, -1, -1); -TPS65090_PDATA_INIT(DCDC3, dcdc3, NULL, 1, 1, 0, true, -1, -1); -TPS65090_PDATA_INIT(LDO1, ldo1, NULL, 1, 1, 0, false, -1, -1); -TPS65090_PDATA_INIT(LDO2, ldo2, NULL, 1, 1, 0, false, -1, -1); -TPS65090_PDATA_INIT(FET1, fet1, NULL, 0, 0, 0, false, -1, 800); -TPS65090_PDATA_INIT(FET3, fet3, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0); -TPS65090_PDATA_INIT(FET4, fet4, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0); -TPS65090_PDATA_INIT(FET5, fet5, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0); -TPS65090_PDATA_INIT(FET6, fet6, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0); -TPS65090_PDATA_INIT(FET7, fet7, tps65090_rails(DCDC2), 0, 0, 0, false, -1, 0); - -static struct tps65090_charger_data bcharger_pdata = { - .irq_base = TPS65090_TEGRA_IRQ_BASE, -}; - -#define ADD_TPS65090_REG(_name) (&tps65090_regulator_pdata_##_name) -static struct tps65090_platform_data tps65090_pdata = { - .irq_base = TPS65090_TEGRA_IRQ_BASE, - .reg_pdata = { - ADD_TPS65090_REG(dcdc1), - ADD_TPS65090_REG(dcdc2), - ADD_TPS65090_REG(dcdc3), - ADD_TPS65090_REG(fet1), - NULL, - ADD_TPS65090_REG(fet3), - ADD_TPS65090_REG(fet4), - ADD_TPS65090_REG(fet5), - ADD_TPS65090_REG(fet6), - ADD_TPS65090_REG(fet7), - ADD_TPS65090_REG(ldo1), - ADD_TPS65090_REG(ldo2), - }, - .charger_pdata = &bcharger_pdata, -}; - -/* MAX77663 consumer rails */ -static struct regulator_consumer_supply max77663_sd0_supply[] = { - REGULATOR_SUPPLY("vdd_core", NULL), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"), -}; - -static struct regulator_consumer_supply max77663_sd1_supply[] = { - REGULATOR_SUPPLY("vddio_ddr", NULL), - REGULATOR_SUPPLY("vddio_ddr0", NULL), - REGULATOR_SUPPLY("vddio_ddr1", NULL), -}; - -static struct regulator_consumer_supply max77663_sd2_supply[] = { - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_cam", "vi"), - REGULATOR_SUPPLY("pwrdet_cam", NULL), - REGULATOR_SUPPLY("avdd_osc", NULL), - REGULATOR_SUPPLY("vddio_sys", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"), - REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), - REGULATOR_SUPPLY("vdd_emmc", NULL), - REGULATOR_SUPPLY("vddio_audio", NULL), - REGULATOR_SUPPLY("pwrdet_audio", NULL), - REGULATOR_SUPPLY("avdd_audio_1v8", NULL), - REGULATOR_SUPPLY("vdd_audio_1v8", NULL), - REGULATOR_SUPPLY("vddio_modem", NULL), - REGULATOR_SUPPLY("vddio_modem_1v8", NULL), - REGULATOR_SUPPLY("vddio_bb", NULL), - REGULATOR_SUPPLY("pwrdet_bb", NULL), - REGULATOR_SUPPLY("vddio_bb_1v8", NULL), - REGULATOR_SUPPLY("vddio_uart", NULL), - REGULATOR_SUPPLY("pwrdet_uart", NULL), - REGULATOR_SUPPLY("vddio_gmi", NULL), - REGULATOR_SUPPLY("pwrdet_nand", NULL), - REGULATOR_SUPPLY("vdd_sensor_1v8", NULL), - REGULATOR_SUPPLY("vdd_mic_1v8", NULL), - REGULATOR_SUPPLY("dvdd", "0-0028"), - REGULATOR_SUPPLY("vdd_ds_1v8", NULL), - REGULATOR_SUPPLY("vdd_spi_1v8", NULL), - REGULATOR_SUPPLY("dvdd_lcd", NULL), - REGULATOR_SUPPLY("vdd_com_1v8", NULL), - REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"), - REGULATOR_SUPPLY("dvdd", "reg-userspace-consumer.2"), - REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"), - REGULATOR_SUPPLY("vdd_dtv_1v8", NULL), - REGULATOR_SUPPLY("vlogic", "0-0069"), - REGULATOR_SUPPLY("vid", "0-000d"), - REGULATOR_SUPPLY("vddio", "0-0078"), -}; - -static struct regulator_consumer_supply max77663_sd3_supply[] = { - REGULATOR_SUPPLY("vcore_emmc", NULL), -}; - -static struct regulator_consumer_supply max77663_ldo0_supply[] = { - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), -}; - -static struct regulator_consumer_supply max77663_ldo1_supply[] = { - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), -}; - -static struct regulator_consumer_supply max77663_ldo2_supply[] = { - REGULATOR_SUPPLY("vdd_sensor_2v85", NULL), - REGULATOR_SUPPLY("vdd_als", NULL), - REGULATOR_SUPPLY("vdd", "0-0048"), - REGULATOR_SUPPLY("vdd", "0-004c"), - REGULATOR_SUPPLY("vdd", "0-0069"), - REGULATOR_SUPPLY("vdd", "0-000d"), - REGULATOR_SUPPLY("vdd", "0-0078"), -}; - -static struct regulator_consumer_supply max77663_ldo3_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply max77663_ldo4_supply[] = { - REGULATOR_SUPPLY("vdd_rtc", NULL), -}; - -static struct regulator_consumer_supply max77663_ldo5_supply[] = { - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_dsi_csi", "vi"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"), - REGULATOR_SUPPLY("pwrdet_mipi", NULL), - REGULATOR_SUPPLY("vddio_bb_hsic", NULL), -}; - -static struct regulator_consumer_supply max77663_ldo6_supply[] = { - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"), - REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), -}; - -/* FIXME!! Put the device address of camera */ -static struct regulator_consumer_supply max77663_ldo7_supply[] = { - REGULATOR_SUPPLY("avdd_cam1", NULL), - REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL), - REGULATOR_SUPPLY("vana", "2-0036"), -}; - -/* FIXME!! Put the device address of camera */ -static struct regulator_consumer_supply max77663_ldo8_supply[] = { - REGULATOR_SUPPLY("avdd_cam2", NULL), - REGULATOR_SUPPLY("avdd", "2-0010"), -}; - -static struct max77663_regulator_fps_cfg max77663_fps_cfgs[] = { - { - .src = FPS_SRC_0, - .en_src = FPS_EN_SRC_EN0, - .time_period = FPS_TIME_PERIOD_DEF, - }, - { - .src = FPS_SRC_1, - .en_src = FPS_EN_SRC_EN1, - .time_period = FPS_TIME_PERIOD_DEF, - }, - { - .src = FPS_SRC_2, - .en_src = FPS_EN_SRC_EN0, - .time_period = FPS_TIME_PERIOD_DEF, - }, -}; - -#define MAX77663_PDATA_INIT(_rid, _id, _min_uV, _max_uV, _supply_reg, \ - _always_on, _boot_on, _apply_uV, \ - _fps_src, _fps_pu_period, _fps_pd_period, _flags) \ - static struct regulator_init_data max77663_regulator_idata_##_id = { \ - .supply_regulator = _supply_reg, \ - .constraints = { \ - .name = max77663_rails(_id), \ - .min_uV = _min_uV, \ - .max_uV = _max_uV, \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - .apply_uV = _apply_uV, \ - }, \ - .num_consumer_supplies = \ - ARRAY_SIZE(max77663_##_id##_supply), \ - .consumer_supplies = max77663_##_id##_supply, \ - }; \ -static struct max77663_regulator_platform_data max77663_regulator_pdata_##_id =\ -{ \ - .reg_init_data = &max77663_regulator_idata_##_id, \ - .id = MAX77663_REGULATOR_ID_##_rid, \ - .fps_src = _fps_src, \ - .fps_pu_period = _fps_pu_period, \ - .fps_pd_period = _fps_pd_period, \ - .fps_cfgs = max77663_fps_cfgs, \ - .flags = _flags, \ - } - -MAX77663_PDATA_INIT(SD0, sd0, 900000, 1400000, tps65090_rails(DCDC3), 1, 1, 0, - FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE); - -MAX77663_PDATA_INIT(SD1, sd1, 1200000, 1200000, tps65090_rails(DCDC3), 1, 1, 1, - FPS_SRC_1, -1, -1, SD_FSRADE_DISABLE); - -MAX77663_PDATA_INIT(SD2, sd2, 1800000, 1800000, tps65090_rails(DCDC3), 1, 1, 1, - FPS_SRC_0, -1, -1, 0); - -MAX77663_PDATA_INIT(SD3, sd3, 2850000, 2850000, tps65090_rails(DCDC3), 1, 1, 1, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO0, ldo0, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1, - FPS_SRC_1, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO1, ldo1, 1050000, 1050000, max77663_rails(sd2), 0, 0, 1, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO2, ldo2, 2850000, 2850000, tps65090_rails(DCDC2), 1, 1, - 1, FPS_SRC_1, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO3, ldo3, 1050000, 1050000, max77663_rails(sd2), 1, 1, 1, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO4, ldo4, 1100000, 1100000, tps65090_rails(DCDC2), 1, 1, - 1, FPS_SRC_NONE, -1, -1, LDO4_EN_TRACKING); - -MAX77663_PDATA_INIT(LDO5, ldo5, 1200000, 1200000, max77663_rails(sd2), 0, 1, 1, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO6, ldo6, 1800000, 3300000, tps65090_rails(DCDC2), 0, 0, 0, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO7, ldo7, 2800000, 2800000, tps65090_rails(DCDC2), 0, 0, 1, - FPS_SRC_NONE, -1, -1, 0); - -MAX77663_PDATA_INIT(LDO8, ldo8, 2800000, 2800000, tps65090_rails(DCDC2), 0, 1, 1, - FPS_SRC_1, -1, -1, 0); - -#define MAX77663_REG(_id, _data) (&max77663_regulator_pdata_##_data) - -static struct max77663_regulator_platform_data *max77663_reg_pdata[] = { - MAX77663_REG(SD0, sd0), - MAX77663_REG(SD1, sd1), - MAX77663_REG(SD2, sd2), - MAX77663_REG(SD3, sd3), - MAX77663_REG(LDO0, ldo0), - MAX77663_REG(LDO1, ldo1), - MAX77663_REG(LDO2, ldo2), - MAX77663_REG(LDO3, ldo3), - MAX77663_REG(LDO4, ldo4), - MAX77663_REG(LDO5, ldo5), - MAX77663_REG(LDO6, ldo6), - MAX77663_REG(LDO7, ldo7), - MAX77663_REG(LDO8, ldo8), -}; - -static struct max77663_gpio_config max77663_gpio_cfgs[] = { - { - .gpio = MAX77663_GPIO0, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_LOW, - .out_drv = GPIO_OUT_DRV_PUSH_PULL, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO1, - .dir = GPIO_DIR_IN, - .dout = GPIO_DOUT_HIGH, - .out_drv = GPIO_OUT_DRV_OPEN_DRAIN, - .pull_up = GPIO_PU_ENABLE, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO2, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_HIGH, - .out_drv = GPIO_OUT_DRV_OPEN_DRAIN, - .pull_up = GPIO_PU_ENABLE, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO3, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_HIGH, - .out_drv = GPIO_OUT_DRV_OPEN_DRAIN, - .pull_up = GPIO_PU_ENABLE, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO4, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_HIGH, - .out_drv = GPIO_OUT_DRV_PUSH_PULL, - .alternate = GPIO_ALT_ENABLE, - }, - { - .gpio = MAX77663_GPIO5, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_LOW, - .out_drv = GPIO_OUT_DRV_PUSH_PULL, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO6, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_LOW, - .out_drv = GPIO_OUT_DRV_OPEN_DRAIN, - .alternate = GPIO_ALT_DISABLE, - }, - { - .gpio = MAX77663_GPIO7, - .dir = GPIO_DIR_OUT, - .dout = GPIO_DOUT_LOW, - .out_drv = GPIO_OUT_DRV_OPEN_DRAIN, - .alternate = GPIO_ALT_DISABLE, - }, -}; - -static struct max77663_platform_data max77663_pdata = { - .irq_base = MAX77663_IRQ_BASE, - .gpio_base = MAX77663_GPIO_BASE, - - .num_gpio_cfgs = ARRAY_SIZE(max77663_gpio_cfgs), - .gpio_cfgs = max77663_gpio_cfgs, - - .regulator_pdata = max77663_reg_pdata, - .num_regulator_pdata = ARRAY_SIZE(max77663_reg_pdata), - - .rtc_i2c_addr = 0x68, - - .use_power_off = false, -}; - -static struct i2c_board_info __initdata max77663_regulators[] = { - { - /* The I2C address was determined by OTP factory setting */ - I2C_BOARD_INFO("max77663", 0x3c), - .irq = INT_EXTERNAL_PMU, - .platform_data = &max77663_pdata, - }, -}; - -static struct i2c_board_info __initdata tps65090_regulators[] = { - { - I2C_BOARD_INFO("tps65090", 0x48), - .platform_data = &tps65090_pdata, - }, -}; - -/************************ Palmas based regulator ****************/ -static struct regulator_consumer_supply palmas_smps12_supply[] = { - REGULATOR_SUPPLY("vddio_ddr3l", NULL), - REGULATOR_SUPPLY("vcore_ddr3l", NULL), - REGULATOR_SUPPLY("vref2_ddr3l", NULL), -}; - -#define palmas_smps3_supply max77663_sd2_supply -#define palmas_smps45_supply max77663_sd0_supply -#define palmas_smps457_supply max77663_sd0_supply - -static struct regulator_consumer_supply palmas_smps8_supply[] = { - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"), -}; - -static struct regulator_consumer_supply palmas_smps8_config2_supply[] = { - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), -}; - -static struct regulator_consumer_supply palmas_smps9_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"), -}; - -#define palmas_ldo1_supply max77663_ldo7_supply - -static struct regulator_consumer_supply palmas_ldo1_config2_supply[] = { - REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"), -}; - -#define palmas_ldo2_supply max77663_ldo8_supply - -/* FIXME!! Put the device address of camera */ -static struct regulator_consumer_supply palmas_ldo2_config2_supply[] = { - REGULATOR_SUPPLY("avdd_cam1", NULL), - REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL), - REGULATOR_SUPPLY("avdd_cam2", NULL), - REGULATOR_SUPPLY("vana", "2-0036"), - REGULATOR_SUPPLY("vana", "2-0010"), - REGULATOR_SUPPLY("vana_imx132", "2-0036"), - REGULATOR_SUPPLY("avdd", "2-0010"), -}; - -#define palmas_ldo3_supply max77663_ldo5_supply - -static struct regulator_consumer_supply palmas_ldo4_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo4_config2_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"), -}; - -#define palmas_ldo6_supply max77663_ldo2_supply - -static struct regulator_consumer_supply palmas_ldo7_supply[] = { - REGULATOR_SUPPLY("vdd_af_cam1", NULL), - REGULATOR_SUPPLY("vdd", "2-000e"), -}; - -#define palmas_ldo8_supply max77663_ldo4_supply -#define palmas_ldo9_supply max77663_ldo6_supply - -static struct regulator_consumer_supply palmas_ldoln_supply[] = { - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"), -}; - -static struct regulator_consumer_supply palmas_ldoln_fab05_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), -}; - -static struct regulator_consumer_supply palmas_ldousb_supply[] = { - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), -}; - -static struct regulator_consumer_supply palmas_ldousb_fab05_supply[] = { - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"), - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply palmas_regen1_supply[] = { -}; - -static struct regulator_consumer_supply palmas_regen2_supply[] = { -}; - -PALMAS_REGS_PDATA(smps12, 1350, 1350, tps65090_rails(DCDC3), 1, 1, 0, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps3, 1800, 1800, tps65090_rails(DCDC3), 0, 0, 0, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps45, 900, 1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(smps457, 900, 1400, tps65090_rails(DCDC2), 1, 1, 0, NORMAL, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(smps8, 1050, 1050, tps65090_rails(DCDC2), 0, 1, 1, NORMAL, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(smps8_config2, 1050, 1050, tps65090_rails(DCDC2), 0, 1, 1, - NORMAL, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(smps9, 2800, 2800, tps65090_rails(DCDC2), 1, 0, 0, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo1, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo1_config2, 1200, 1200, tps65090_rails(DCDC2), 0, 0, 1, 0, - 1, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo2, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo2_config2, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo3, 1200, 1200, palmas_rails(smps3), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo4_config2, 1200, 1200, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo4, 1800, 1800, tps65090_rails(DCDC2), 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo6, 2850, 2850, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo7, 2800, 2800, tps65090_rails(DCDC2), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo8, 900, 900, tps65090_rails(DCDC3), 1, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo9, 1800, 3300, palmas_rails(smps9), 0, 0, 1, 0, - 1, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldoln, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldoln_fab05, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldousb, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldousb_fab05, 3300, 3300, tps65090_rails(DCDC1), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(regen1, 3300, 3300, NULL, 1, 1, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(regen2, 5000, 5000, NULL, 1, 1, 0, 0, - 0, 0, 0, 0, 0); - -#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname - -static struct regulator_init_data *dalmore_e1611_reg_data[PALMAS_NUM_REGS] = { - PALMAS_REG_PDATA(smps12), - NULL, - PALMAS_REG_PDATA(smps3), - PALMAS_REG_PDATA(smps45), - PALMAS_REG_PDATA(smps457), - NULL, - NULL, - PALMAS_REG_PDATA(smps8), - PALMAS_REG_PDATA(smps9), - NULL, - NULL, - PALMAS_REG_PDATA(ldo1), - PALMAS_REG_PDATA(ldo2), - PALMAS_REG_PDATA(ldo3), - PALMAS_REG_PDATA(ldo4), - NULL, - PALMAS_REG_PDATA(ldo6), - PALMAS_REG_PDATA(ldo7), - PALMAS_REG_PDATA(ldo8), - PALMAS_REG_PDATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_PDATA(ldoln), - PALMAS_REG_PDATA(ldousb), - PALMAS_REG_PDATA(regen1), - PALMAS_REG_PDATA(regen2), - NULL, - NULL, - NULL, -}; - -#define PALMAS_REG_INIT_DATA(_sname) ®_init_data_##_sname -static struct palmas_reg_init *dalmore_e1611_reg_init[PALMAS_NUM_REGS] = { - PALMAS_REG_INIT_DATA(smps12), - NULL, - PALMAS_REG_INIT_DATA(smps3), - PALMAS_REG_INIT_DATA(smps45), - PALMAS_REG_INIT_DATA(smps457), - NULL, - NULL, - PALMAS_REG_INIT_DATA(smps8), - PALMAS_REG_INIT_DATA(smps9), - NULL, - NULL, - PALMAS_REG_INIT_DATA(ldo1), - PALMAS_REG_INIT_DATA(ldo2), - PALMAS_REG_INIT_DATA(ldo3), - PALMAS_REG_INIT_DATA(ldo4), - NULL, - PALMAS_REG_INIT_DATA(ldo6), - PALMAS_REG_INIT_DATA(ldo7), - PALMAS_REG_INIT_DATA(ldo8), - PALMAS_REG_INIT_DATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_INIT_DATA(ldoln), - PALMAS_REG_INIT_DATA(ldousb), - PALMAS_REG_INIT_DATA(regen1), - PALMAS_REG_INIT_DATA(regen2), - NULL, - NULL, - NULL, -}; - -static struct palmas_pmic_platform_data pmic_platform = { - .disable_smps10_boost_suspend = false, -}; - -static struct palmas_rtc_platform_data rtc_platform = { - .backup_battery_chargeable = true, - .backup_battery_charge_high_current = true, -}; - -static struct palmas_pinctrl_config palmas_pincfg[] = { - PALMAS_PINMUX("powergood", "powergood", NULL, NULL), - PALMAS_PINMUX("vac", "vac", NULL, NULL), - PALMAS_PINMUX("gpio0", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio1", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio2", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio3", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio4", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio5", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio6", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio7", "gpio", NULL, NULL), -}; - -static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = { - .pincfg = palmas_pincfg, - .num_pinctrl = ARRAY_SIZE(palmas_pincfg), - .dvfs1_enable = true, - .dvfs2_enable = false, -}; - -static struct palmas_platform_data palmas_pdata = { - .gpio_base = PALMAS_TEGRA_GPIO_BASE, - .irq_base = PALMAS_TEGRA_IRQ_BASE, - .pmic_pdata = &pmic_platform, - .rtc_pdata = &rtc_platform, - .pinctrl_pdata = &palmas_pinctrl_pdata, - #ifndef CONFIG_ANDROID - .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_8SECONDS, - #else - /* Retaining default value, 12 Seconds */ - .long_press_delay = PALMAS_LONG_PRESS_KEY_TIME_DEFAULT, - #endif -}; - -static struct i2c_board_info palma_device[] = { - { - I2C_BOARD_INFO("tps65913", 0x58), - .irq = INT_EXTERNAL_PMU, - .platform_data = &palmas_pdata, - }, -}; - -/* EN_AVDD_USB_HDMI From PMU GP1 */ -static struct regulator_consumer_supply fixed_reg_avdd_usb_hdmi_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), -}; - -/* EN_CAM_1v8 From PMU GP5 */ -static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = { - REGULATOR_SUPPLY("vi2c", "2-0030"), - REGULATOR_SUPPLY("vif", "2-0036"), - REGULATOR_SUPPLY("dovdd", "2-0010"), - REGULATOR_SUPPLY("dvdd", "2-0010"), - REGULATOR_SUPPLY("vdd_i2c", "2-000e"), -}; - -/* EN_CAM_1v8 on e1611 From PMU GP6 */ -static struct regulator_consumer_supply fixed_reg_en_1v8_cam_e1611_supply[] = { - REGULATOR_SUPPLY("vi2c", "2-0030"), - REGULATOR_SUPPLY("vif", "2-0036"), - REGULATOR_SUPPLY("dovdd", "2-0010"), - REGULATOR_SUPPLY("dvdd", "2-0010"), - REGULATOR_SUPPLY("vdd_i2c", "2-000e"), -}; - -static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = { - REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"), -}; - -static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL), -}; - -/* EN_USB1_VBUS From TEGRA GPIO PN4 PR3(T30) */ -static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"), - REGULATOR_SUPPLY("usb_vbus", "tegra-otg"), - REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"), -}; - -/* EN_3V3_FUSE From TEGRA GPIO PX4 */ -static struct regulator_consumer_supply fixed_reg_vpp_fuse_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), -}; - -/* EN_USB3_VBUS From TEGRA GPIO PM5 */ -static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"), - REGULATOR_SUPPLY("usb_vbus1", "tegra-xhci"), -}; - -/* EN_1V8_TS From TEGRA_GPIO_PH5 */ -static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = { - REGULATOR_SUPPLY("dvdd", "spi3.2"), -}; - -/* EN_AVDD_HDMI_PLL From TEGRA_GPIO_PO1 */ -static struct regulator_consumer_supply fixed_reg_avdd_hdmi_pll_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), -}; - -/* Macro for defining fixed regulator sub device data */ -#define FIXED_SUPPLY(_name) "fixed_reg_"#_name -#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ - _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \ - static struct regulator_init_data ri_data_##_var = \ - { \ - .supply_regulator = _in_supply, \ - .num_consumer_supplies = \ - ARRAY_SIZE(fixed_reg_##_name##_supply), \ - .consumer_supplies = fixed_reg_##_name##_supply, \ - .constraints = { \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - }, \ - }; \ - static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ - { \ - .supply_name = FIXED_SUPPLY(_name), \ - .microvolts = _millivolts * 1000, \ - .gpio = _gpio_nr, \ - .gpio_is_open_drain = _open_drain, \ - .enable_high = _active_high, \ - .enabled_at_boot = _boot_state, \ - .init_data = &ri_data_##_var, \ - }; \ - static struct platform_device fixed_reg_##_var##_dev = { \ - .name = "reg-fixed-voltage", \ - .id = _id, \ - .dev = { \ - .platform_data = &fixed_reg_##_var##_pdata, \ - }, \ - } - -FIXED_REG(1, avdd_usb_hdmi, avdd_usb_hdmi, - tps65090_rails(DCDC2), 0, 0, - MAX77663_GPIO_BASE + MAX77663_GPIO1, true, true, 1, 3300); - -FIXED_REG(2, en_1v8_cam, en_1v8_cam, - max77663_rails(sd2), 0, 0, - MAX77663_GPIO_BASE + MAX77663_GPIO5, false, true, 0, 1800); - -FIXED_REG(3, vdd_hdmi_5v0, vdd_hdmi_5v0, - tps65090_rails(DCDC1), 0, 0, - TEGRA_GPIO_PK1, false, true, 0, 5000); - -FIXED_REG(4, vpp_fuse, vpp_fuse, - max77663_rails(sd2), 0, 0, - TEGRA_GPIO_PX4, false, true, 0, 3300); - -FIXED_REG(5, usb1_vbus, usb1_vbus, - tps65090_rails(DCDC1), 0, 0, - TEGRA_GPIO_PN4, true, true, 0, 5000); - -FIXED_REG(6, usb3_vbus, usb3_vbus, - tps65090_rails(DCDC1), 0, 0, - TEGRA_GPIO_PK6, true, true, 0, 5000); - -FIXED_REG(7, en_1v8_cam_e1611, en_1v8_cam_e1611, - palmas_rails(smps3), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 1800); - -FIXED_REG(8, dvdd_ts, dvdd_ts, - palmas_rails(smps3), 0, 0, - TEGRA_GPIO_PH5, false, false, 1, 1800); - -FIXED_REG(9, lcd_bl_en, lcd_bl_en, - NULL, 0, 0, - TEGRA_GPIO_PH2, false, true, 0, 5000); - -FIXED_REG(10, avdd_hdmi_pll, avdd_hdmi_pll, - palmas_rails(ldo3), 0, 0, - TEGRA_GPIO_PO1, false, true, 1, 1200); -/* - * Creating the fixed regulator device tables - */ - -#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) - -#define DALMORE_COMMON_FIXED_REG \ - ADD_FIXED_REG(usb1_vbus), \ - ADD_FIXED_REG(usb3_vbus), \ - ADD_FIXED_REG(vdd_hdmi_5v0), \ - ADD_FIXED_REG(lcd_bl_en), - -#define E1612_FIXED_REG \ - ADD_FIXED_REG(avdd_usb_hdmi), \ - ADD_FIXED_REG(en_1v8_cam), \ - ADD_FIXED_REG(vpp_fuse), \ - -#define E1611_FIXED_REG \ - ADD_FIXED_REG(en_1v8_cam_e1611), \ - ADD_FIXED_REG(dvdd_ts), - -#define DALMORE_POWER_CONFIG_2 \ - ADD_FIXED_REG(avdd_hdmi_pll), - -/* Gpio switch regulator platform data for Dalmore E1611 */ -static struct platform_device *fixed_reg_devs_e1611_a00[] = { - DALMORE_COMMON_FIXED_REG - E1611_FIXED_REG -}; - -/* Gpio switch regulator platform data for Dalmore E1612 */ -static struct platform_device *fixed_reg_devs_e1612_a00[] = { - DALMORE_COMMON_FIXED_REG - E1612_FIXED_REG -}; - -static struct platform_device *fixed_reg_devs_dalmore_config2[] = { - DALMORE_POWER_CONFIG_2 -}; - -static void set_dalmore_power_fab05(void) -{ - dalmore_e1611_reg_data[PALMAS_REG_LDOLN] = - PALMAS_REG_PDATA(ldoln_fab05); - dalmore_e1611_reg_init[PALMAS_REG_LDOLN] = - PALMAS_REG_INIT_DATA(ldoln_fab05); - dalmore_e1611_reg_data[PALMAS_REG_LDOUSB] = - PALMAS_REG_PDATA(ldousb_fab05); - dalmore_e1611_reg_init[PALMAS_REG_LDOUSB] = - PALMAS_REG_INIT_DATA(ldousb_fab05); - return; -} - -static void set_dalmore_power_config2(void) -{ - dalmore_e1611_reg_data[PALMAS_REG_SMPS8] = - PALMAS_REG_PDATA(smps8_config2); - dalmore_e1611_reg_init[PALMAS_REG_SMPS8] = - PALMAS_REG_INIT_DATA(smps8_config2); - dalmore_e1611_reg_data[PALMAS_REG_LDO1] = - PALMAS_REG_PDATA(ldo1_config2); - dalmore_e1611_reg_init[PALMAS_REG_LDO1] = - PALMAS_REG_INIT_DATA(ldo1_config2); - dalmore_e1611_reg_data[PALMAS_REG_LDO2] = - PALMAS_REG_PDATA(ldo2_config2); - dalmore_e1611_reg_init[PALMAS_REG_LDO2] = - PALMAS_REG_INIT_DATA(ldo2_config2); - dalmore_e1611_reg_data[PALMAS_REG_LDO4] = - PALMAS_REG_PDATA(ldo4_config2); - dalmore_e1611_reg_init[PALMAS_REG_LDO4] = - PALMAS_REG_INIT_DATA(ldo4_config2); - return; -} - -int __init dalmore_palmas_regulator_init(void) -{ - void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - u32 pmc_ctrl; - u8 power_config; - struct board_info board_info; - int i; - - tegra_get_board_info(&board_info); - - /* TPS65913: Normal state of INT request line is LOW. - * configure the power management controller to trigger PMU - * interrupts when HIGH. - */ - pmc_ctrl = readl(pmc + PMC_CTRL); - writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); - - /* Enable regulator full constraints */ - regulator_has_full_constraints(); - - reg_idata_ldo6.constraints.enable_time = 1000; - ri_data_fet1.constraints.disable_time = 1500; - - /* Tracking configuration */ - reg_init_data_ldo8.config_flags = - PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE | - PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE; - - power_config = get_power_config(); - if (board_info.fab == BOARD_FAB_A05) { - set_dalmore_power_config2(); - set_dalmore_power_fab05(); - } else if (power_config & POWER_CONFIG2) { - set_dalmore_power_config2(); - } - - for (i = 0; i < PALMAS_NUM_REGS ; i++) { - pmic_platform.reg_data[i] = dalmore_e1611_reg_data[i]; - pmic_platform.reg_init[i] = dalmore_e1611_reg_init[i]; - } - - i2c_register_board_info(4, palma_device, - ARRAY_SIZE(palma_device)); - return 0; -} - -static int ac_online(void) -{ - return 1; -} - -static struct resource dalmore_pda_resources[] = { - [0] = { - .name = "ac", - }, -}; - -static struct pda_power_pdata dalmore_pda_data = { - .is_ac_online = ac_online, -}; - -static struct platform_device dalmore_pda_power_device = { - .name = "pda-power", - .id = -1, - .resource = dalmore_pda_resources, - .num_resources = ARRAY_SIZE(dalmore_pda_resources), - .dev = { - .platform_data = &dalmore_pda_data, - }, -}; - -static struct tegra_suspend_platform_data dalmore_suspend_data = { - .cpu_timer = 500, - .cpu_off_timer = 300, - .suspend_mode = TEGRA_SUSPEND_LP0, - .core_timer = 0x157e, - .core_off_timer = 2000, - .corereq_high = true, - .sysclkreq_high = true, - .cpu_lp2_min_residency = 1000, - .min_residency_crail = 20000, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .lp1_lowvolt_support = false, - .i2c_base_addr = 0, - .pmuslave_addr = 0, - .core_reg_addr = 0, - .lp1_core_volt_low_cold = 0, - .lp1_core_volt_low = 0, - .lp1_core_volt_high = 0, -#endif - .usb_vbus_internal_wake = true, - .usb_id_internal_wake = true, -}; -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -/* board parameters for cpu dfll */ -static struct tegra_cl_dvfs_cfg_param dalmore_cl_dvfs_param = { - .sample_rate = 12500, - - .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, - .cf = 10, - .ci = 0, - .cg = 2, - - .droop_cut_value = 0xF, - .droop_restore_ramp = 0x0, - .scale_out_ramp = 0x0, -}; -#endif - -/* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */ -#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) -static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; -static inline void fill_reg_map(void) -{ - int i; - for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { - pmu_cpu_vdd_map[i].reg_value = i + 0x23; - pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; - } -} - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static struct tegra_cl_dvfs_platform_data dalmore_cl_dvfs_data = { - .dfll_clk_name = "dfll_cpu", - .pmu_if = TEGRA_CL_DVFS_PMU_I2C, - .u.pmu_i2c = { - .fs_rate = 400000, - .slave_addr = 0x86, - .reg = 0x00, - }, - .vdd_map = pmu_cpu_vdd_map, - .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, - - .cfg_param = &dalmore_cl_dvfs_param, -}; - -static int __init dalmore_cl_dvfs_init(void) -{ - fill_reg_map(); - if (tegra_revision < TEGRA_REVISION_A02) - dalmore_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET; - tegra_cl_dvfs_device.dev.platform_data = &dalmore_cl_dvfs_data; - platform_device_register(&tegra_cl_dvfs_device); - - return 0; -} -#endif - -static int __init dalmore_max77663_regulator_init(void) -{ - struct board_info board_info; - void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - u32 pmc_ctrl; - - tegra_get_board_info(&board_info); - if (board_info.fab < BOARD_FAB_A02) - max77663_regulator_pdata_ldo4.flags = 0; - - /* configure the power management controller to trigger PMU - * interrupts when low */ - pmc_ctrl = readl(pmc + PMC_CTRL); - writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); - - i2c_register_board_info(4, max77663_regulators, - ARRAY_SIZE(max77663_regulators)); - - return 0; -} - -static struct regulator_bulk_data dalmore_gps_regulator_supply[] = { - [0] = { - .supply = "avdd", - }, - [1] = { - .supply = "dvdd", - }, -}; - -static struct regulator_userspace_consumer_data dalmore_gps_regulator_pdata = { - .num_supplies = ARRAY_SIZE(dalmore_gps_regulator_supply), - .supplies = dalmore_gps_regulator_supply, -}; - -static struct platform_device dalmore_gps_regulator_device = { - .name = "reg-userspace-consumer", - .id = 2, - .dev = { - .platform_data = &dalmore_gps_regulator_pdata, - }, -}; - -static int __init dalmore_fixed_regulator_init(void) -{ - struct board_info board_info; - u8 power_config; - - if (!of_machine_is_compatible("nvidia,dalmore")) - return 0; - - power_config = get_power_config(); - tegra_get_board_info(&board_info); - - /* Fab05 and power-type2 have the same fixed regs */ - if (board_info.fab == BOARD_FAB_A05 || power_config & POWER_CONFIG2) - platform_add_devices(fixed_reg_devs_dalmore_config2, - ARRAY_SIZE(fixed_reg_devs_dalmore_config2)); - - if (board_info.board_id == BOARD_E1611 || - board_info.board_id == BOARD_P2454) - return platform_add_devices(fixed_reg_devs_e1611_a00, - ARRAY_SIZE(fixed_reg_devs_e1611_a00)); - else - return platform_add_devices(fixed_reg_devs_e1612_a00, - ARRAY_SIZE(fixed_reg_devs_e1612_a00)); -} -subsys_initcall_sync(dalmore_fixed_regulator_init); - -static void dalmore_tps65090_init(void) -{ - int err; - - err = gpio_request(TPS65090_CHARGER_INT, "CHARGER_INT"); - if (err < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, err); - goto fail_init_irq; - } - - err = gpio_direction_input(TPS65090_CHARGER_INT); - if (err < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, err); - goto fail_init_irq; - } - - tps65090_regulators[0].irq = gpio_to_irq(TPS65090_CHARGER_INT); -fail_init_irq: - i2c_register_board_info(4, tps65090_regulators, - ARRAY_SIZE(tps65090_regulators)); - return; -} - -int __init dalmore_regulator_init(void) -{ - struct board_info board_info; - - dalmore_tps65090_init(); -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - dalmore_cl_dvfs_init(); -#endif - tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_E1611 || - board_info.board_id == BOARD_P2454) - dalmore_palmas_regulator_init(); - else - dalmore_max77663_regulator_init(); - - platform_device_register(&dalmore_pda_power_device); - platform_device_register(&dalmore_gps_regulator_device); - return 0; -} - -int __init dalmore_suspend_init(void) -{ - tegra_init_suspend(&dalmore_suspend_data); - /* Enable dalmore USB wake for VBUS/ID without using PMIC */ - tegra_set_usb_vbus_internal_wake( - dalmore_suspend_data.usb_vbus_internal_wake); - tegra_set_usb_id_internal_wake( - dalmore_suspend_data.usb_id_internal_wake); - return 0; -} - -int __init dalmore_edp_init(void) -{ - unsigned int regulator_mA; - - regulator_mA = get_maximum_cpu_current_supported(); - if (!regulator_mA) - regulator_mA = 15000; - - pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); - tegra_init_cpu_edp_limits(regulator_mA); - - regulator_mA = get_maximum_core_current_supported(); - if (!regulator_mA) - regulator_mA = 4000; - - pr_info("%s: core regulator %d mA\n", __func__, regulator_mA); - tegra_init_core_edp_limits(regulator_mA); - - return 0; -} - -static struct pid_thermal_gov_params soctherm_pid_params = { - .max_err_temp = 9000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 20, - .down_compensation = 20, -}; - -static struct thermal_zone_params soctherm_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &soctherm_pid_params, -}; - -static struct tegra_thermtrip_pmic_data tpdata_palmas = { - .reset_tegra = 1, - .pmu_16bit_ops = 0, - .controller_type = 0, - .pmu_i2c_addr = 0x58, - .i2c_controller_id = 4, - .poweroff_reg_addr = 0xa0, - .poweroff_reg_data = 0x0, -}; - -static struct tegra_thermtrip_pmic_data tpdata_max77663 = { - .reset_tegra = 1, - .pmu_16bit_ops = 0, - .controller_type = 0, - .pmu_i2c_addr = 0x3c, - .i2c_controller_id = 4, - .poweroff_reg_addr = 0x41, - .poweroff_reg_data = 0x80, -}; - -static struct soctherm_platform_data dalmore_soctherm_data = { - .therm = { - [THERM_CPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &soctherm_tzp, - }, - [THERM_GPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &soctherm_tzp, - }, - [THERM_PLL] = { - .zone_enable = true, - }, - }, - .throttle = { - [THROTTLE_HEAVY] = { - .priority = 100, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 80, - }, - [THROTTLE_DEV_GPU] = { - .enable = true, - .depth = 80, - }, - }, - }, - }, - .tshut_pmu_trip_data = &tpdata_palmas, -}; - -int __init dalmore_soctherm_init(void) -{ - struct board_info board_info; - - tegra_get_board_info(&board_info); - if (!(board_info.board_id == BOARD_E1611 || - board_info.board_id == BOARD_P2454)) - dalmore_soctherm_data.tshut_pmu_trip_data = &tpdata_max77663; - - tegra_platform_edp_init(dalmore_soctherm_data.therm[THERM_CPU].trips, - &dalmore_soctherm_data.therm[THERM_CPU].num_trips, - 6000); /* edp temperature margin */ - tegra_add_cpu_vmax_trips(dalmore_soctherm_data.therm[THERM_CPU].trips, - &dalmore_soctherm_data.therm[THERM_CPU].num_trips); - tegra_add_core_edp_trips(dalmore_soctherm_data.therm[THERM_CPU].trips, - &dalmore_soctherm_data.therm[THERM_CPU].num_trips); - - return tegra11_soctherm_init(&dalmore_soctherm_data); -} diff --git a/arch/arm/mach-tegra/board-dalmore-sdhci.c b/arch/arm/mach-tegra/board-dalmore-sdhci.c deleted file mode 100644 index 1933479888c4..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-sdhci.c +++ /dev/null @@ -1,441 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore-sdhci.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/wlan_plat.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/regulator/consumer.h> -#include <linux/mmc/host.h> -#include <linux/wl12xx.h> -#include <linux/platform_data/mmc-sdhci-tegra.h> - -#include <asm/mach-types.h> -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> - -#include "tegra-board-id.h" -#include "gpio-names.h" -#include "board.h" -#include "board-dalmore.h" -#include "dvfs.h" -#include "iomap.h" - -#define DALMORE_WLAN_PWR TEGRA_GPIO_PCC5 -#define DALMORE_WLAN_RST TEGRA_GPIO_PX7 -#define DALMORE_WLAN_WOW TEGRA_GPIO_PU5 -#define DALMORE_SD_CD TEGRA_GPIO_PV2 -#define DALMORE_SD_WP TEGRA_GPIO_PQ4 -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; -static int dalmore_wifi_status_register(void (*callback)(int , void *), void *); - -static int dalmore_wifi_reset(int on); -static int dalmore_wifi_power(int on); -static int dalmore_wifi_set_carddetect(int val); - -static struct wifi_platform_data dalmore_wifi_control = { - .set_power = dalmore_wifi_power, - .set_reset = dalmore_wifi_reset, - .set_carddetect = dalmore_wifi_set_carddetect, -}; - -static struct resource wifi_resource[] = { - [0] = { - .name = "bcm4329_wlan_irq", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - | IORESOURCE_IRQ_SHAREABLE, - }, -}; - -static struct platform_device dalmore_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .num_resources = 1, - .resource = wifi_resource, - .dev = { - .platform_data = &dalmore_wifi_control, - }, -}; - -#ifdef CONFIG_MMC_EMBEDDED_SDIO -static struct embedded_sdio_data embedded_sdio_data0 = { - .cccr = { - .sdio_vsn = 2, - .multi_block = 1, - .low_speed = 0, - .wide_bus = 0, - .high_power = 1, - .high_speed = 1, - }, - .cis = { - .vendor = 0x02d0, - .device = 0x4329, - }, -}; -#endif - -struct tegra_sdhci_platform_data dalmore_tegra_sdhci_platform_data0 = { - .mmc_data = { - .register_status_notify = dalmore_wifi_status_register, -#ifdef CONFIG_MMC_EMBEDDED_SDIO - .embedded_sdio = &embedded_sdio_data0, -#endif - .built_in = 0, - .ocr_mask = MMC_OCR_1V8_MASK, - }, -#ifndef CONFIG_MMC_EMBEDDED_SDIO - .pm_flags = MMC_PM_KEEP_POWER, -#endif - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x2, - .trim_delay = 0x2, - .ddr_clk_limit = 41000000, - .max_clk_limit = 82000000, -/*FIXME: Enable UHS modes for WiFI */ - .uhs_mask = MMC_UHS_MASK_DDR50 | MMC_UHS_MASK_SDR50 | - MMC_UHS_MASK_SDR104 | MMC_UHS_MASK_SDR12 | MMC_UHS_MASK_SDR25, - .disable_clock_gate = true, -}; - -static struct resource sdhci_resource0[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { - .cd_gpio = DALMORE_SD_CD, - .wp_gpio = DALMORE_SD_WP, - .power_gpio = -1, - .tap_delay = 0x3, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, - .max_clk_limit = 82000000, - .uhs_mask = MMC_UHS_MASK_DDR50, - .power_off_rail = true, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, - .tap_delay = 0x5, - .trim_delay = 0xA, - .ddr_trim_delay = -1, - .ddr_clk_limit = 41000000, - .max_clk_limit = 156000000, - .mmc_data = { - .built_in = 1, - .ocr_mask = MMC_OCR_1V8_MASK, - } -}; - -static struct platform_device tegra_sdhci_device0 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource0, - .num_resources = ARRAY_SIZE(sdhci_resource0), - .dev = { - .platform_data = &dalmore_tegra_sdhci_platform_data0, - }, -}; - -static struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), - .dev = { - .platform_data = &tegra_sdhci_platform_data2, - }, -}; - -static struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), - .dev = { - .platform_data = &tegra_sdhci_platform_data3, - }, -}; - -static int dalmore_wifi_status_register( - void (*callback)(int card_present, void *dev_id), - void *dev_id) -{ - if (wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -static int dalmore_wifi_set_carddetect(int val) -{ - pr_debug("%s: %d\n", __func__, val); - if (wifi_status_cb) - wifi_status_cb(val, wifi_status_cb_devid); - else - pr_warning("%s: Nobody to notify\n", __func__); - return 0; -} - -static struct regulator *dalmore_vdd_com_3v3; -static struct regulator *dalmore_vddio_com_1v8; -#define DALMORE_VDD_WIFI_3V3 "avdd" -#define DALMORE_VDD_WIFI_1V8 "dvdd" - -static int dalmore_wifi_regulator_enable(void) -{ - int ret = 0; - - /* Enable COM's vdd_com_3v3 regulator*/ - if (IS_ERR_OR_NULL(dalmore_vdd_com_3v3)) { - dalmore_vdd_com_3v3 = regulator_get(&dalmore_wifi_device.dev, - DALMORE_VDD_WIFI_3V3); - if (IS_ERR(dalmore_vdd_com_3v3)) { - pr_err("Couldn't get regulator " - DALMORE_VDD_WIFI_3V3 "\n"); - return PTR_ERR(dalmore_vdd_com_3v3); - } - - ret = regulator_enable(dalmore_vdd_com_3v3); - if (ret < 0) { - pr_err("Couldn't enable regulator " - DALMORE_VDD_WIFI_3V3 "\n"); - regulator_put(dalmore_vdd_com_3v3); - dalmore_vdd_com_3v3 = NULL; - return ret; - } - } - - /* Enable COM's vddio_com_1v8 regulator*/ - if (IS_ERR_OR_NULL(dalmore_vddio_com_1v8)) { - dalmore_vddio_com_1v8 = regulator_get(&dalmore_wifi_device.dev, - DALMORE_VDD_WIFI_1V8); - if (IS_ERR(dalmore_vddio_com_1v8)) { - pr_err("Couldn't get regulator " - DALMORE_VDD_WIFI_1V8 "\n"); - regulator_disable(dalmore_vdd_com_3v3); - - regulator_put(dalmore_vdd_com_3v3); - dalmore_vdd_com_3v3 = NULL; - return PTR_ERR(dalmore_vddio_com_1v8); - } - - ret = regulator_enable(dalmore_vddio_com_1v8); - if (ret < 0) { - pr_err("Couldn't enable regulator " - DALMORE_VDD_WIFI_1V8 "\n"); - regulator_put(dalmore_vddio_com_1v8); - dalmore_vddio_com_1v8 = NULL; - - regulator_disable(dalmore_vdd_com_3v3); - regulator_put(dalmore_vdd_com_3v3); - dalmore_vdd_com_3v3 = NULL; - return ret; - } - } - - return ret; -} - -static void dalmore_wifi_regulator_disable(void) -{ - /* Disable COM's vdd_com_3v3 regulator*/ - if (!IS_ERR_OR_NULL(dalmore_vdd_com_3v3)) { - regulator_disable(dalmore_vdd_com_3v3); - regulator_put(dalmore_vdd_com_3v3); - dalmore_vdd_com_3v3 = NULL; - } - - /* Disable COM's vddio_com_1v8 regulator*/ - if (!IS_ERR_OR_NULL(dalmore_vddio_com_1v8)) { - regulator_disable(dalmore_vddio_com_1v8); - regulator_put(dalmore_vddio_com_1v8); - dalmore_vddio_com_1v8 = NULL; - } -} - -static int dalmore_wifi_power(int on) -{ - int ret = 0; - - pr_debug("%s: %d\n", __func__, on); - /* Enable COM's regulators on wi-fi poer on*/ - if (on == 1) { - ret = dalmore_wifi_regulator_enable(); - if (ret < 0) { - pr_err("Failed to enable COM regulators\n"); - return ret; - } - } - - gpio_set_value(DALMORE_WLAN_PWR, on); - mdelay(100); - gpio_set_value(DALMORE_WLAN_RST, on); - mdelay(200); - - /* Disable COM's regulators on wi-fi poer off*/ - if (on != 1) { - pr_debug("Disabling COM regulators\n"); - dalmore_wifi_regulator_disable(); - } - - return ret; -} - -static int dalmore_wifi_reset(int on) -{ - pr_debug("%s: do nothing\n", __func__); - return 0; -} - -static int __init dalmore_wifi_init(void) -{ - int rc; - - rc = gpio_request(DALMORE_WLAN_PWR, "wlan_power"); - if (rc) - pr_err("WLAN_PWR gpio request failed:%d\n", rc); - rc = gpio_request(DALMORE_WLAN_RST, "wlan_rst"); - if (rc) - pr_err("WLAN_RST gpio request failed:%d\n", rc); - rc = gpio_request(DALMORE_WLAN_WOW, "bcmsdh_sdmmc"); - if (rc) - pr_err("WLAN_WOW gpio request failed:%d\n", rc); - - rc = gpio_direction_output(DALMORE_WLAN_PWR, 0); - if (rc) - pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc); - gpio_direction_output(DALMORE_WLAN_RST, 0); - if (rc) - pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc); - rc = gpio_direction_input(DALMORE_WLAN_WOW); - if (rc) - pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc); - - wifi_resource[0].start = wifi_resource[0].end = - gpio_to_irq(DALMORE_WLAN_WOW); - - platform_device_register(&dalmore_wifi_device); - return 0; -} - -#ifdef CONFIG_TEGRA_PREPOWER_WIFI -static int __init dalmore_wifi_prepower(void) -{ - if (!machine_is_dalmore()) - return 0; - - dalmore_wifi_power(1); - - return 0; -} - -subsys_initcall_sync(dalmore_wifi_prepower); -#endif - -int __init dalmore_sdhci_init(void) -{ - int nominal_core_mv; - int min_vcore_override_mv; - int boot_vcore_mv; - struct board_info board_info; - - nominal_core_mv = - tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); - if (nominal_core_mv) { - dalmore_tegra_sdhci_platform_data0.nominal_vcore_mv = - nominal_core_mv; - tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv; - tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv; - } - min_vcore_override_mv = - tegra_dvfs_rail_get_override_floor(tegra_core_rail); - if (min_vcore_override_mv) { - dalmore_tegra_sdhci_platform_data0.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data2.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data3.min_vcore_override_mv = - min_vcore_override_mv; - } - boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail); - if (boot_vcore_mv) { - dalmore_tegra_sdhci_platform_data0.boot_vcore_mv = - boot_vcore_mv; - tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv; - } - if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200) - && (!(tegra_sdhci_platform_data3.uhs_mask & - MMC_UHS_MASK_DDR50))) - tegra_sdhci_platform_data3.trim_delay = 0; - tegra_get_board_info(&board_info); - if (board_info.fab == BOARD_FAB_A05) { - tegra_sdhci_platform_data2.wp_gpio = -1; - dalmore_tegra_sdhci_platform_data0.max_clk_limit = 156000000; - tegra_sdhci_platform_data2.max_clk_limit = 156000000; - } - platform_device_register(&tegra_sdhci_device3); - platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device0); - dalmore_wifi_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-dalmore-sensors.c b/arch/arm/mach-tegra/board-dalmore-sensors.c deleted file mode 100644 index 8011e6821949..000000000000 --- a/arch/arm/mach-tegra/board-dalmore-sensors.c +++ /dev/null @@ -1,862 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore-sensors.c - * - * Copyright (c) 2012-2014 NVIDIA CORPORATION, All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * Neither the name of NVIDIA CORPORATION nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/i2c.h> -#include <linux/delay.h> -#include <linux/mpu.h> -#include <linux/regulator/consumer.h> -#include <linux/gpio.h> -#include <linux/therm_est.h> -#include <linux/nct1008.h> -#include <linux/pid_thermal_gov.h> -#include <mach/edp.h> -#include <linux/edp.h> -#include <mach/gpio-tegra.h> -#include <mach/pinmux-t11.h> -#include <mach/pinmux.h> -#ifndef CONFIG_OF -#include <media/imx091.h> -#include <media/ad5816.h> -#include <media/ov9772.h> -#endif -#include <media/as364x.h> -#include <generated/mach-types.h> -#include <linux/power/sbs-battery.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-common.h" -#include "board-dalmore.h" -#include "cpu-tegra.h" -#include "devices.h" -#include "tegra-board-id.h" -#include "dvfs.h" - -#ifndef CONFIG_OF -static struct nvc_gpio_pdata imx091_gpio_pdata[] = { - {IMX091_GPIO_RESET, CAM_RSTN, true, false}, - {IMX091_GPIO_PWDN, CAM1_POWER_DWN_GPIO, true, false}, - {IMX091_GPIO_GP1, CAM_GPIO1, true, false} -}; -#endif - -static struct board_info board_info; - -static struct throttle_table tj_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle tj_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_throttle_table), - .throt_tab = tj_throttle_table, -}; - -static int __init dalmore_throttle_init(void) -{ - if (machine_is_dalmore()) - balanced_throttle_register(&tj_throttle, "tegra-balanced"); - return 0; -} -module_init(dalmore_throttle_init); - -static struct nct1008_platform_data dalmore_nct1008_pdata = { - .supported_hwrev = true, - .extended_range = true, - .conv_rate = 0x06, /* 4Hz conversion rate */ - - .sensors = { - [LOC] = { - .shutdown_limit = 120, /* C */ - .num_trips = 0, - .tzp = NULL, - }, - [EXT] = { - .shutdown_limit = 105, /* C */ - .num_trips = 1, - .tzp = NULL, - .trips = { - { - .cdev_type = "suspend_soctherm", - .trip_temp = 50000, - .trip_type = THERMAL_TRIP_ACTIVE, - .upper = 1, - .lower = 1, - .hysteresis = 5000, - .mask = 1, - }, - }, - } - } -}; - -static struct i2c_board_info dalmore_i2c4_nct1008_board_info[] = { - { - I2C_BOARD_INFO("nct1008", 0x4C), - .platform_data = &dalmore_nct1008_pdata, - .irq = -1, - } -}; - -#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ - { \ - .pingroup = TEGRA_PINGROUP_##_pingroup, \ - .func = TEGRA_MUX_##_mux, \ - .pupd = TEGRA_PUPD_##_pupd, \ - .tristate = TEGRA_TRI_##_tri, \ - .io = TEGRA_PIN_##_io, \ - .lock = TEGRA_PIN_LOCK_##_lock, \ - .od = TEGRA_PIN_OD_DEFAULT, \ - .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ -} - -#ifndef CONFIG_OF -static int dalmore_focuser_power_on(struct ad5816_power_rail *pw) -{ - int err; - - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - err = regulator_enable(pw->vdd_i2c); - if (unlikely(err)) - goto ad5816_vdd_i2c_fail; - - err = regulator_enable(pw->vdd); - if (unlikely(err)) - goto ad5816_vdd_fail; - - return 0; - -ad5816_vdd_fail: - regulator_disable(pw->vdd_i2c); - -ad5816_vdd_i2c_fail: - pr_err("%s FAILED\n", __func__); - - return -ENODEV; -} - -static int dalmore_focuser_power_off(struct ad5816_power_rail *pw) -{ - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - regulator_disable(pw->vdd); - regulator_disable(pw->vdd_i2c); - - return 0; -} - -static struct tegra_pingroup_config mclk_disable = - VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config mclk_enable = - VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_disable = - VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_enable = - VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); -#endif - -/* - * As a workaround, dalmore_vcmvdd need to be allocated to activate the - * sensor devices. This is due to the focuser device(AD5816) will hook up - * the i2c bus if it is not powered up. -*/ -static struct regulator *dalmore_vcmvdd; - -static int dalmore_get_vcmvdd(void) -{ - if (!dalmore_vcmvdd) { - dalmore_vcmvdd = regulator_get(NULL, "vdd_af_cam1"); - if (unlikely(WARN_ON(IS_ERR(dalmore_vcmvdd)))) { - pr_err("%s: can't get regulator vcmvdd: %ld\n", - __func__, PTR_ERR(dalmore_vcmvdd)); - dalmore_vcmvdd = NULL; - return -ENODEV; - } - } - return 0; -} - -#ifndef CONFIG_OF -static int dalmore_imx091_power_on(struct nvc_regulator *vreg) -{ - int err; - - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - if (dalmore_get_vcmvdd()) - goto imx091_poweron_fail; - - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(10, 20); - - err = regulator_enable(vreg[IMX091_VREG_AVDD].vreg); - if (err) - goto imx091_avdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_IOVDD].vreg); - if (err) - goto imx091_iovdd_fail; - - usleep_range(1, 2); - gpio_set_value(CAM1_POWER_DWN_GPIO, 1); - - err = regulator_enable(dalmore_vcmvdd); - if (unlikely(err)) - goto imx091_vcmvdd_fail; - - tegra_pinmux_config_table(&mclk_enable, 1); - usleep_range(300, 310); - - return 1; - -imx091_vcmvdd_fail: - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - -imx091_iovdd_fail: - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - -imx091_avdd_fail: - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - -imx091_poweron_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int dalmore_imx091_power_off(struct nvc_regulator *vreg) -{ - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - usleep_range(1, 2); - tegra_pinmux_config_table(&mclk_disable, 1); - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(1, 2); - - regulator_disable(dalmore_vcmvdd); - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - - return 1; -} - -static struct nvc_imager_cap imx091_cap = { - .identifier = "IMX091", - .sensor_nvc_interface = 3, - .pixel_types[0] = 0x100, - .orientation = 0, - .direction = 0, - .initial_clock_rate_khz = 6000, - .clock_profiles[0] = { - .external_clock_khz = 24000, - .clock_multiplier = 850000, /* value / 1,000,000 */ - }, - .clock_profiles[1] = { - .external_clock_khz = 0, - .clock_multiplier = 0, - }, - .h_sync_edge = 0, - .v_sync_edge = 0, - .mclk_on_vgp0 = 0, - .csi_port = 0, - .data_lanes = 4, - .virtual_channel_id = 0, - .discontinuous_clk_mode = 1, - .cil_threshold_settle = 0x0, - .min_blank_time_width = 16, - .min_blank_time_height = 16, - .preferred_mode_index = 0, - .focuser_guid = NVC_FOCUS_GUID(0), - .torch_guid = NVC_TORCH_GUID(0), - .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2, -}; - -static struct imx091_platform_data imx091_pdata = { - .num = 0, - .sync = 0, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(imx091_gpio_pdata), - .gpio = imx091_gpio_pdata, - .flash_cap = { - .sdo_trigger_enabled = 1, - .adjustable_flash_timing = 1, - }, - .cap = &imx091_cap, - .power_on = dalmore_imx091_power_on, - .power_off = dalmore_imx091_power_off, -}; -#endif - -static struct sbs_platform_data sbs_pdata = { - .poll_retry_count = 100, - .i2c_retry_count = 2, -}; - -#ifndef CONFIG_OF -static int dalmore_ov9772_power_on(struct ov9772_power_rail *pw) -{ - int err; - - if (unlikely(!pw || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - if (dalmore_get_vcmvdd()) - goto ov9772_get_vcmvdd_fail; - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - err = regulator_enable(pw->avdd); - if (unlikely(err)) - goto ov9772_avdd_fail; - - err = regulator_enable(pw->dovdd); - if (unlikely(err)) - goto ov9772_dovdd_fail; - - gpio_set_value(CAM_RSTN, 1); - gpio_set_value(CAM2_POWER_DWN_GPIO, 1); - - err = regulator_enable(dalmore_vcmvdd); - if (unlikely(err)) - goto ov9772_vcmvdd_fail; - - tegra_pinmux_config_table(&pbb0_enable, 1); - usleep_range(340, 380); - - /* return 1 to skip the in-driver power_on sequence */ - return 1; - -ov9772_vcmvdd_fail: - regulator_disable(pw->dovdd); - -ov9772_dovdd_fail: - regulator_disable(pw->avdd); - -ov9772_avdd_fail: - gpio_set_value(CAM_RSTN, 0); - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - -ov9772_get_vcmvdd_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int dalmore_ov9772_power_off(struct ov9772_power_rail *pw) -{ - if (unlikely(!pw || !dalmore_vcmvdd || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - usleep_range(21, 25); - tegra_pinmux_config_table(&pbb0_disable, 1); - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - regulator_disable(dalmore_vcmvdd); - regulator_disable(pw->dovdd); - regulator_disable(pw->avdd); - - /* return 1 to skip the in-driver power_off sequence */ - return 1; -} - -static struct nvc_gpio_pdata ov9772_gpio_pdata[] = { - { OV9772_GPIO_TYPE_SHTDN, CAM2_POWER_DWN_GPIO, true, 0, }, - { OV9772_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, }, -}; - -static struct ov9772_platform_data dalmore_ov9772_pdata = { - .num = 1, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(ov9772_gpio_pdata), - .gpio = ov9772_gpio_pdata, - .power_on = dalmore_ov9772_power_on, - .power_off = dalmore_ov9772_power_off, -}; -#endif - -static int dalmore_as3648_power_on(struct as364x_power_rail *pw) -{ - int err = dalmore_get_vcmvdd(); - - if (err) - return err; - - return regulator_enable(dalmore_vcmvdd); -} - -static int dalmore_as3648_power_off(struct as364x_power_rail *pw) -{ - if (!dalmore_vcmvdd) - return -ENODEV; - - return regulator_disable(dalmore_vcmvdd); -} - -static struct as364x_platform_data dalmore_as3648_pdata = { - .config = { - .led_mask = 3, - .max_total_current_mA = 1000, - .max_peak_current_mA = 600, - .vin_low_v_run_mV = 3070, - .strobe_type = 1, - }, - .pinstate = { - .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0), - .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0) - }, - .dev_name = "torch", - .type = AS3648, - .gpio_strobe = CAM_FLASH_STROBE, - - .power_on_callback = dalmore_as3648_power_on, - .power_off_callback = dalmore_as3648_power_off, -}; - -#ifndef CONFIG_OF -static struct ad5816_platform_data dalmore_ad5816_pdata = { - .cfg = 0, - .num = 0, - .sync = 0, - .dev_name = "focuser", - .power_on = dalmore_focuser_power_on, - .power_off = dalmore_focuser_power_off, -}; -#endif - -static struct i2c_board_info dalmore_i2c_board_info_e1625[] = { -#ifndef CONFIG_OF - { - I2C_BOARD_INFO("imx091", 0x36), - .platform_data = &imx091_pdata, - }, - { - I2C_BOARD_INFO("ov9772", 0x10), - .platform_data = &dalmore_ov9772_pdata, - }, -#endif - { - I2C_BOARD_INFO("as3648", 0x30), - .platform_data = &dalmore_as3648_pdata, - }, -#ifndef CONFIG_OF - { - I2C_BOARD_INFO("ad5816", 0x0E), - .platform_data = &dalmore_ad5816_pdata, - }, -#endif -}; - -static int dalmore_camera_init(void) -{ -#ifndef CONFIG_OF - tegra_pinmux_config_table(&mclk_disable, 1); - tegra_pinmux_config_table(&pbb0_disable, 1); -#endif - - i2c_register_board_info(2, dalmore_i2c_board_info_e1625, - ARRAY_SIZE(dalmore_i2c_board_info_e1625)); - return 0; -} - -#define TEGRA_CAMERA_GPIO(_gpio, _label, _value) \ - { \ - .gpio = _gpio, \ - .label = _label, \ - .value = _value, \ - } - -static struct i2c_board_info dalmore_i2c_board_info_cm3218[] = { - { - I2C_BOARD_INFO("cm3218", 0x48), - }, -}; - -/* MPU board file definition */ -static struct mpu_platform_data mpu9150_gyro_data = { - .int_config = 0x10, - .level_shifter = 0, - /* Located in board_[platformname].h */ - .orientation = MPU_GYRO_ORIENTATION, - .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE, - .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22, - 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89}, -}; - -static struct mpu_platform_data mpu_compass_data = { - .orientation = MPU_COMPASS_ORIENTATION, - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct mpu_platform_data bmp180_pdata = { - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct i2c_board_info __initdata inv_mpu9150_i2c2_board_info[] = { - { - I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR), - .platform_data = &mpu9150_gyro_data, - }, - { - /* The actual BMP180 address is 0x77 but because this conflicts - * with another device, this address is hacked so Linux will - * call the driver. The conflict is technically okay since the - * BMP180 is behind the MPU. Also, the BMP180 driver uses a - * hard-coded address of 0x77 since it can't be changed anyway. - */ - I2C_BOARD_INFO("bmp180", 0x78), - .platform_data = &bmp180_pdata, - }, - { - I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR), - .platform_data = &mpu_compass_data, - }, -}; - -static void mpuirq_init(void) -{ - int ret = 0; - unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO; - unsigned gyro_bus_num = MPU_GYRO_BUS_NUM; - char *gyro_name = MPU_GYRO_NAME; - - pr_info("*** MPU START *** mpuirq_init...\n"); - - ret = gpio_request(gyro_irq_gpio, gyro_name); - - if (ret < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, ret); - return; - } - - ret = gpio_direction_input(gyro_irq_gpio); - if (ret < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, ret); - gpio_free(gyro_irq_gpio); - return; - } - pr_info("*** MPU END *** mpuirq_init...\n"); - - inv_mpu9150_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO); - i2c_register_board_info(gyro_bus_num, inv_mpu9150_i2c2_board_info, - ARRAY_SIZE(inv_mpu9150_i2c2_board_info)); -} - -static int dalmore_nct1008_init(void) -{ - int nct1008_port; - int ret = 0; - - if ((board_info.board_id == BOARD_E1612) || - (board_info.board_id == BOARD_E1641) || - (board_info.board_id == BOARD_E1613) || - (board_info.board_id == BOARD_P2454)) - { - /* per email from Matt 9/10/2012 */ - nct1008_port = TEGRA_GPIO_PX6; - } else if (board_info.board_id == BOARD_E1611) { - if (board_info.fab == 0x04) - nct1008_port = TEGRA_GPIO_PO4; - else - nct1008_port = TEGRA_GPIO_PX6; - } else { - nct1008_port = TEGRA_GPIO_PX6; - pr_err("Warning: nct alert_port assumed TEGRA_GPIO_PX6" - " for unknown dalmore board id E%d\n", - board_info.board_id); - } - - tegra_add_all_vmin_trips(dalmore_nct1008_pdata.sensors[EXT].trips, - &dalmore_nct1008_pdata.sensors[EXT].num_trips); - - dalmore_i2c4_nct1008_board_info[0].irq = gpio_to_irq(nct1008_port); - pr_info("%s: dalmore nct1008 irq %d", - __func__, dalmore_i2c4_nct1008_board_info[0].irq); - - ret = gpio_request(nct1008_port, "temp_alert"); - if (ret < 0) - return ret; - - ret = gpio_direction_input(nct1008_port); - if (ret < 0) { - pr_info("%s: calling gpio_free(nct1008_port)", __func__); - gpio_free(nct1008_port); - } - - /* dalmore has thermal sensor on GEN1-I2C i.e. instance 0 */ - i2c_register_board_info(0, dalmore_i2c4_nct1008_board_info, - ARRAY_SIZE(dalmore_i2c4_nct1008_board_info)); - - return ret; -} - -static struct i2c_board_info __initdata bq20z45_pdata[] = { - { - I2C_BOARD_INFO("sbs-battery", 0x0B), - .platform_data = &sbs_pdata, - }, -}; - -#ifdef CONFIG_TEGRA_SKIN_THROTTLE -static struct thermal_trip_info skin_trips[] = { - { - .cdev_type = "skin-balanced", - .trip_temp = 43000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 57000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, -}; - -static struct therm_est_subdevice skin_devs[] = { - { - .dev_data = "Tdiode", - .coeffs = { - 2, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 0, - 1, 1, 0, 0, - 0, 0, -1, -7 - }, - }, - { - .dev_data = "Tboard", - .coeffs = { - -11, -7, -5, -3, - -3, -2, -1, 0, - 0, 0, 1, 1, - 1, 2, 2, 3, - 4, 6, 11, 18 - }, - }, -}; - -static struct pid_thermal_gov_params skin_pid_params = { - .max_err_temp = 4000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 15, - .down_compensation = 15, -}; - -static struct thermal_zone_params skin_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &skin_pid_params, -}; - -static struct therm_est_data skin_data = { - .num_trips = ARRAY_SIZE(skin_trips), - .trips = skin_trips, - .toffset = 9793, - .polling_period = 1100, - .passive_delay = 15000, - .tc1 = 10, - .tc2 = 1, - .ndevs = ARRAY_SIZE(skin_devs), - .devs = skin_devs, - .tzp = &skin_tzp, -}; - -static struct throttle_table skin_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle skin_throttle = { - .throt_tab_size = ARRAY_SIZE(skin_throttle_table), - .throt_tab = skin_throttle_table, -}; - -static int __init dalmore_skin_init(void) -{ - if (machine_is_dalmore()) { - balanced_throttle_register(&skin_throttle, "skin-balanced"); - tegra_skin_therm_est_device.dev.platform_data = &skin_data; - platform_device_register(&tegra_skin_therm_est_device); - } - - return 0; -} -late_initcall(dalmore_skin_init); -#endif - -int __init dalmore_sensors_init(void) -{ - int err; - - tegra_get_board_info(&board_info); - - err = dalmore_nct1008_init(); - if (err) - return err; - - dalmore_camera_init(); - mpuirq_init(); - - i2c_register_board_info(0, dalmore_i2c_board_info_cm3218, - ARRAY_SIZE(dalmore_i2c_board_info_cm3218)); - - i2c_register_board_info(0, bq20z45_pdata, - ARRAY_SIZE(bq20z45_pdata)); - - return 0; -} diff --git a/arch/arm/mach-tegra/board-dalmore.c b/arch/arm/mach-tegra/board-dalmore.c deleted file mode 100644 index 42dfda4f697d..000000000000 --- a/arch/arm/mach-tegra/board-dalmore.c +++ /dev/null @@ -1,750 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ctype.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/i2c-tegra.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_data/tegra_usb.h> -#include <linux/spi/spi.h> -#include <linux/spi/rm31080a_ts.h> -#include <linux/platform_data/serial-tegra.h> -#include <linux/memblock.h> -#include <linux/spi/spi-tegra.h> -#include <linux/nfc/pn544.h> -#include <linux/rfkill-gpio.h> -#include <linux/skbuff.h> -#include <linux/ti_wilink_st.h> -#include <linux/regulator/consumer.h> -#include <linux/smb349-charger.h> -#include <linux/max17048_battery.h> -#include <linux/leds.h> -#include <linux/i2c/at24.h> -#include <linux/of_platform.h> -#include <linux/edp.h> -#include <linux/usb/tegra_usb_phy.h> -#include <linux/clk/tegra.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> -#include <linux/irqchip/tegra.h> -#include <linux/tegra_fiq_debugger.h> -#include <linux/platform_data/tegra_usb_modem_power.h> - -#include <mach/irqs.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <mach/io_dpd.h> -#include <mach/i2s.h> -#include <mach/isomgr.h> -#include <mach/tegra_asoc_pdata.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/gpio-tegra.h> -#include <mach/xusb.h> - -#include "board-touch-raydium.h" -#include "board.h" -#include "board-common.h" -#include "clock.h" -#include "board-dalmore.h" -#include "devices.h" -#include "gpio-names.h" -#include "iomap.h" -#include "pm.h" -#include "common.h" -#include "tegra-board-id.h" -#include "tegra-of-dev-auxdata.h" - -static struct board_info board_info, display_board_info; - -#if defined(CONFIG_BT_BLUESLEEP) || defined(CONFIG_BT_BLUESLEEP_MODULE) -static struct rfkill_gpio_platform_data dalmore_bt_rfkill_pdata = { - .name = "bt_rfkill", - .shutdown_gpio = TEGRA_GPIO_PQ7, - .reset_gpio = TEGRA_GPIO_PQ6, - .type = RFKILL_TYPE_BLUETOOTH, -}; - -static struct platform_device dalmore_bt_rfkill_device = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &dalmore_bt_rfkill_pdata, - }, -}; - -static struct resource dalmore_bluesleep_resources[] = { - [0] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [2] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device dalmore_bluesleep_device = { - .name = "bluesleep", - .id = -1, - .num_resources = ARRAY_SIZE(dalmore_bluesleep_resources), - .resource = dalmore_bluesleep_resources, -}; - -static noinline void __init dalmore_setup_bt_rfkill(void) -{ - platform_device_register(&dalmore_bt_rfkill_device); -} - -static noinline void __init dalmore_setup_bluesleep(void) -{ - dalmore_bluesleep_resources[2].start = - dalmore_bluesleep_resources[2].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&dalmore_bluesleep_device); - return; -} -#elif defined(CONFIG_BLUEDROID_PM) || defined(CONFIG_BLUEDROID_PM_MODULE) -static struct resource dalmore_bluedroid_pm_resources[] = { - [0] = { - .name = "shutdown_gpio", - .start = TEGRA_GPIO_PQ7, - .end = TEGRA_GPIO_PQ7, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, - [2] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [3] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [4] = { - .name = "reset_gpio", - .start = TEGRA_GPIO_PQ6, - .end = TEGRA_GPIO_PQ6, - .flags = IORESOURCE_IO, - }, -}; - -static struct platform_device dalmore_bluedroid_pm_device = { - .name = "bluedroid_pm", - .id = 0, - .num_resources = ARRAY_SIZE(dalmore_bluedroid_pm_resources), - .resource = dalmore_bluedroid_pm_resources, -}; - -static noinline void __init dalmore_setup_bluedroid_pm(void) -{ - dalmore_bluedroid_pm_resources[1].start = - dalmore_bluedroid_pm_resources[1].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&dalmore_bluedroid_pm_device); -} -#endif - -static __initdata struct tegra_clk_init_table dalmore_clk_init_table[] = { - /* name parent rate enabled */ - { "pll_m", NULL, 0, false}, - { "hda", "pll_p", 108000000, false}, - { "hda2codec_2x", "pll_p", 48000000, false}, - { "pwm", "pll_p", 3187500, false}, - { "blink", "clk_32k", 32768, true}, - { "i2s1", "pll_a_out0", 0, false}, - { "i2s3", "pll_a_out0", 0, false}, - { "i2s4", "pll_a_out0", 0, false}, - { "spdif_out", "pll_a_out0", 0, false}, - { "d_audio", "clk_m", 12000000, false}, - { "dam0", "clk_m", 12000000, false}, - { "dam1", "clk_m", 12000000, false}, - { "dam2", "clk_m", 12000000, false}, - { "audio1", "i2s1_sync", 0, false}, - { "audio3", "i2s3_sync", 0, false}, - /* Setting vi_sensor-clk to true for validation purpose, will imapact - * power, later set to be false.*/ - { "vi_sensor", "pll_p", 150000000, false}, - { "cilab", "pll_p", 150000000, false}, - { "cilcd", "pll_p", 150000000, false}, - { "cile", "pll_p", 150000000, false}, - { "i2c1", "pll_p", 3200000, false}, - { "i2c2", "pll_p", 3200000, false}, - { "i2c3", "pll_p", 3200000, false}, - { "i2c4", "pll_p", 3200000, false}, - { "i2c5", "pll_p", 3200000, false}, - { "sbc1", "pll_p", 25000000, false}, - { "sbc2", "pll_p", 25000000, false}, - { "sbc3", "pll_p", 25000000, false}, - { "sbc4", "pll_p", 25000000, false}, - { "sbc5", "pll_p", 25000000, false}, - { "sbc6", "pll_p", 25000000, false}, - { "uarta", "pll_p", 408000000, false}, - { "uartb", "pll_p", 408000000, false}, - { "uartc", "pll_p", 408000000, false}, - { "uartd", "pll_p", 408000000, false}, - { NULL, NULL, 0, 0}, -}; - -static struct i2c_board_info __initdata rt5640_board_info = { - I2C_BOARD_INFO("rt5640", 0x1c), -}; - -static struct pn544_i2c_platform_data nfc_pdata = { - .irq_gpio = TEGRA_GPIO_PW2, - .ven_gpio = TEGRA_GPIO_PQ3, - .firm_gpio = TEGRA_GPIO_PH0, -}; - -static struct i2c_board_info __initdata nfc_board_info = { - I2C_BOARD_INFO("pn544", 0x28), - .platform_data = &nfc_pdata, -}; - -static void dalmore_i2c_init(void) -{ - nfc_board_info.irq = gpio_to_irq(TEGRA_GPIO_PW2); - i2c_register_board_info(0, &nfc_board_info, 1); - i2c_register_board_info(0, &rt5640_board_info, 1); -} - -static struct tegra_serial_platform_data dalmore_uartd_pdata = { - .dma_req_selector = 19, - .modem_interrupt = false, -}; - -static void __init dalmore_uart_init(void) -{ - int debug_port_id; - - /* Register low speed only if it is selected */ - if (!is_tegra_debug_uartport_hs()) { - debug_port_id = uart_console_debug_init(3); - if (debug_port_id < 0) - return; - - platform_device_register(uart_console_debug_device); - - } else { - tegra_uartd_device.dev.platform_data = &dalmore_uartd_pdata; - platform_device_register(&tegra_uartd_device); - } - -} - -static struct resource tegra_rtc_resources[] = { - [0] = { - .start = TEGRA_RTC_BASE, - .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_RTC, - .end = INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tegra_rtc_device = { - .name = "tegra_rtc", - .id = -1, - .resource = tegra_rtc_resources, - .num_resources = ARRAY_SIZE(tegra_rtc_resources), -}; - -static struct tegra_asoc_platform_data dalmore_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .gpio_codec1 = TEGRA_GPIO_CODEC1_EN, - .gpio_codec2 = TEGRA_GPIO_CODEC2_EN, - .gpio_codec3 = TEGRA_GPIO_CODEC3_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - }, -}; - -static struct platform_device dalmore_audio_device = { - .name = "tegra-snd-rt5640", - .id = 0, - .dev = { - .platform_data = &dalmore_audio_pdata, - }, -}; - -static struct platform_device *dalmore_devices[] __initdata = { - &tegra_pmu_device, - &tegra_rtc_device, - &tegra_udc_device, -#if defined(CONFIG_TEGRA_AVP) - &tegra_avp_device, -#endif -#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) - &tegra11_se_device, -#endif - &tegra_ahub_device, - &tegra_dam_device0, - &tegra_dam_device1, - &tegra_dam_device2, - &tegra_i2s_device1, - &tegra_i2s_device3, - &tegra_i2s_device4, - &tegra_spdif_device, - &spdif_dit_device, - &bluetooth_dit_device, - &tegra_pcm_device, - &tegra_offload_device, - &tegra30_avp_audio_device, - &dalmore_audio_device, - &tegra_hda_device, -#if defined(CONFIG_TEGRA_CEC_SUPPORT) - &tegra_cec_device, -#endif -#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) - &tegra_aes_device, -#endif -}; - -#ifdef CONFIG_USB_SUPPORT -static struct tegra_usb_platform_data tegra_udc_pdata = { - .port_otg = true, - .has_hostpc = true, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .unaligned_dma_buf_supported = false, - .op_mode = TEGRA_USB_OPMODE_DEVICE, - .u_data.dev = { - .vbus_pmu_irq = 0, - .vbus_gpio = -1, - .charging_supported = true, - .remote_wakeup_supported = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { - .port_otg = true, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x4, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x5, - }, -}; - -static struct tegra_usb_otg_data tegra_otg_pdata = { - .ehci_device = &tegra_ehci1_device, - .ehci_pdata = &tegra_ehci1_utmi_pdata, -}; - -static void dalmore_usb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - /* Set USB wake sources for dalmore */ - tegra_set_usb_wake_source(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) { - tegra_otg_pdata.is_xhci = false; - tegra_udc_pdata.u_data.dev.is_xhci = false; - } else { - tegra_otg_pdata.is_xhci = true; - tegra_udc_pdata.u_data.dev.is_xhci = true; - } - tegra_otg_device.dev.platform_data = &tegra_otg_pdata; - platform_device_register(&tegra_otg_device); - /* Setup the udc platform data */ - tegra_udc_device.dev.platform_data = &tegra_udc_pdata; - - if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) { - tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; - platform_device_register(&tegra_ehci3_device); - } -} - -static struct tegra_xusb_platform_data xusb_pdata = { - .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P1 | - TEGRA_XUSB_USB2_P0, -}; - -static void dalmore_xusb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) - xusb_pdata.portmap &= ~TEGRA_XUSB_USB2_P0; - if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) - xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0); -} - -static struct gpio modem_gpios[] = { /* Nemo modem */ - {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"}, - {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"}, -}; - -static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static int baseband_init(void) -{ - int ret; - - ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios)); - if (ret) { - pr_warn("%s:gpio request failed\n", __func__); - return ret; - } - - /* enable pull-down for MDM_COLD_BOOT */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_KB_COL5, - TEGRA_PUPD_PULL_DOWN); - - /* export GPIO for user space access through sysfs */ - gpio_export(MDM_RST, false); - - return 0; -} - -static const struct tegra_modem_operations baseband_operations = { - .init = baseband_init, -}; - -static struct tegra_usb_modem_power_platform_data baseband_pdata = { - .ops = &baseband_operations, - .regulator_name = "vdd_modem_3v3", - .wake_gpio = -1, - .boot_gpio = MDM_COLDBOOT, - .boot_irq_flags = IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING | - IRQF_ONESHOT, - .autosuspend_delay = 2000, - .short_autosuspend_delay = 50, - .tegra_ehci_device = &tegra_ehci2_device, - .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata, -}; - -static struct platform_device icera_nemo_device = { - .name = "tegra_usb_modem_power", - .id = -1, - .dev = { - .platform_data = &baseband_pdata, - }, -}; - -static void dalmore_modem_init(void) -{ - int modem_id = tegra_get_modem_id(); - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - switch (modem_id) { - case TEGRA_BB_NEMO: /* on board i500 HSIC */ - if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) { - platform_device_register(&icera_nemo_device); - } - break; - } -} - -#else -static void dalmore_usb_init(void) { } -static void dalmore_modem_init(void) { } -static void dalmore_xusb_init(void) { } -#endif - -static void dalmore_audio_init(void) -{ - dalmore_audio_pdata.codec_name = "rt5640.0-001c"; - dalmore_audio_pdata.codec_dai_name = "rt5640-aif1"; -} - -static __initdata struct tegra_clk_init_table touch_clk_init_table[] = { - /* name parent rate enabled */ - { "extern2", "pll_p", 41000000, false}, - { "clk_out_2", "extern2", 40800000, false}, - { NULL, NULL, 0, 0}, -}; - -struct rm_spi_ts_platform_data rm31080ts_dalmore_data = { - .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI, - .config = 0, - .platform_id = RM_PLATFORM_D010, - .name_of_clock = "clk_out_2", - .name_of_clock_con = "extern2", -}; - -static struct tegra_spi_device_controller_data dev_cdata = { - .rx_clk_tap_delay = 16, - .tx_clk_tap_delay = 16, -}; - -struct spi_board_info rm31080a_dalmore_spi_board[1] = { - { - .modalias = "rm_ts_spidev", - .bus_num = 3, - .chip_select = 2, - .max_speed_hz = 12 * 1000 * 1000, - .mode = SPI_MODE_0, - .controller_data = &dev_cdata, - .platform_data = &rm31080ts_dalmore_data, - }, -}; - -static int __init dalmore_touch_init(void) -{ - tegra_clk_init_from_table(touch_clk_init_table); - if (display_board_info.board_id == BOARD_E1582) - rm31080ts_dalmore_data.platform_id = RM_PLATFORM_P005; - else - rm31080ts_dalmore_data.platform_id = RM_PLATFORM_D010; - mdelay(20); - rm31080a_dalmore_spi_board[0].irq = gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI); - touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI, - TOUCH_GPIO_RST_RAYDIUM_SPI, - &rm31080ts_dalmore_data, - &rm31080a_dalmore_spi_board[0], - ARRAY_SIZE(rm31080a_dalmore_spi_board)); - return 0; -} - -#ifdef CONFIG_USE_OF -struct of_dev_auxdata dalmore_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000600, "sdhci-tegra.3", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000400, "sdhci-tegra.2", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000000, "sdhci-tegra.0", - &dalmore_tegra_sdhci_platform_data0), - OF_DEV_AUXDATA("nvidia,tegra114-camera", 0x0, "tegra_camera", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", - NULL), - - T114_I2C_OF_DEV_AUXDATA, - T114_SPI_OF_DEV_AUXDATA, - OF_DEV_AUXDATA("nvidia,tegra114-apbdma", 0x6000a000, "tegra-apbdma", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-xhci", 0x70090000, "tegra-xhci", - &xusb_pdata), - OF_DEV_AUXDATA("nvidia,tegra114-nvavp", 0x60001000, "nvavp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-pwm", 0x7000a000, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-efuse", TEGRA_FUSE_BASE, "tegra-fuse", - NULL), - {} -}; -#endif - -static void __init tegra_dalmore_early_init(void) -{ - tegra_clk_init_from_table(dalmore_clk_init_table); - tegra_clk_verify_parents(); - tegra_soc_device_init("dalmore"); -} - -static void __init tegra_dalmore_late_init(void) -{ - dalmore_i2c_init(); - dalmore_usb_init(); - dalmore_xusb_init(); - dalmore_uart_init(); - dalmore_audio_init(); - platform_add_devices(dalmore_devices, ARRAY_SIZE(dalmore_devices)); - tegra_io_dpd_init(); - dalmore_regulator_init(); - dalmore_sdhci_init(); - dalmore_suspend_init(); - dalmore_emc_init(); - dalmore_edp_init(); - isomgr_init(); - dalmore_touch_init(); - if (board_info.board_id == BOARD_E1582) - roth_panel_init(board_info.board_id); - else - dalmore_panel_init(); - dalmore_kbc_init(); -#if defined(CONFIG_BT_BLUESLEEP) || defined(CONFIG_BT_BLUESLEEP_MODULE) - dalmore_setup_bluesleep(); - dalmore_setup_bt_rfkill(); -#elif defined(CONFIG_BLUEDROID_PM) || defined(CONFIG_BLUEDROID_PM_MODULE) - dalmore_setup_bluedroid_pm(); -#endif - dalmore_modem_init(); -#ifdef CONFIG_TEGRA_WDT_RECOVERY - tegra_wdt_recovery_init(); -#endif - tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); - dalmore_sensors_init(); - dalmore_soctherm_init(); -} - -static void __init tegra_dalmore_dt_init(void) -{ - tegra_get_board_info(&board_info); - tegra_get_display_board_info(&display_board_info); - - tegra_dalmore_early_init(); - - of_platform_populate(NULL, - of_default_bus_match_table, dalmore_auxdata_lookup, - &platform_bus); - - tegra_dalmore_late_init(); -} - -static void __init tegra_dalmore_reserve(void) -{ -#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* 1920*1200*4*2 = 18432000 bytes */ - tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M); -#else - tegra_reserve(SZ_512M, SZ_16M + SZ_2M, SZ_4M); -#endif -} - -static const char * const dalmore_dt_board_compat[] = { - "nvidia,dalmore", - NULL -}; - -MACHINE_START(DALMORE, "dalmore") - .atag_offset = 0x100, - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .reserve = tegra_dalmore_reserve, - .init_early = tegra11x_init_early, - .init_irq = irqchip_init, - .init_time = clocksource_of_init, - .init_machine = tegra_dalmore_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = dalmore_dt_board_compat, - .init_late = tegra_init_late, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-dalmore.h b/arch/arm/mach-tegra/board-dalmore.h deleted file mode 100644 index b0b54649c251..000000000000 --- a/arch/arm/mach-tegra/board-dalmore.h +++ /dev/null @@ -1,131 +0,0 @@ -/* - * arch/arm/mach-tegra/board-dalmore.h - * - * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_BOARD_DALMORE_H -#define _MACH_TEGRA_BOARD_DALMORE_H - -#include <mach/irqs.h> -#include <linux/mfd/max77663-core.h> -#include <linux/mfd/tps65090.h> -#include "gpio-names.h" - -/* External peripheral act as gpio */ -/* MAX77663 GPIO */ -#define MAX77663_GPIO_BASE TEGRA_NR_GPIOS -#define PALMAS_TEGRA_GPIO_BASE TEGRA_NR_GPIOS -#define MAX77663_GPIO_END (MAX77663_GPIO_BASE + MAX77663_GPIO_NR) - -/* Hall Effect Sensor GPIO */ -#define TEGRA_GPIO_HALL TEGRA_GPIO_PS0 - -/* Audio-related GPIOs */ -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 -#define TEGRA_GPIO_LDO1_EN TEGRA_GPIO_PV3 -#define TEGRA_GPIO_CODEC1_EN TEGRA_GPIO_PP3 -#define TEGRA_GPIO_CODEC2_EN TEGRA_GPIO_PP1 -#define TEGRA_GPIO_CODEC3_EN TEGRA_GPIO_PV0 - -#define TEGRA_GPIO_SPKR_EN -1 -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7 -#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PK3 -#define TEGRA_GPIO_EXT_MIC_EN -1 - -#define TEGRA_GPIO_W_DISABLE TEGRA_GPIO_PDD7 -#define TEGRA_GPIO_MODEM_RSVD1 TEGRA_GPIO_PV0 -#define TEGRA_GPIO_MODEM_RSVD2 TEGRA_GPIO_PH7 - -#define TPS65090_TEGRA_IRQ_BASE TEGRA_NR_IRQS -#define TPS65090_TEGRA_IRQ_END (TPS65090_TEGRA_IRQ_BASE + 16) -/* External peripheral act as interrupt controller */ -/* MAX77663 IRQs */ -#define PALMAS_TEGRA_IRQ_BASE TPS65090_TEGRA_IRQ_END -#define PALMAS_TEGRA_IRQ_END (PALMAS_TEGRA_IRQ_BASE + PALMAS_NUM_IRQ) -#define MAX77663_IRQ_BASE TPS65090_TEGRA_IRQ_END -#define MAX77663_IRQ_END (MAX77663_IRQ_BASE + MAX77663_IRQ_NR) -#define MAX77663_IRQ_ACOK_RISING MAX77663_IRQ_ONOFF_ACOK_RISING - -/* PMC Wake status registers */ -#define PMC_WAKE_STATUS 0x14 -#define PMC_WAKE2_STATUS 0x168 - -/* I2C related GPIOs */ -#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4 -#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5 -#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5 -#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6 -#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1 -#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2 -#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4 -#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5 -#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6 -#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7 - -/* Camera related GPIOs */ -#define CAM_RSTN TEGRA_GPIO_PBB3 -#define CAM_FLASH_STROBE TEGRA_GPIO_PBB4 -#define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 -#define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 -#define CAM_AF_PWDN TEGRA_GPIO_PBB7 -#define CAM_GPIO1 TEGRA_GPIO_PCC1 -#define CAM_GPIO2 TEGRA_GPIO_PCC2 - -/* Touchscreen definitions */ -#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2 -#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4 - -/* Invensense MPU Definitions */ -#define MPU_GYRO_NAME "mpu9150" -#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PR3 -#define MPU_GYRO_ADDR 0x69 -#define MPU_GYRO_BUS_NUM 0 -#define MPU_GYRO_ORIENTATION { -1, 0, 0, 0, 1, 0, 0, 0, -1 } -#define MPU_COMPASS_NAME "ak8975" -#define MPU_COMPASS_IRQ_GPIO 0 -#define MPU_COMPASS_ADDR 0x0D -#define MPU_COMPASS_BUS_NUM 0 -#define MPU_COMPASS_ORIENTATION { 0, -1, 0, 1, 0, 0, 0, 0, 1 } - -/* Modem related GPIOs */ -#define MODEM_EN TEGRA_GPIO_PP2 -#define MDM_RST TEGRA_GPIO_PP0 -#define MDM_COLDBOOT TEGRA_GPIO_PQ5 - -int dalmore_regulator_init(void); -int dalmore_suspend_init(void); -int dalmore_sdhci_init(void); -int dalmore_sensors_init(void); -int dalmore_emc_init(void); -int dalmore_edp_init(void); -int dalmore_panel_init(void); -int roth_panel_init(int board_id); -int dalmore_kbc_init(void); -int dalmore_soctherm_init(void); - -extern struct tegra_sdhci_platform_data dalmore_tegra_sdhci_platform_data0; - -/* Baseband IDs */ -enum tegra_bb_type { - TEGRA_BB_NEMO = 1, -}; - -#define UTMI1_PORT_OWNER_XUSB 0x1 -#define UTMI2_PORT_OWNER_XUSB 0x2 -#define HSIC1_PORT_OWNER_XUSB 0x4 - -#endif diff --git a/arch/arm/mach-tegra/board-macallan-kbc.c b/arch/arm/mach-tegra/board-macallan-kbc.c deleted file mode 100644 index 37e387e553ac..000000000000 --- a/arch/arm/mach-tegra/board-macallan-kbc.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan-kbc.c - * Keys configuration for Nvidia t114 macallan platform. - * - * Copyright (C) 2013 NVIDIA, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/input/tegra_kbc.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/mfd/palmas.h> - -#include "tegra-board-id.h" -#include "board.h" -#include "board-macallan.h" -#include "devices.h" -#include "iomap.h" -#include "wakeups-t11x.h" - -#define GPIO_KEY(_id, _gpio, _iswake) \ - { \ - .code = _id, \ - .gpio = TEGRA_GPIO_##_gpio, \ - .active_low = 1, \ - .desc = #_id, \ - .type = EV_KEY, \ - .wakeup = _iswake, \ - .debounce_interval = 10, \ - } - -static struct gpio_keys_button macallan_e1545_keys[] = { - [0] = GPIO_KEY(KEY_POWER, PQ0, 1), - [1] = GPIO_KEY(KEY_VOLUMEUP, PR2, 0), - [2] = GPIO_KEY(KEY_VOLUMEDOWN, PR1, 0), - [3] = GPIO_KEY(KEY_HOME, PI5, 0), - [4] = GPIO_KEY(KEY_BACK, PQ2, 0), /* Todo : CAMF */ - [5] = GPIO_KEY(KEY_MENU, PR0, 0), /* Todo : CAMS */ -}; - -static int macallan_wakeup_key(void) -{ - int wakeup_key; - u64 status = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS) - | (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE) - + PMC_WAKE2_STATUS) << 32; - if (status & ((u64)1 << TEGRA_WAKE_GPIO_PQ0)) - wakeup_key = KEY_POWER; - else if (status & ((u64)1 << TEGRA_WAKE_GPIO_PS0)) - wakeup_key = SW_LID; - else - wakeup_key = KEY_RESERVED; - - return wakeup_key; -} - -static struct gpio_keys_platform_data macallan_e1545_keys_pdata = { - .buttons = macallan_e1545_keys, - .nbuttons = ARRAY_SIZE(macallan_e1545_keys), - .wakeup_key = macallan_wakeup_key, -}; - -static struct platform_device macallan_e1545_keys_device = { - .name = "gpio-keys", - .id = 0, - .dev = { - .platform_data = &macallan_e1545_keys_pdata, - }, -}; - -int __init macallan_kbc_init(void) -{ - platform_device_register(&macallan_e1545_keys_device); - - return 0; -} - diff --git a/arch/arm/mach-tegra/board-macallan-memory.c b/arch/arm/mach-tegra/board-macallan-memory.c deleted file mode 100644 index 400d989d37b5..000000000000 --- a/arch/arm/mach-tegra/board-macallan-memory.c +++ /dev/null @@ -1,2010 +0,0 @@ -/* - * Copyright (C) 2013-2014, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include "board.h" -#include "board-macallan.h" - -#include "tegra-board-id.h" -#include "tegra11_emc.h" -#include "devices.h" - -static struct tegra11_emc_table e1545_h5tc4g63mfr_pba_T40S_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000131, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004c, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000b, /* EMC_TXSR */ - 0x0000000b, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000036b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0006c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0006c000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000e, /* EMC_RC */ - 0x00000050, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000009, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x00000009, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004d, /* EMC_AR2PDEN */ - 0x0000000e, /* EMC_RW2PDEN */ - 0x00000055, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000d, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000986, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT */ - 0x0171000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ - 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00028000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00028000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x5320000e, /* EMC_CFG */ - 0x80000321, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 2180, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00028000, /* EMC_DLL_XFORM_DQS4 */ - 0x00028000, /* EMC_DLL_XFORM_DQS5 */ - 0x00028000, /* EMC_DLL_XFORM_DQS6 */ - 0x00028000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00028000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS1 */ - 0x00028000, /* EMC_DLL_XFORM_DQS2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00028000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00014000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00014000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS1 */ - 0x00028000, /* EMC_DLL_XFORM_DQS2 */ - 0x00028000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001d, /* EMC_RC */ - 0x000000a1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000014, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x00000010, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x000012cb, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004b2, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000d, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000009c, /* EMC_AR2PDEN */ - 0x00000015, /* EMC_RW2PDEN */ - 0x000000a9, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000019, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000006, /* EMC_TCLKSTABLE */ - 0x00000007, /* EMC_TCLKSTOP */ - 0x0000130b, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf00d0191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS4 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS5 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS6 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT */ - 0x0122000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80002626, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x0028a28a, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS1 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */ - 0x007fc00a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000009, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000b61, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200010, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1230, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000025, /* EMC_RC */ - 0x000000cd, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001a, /* EMC_RAS */ - 0x00000009, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x00000009, /* EMC_RD_RCD */ - 0x00000009, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x00000006, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000017ee, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005fb, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000012, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000c6, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x000000d7, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x0000182f, /* EMC_TREFBW */ - 0x0000000a, /* EMC_QUSE_EXTRA */ - 0x80000000, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000008, /* EMC_DLL_XFORM_DQS4 */ - 0x00000008, /* EMC_DLL_XFORM_DQS5 */ - 0x00000008, /* EMC_DLL_XFORM_DQS6 */ - 0x00000008, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07076604, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000c, /* EMC_MRS_WAIT_CNT */ - 0x00f8000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000302b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000008, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410400, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000008, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000b0b, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS1 */ - 0x00000008, /* EMC_DLL_XFORM_DQS2 */ - 0x00000008, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x00000001, /* EMC_AUTO_CAL_INTERVAL */ - 0x53200000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200418, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_pdata e1545_h5tc4g63mfr_pba_T40S_pdata = { - .description = "e1545_h5tc4g63mfr_pba_T40S", - .tables = e1545_h5tc4g63mfr_pba_T40S_table, - .num_tables = ARRAY_SIZE(e1545_h5tc4g63mfr_pba_T40S_table), -}; - -static struct tegra11_emc_pdata *macallan_get_emc_data(void) -{ - return &e1545_h5tc4g63mfr_pba_T40S_pdata; -} - -int __init macallan_emc_init(void) -{ - tegra_emc_device.dev.platform_data = macallan_get_emc_data(); - platform_device_register(&tegra_emc_device); - tegra11_emc_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-macallan-panel.c b/arch/arm/mach-tegra/board-macallan-panel.c deleted file mode 100644 index 36d7d758cc37..000000000000 --- a/arch/arm/mach-tegra/board-macallan-panel.c +++ /dev/null @@ -1,450 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan-panel.c - * - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <linux/ioport.h> -#include <linux/fb.h> -#include <linux/nvmap.h> -#include <linux/nvhost.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> - -#include <mach/irqs.h> -#include <mach/dc.h> - -#include "board.h" -#include "devices.h" -#include "gpio-names.h" -#include "board-panel.h" -#include "common.h" -#include "iomap.h" -#include "tegra11_host1x_devices.h" - -#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH5 -#define DSI_PANEL_BL_PWM_GPIO TEGRA_GPIO_PH1 - -struct platform_device * __init macallan_host1x_init(void) -{ - struct platform_device *pdev = NULL; - -#ifdef CONFIG_TEGRA_GRHOST - if (!of_have_populated_dt()) - pdev = tegra11_register_host1x_devices(); - else - pdev = to_platform_device(bus_find_device_by_name( - &platform_bus_type, NULL, "host1x")); -#endif - return pdev; -} - -#ifdef CONFIG_TEGRA_DC - -/* HDMI Hotplug detection pin */ -#define macallan_hdmi_hpd TEGRA_GPIO_PN7 - -static struct regulator *macallan_hdmi_reg; -static struct regulator *macallan_hdmi_pll; -static struct regulator *macallan_hdmi_vddio; - -static struct resource macallan_disp1_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_GENERAL, - .end = INT_DISPLAY_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY_BASE, - .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by macallan_panel_init() */ - .end = 0, /* Filled in by macallan_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsia_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsib_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "dsi_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "mipi_cal", - .start = TEGRA_MIPI_CAL_BASE, - .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource macallan_disp2_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_B_GENERAL, - .end = INT_DISPLAY_B_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY2_BASE, - .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by macallan_panel_init() */ - .end = 0, /* Filled in by macallan_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "hdmi_regs", - .start = TEGRA_HDMI_BASE, - .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - - -static struct tegra_dc_sd_settings sd_settings; - -static struct tegra_dc_out macallan_disp1_out = { - .type = TEGRA_DC_OUT_DSI, - .sd_settings = &sd_settings, -}; - -static int macallan_hdmi_enable(struct device *dev) -{ - int ret; - if (!macallan_hdmi_reg) { - macallan_hdmi_reg = regulator_get(dev, "avdd_hdmi"); - if (IS_ERR(macallan_hdmi_reg)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); - macallan_hdmi_reg = NULL; - return PTR_ERR(macallan_hdmi_reg); - } - } - ret = regulator_enable(macallan_hdmi_reg); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); - return ret; - } - if (!macallan_hdmi_pll) { - macallan_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll"); - if (IS_ERR(macallan_hdmi_pll)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); - macallan_hdmi_pll = NULL; - regulator_put(macallan_hdmi_reg); - macallan_hdmi_reg = NULL; - return PTR_ERR(macallan_hdmi_pll); - } - } - ret = regulator_enable(macallan_hdmi_pll); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); - return ret; - } - return 0; -} - -static int macallan_hdmi_disable(void) -{ - if (macallan_hdmi_reg) { - regulator_disable(macallan_hdmi_reg); - regulator_put(macallan_hdmi_reg); - macallan_hdmi_reg = NULL; - } - - if (macallan_hdmi_pll) { - regulator_disable(macallan_hdmi_pll); - regulator_put(macallan_hdmi_pll); - macallan_hdmi_pll = NULL; - } - - return 0; -} - -static int macallan_hdmi_postsuspend(void) -{ - if (macallan_hdmi_vddio) { - regulator_disable(macallan_hdmi_vddio); - regulator_put(macallan_hdmi_vddio); - macallan_hdmi_vddio = NULL; - } - return 0; -} - -static int macallan_hdmi_hotplug_init(struct device *dev) -{ - int e = 0; - - if (!macallan_hdmi_vddio) { - macallan_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0"); - if (WARN_ON(IS_ERR(macallan_hdmi_vddio))) { - e = PTR_ERR(macallan_hdmi_vddio); - pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %d\n", - __func__, e); - macallan_hdmi_vddio = NULL; - } else { - e = regulator_enable(macallan_hdmi_vddio); - mdelay(5); - } - } - - return e; -} - -static struct tegra_dc_out macallan_disp2_out = { - .type = TEGRA_DC_OUT_HDMI, - .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, - .parent_clk = "pll_d2_out0", - - .ddc_bus = 3, - .hotplug_gpio = macallan_hdmi_hpd, - - .max_pixclock = KHZ2PICOS(297000), - - .align = TEGRA_DC_ALIGN_MSB, - .order = TEGRA_DC_ORDER_RED_BLUE, - - .enable = macallan_hdmi_enable, - .disable = macallan_hdmi_disable, - .postsuspend = macallan_hdmi_postsuspend, - .hotplug_init = macallan_hdmi_hotplug_init, -}; - -static struct tegra_fb_data macallan_disp1_fb_data = { - .win = 0, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data macallan_disp1_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &macallan_disp1_out, - .fb = &macallan_disp1_fb_data, - .emc_clk_rate = 204000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct tegra_fb_data macallan_disp2_fb_data = { - .win = 0, - .xres = 1024, - .yres = 600, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data macallan_disp2_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &macallan_disp2_out, - .fb = &macallan_disp2_fb_data, - .emc_clk_rate = 300000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct platform_device macallan_disp2_device = { - .name = "tegradc", - .id = 1, - .resource = macallan_disp2_resources, - .num_resources = ARRAY_SIZE(macallan_disp2_resources), - .dev = { - .platform_data = &macallan_disp2_pdata, - }, -}; - -static struct platform_device macallan_disp1_device = { - .name = "tegradc", - .id = 0, - .resource = macallan_disp1_resources, - .num_resources = ARRAY_SIZE(macallan_disp1_resources), - .dev = { - .platform_data = &macallan_disp1_pdata, - }, -}; - -static struct nvmap_platform_carveout macallan_carveouts[] = { - [0] = { - .name = "iram", - .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, - .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, - .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, - }, - [1] = { - .name = "generic-0", - .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, - .base = 0, /* Filled in by macallan_panel_init() */ - .size = 0, /* Filled in by macallan_panel_init() */ - }, - [2] = { - .name = "vpr", - .usage_mask = NVMAP_HEAP_CARVEOUT_VPR, - .base = 0, /* Filled in by macallan_panel_init() */ - .size = 0, /* Filled in by macallan_panel_init() */ - }, -}; - -static struct nvmap_platform_data macallan_nvmap_data = { - .carveouts = macallan_carveouts, - .nr_carveouts = ARRAY_SIZE(macallan_carveouts), -}; -static struct platform_device macallan_nvmap_device = { - .name = "tegra-nvmap", - .id = -1, - .dev = { - .platform_data = &macallan_nvmap_data, - }, -}; - -static void macallan_panel_select(void) -{ - struct tegra_panel *panel = NULL; - struct board_info board; - u8 dsi_instance = DSI_INSTANCE_0; - - tegra_get_display_board_info(&board); - - switch (board.board_id) { - case BOARD_E1639: - panel = &dsi_s_wqxga_10_1; - break; - default: - panel = &dsi_p_wuxga_10_1; - break; - } - if (panel) { - if (panel->init_sd_settings) - panel->init_sd_settings(&sd_settings); - - if (panel->init_dc_out) { - panel->init_dc_out(&macallan_disp1_out); - macallan_disp1_out.dsi->dsi_instance = dsi_instance; - macallan_disp1_out.dsi->dsi_panel_rst_gpio = - DSI_PANEL_RST_GPIO; - macallan_disp1_out.dsi->dsi_panel_bl_pwm_gpio = - DSI_PANEL_BL_PWM_GPIO; - } - - if (panel->init_fb_data) - panel->init_fb_data(&macallan_disp1_fb_data); - - if (panel->init_cmu_data) - panel->init_cmu_data(&macallan_disp1_pdata); - - if (panel->set_disp_device) - panel->set_disp_device(&macallan_disp1_device); - - tegra_dsi_resources_init(dsi_instance, macallan_disp1_resources, - ARRAY_SIZE(macallan_disp1_resources)); - - if (panel->register_bl_dev) - panel->register_bl_dev(); - - if (panel->register_i2c_bridge) - panel->register_i2c_bridge(); - } - -} -int __init macallan_panel_init(void) -{ - int err = 0; - struct resource __maybe_unused *res; - struct platform_device *phost1x = NULL; - - macallan_panel_select(); - -#ifdef CONFIG_TEGRA_NVMAP - macallan_carveouts[1].base = tegra_carveout_start; - macallan_carveouts[1].size = tegra_carveout_size; - macallan_carveouts[2].base = tegra_vpr_start; - macallan_carveouts[2].size = tegra_vpr_size; - - err = platform_device_register(&macallan_nvmap_device); - if (err) { - pr_err("nvmap device registration failed\n"); - return err; - } -#endif - - phost1x = macallan_host1x_init(); - if (!phost1x) { - pr_err("host1x devices registration failed\n"); - return -EINVAL; - } - - res = platform_get_resource_byname(&macallan_disp1_device, - IORESOURCE_MEM, "fbmem"); - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; - - /* Copy the bootloader fb to the fb. */ - __tegra_move_framebuffer(&macallan_nvmap_device, - tegra_fb_start, tegra_bootloader_fb_start, - min(tegra_fb_size, tegra_bootloader_fb_size)); - - macallan_disp1_device.dev.parent = &phost1x->dev; - err = platform_device_register(&macallan_disp1_device); - if (err) { - pr_err("disp1 device registration failed\n"); - return err; - } - - err = tegra_init_hdmi(&macallan_disp2_device, phost1x); - if (err) - return err; - -#ifdef CONFIG_TEGRA_NVAVP - nvavp_device.dev.parent = &phost1x->dev; - err = platform_device_register(&nvavp_device); - if (err) { - pr_err("nvavp device registration failed\n"); - return err; - } -#endif - return err; -} -#else -int __init macallan_panel_init(void) -{ - if (macallan_host1x_init()) - return 0; - else - return -EINVAL; -} -#endif diff --git a/arch/arm/mach-tegra/board-macallan-power.c b/arch/arm/mach-tegra/board-macallan-power.c deleted file mode 100644 index a6c022e26fc8..000000000000 --- a/arch/arm/mach-tegra/board-macallan-power.c +++ /dev/null @@ -1,890 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan-power.c - * - * Copyright (C) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/pda_power.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/io.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/driver.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/palmas.h> -#include <linux/power/bq2419x-charger.h> -#include <linux/max17048_battery.h> -#include <linux/power/power_supply_extcon.h> -#include <linux/gpio.h> -#include <linux/interrupt.h> -#include <linux/regulator/userspace-consumer.h> -#include <linux/pid_thermal_gov.h> -#include <linux/tegra-soc.h> -#include <linux/tegra-pmc.h> - -#include <asm/mach-types.h> -#include <linux/power/sbs-battery.h> - -#include <mach/irqs.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> - -#include "cpu-tegra.h" -#include "pm.h" -#include "tegra-board-id.h" -#include "board-pmu-defines.h" -#include "board.h" -#include "gpio-names.h" -#include "board-common.h" -#include "board-macallan.h" -#include "tegra_cl_dvfs.h" -#include "devices.h" -#include "tegra11_soctherm.h" -#include "iomap.h" -#include "battery-ini-model-data.h" - -#define PMC_CTRL 0x0 -#define PMC_CTRL_INTR_LOW (1 << 17) - -/* BQ2419X VBUS regulator */ -static struct regulator_consumer_supply bq2419x_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"), - REGULATOR_SUPPLY("usb_vbus", "tegra-otg"), -}; - -static struct regulator_consumer_supply bq2419x_batt_supply[] = { - REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"), -}; - -static struct bq2419x_vbus_platform_data macallan_bq2419x_vbus_pdata = { - .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply), - .consumer_supplies = bq2419x_vbus_supply, -}; - -struct bq2419x_charger_platform_data macallan_bq2419x_charger_pdata = { - .max_charge_current_mA = 3000, - .termination_current_limit_mA = 100, - .consumer_supplies = bq2419x_batt_supply, - .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply), - .wdt_timeout = 40, - .rtc_alarm_time = 3600, - .chg_restart_time = 1800, -}; - -struct max17048_platform_data macallan_max17048_pdata = { - .model_data = &macallan_yoku_4100mA_max17048_battery, -}; - -static struct i2c_board_info __initdata macallan_max17048_boardinfo[] = { - { - I2C_BOARD_INFO("max17048", 0x36), - .platform_data = &macallan_max17048_pdata, - }, -}; - -struct bq2419x_platform_data macallan_bq2419x_pdata = { - .vbus_pdata = &macallan_bq2419x_vbus_pdata, - .bcharger_pdata = &macallan_bq2419x_charger_pdata, -}; - -static struct i2c_board_info __initdata bq2419x_boardinfo[] = { - { - I2C_BOARD_INFO("bq2419x", 0x6b), - .platform_data = &macallan_bq2419x_pdata, - }, -}; - -static struct power_supply_extcon_plat_data psy_extcon_pdata = { - .extcon_name = "tegra-udc", -}; - -static struct platform_device psy_extcon_device = { - .name = "power-supply-extcon", - .id = -1, - .dev = { - .platform_data = &psy_extcon_pdata, - }, -}; - -/************************ Macallan based regulator ****************/ -static struct regulator_consumer_supply palmas_smps123_supply[] = { - REGULATOR_SUPPLY("vdd_cpu", NULL), -}; - -static struct regulator_consumer_supply palmas_smps45_supply[] = { - REGULATOR_SUPPLY("vdd_core", NULL), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"), -}; - -static struct regulator_consumer_supply palmas_smps6_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_hv", NULL), - REGULATOR_SUPPLY("avdd_lcd", NULL), - REGULATOR_SUPPLY("avdd", "spi0.0"), -}; - -static struct regulator_consumer_supply palmas_smps7_supply[] = { - REGULATOR_SUPPLY("vddio_ddr", NULL), -}; - -static struct regulator_consumer_supply palmas_smps8_supply[] = { - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_osc", NULL), - REGULATOR_SUPPLY("vddio_sys", NULL), - REGULATOR_SUPPLY("vddio_bb", NULL), - REGULATOR_SUPPLY("pwrdet_bb", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"), - REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), - REGULATOR_SUPPLY("vddio_audio", NULL), - REGULATOR_SUPPLY("pwrdet_audio", NULL), - REGULATOR_SUPPLY("vddio_uart", NULL), - REGULATOR_SUPPLY("pwrdet_uart", NULL), - REGULATOR_SUPPLY("vddio_gmi", NULL), - REGULATOR_SUPPLY("pwrdet_nand", NULL), - REGULATOR_SUPPLY("vlogic", "0-0069"), - REGULATOR_SUPPLY("vid", "0-000d"), - REGULATOR_SUPPLY("vddio", "0-0078"), - REGULATOR_SUPPLY("vdd", "0-004c"), -}; - -static struct regulator_consumer_supply palmas_smps9_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"), - REGULATOR_SUPPLY("vddio_hv", "tegradc.1"), - REGULATOR_SUPPLY("pwrdet_hv", NULL), -}; - -static struct regulator_consumer_supply palmas_smps10_out1_supply[] = { -}; - -static struct regulator_consumer_supply palmas_ldo1_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo2_supply[] = { - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_dsi_csi", "vi"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"), - REGULATOR_SUPPLY("pwrdet_mipi", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo3_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo4_supply[] = { - REGULATOR_SUPPLY("vdd_1v2_cam", NULL), - REGULATOR_SUPPLY("dvdd", "2-0010"), - REGULATOR_SUPPLY("vdig", "2-0036"), -}; - -static struct regulator_consumer_supply palmas_ldo5_supply[] = { - REGULATOR_SUPPLY("avdd_cam2", NULL), - REGULATOR_SUPPLY("avdd", "2-0010"), -}; - -static struct regulator_consumer_supply palmas_ldo5_e1569_supply[] = { - REGULATOR_SUPPLY("avdd_cam2", NULL), - REGULATOR_SUPPLY("avdd", "2-0010"), - REGULATOR_SUPPLY("vdd_af_cam1", NULL), - REGULATOR_SUPPLY("vdd", "2-000e"), -}; - -static struct regulator_consumer_supply palmas_ldo6_supply[] = { - REGULATOR_SUPPLY("vdd", "0-0069"), - REGULATOR_SUPPLY("vdd", "0-000d"), - REGULATOR_SUPPLY("vdd", "0-0078"), -}; - -static struct regulator_consumer_supply palmas_ldo7_supply[] = { - REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL), - REGULATOR_SUPPLY("vdd_af_cam1", NULL), - REGULATOR_SUPPLY("avdd_cam1", NULL), - REGULATOR_SUPPLY("vana", "2-0036"), - REGULATOR_SUPPLY("vdd", "2-000e"), -}; - -static struct regulator_consumer_supply palmas_ldo7_e1569_supply[] = { - REGULATOR_SUPPLY("avdd_2v8_cam_af", NULL), - REGULATOR_SUPPLY("avdd_cam1", NULL), - REGULATOR_SUPPLY("vana", "2-0036"), -}; - -static struct regulator_consumer_supply palmas_ldo8_supply[] = { - REGULATOR_SUPPLY("vdd_rtc", NULL), -}; -static struct regulator_consumer_supply palmas_ldo9_supply[] = { - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"), - REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), -}; -static struct regulator_consumer_supply palmas_ldoln_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), -}; - -static struct regulator_consumer_supply palmas_ldousb_supply[] = { - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), - -}; - -static struct regulator_consumer_supply palmas_regen1_supply[] = { -}; - -static struct regulator_consumer_supply palmas_regen2_supply[] = { -}; - -PALMAS_REGS_PDATA(smps123, 900, 1350, NULL, 0, 0, 0, 0, - 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 0, 0); -PALMAS_REGS_PDATA(smps45, 900, 1400, NULL, 0, 0, 0, 0, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(smps6, 3200, 3200, NULL, 0, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps7, 1350, 1350, NULL, 0, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps9, 2900, 2900, NULL, 1, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps10_out1, 5000, 5000, NULL, 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo1, 1050, 1050, palmas_rails(smps7), 1, 0, 1, 0, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(ldo2, 1200, 1200, palmas_rails(smps7), 0, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo3, 1800, 1800, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo4, 1200, 1200, palmas_rails(smps8), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo5, 2800, 2800, palmas_rails(smps9), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo6, 2850, 2850, palmas_rails(smps9), 1, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo7, 2700, 2700, palmas_rails(smps9), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo8, 950, 950, NULL, 1, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo9, 1800, 2900, palmas_rails(smps9), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldoln, 3300, 3300, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldousb, 3300, 3300, NULL, 0, 0, 1, 0, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(regen1, 4200, 4200, NULL, 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(regen2, 4200, 4200, palmas_rails(smps8), 0, 0, 0, 0, - 0, 0, 0, 0, 0); - -#define PALMAS_REG_PDATA(_sname) (®_idata_##_sname) -static struct regulator_init_data *macallan_reg_data[PALMAS_NUM_REGS] = { - NULL, - PALMAS_REG_PDATA(smps123), - NULL, - PALMAS_REG_PDATA(smps45), - NULL, - PALMAS_REG_PDATA(smps6), - PALMAS_REG_PDATA(smps7), - PALMAS_REG_PDATA(smps8), - PALMAS_REG_PDATA(smps9), - NULL, - PALMAS_REG_PDATA(smps10_out1), - PALMAS_REG_PDATA(ldo1), - PALMAS_REG_PDATA(ldo2), - PALMAS_REG_PDATA(ldo3), - PALMAS_REG_PDATA(ldo4), - PALMAS_REG_PDATA(ldo5), - PALMAS_REG_PDATA(ldo6), - PALMAS_REG_PDATA(ldo7), - PALMAS_REG_PDATA(ldo8), - PALMAS_REG_PDATA(ldo9), - PALMAS_REG_PDATA(ldoln), - PALMAS_REG_PDATA(ldousb), - PALMAS_REG_PDATA(regen1), - PALMAS_REG_PDATA(regen2), - NULL, - NULL, - NULL, -}; - -#define PALMAS_REG_INIT_DATA(_sname) (®_init_data_##_sname) -static struct palmas_reg_init *macallan_reg_init[PALMAS_NUM_REGS] = { - NULL, - PALMAS_REG_INIT_DATA(smps123), - NULL, - PALMAS_REG_INIT_DATA(smps45), - NULL, - PALMAS_REG_INIT_DATA(smps6), - PALMAS_REG_INIT_DATA(smps7), - PALMAS_REG_INIT_DATA(smps8), - PALMAS_REG_INIT_DATA(smps9), - NULL, - PALMAS_REG_INIT_DATA(smps10_out1), - PALMAS_REG_INIT_DATA(ldo1), - PALMAS_REG_INIT_DATA(ldo2), - PALMAS_REG_INIT_DATA(ldo3), - PALMAS_REG_INIT_DATA(ldo4), - PALMAS_REG_INIT_DATA(ldo5), - PALMAS_REG_INIT_DATA(ldo6), - PALMAS_REG_INIT_DATA(ldo7), - PALMAS_REG_INIT_DATA(ldo8), - PALMAS_REG_INIT_DATA(ldo9), - PALMAS_REG_INIT_DATA(ldoln), - PALMAS_REG_INIT_DATA(ldousb), - PALMAS_REG_INIT_DATA(regen1), - PALMAS_REG_INIT_DATA(regen2), - NULL, - NULL, - NULL, -}; - -static struct palmas_pmic_platform_data pmic_platform = { - .disable_smps10_boost_suspend = true, -}; - -static struct palmas_pinctrl_config palmas_pincfg[] = { - PALMAS_PINMUX("powergood", "powergood", NULL, NULL), - PALMAS_PINMUX("vac", "vac", NULL, NULL), - PALMAS_PINMUX("gpio0", "id", "pull-up", NULL), - PALMAS_PINMUX("gpio1", "vbus_det", NULL, NULL), - PALMAS_PINMUX("gpio2", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio3", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio4", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio5", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio6", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio7", "gpio", NULL, NULL), -}; - -static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = { - .pincfg = palmas_pincfg, - .num_pinctrl = ARRAY_SIZE(palmas_pincfg), - .dvfs1_enable = true, - .dvfs2_enable = false, -}; - -static struct palmas_extcon_platform_data palmas_extcon_pdata = { - .connection_name = "palmas-extcon", - .enable_vbus_detection = true, - .enable_id_pin_detection = true, -}; - -static struct palmas_platform_data palmas_pdata = { - .gpio_base = PALMAS_TEGRA_GPIO_BASE, - .irq_base = PALMAS_TEGRA_IRQ_BASE, - .pmic_pdata = &pmic_platform, - .pinctrl_pdata = &palmas_pinctrl_pdata, - .extcon_pdata = &palmas_extcon_pdata, -}; - -static struct i2c_board_info palma_device[] = { - { - I2C_BOARD_INFO("tps65913", 0x58), - .irq = INT_EXTERNAL_PMU, - .platform_data = &palmas_pdata, - }, -}; - -static struct regulator_consumer_supply fixed_reg_dvdd_lcd_1v8_supply[] = { - REGULATOR_SUPPLY("dvdd_lcd", NULL), -}; - -static struct regulator_consumer_supply fixed_reg_vdd_lcd_bl_en_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL), -}; - -/* EN_1V8_TS From TEGRA_GPIO_PH4 */ -static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = { - REGULATOR_SUPPLY("dvdd", "spi0.0"), -}; - -/* ENABLE 5v0 for HDMI */ -static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = { - REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"), -}; - -static struct regulator_consumer_supply fixed_reg_vddio_sd_slot_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"), -}; - -static struct regulator_consumer_supply fixed_reg_vd_cam_1v8_supply[] = { - REGULATOR_SUPPLY("vdd_cam_1v8", NULL), - REGULATOR_SUPPLY("vi2c", "2-0030"), - REGULATOR_SUPPLY("vif", "2-0036"), - REGULATOR_SUPPLY("dovdd", "2-0010"), - REGULATOR_SUPPLY("vdd_i2c", "2-000e"), - REGULATOR_SUPPLY("vddio_cam", "vi"), - REGULATOR_SUPPLY("pwrdet_cam", NULL), -}; - -/* Macro for defining fixed regulator sub device data */ -#define FIXED_SUPPLY(_name) "fixed_reg_"#_name -#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ - _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \ - static struct regulator_init_data ri_data_##_var = \ - { \ - .supply_regulator = _in_supply, \ - .num_consumer_supplies = \ - ARRAY_SIZE(fixed_reg_##_name##_supply), \ - .consumer_supplies = fixed_reg_##_name##_supply, \ - .constraints = { \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - }, \ - }; \ - static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ - { \ - .supply_name = FIXED_SUPPLY(_name), \ - .microvolts = _millivolts * 1000, \ - .gpio = _gpio_nr, \ - .gpio_is_open_drain = _open_drain, \ - .enable_high = _active_high, \ - .enabled_at_boot = _boot_state, \ - .init_data = &ri_data_##_var, \ - }; \ - static struct platform_device fixed_reg_##_var##_dev = { \ - .name = "reg-fixed-voltage", \ - .id = _id, \ - .dev = { \ - .platform_data = &fixed_reg_##_var##_pdata, \ - }, \ - } - -/* - * Creating the fixed regulator device table - */ - -FIXED_REG(1, dvdd_lcd_1v8, dvdd_lcd_1v8, - palmas_rails(smps8), 0, 1, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 1, 1800); - -FIXED_REG(2, vdd_lcd_bl_en, vdd_lcd_bl_en, - NULL, 0, 1, - TEGRA_GPIO_PH2, false, true, 1, 3700); - -FIXED_REG(3, dvdd_ts, dvdd_ts, - palmas_rails(smps8), 0, 0, - TEGRA_GPIO_PH4, false, false, 1, 1800); - -FIXED_REG(4, vdd_hdmi_5v0, vdd_hdmi_5v0, - palmas_rails(smps10_out1), 0, 0, - TEGRA_GPIO_PK6, true, true, 0, 5000); - -FIXED_REG(5, vddio_sd_slot, vddio_sd_slot, - palmas_rails(smps9), 0, 0, - TEGRA_GPIO_PK1, false, true, 0, 2900); - -FIXED_REG(6, vd_cam_1v8, vd_cam_1v8, - palmas_rails(smps8), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 1800); - -#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) - -/* Gpio switch regulator platform data for Macallan E1545 */ -static struct platform_device *fixed_reg_devs[] = { - ADD_FIXED_REG(dvdd_lcd_1v8), - ADD_FIXED_REG(vdd_lcd_bl_en), - ADD_FIXED_REG(dvdd_ts), - ADD_FIXED_REG(vdd_hdmi_5v0), - ADD_FIXED_REG(vddio_sd_slot), - ADD_FIXED_REG(vd_cam_1v8), -}; - - -int __init macallan_palmas_regulator_init(void) -{ - void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - u32 pmc_ctrl; - int i; - struct board_info board_info; - - /* TPS65913: Normal state of INT request line is LOW. - * configure the power management controller to trigger PMU - * interrupts when HIGH. - */ - pmc_ctrl = readl(pmc + PMC_CTRL); - writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); - - /* Tracking configuration */ - reg_init_data_ldo8.config_flags = - PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE | - PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE; - - tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_E1569) { - reg_idata_ldo5.consumer_supplies = palmas_ldo5_e1569_supply; - reg_idata_ldo5.num_consumer_supplies = - ARRAY_SIZE(palmas_ldo5_e1569_supply); - reg_idata_ldo7.consumer_supplies = palmas_ldo7_e1569_supply; - reg_idata_ldo7.num_consumer_supplies = - ARRAY_SIZE(palmas_ldo7_e1569_supply); - } - - for (i = 0; i < PALMAS_NUM_REGS ; i++) { - pmic_platform.reg_data[i] = macallan_reg_data[i]; - pmic_platform.reg_init[i] = macallan_reg_init[i]; - } - - i2c_register_board_info(4, palma_device, - ARRAY_SIZE(palma_device)); - - return 0; -} - -static int ac_online(void) -{ - return 1; -} - -static struct resource macallan_pda_resources[] = { - [0] = { - .name = "ac", - }, -}; - -static struct pda_power_pdata macallan_pda_data = { - .is_ac_online = ac_online, -}; - -static struct platform_device macallan_pda_power_device = { - .name = "pda-power", - .id = -1, - .resource = macallan_pda_resources, - .num_resources = ARRAY_SIZE(macallan_pda_resources), - .dev = { - .platform_data = &macallan_pda_data, - }, -}; - -static void macallan_board_suspend(int state, enum suspend_stage stage) -{ -} - -static struct tegra_suspend_platform_data macallan_suspend_data = { - .cpu_timer = 300, - .cpu_off_timer = 300, - .suspend_mode = TEGRA_SUSPEND_LP0, - .core_timer = 0x157e, - .core_off_timer = 2000, - .corereq_high = true, - .sysclkreq_high = true, - .cpu_lp2_min_residency = 1000, - .min_residency_crail = 20000, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .lp1_lowvolt_support = false, - .i2c_base_addr = 0, - .pmuslave_addr = 0, - .core_reg_addr = 0, - .lp1_core_volt_low_cold = 0, - .lp1_core_volt_low = 0, - .lp1_core_volt_high = 0, -#endif - .board_suspend = macallan_board_suspend, -}; -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -/* board parameters for cpu dfll */ -static struct tegra_cl_dvfs_cfg_param macallan_cl_dvfs_param = { - .sample_rate = 12500, - - .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, - .cf = 10, - .ci = 0, - .cg = 2, - - .droop_cut_value = 0xF, - .droop_restore_ramp = 0x0, - .scale_out_ramp = 0x0, -}; -#endif - -/* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */ -#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) -static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; -static inline void fill_reg_map(void) -{ - int i; - for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { - pmu_cpu_vdd_map[i].reg_value = i + 0x10; - pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; - } -} - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static struct tegra_cl_dvfs_platform_data macallan_cl_dvfs_data = { - .dfll_clk_name = "dfll_cpu", - .pmu_if = TEGRA_CL_DVFS_PMU_I2C, - .u.pmu_i2c = { - .fs_rate = 400000, - .slave_addr = 0xb0, - .reg = 0x23, - }, - .vdd_map = pmu_cpu_vdd_map, - .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, - .pmu_undershoot_gb = 100, - - .cfg_param = &macallan_cl_dvfs_param, -}; - -static int __init macallan_cl_dvfs_init(void) -{ - fill_reg_map(); - if (tegra_revision < TEGRA_REVISION_A02) - macallan_cl_dvfs_data.flags = - TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET; - tegra_cl_dvfs_device.dev.platform_data = &macallan_cl_dvfs_data; - platform_device_register(&tegra_cl_dvfs_device); - - return 0; -} -#endif - -static int __init macallan_fixed_regulator_init(void) -{ - if (!of_machine_is_compatible("nvidia,macallan")) - return 0; - - return platform_add_devices(fixed_reg_devs, - ARRAY_SIZE(fixed_reg_devs)); -} -subsys_initcall_sync(macallan_fixed_regulator_init); - -int __init macallan_regulator_init(void) -{ - struct board_info board_info; - tegra_get_board_info(&board_info); - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - macallan_cl_dvfs_init(); -#endif - macallan_palmas_regulator_init(); - - if (board_info.board_id == BOARD_E1569) { - if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY) { - /* Disable charger when adapter is power source. */ - macallan_bq2419x_pdata.bcharger_pdata = NULL; - } else { - /* Only register fuel gauge when using battery. */ - i2c_register_board_info(0, macallan_max17048_boardinfo, - 1); - } - } else { - /* forced make null to prevent charging for E1545. */ - macallan_bq2419x_pdata.bcharger_pdata = NULL; - } - - bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0); - i2c_register_board_info(0, bq2419x_boardinfo, - ARRAY_SIZE(bq2419x_boardinfo)); - - platform_device_register(&psy_extcon_device); - platform_device_register(&macallan_pda_power_device); - - return 0; -} - -int __init macallan_suspend_init(void) -{ - tegra_init_suspend(&macallan_suspend_data); - return 0; -} - -int __init macallan_edp_init(void) -{ - unsigned int regulator_mA; - - regulator_mA = get_maximum_cpu_current_supported(); - if (!regulator_mA) - regulator_mA = 15000; - - pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); - tegra_init_cpu_edp_limits(regulator_mA); - - regulator_mA = get_maximum_core_current_supported(); - if (!regulator_mA) - regulator_mA = 4000; - - pr_info("%s: core regulator %d mA\n", __func__, regulator_mA); - tegra_init_core_edp_limits(regulator_mA); - - return 0; -} - -static struct pid_thermal_gov_params soctherm_cpu_pid_params = { - .max_err_temp = 9000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 20, - .down_compensation = 20, -}; - -static struct thermal_zone_params macallan_soctherm_therm_cpu_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &soctherm_cpu_pid_params, -}; - -static struct tegra_thermtrip_pmic_data tpdata_palmas = { - .reset_tegra = 1, - .pmu_16bit_ops = 0, - .controller_type = 0, - .pmu_i2c_addr = 0x58, - .i2c_controller_id = 4, - .poweroff_reg_addr = 0xa0, - .poweroff_reg_data = 0x0, -}; - -static struct soctherm_platform_data macallan_soctherm_data = { - .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE, - .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ, - .therm = { - [THERM_CPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &macallan_soctherm_therm_cpu_tzp, - }, - [THERM_GPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &macallan_soctherm_therm_cpu_tzp, - }, - [THERM_PLL] = { - .zone_enable = true, - }, - }, - .throttle = { - [THROTTLE_HEAVY] = { - .priority = 100, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 80, - }, - [THROTTLE_DEV_GPU] = { - .enable = true, - .depth = 80, - }, - }, - }, - [THROTTLE_OC4] = { - .throt_mode = BRIEF, - .polarity = 1, - .intr = true, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 50, - }, - [THROTTLE_DEV_GPU] = { - .enable = true, - .depth = 50, - }, - }, - }, - }, - .tshut_pmu_trip_data = &tpdata_palmas, -}; - -int __init macallan_soctherm_init(void) -{ - struct board_info board_info; - tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_E1545) - tegra_add_all_vmin_trips( - macallan_soctherm_data.therm[THERM_CPU].trips, - &macallan_soctherm_data.therm[THERM_CPU].num_trips); - tegra_platform_edp_init(macallan_soctherm_data.therm[THERM_CPU].trips, - &macallan_soctherm_data.therm[THERM_CPU].num_trips, - 6000); /* edp temperature margin */ - tegra_add_cpu_vmax_trips(macallan_soctherm_data.therm[THERM_CPU].trips, - &macallan_soctherm_data.therm[THERM_CPU].num_trips); - tegra_add_core_edp_trips(macallan_soctherm_data.therm[THERM_CPU].trips, - &macallan_soctherm_data.therm[THERM_CPU].num_trips); - - return tegra11_soctherm_init(&macallan_soctherm_data); -} diff --git a/arch/arm/mach-tegra/board-macallan-sdhci.c b/arch/arm/mach-tegra/board-macallan-sdhci.c deleted file mode 100644 index 732b470fd84d..000000000000 --- a/arch/arm/mach-tegra/board-macallan-sdhci.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan-sdhci.c - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/regulator/consumer.h> -#include <linux/mmc/host.h> -#include <linux/platform_data/mmc-sdhci-tegra.h> - -#include <asm/mach-types.h> -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> -#include <mach/io_dpd.h> -#include <linux/wl12xx.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-macallan.h" -#include "dvfs.h" -#include "iomap.h" - -#define MACALLAN_SD_CD TEGRA_GPIO_PV2 -#define MACALLAN_SD_WP TEGRA_GPIO_PQ4 -#define MACALLAN_WLAN_PWR TEGRA_GPIO_PCC5 -#define MACALLAN_WLAN_RST TEGRA_GPIO_PX7 -#define MACALLAN_WLAN_WOW TEGRA_GPIO_PU5 -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; -static int macallan_wifi_status_register(void (*callback)(int , void *), void *); - -static int macallan_wifi_power(int on); -static int macallan_wifi_set_carddetect(int val); - -static struct wl12xx_platform_data macallan_wl12xx_wlan_data __initdata = { - .board_ref_clock = WL12XX_REFCLOCK_26, - .board_tcxo_clock = 1, - .set_power = macallan_wifi_power, - .set_carddetect = macallan_wifi_set_carddetect, -}; - -#ifdef CONFIG_MMC_EMBEDDED_SDIO -static struct embedded_sdio_data embedded_sdio_data0 = { - .cccr = { - .sdio_vsn = 2, - .multi_block = 1, - .low_speed = 0, - .wide_bus = 0, - .high_power = 1, - .high_speed = 1, - }, - .cis = { - .vendor = 0x02d0, - .device = 0x4329, - }, -}; -#endif - -struct tegra_sdhci_platform_data macallan_tegra_sdhci_platform_data0 = { - .mmc_data = { - .register_status_notify = macallan_wifi_status_register, -#ifdef CONFIG_MMC_EMBEDDED_SDIO - .embedded_sdio = &embedded_sdio_data0, -#endif - .built_in = 0, - .ocr_mask = MMC_OCR_1V8_MASK, - }, -#ifndef CONFIG_MMC_EMBEDDED_SDIO - .pm_flags = MMC_PM_KEEP_POWER, -#endif - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x2, - .trim_delay = 0x2, - .ddr_clk_limit = 41000000, - .uhs_mask = MMC_UHS_MASK_DDR50, - .disable_clock_gate = true, -}; - -#ifndef CONFIG_USE_OF -static struct resource sdhci_resource0[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { - .cd_gpio = MACALLAN_SD_CD, - .wp_gpio = MACALLAN_SD_WP, - .power_gpio = -1, - .tap_delay = 0x3, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, - .uhs_mask = MMC_UHS_MASK_DDR50, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, - .tap_delay = 0x5, - .trim_delay = 0xA, - .ddr_trim_delay = -1, - .ddr_clk_limit = 41000000, - .max_clk_limit = 156000000, - .mmc_data = { - .built_in = 1, - .ocr_mask = MMC_OCR_1V8_MASK, - } -}; - -static struct platform_device tegra_sdhci_device0 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource0, - .num_resources = ARRAY_SIZE(sdhci_resource0), - .dev = { - .platform_data = &macallan_tegra_sdhci_platform_data0, - }, -}; - -static struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), - .dev = { - .platform_data = &tegra_sdhci_platform_data2, - }, -}; - -static struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), - .dev = { - .platform_data = &tegra_sdhci_platform_data3, - }, -}; -#endif - -static int macallan_wifi_status_register( - void (*callback)(int card_present, void *dev_id), - void *dev_id) -{ - if (wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -static int macallan_wifi_set_carddetect(int val) -{ - pr_debug("%s: %d\n", __func__, val); - if (wifi_status_cb) - wifi_status_cb(val, wifi_status_cb_devid); - else - pr_warning("%s: Nobody to notify\n", __func__); - return 0; -} - -static int macallan_wifi_power(int on) -{ - pr_debug("%s: %d\n", __func__, on); - - if (on) { - gpio_set_value(MACALLAN_WLAN_RST, 1); - mdelay(100); - gpio_set_value(MACALLAN_WLAN_RST, 0); - mdelay(100); - gpio_set_value(MACALLAN_WLAN_RST, 1); - mdelay(100); - gpio_set_value(MACALLAN_WLAN_PWR, 1); - mdelay(200); - } else { - gpio_set_value(MACALLAN_WLAN_RST, 0); - mdelay(100); - gpio_set_value(MACALLAN_WLAN_PWR, 0); - } - - return 0; -} - -static int __init macallan_wifi_init(void) -{ - int rc; - - rc = gpio_request(MACALLAN_WLAN_PWR, "wlan_power"); - if (rc) - pr_err("WLAN_PWR gpio request failed:%d\n", rc); - rc = gpio_request(MACALLAN_WLAN_RST, "wlan_rst"); - if (rc) - pr_err("WLAN_RST gpio request failed:%d\n", rc); - rc = gpio_request(MACALLAN_WLAN_WOW, "bcmsdh_sdmmc"); - if (rc) - pr_err("WLAN_WOW gpio request failed:%d\n", rc); - - rc = gpio_direction_output(MACALLAN_WLAN_PWR, 0); - if (rc) - pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc); - rc = gpio_direction_output(MACALLAN_WLAN_RST, 0); - if (rc) - pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc); - rc = gpio_direction_input(MACALLAN_WLAN_WOW); - if (rc) - pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc); - macallan_wl12xx_wlan_data.irq = gpio_to_irq(MACALLAN_WLAN_WOW); - wl12xx_set_platform_data(&macallan_wl12xx_wlan_data); - return 0; -} - -#ifdef CONFIG_TEGRA_PREPOWER_WIFI -static int __init macallan_wifi_prepower(void) -{ - if (!machine_is_macallan()) - return 0; - - macallan_wifi_power(1); - - return 0; -} - -subsys_initcall_sync(macallan_wifi_prepower); -#endif - -int __init macallan_sdhci_init(void) -{ -#ifndef CONFIG_USE_OF - if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200) - && (!(tegra_sdhci_platform_data3.uhs_mask & - MMC_UHS_MASK_DDR50))) - tegra_sdhci_platform_data3.trim_delay = 0; - - int nominal_core_mv; - int min_vcore_override_mv; - int boot_vcore_mv; - - nominal_core_mv = - tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); - if (nominal_core_mv > 0) { - macallan_tegra_sdhci_platform_data0.nominal_vcore_mv = - nominal_core_mv; - tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv; - tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv; - } - min_vcore_override_mv = - tegra_dvfs_rail_get_override_floor(tegra_core_rail); - if (min_vcore_override_mv) { - macallan_tegra_sdhci_platform_data0.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data2.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data3.min_vcore_override_mv = - min_vcore_override_mv; - } - boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail); - if (boot_vcore_mv) { - macallan_tegra_sdhci_platform_data0.boot_vcore_mv = - boot_vcore_mv; - tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv; - } - - if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200) - && (!(tegra_sdhci_platform_data3.uhs_mask & - MMC_UHS_MASK_DDR50))) - tegra_sdhci_platform_data3.trim_delay = 0; - - platform_device_register(&tegra_sdhci_device3); - platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device0); -#endif - macallan_wifi_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-macallan-sensors.c b/arch/arm/mach-tegra/board-macallan-sensors.c deleted file mode 100644 index dfbdeeb7f0cb..000000000000 --- a/arch/arm/mach-tegra/board-macallan-sensors.c +++ /dev/null @@ -1,840 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan-sensors.c - * - * Copyright (c) 2013-2014 NVIDIA CORPORATION, All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * Neither the name of NVIDIA CORPORATION nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/i2c.h> -#include <linux/delay.h> -#include <linux/mpu.h> -#include <linux/regulator/consumer.h> -#include <linux/gpio.h> -#include <linux/therm_est.h> -#include <linux/nct1008.h> -#include <linux/cm3217.h> -#include <linux/pid_thermal_gov.h> -#include <mach/edp.h> -#include <linux/edp.h> -#include <mach/gpio-tegra.h> -#include <mach/pinmux-t11.h> -#include <mach/pinmux.h> -#include <media/imx091.h> -#include <media/ov9772.h> -#include <media/as364x.h> -#include <media/ad5816.h> -#include <generated/mach-types.h> -#include <linux/power/sbs-battery.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-common.h" -#include "board-macallan.h" -#include "cpu-tegra.h" -#include "devices.h" -#include "tegra-board-id.h" -#include "dvfs.h" - -static struct nvc_gpio_pdata imx091_gpio_pdata[] = { - {IMX091_GPIO_RESET, CAM_RSTN, true, false}, - {IMX091_GPIO_PWDN, CAM1_POWER_DWN_GPIO, true, false}, - {IMX091_GPIO_GP1, CAM_GPIO1, true, false} -}; - -static struct board_info board_info; - -static struct throttle_table tj_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle tj_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_throttle_table), - .throt_tab = tj_throttle_table, -}; - -static int __init macallan_throttle_init(void) -{ - if (machine_is_macallan()) - balanced_throttle_register(&tj_throttle, "tegra-balanced"); - return 0; -} -module_init(macallan_throttle_init); - -static struct nct1008_platform_data macallan_nct1008_pdata = { - .supported_hwrev = true, - .extended_range = true, - .conv_rate = 0x06, /* 4Hz conversion rate */ - - .sensors = { - [LOC] = { - .shutdown_limit = 120, /* C */ - .num_trips = 0, - .tzp = NULL, - }, - [EXT] = { - .shutdown_limit = 105, /* C */ - .num_trips = 1, - .tzp = NULL, - .trips = { - { - .cdev_type = "suspend_soctherm", - .trip_temp = 50000, - .trip_type = THERMAL_TRIP_ACTIVE, - .upper = 1, - .lower = 1, - .hysteresis = 5000, - .mask = 1, - }, - }, - } - } -}; - -static struct i2c_board_info macallan_i2c4_nct1008_board_info[] = { - { - I2C_BOARD_INFO("nct1008", 0x4C), - .platform_data = &macallan_nct1008_pdata, - .irq = -1, - } -}; - -#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ - { \ - .pingroup = TEGRA_PINGROUP_##_pingroup, \ - .func = TEGRA_MUX_##_mux, \ - .pupd = TEGRA_PUPD_##_pupd, \ - .tristate = TEGRA_TRI_##_tri, \ - .io = TEGRA_PIN_##_io, \ - .lock = TEGRA_PIN_LOCK_##_lock, \ - .od = TEGRA_PIN_OD_DEFAULT, \ - .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ -} - -static int macallan_focuser_power_on(struct ad5816_power_rail *pw) -{ - int err; - - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - err = regulator_enable(pw->vdd_i2c); - if (unlikely(err)) - goto ad5816_vdd_i2c_fail; - - err = regulator_enable(pw->vdd); - if (unlikely(err)) - goto ad5816_vdd_fail; - - return 0; - -ad5816_vdd_fail: - regulator_disable(pw->vdd_i2c); - -ad5816_vdd_i2c_fail: - pr_err("%s FAILED\n", __func__); - - return -ENODEV; -} - -static int macallan_focuser_power_off(struct ad5816_power_rail *pw) -{ - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - regulator_disable(pw->vdd); - regulator_disable(pw->vdd_i2c); - - return 0; -} - -static struct tegra_pingroup_config mclk_disable = - VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config mclk_enable = - VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_disable = - VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_enable = - VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -/* - * As a workaround, macallan_vcmvdd need to be allocated to activate the - * sensor devices. This is due to the focuser device(AD5816) will hook up - * the i2c bus if it is not powered up. -*/ -static struct regulator *macallan_vcmvdd; - -static int macallan_get_vcmvdd(void) -{ - if (!macallan_vcmvdd) { - macallan_vcmvdd = regulator_get(NULL, "vdd_af_cam1"); - if (unlikely(WARN_ON(IS_ERR(macallan_vcmvdd)))) { - pr_err("%s: can't get regulator vcmvdd: %ld\n", - __func__, PTR_ERR(macallan_vcmvdd)); - macallan_vcmvdd = NULL; - return -ENODEV; - } - } - return 0; -} - -static int macallan_imx091_power_on(struct nvc_regulator *vreg) -{ - int err; - - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - if (macallan_get_vcmvdd()) - goto imx091_poweron_fail; - - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(10, 20); - - err = regulator_enable(vreg[IMX091_VREG_AVDD].vreg); - if (err) - goto imx091_avdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_DVDD].vreg); - if (err) - goto imx091_dvdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_IOVDD].vreg); - if (err) - goto imx091_iovdd_fail; - - usleep_range(1, 2); - gpio_set_value(CAM1_POWER_DWN_GPIO, 1); - - err = regulator_enable(macallan_vcmvdd); - if (unlikely(err)) - goto imx091_vcmvdd_fail; - - tegra_pinmux_config_table(&mclk_enable, 1); - usleep_range(300, 310); - - return 1; - -imx091_vcmvdd_fail: - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - -imx091_iovdd_fail: - regulator_disable(vreg[IMX091_VREG_DVDD].vreg); - -imx091_dvdd_fail: - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - -imx091_avdd_fail: - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - -imx091_poweron_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int macallan_imx091_power_off(struct nvc_regulator *vreg) -{ - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - usleep_range(1, 2); - tegra_pinmux_config_table(&mclk_disable, 1); - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(1, 2); - - regulator_disable(macallan_vcmvdd); - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - regulator_disable(vreg[IMX091_VREG_DVDD].vreg); - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - - return 1; -} - -static struct nvc_imager_cap imx091_cap = { - .identifier = "IMX091", - .sensor_nvc_interface = 3, - .pixel_types[0] = 0x100, - .orientation = 0, - .direction = 0, - .initial_clock_rate_khz = 6000, - .clock_profiles[0] = { - .external_clock_khz = 24000, - .clock_multiplier = 850000, /* value / 1,000,000 */ - }, - .clock_profiles[1] = { - .external_clock_khz = 0, - .clock_multiplier = 0, - }, - .h_sync_edge = 0, - .v_sync_edge = 0, - .mclk_on_vgp0 = 0, - .csi_port = 0, - .data_lanes = 4, - .virtual_channel_id = 0, - .discontinuous_clk_mode = 1, - .cil_threshold_settle = 0x0, - .min_blank_time_width = 16, - .min_blank_time_height = 16, - .preferred_mode_index = 0, - .focuser_guid = NVC_FOCUS_GUID(0), - .torch_guid = NVC_TORCH_GUID(0), - .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2, -}; - -static struct imx091_platform_data imx091_pdata = { - .num = 0, - .sync = 0, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(imx091_gpio_pdata), - .gpio = imx091_gpio_pdata, - .flash_cap = { - .sdo_trigger_enabled = 1, - .adjustable_flash_timing = 1, - }, - .cap = &imx091_cap, - .power_on = macallan_imx091_power_on, - .power_off = macallan_imx091_power_off, -}; - -static int macallan_ov9772_power_on(struct ov9772_power_rail *pw) -{ - int err; - - if (unlikely(!pw || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - if (macallan_get_vcmvdd()) - goto ov9772_get_vcmvdd_fail; - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - err = regulator_enable(pw->avdd); - if (unlikely(err)) - goto ov9772_avdd_fail; - - err = regulator_enable(pw->dvdd); - if (unlikely(err)) - goto ov9772_dvdd_fail; - - err = regulator_enable(pw->dovdd); - if (unlikely(err)) - goto ov9772_dovdd_fail; - - gpio_set_value(CAM_RSTN, 1); - gpio_set_value(CAM2_POWER_DWN_GPIO, 1); - - err = regulator_enable(macallan_vcmvdd); - if (unlikely(err)) - goto ov9772_vcmvdd_fail; - - tegra_pinmux_config_table(&pbb0_enable, 1); - usleep_range(340, 380); - - /* return 1 to skip the in-driver power_on sequence */ - return 1; - -ov9772_vcmvdd_fail: - regulator_disable(pw->dovdd); - -ov9772_dovdd_fail: - regulator_disable(pw->dvdd); - -ov9772_dvdd_fail: - regulator_disable(pw->avdd); - -ov9772_avdd_fail: - gpio_set_value(CAM_RSTN, 0); - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - -ov9772_get_vcmvdd_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int macallan_ov9772_power_off(struct ov9772_power_rail *pw) -{ - if (unlikely(!pw || !macallan_vcmvdd || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - usleep_range(21, 25); - tegra_pinmux_config_table(&pbb0_disable, 1); - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - regulator_disable(macallan_vcmvdd); - regulator_disable(pw->dovdd); - regulator_disable(pw->dvdd); - regulator_disable(pw->avdd); - - /* return 1 to skip the in-driver power_off sequence */ - return 1; -} - -static struct nvc_gpio_pdata ov9772_gpio_pdata[] = { - { OV9772_GPIO_TYPE_SHTDN, CAM2_POWER_DWN_GPIO, true, 0, }, - { OV9772_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, }, -}; - -static struct ov9772_platform_data macallan_ov9772_pdata = { - .num = 1, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(ov9772_gpio_pdata), - .gpio = ov9772_gpio_pdata, - .power_on = macallan_ov9772_power_on, - .power_off = macallan_ov9772_power_off, -}; - -static int macallan_as3648_power_on(struct as364x_power_rail *pw) -{ - int err = macallan_get_vcmvdd(); - - if (err) - return err; - - return regulator_enable(macallan_vcmvdd); -} - -static int macallan_as3648_power_off(struct as364x_power_rail *pw) -{ - if (!macallan_vcmvdd) - return -ENODEV; - - return regulator_disable(macallan_vcmvdd); -} - -static struct as364x_platform_data macallan_as3648_pdata = { - .config = { - .led_mask = 3, - .max_total_current_mA = 1000, - .max_peak_current_mA = 600, - .vin_low_v_run_mV = 3070, - .strobe_type = 1, - }, - .pinstate = { - .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0), - .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0) - }, - .dev_name = "torch", - .type = AS3648, - .gpio_strobe = CAM_FLASH_STROBE, - .power_on_callback = macallan_as3648_power_on, - .power_off_callback = macallan_as3648_power_off, -}; - -static struct ad5816_platform_data macallan_ad5816_pdata = { - .cfg = 0, - .num = 0, - .sync = 0, - .dev_name = "focuser", - .power_on = macallan_focuser_power_on, - .power_off = macallan_focuser_power_off, -}; - -static struct i2c_board_info macallan_i2c_board_info_e1625[] = { - { - I2C_BOARD_INFO("imx091", 0x36), - .platform_data = &imx091_pdata, - }, - { - I2C_BOARD_INFO("ov9772", 0x10), - .platform_data = &macallan_ov9772_pdata, - }, - { - I2C_BOARD_INFO("as3648", 0x30), - .platform_data = &macallan_as3648_pdata, - }, - { - I2C_BOARD_INFO("ad5816", 0x0E), - .platform_data = &macallan_ad5816_pdata, - }, -}; - -static int macallan_camera_init(void) -{ - tegra_pinmux_config_table(&mclk_disable, 1); - tegra_pinmux_config_table(&pbb0_disable, 1); - - i2c_register_board_info(2, macallan_i2c_board_info_e1625, - ARRAY_SIZE(macallan_i2c_board_info_e1625)); - return 0; -} - -#define TEGRA_CAMERA_GPIO(_gpio, _label, _value) \ - { \ - .gpio = _gpio, \ - .label = _label, \ - .value = _value, \ - } - -static struct cm3217_platform_data macallan_cm3217_pdata = { - .levels = {10, 160, 225, 320, 640, 1280, 2600, 5800, 8000, 10240}, - .golden_adc = 0, - .power = 0, -}; - -static struct i2c_board_info macallan_i2c0_board_info_cm3217[] = { - { - I2C_BOARD_INFO("cm3217", 0x10), - .platform_data = &macallan_cm3217_pdata, - }, -}; - -/* MPU board file definition */ -static struct mpu_platform_data mpu6050_gyro_data = { - .int_config = 0x10, - .level_shifter = 0, - /* Located in board_[platformname].h */ - .orientation = MPU_GYRO_ORIENTATION, - .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE, - .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22, - 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89}, -}; - -static struct mpu_platform_data mpu_compass_data = { - .orientation = MPU_COMPASS_ORIENTATION, - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct mpu_platform_data bmp180_pdata = { - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct i2c_board_info __initdata inv_mpu6050_i2c2_board_info[] = { - { - I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR), - .platform_data = &mpu6050_gyro_data, - }, - { - /* The actual BMP180 address is 0x77 but because this conflicts - * with another device, this address is hacked so Linux will - * call the driver. The conflict is technically okay since the - * BMP180 is behind the MPU. Also, the BMP180 driver uses a - * hard-coded address of 0x77 since it can't be changed anyway. - */ - I2C_BOARD_INFO("bmp180", 0x78), - .platform_data = &bmp180_pdata, - }, - { - I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR), - .platform_data = &mpu_compass_data, - }, -}; - -static void mpuirq_init(void) -{ - int ret = 0; - unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO; - unsigned gyro_bus_num = MPU_GYRO_BUS_NUM; - char *gyro_name = MPU_GYRO_NAME; - - pr_info("*** MPU START *** mpuirq_init...\n"); - - ret = gpio_request(gyro_irq_gpio, gyro_name); - - if (ret < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, ret); - return; - } - - ret = gpio_direction_input(gyro_irq_gpio); - if (ret < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, ret); - gpio_free(gyro_irq_gpio); - return; - } - pr_info("*** MPU END *** mpuirq_init...\n"); - - inv_mpu6050_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO); - i2c_register_board_info(gyro_bus_num, inv_mpu6050_i2c2_board_info, - ARRAY_SIZE(inv_mpu6050_i2c2_board_info)); -} - -static int macallan_nct1008_init(void) -{ - int nct1008_port; - int ret = 0; - - nct1008_port = TEGRA_GPIO_PO4; - - tegra_add_all_vmin_trips(macallan_nct1008_pdata.sensors[EXT].trips, - &macallan_nct1008_pdata.sensors[EXT].num_trips); - - macallan_i2c4_nct1008_board_info[0].irq = gpio_to_irq(nct1008_port); - pr_info("%s: macallan nct1008 irq %d", - __func__, macallan_i2c4_nct1008_board_info[0].irq); - - ret = gpio_request(nct1008_port, "temp_alert"); - if (ret < 0) - return ret; - - ret = gpio_direction_input(nct1008_port); - if (ret < 0) { - pr_info("%s: calling gpio_free(nct1008_port)", __func__); - gpio_free(nct1008_port); - } - - /* macallan has thermal sensor on GEN1-I2C i.e. instance 0 */ - i2c_register_board_info(0, macallan_i2c4_nct1008_board_info, - ARRAY_SIZE(macallan_i2c4_nct1008_board_info)); - - return ret; -} - -#ifdef CONFIG_TEGRA_SKIN_THROTTLE -static struct thermal_trip_info skin_trips[] = { - { - .cdev_type = "skin-balanced", - .trip_temp = 43000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 57000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, -}; - -static struct therm_est_subdevice skin_devs[] = { - { - .dev_data = "Tdiode", - .coeffs = { - 2, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 0, - 1, 1, 0, 0, - 0, 0, -1, -7 - }, - }, - { - .dev_data = "Tboard", - .coeffs = { - -11, -7, -5, -3, - -3, -2, -1, 0, - 0, 0, 1, 1, - 1, 2, 2, 3, - 4, 6, 11, 18 - }, - }, -}; - -static struct pid_thermal_gov_params skin_pid_params = { - .max_err_temp = 4000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 15, - .down_compensation = 15, -}; - -static struct thermal_zone_params skin_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &skin_pid_params, -}; - -static struct therm_est_data skin_data = { - .num_trips = ARRAY_SIZE(skin_trips), - .trips = skin_trips, - .toffset = 9793, - .polling_period = 1100, - .passive_delay = 15000, - .tc1 = 10, - .tc2 = 1, - .ndevs = ARRAY_SIZE(skin_devs), - .devs = skin_devs, - .tzp = &skin_tzp, -}; - -static struct throttle_table skin_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle skin_throttle = { - .throt_tab_size = ARRAY_SIZE(skin_throttle_table), - .throt_tab = skin_throttle_table, -}; - -static int __init macallan_skin_init(void) -{ - if (machine_is_macallan()) { - balanced_throttle_register(&skin_throttle, "skin-balanced"); - tegra_skin_therm_est_device.dev.platform_data = &skin_data; - platform_device_register(&tegra_skin_therm_est_device); - } - - return 0; -} -late_initcall(macallan_skin_init); -#endif - -int __init macallan_sensors_init(void) -{ - int err; - - tegra_get_board_info(&board_info); - - /* E1545+E1604 has no temp sensor. */ - if (board_info.board_id != BOARD_E1545) { - err = macallan_nct1008_init(); - if (err) { - pr_err("%s: nct1008 register failed.\n", __func__); - return err; - } - } - - macallan_camera_init(); - mpuirq_init(); - - i2c_register_board_info(0, macallan_i2c0_board_info_cm3217, - ARRAY_SIZE(macallan_i2c0_board_info_cm3217)); - - return 0; -} diff --git a/arch/arm/mach-tegra/board-macallan.c b/arch/arm/mach-tegra/board-macallan.c deleted file mode 100644 index e32101661e7b..000000000000 --- a/arch/arm/mach-tegra/board-macallan.c +++ /dev/null @@ -1,619 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan.c - * - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ctype.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/i2c-tegra.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_data/tegra_usb.h> -#include <linux/usb/tegra_usb_phy.h> -#include <linux/spi/spi.h> -#include <linux/spi/rm31080a_ts.h> -#include <linux/memblock.h> -#include <linux/spi/spi-tegra.h> -#include <linux/nfc/pn544.h> -#include <linux/skbuff.h> -#include <linux/ti_wilink_st.h> -#include <linux/regulator/consumer.h> -#include <linux/smb349-charger.h> -#include <linux/max17048_battery.h> -#include <linux/leds.h> -#include <linux/i2c/at24.h> -#include <linux/of_platform.h> -#include <linux/clk/tegra.h> -#include <linux/tegra-soc.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> -#include <linux/irqchip/tegra.h> -#include <linux/tegra_fiq_debugger.h> - -#include <mach/irqs.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <mach/io_dpd.h> -#include <mach/i2s.h> -#include <mach/isomgr.h> -#include <mach/tegra_asoc_pdata.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/gpio-tegra.h> -#include <linux/platform_data/tegra_usb_modem_power.h> - -#include "board-touch-raydium.h" -#include "board.h" -#include "board-common.h" -#include "clock.h" -#include "board-macallan.h" -#include "devices.h" -#include "gpio-names.h" -#include "iomap.h" -#include "pm.h" -#include "common.h" -#include "tegra-board-id.h" -#include "tegra-of-dev-auxdata.h" - -static struct board_info board_info, display_board_info; - -#if defined CONFIG_TI_ST || defined CONFIG_TI_ST_MODULE -struct ti_st_plat_data macallan_wilink_pdata = { - .nshutdown_gpio = TEGRA_GPIO_PQ7, - .dev_name = BLUETOOTH_UART_DEV_NAME, - .flow_cntrl = 1, - .baud_rate = 3000000, -}; - -static struct platform_device wl128x_device = { - .name = "kim", - .id = -1, - .dev.platform_data = &macallan_wilink_pdata, -}; - -static struct platform_device btwilink_device = { - .name = "btwilink", - .id = -1, -}; - -static noinline void __init macallan_bt_st(void) -{ - pr_info("macallan_bt_st"); - - platform_device_register(&wl128x_device); - platform_device_register(&btwilink_device); -} - -static struct resource macallan_st_host_wake_resources[] = { - [0] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device macallan_st_host_wake_device = { - .name = "st_host_wake", - .id = 0, - .num_resources = ARRAY_SIZE(macallan_st_host_wake_resources), - .resource = macallan_st_host_wake_resources, -}; - -static noinline void __init macallan_tegra_setup_st_host_wake(void) -{ - macallan_st_host_wake_resources[0].start = - macallan_st_host_wake_resources[0].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&macallan_st_host_wake_device); -} -#endif - -static __initdata struct tegra_clk_init_table macallan_clk_init_table[] = { - /* name parent rate enabled */ - { "pll_m", NULL, 0, false}, - { "hda", "pll_p", 108000000, false}, - { "hda2codec_2x", "pll_p", 48000000, false}, - { "pwm", "pll_p", 3187500, false}, - { "blink", "clk_32k", 32768, true}, - { "i2s1", "pll_a_out0", 0, false}, - { "i2s3", "pll_a_out0", 0, false}, - { "i2s4", "pll_a_out0", 0, false}, - { "spdif_out", "pll_a_out0", 0, false}, - { "d_audio", "clk_m", 12000000, false}, - { "dam0", "clk_m", 12000000, false}, - { "dam1", "clk_m", 12000000, false}, - { "dam2", "clk_m", 12000000, false}, - { "audio1", "i2s1_sync", 0, false}, - { "audio3", "i2s3_sync", 0, false}, - /* Setting vi_sensor-clk to true for validation purpose, will imapact - * power, later set to be false.*/ - { "vi_sensor", "pll_p", 150000000, false}, - { "cilab", "pll_p", 150000000, false}, - { "cilcd", "pll_p", 150000000, false}, - { "cile", "pll_p", 150000000, false}, - { "i2c1", "pll_p", 3200000, false}, - { "i2c2", "pll_p", 3200000, false}, - { "i2c3", "pll_p", 3200000, false}, - { "i2c4", "pll_p", 3200000, false}, - { "i2c5", "pll_p", 3200000, false}, - { NULL, NULL, 0, 0}, -}; - -static struct i2c_board_info __initdata rt5640_board_info = { - I2C_BOARD_INFO("rt5640", 0x1c), -}; - -static struct pn544_i2c_platform_data nfc_pdata = { - .irq_gpio = TEGRA_GPIO_PW2, - .ven_gpio = TEGRA_GPIO_PQ3, - .firm_gpio = TEGRA_GPIO_PH0, -}; - -static struct i2c_board_info __initdata nfc_board_info = { - I2C_BOARD_INFO("pn544", 0x28), - .platform_data = &nfc_pdata, -}; - -static void macallan_i2c_init(void) -{ - nfc_board_info.irq = gpio_to_irq(TEGRA_GPIO_PW2); - i2c_register_board_info(0, &nfc_board_info, 1); - i2c_register_board_info(0, &rt5640_board_info, 1); -} - -static struct platform_device *macallan_uart_devices[] __initdata = { - &tegra_uarta_device, - &tegra_uartb_device, - &tegra_uartc_device, - &tegra_uartd_device, -}; - -static void __init uart_debug_init(void) -{ - int debug_port_id; - - debug_port_id = uart_console_debug_init(3); - if (debug_port_id < 0) - return; - - macallan_uart_devices[debug_port_id] = uart_console_debug_device; -} - -static void __init macallan_uart_init(void) -{ - /* Register low speed only if it is selected */ - if (!is_tegra_debug_uartport_hs()) - uart_debug_init(); - - platform_add_devices(macallan_uart_devices, - ARRAY_SIZE(macallan_uart_devices)); -} - -static struct resource tegra_rtc_resources[] = { - [0] = { - .start = TEGRA_RTC_BASE, - .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_RTC, - .end = INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tegra_rtc_device = { - .name = "tegra_rtc", - .id = -1, - .resource = tegra_rtc_resources, - .num_resources = ARRAY_SIZE(tegra_rtc_resources), -}; - -static struct tegra_asoc_platform_data macallan_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .gpio_codec1 = TEGRA_GPIO_CODEC1_EN, - .gpio_codec2 = TEGRA_GPIO_CODEC2_EN, - .gpio_codec3 = TEGRA_GPIO_CODEC3_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - }, -}; - -static struct platform_device macallan_audio_device = { - .name = "tegra-snd-rt5640", - .id = 0, - .dev = { - .platform_data = &macallan_audio_pdata, - }, -}; - -static struct platform_device *macallan_devices[] __initdata = { - &tegra_pmu_device, - &tegra_rtc_device, - &tegra_udc_device, -#if defined(CONFIG_TEGRA_AVP) - &tegra_avp_device, -#endif -#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) - &tegra11_se_device, -#endif - &tegra_ahub_device, - &tegra_dam_device0, - &tegra_dam_device1, - &tegra_dam_device2, - &tegra_i2s_device1, - &tegra_i2s_device3, - &tegra_i2s_device4, - &tegra_spdif_device, - &spdif_dit_device, - &bluetooth_dit_device, - &macallan_audio_device, - &tegra_hda_device, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) - &tegra_aes_device, -#endif -}; - -#ifdef CONFIG_USB_SUPPORT -static struct tegra_usb_platform_data tegra_udc_pdata = { - .port_otg = true, - .has_hostpc = true, - .support_pmu_vbus = true, - .id_det_type = TEGRA_USB_PMU_ID, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_DEVICE, - .vbus_extcon_dev_name = "palmas-extcon", - .u_data.dev = { - .vbus_pmu_irq = 0, - .vbus_gpio = -1, - .charging_supported = true, - .remote_wakeup_supported = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { - .port_otg = true, - .has_hostpc = true, - .support_pmu_vbus = true, - .id_det_type = TEGRA_USB_PMU_ID, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .vbus_extcon_dev_name = "palmas-extcon", - .id_extcon_dev_name = "palmas-extcon", - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x4, - }, -}; - -static struct tegra_usb_otg_data tegra_otg_pdata = { - .ehci_device = &tegra_ehci1_device, - .ehci_pdata = &tegra_ehci1_utmi_pdata, -}; - -static void macallan_usb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - /* Set USB wake sources for macallan */ - tegra_set_usb_wake_source(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) { - tegra_otg_device.dev.platform_data = &tegra_otg_pdata; - platform_device_register(&tegra_otg_device); - /* Setup the udc platform data */ - tegra_udc_device.dev.platform_data = &tegra_udc_pdata; - } -} - -static struct gpio modem_gpios[] = { /* Nemo modem */ - {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"}, - {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"}, -}; - -static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static int baseband_init(void) -{ - int ret; - - ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios)); - if (ret) { - pr_warn("%s:gpio request failed\n", __func__); - return ret; - } - - /* enable pull-down for MDM_COLD_BOOT */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4, - TEGRA_PUPD_PULL_DOWN); - - /* export GPIO for user space access through sysfs */ - gpio_export(MDM_RST, false); - - return 0; -} - -static const struct tegra_modem_operations baseband_operations = { - .init = baseband_init, -}; - -static struct tegra_usb_modem_power_platform_data baseband_pdata = { - .ops = &baseband_operations, - .wake_gpio = -1, - .boot_gpio = MDM_COLDBOOT, - .boot_irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - .autosuspend_delay = 2000, - .short_autosuspend_delay = 50, - .tegra_ehci_device = &tegra_ehci2_device, - .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata, -}; - -static struct platform_device icera_nemo_device = { - .name = "tegra_usb_modem_power", - .id = -1, - .dev = { - .platform_data = &baseband_pdata, - }, -}; - -static void macallan_modem_init(void) -{ - int modem_id = tegra_get_modem_id(); - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - switch (modem_id) { - case TEGRA_BB_NEMO: /* on board i500 HSIC */ - if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) - platform_device_register(&icera_nemo_device); - break; - } -} - -#else -static void macallan_usb_init(void) { } -static void macallan_modem_init(void) { } -#endif - -static void macallan_audio_init(void) -{ - macallan_audio_pdata.codec_name = "rt5640.0-001c"; - macallan_audio_pdata.codec_dai_name = "rt5640-aif1"; -} - - -static __initdata struct tegra_clk_init_table touch_clk_init_table[] = { - /* name parent rate enabled */ - { "extern2", "pll_p", 41000000, false}, - { "clk_out_2", "extern2", 40800000, false}, - { NULL, NULL, 0, 0}, -}; - -struct rm_spi_ts_platform_data rm31080ts_macallan_data = { - .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI, - .config = 0, - .platform_id = RM_PLATFORM_D010, - .name_of_clock = "clk_out_2", - .name_of_clock_con = "extern2", -}; - -static struct tegra_spi_device_controller_data dev_cdata = { - .rx_clk_tap_delay = 16, - .tx_clk_tap_delay = 16, -}; - -struct spi_board_info rm31080a_macallan_spi_board[1] = { - { - .modalias = "rm_ts_spidev", - .bus_num = 0, - .chip_select = 0, - .max_speed_hz = 12 * 1000 * 1000, - .mode = SPI_MODE_0, - .controller_data = &dev_cdata, - .platform_data = &rm31080ts_macallan_data, - }, -}; - -static int __init macallan_touch_init(void) -{ - tegra_clk_init_from_table(touch_clk_init_table); - if (display_board_info.board_id == BOARD_E1582) - rm31080ts_macallan_data.platform_id = RM_PLATFORM_P005; - else - rm31080ts_macallan_data.platform_id = RM_PLATFORM_D010; - mdelay(20); - rm31080a_macallan_spi_board[0].irq = gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI); - touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI, - TOUCH_GPIO_RST_RAYDIUM_SPI, - &rm31080ts_macallan_data, - &rm31080a_macallan_spi_board[0], - ARRAY_SIZE(rm31080a_macallan_spi_board)); - return 0; -} - -#ifdef CONFIG_USE_OF -struct of_dev_auxdata macallan_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000600, "sdhci-tegra.3", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000400, "sdhci-tegra.2", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000000, "sdhci-tegra.0", - &macallan_tegra_sdhci_platform_data0), - OF_DEV_AUXDATA("nvidia,tegra114-camera", 0x0, "tegra_camera", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", - NULL), - T114_I2C_OF_DEV_AUXDATA, - T114_SPI_OF_DEV_AUXDATA, - OF_DEV_AUXDATA("nvidia,tegra114-nvavp", 0x60001000, "nvavp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-pwm", 0x7000a000, "tegra-pwm", NULL), - {} -}; -#endif - -static void __init tegra_macallan_early_init(void) -{ - tegra_clk_init_from_table(macallan_clk_init_table); - tegra_clk_verify_parents(); - tegra_soc_device_init("macallan"); -} - - -static void __init tegra_macallan_late_init(void) -{ - macallan_i2c_init(); - macallan_usb_init(); - macallan_uart_init(); - macallan_audio_init(); - platform_add_devices(macallan_devices, ARRAY_SIZE(macallan_devices)); - tegra_io_dpd_init(); - macallan_regulator_init(); - macallan_sdhci_init(); - macallan_suspend_init(); - macallan_emc_init(); - macallan_edp_init(); - isomgr_init(); - macallan_touch_init(); - macallan_panel_init(); - macallan_kbc_init(); -#if defined CONFIG_TI_ST || defined CONFIG_TI_ST_MODULE - macallan_bt_st(); - macallan_tegra_setup_st_host_wake(); -#endif - macallan_modem_init(); -#ifdef CONFIG_TEGRA_WDT_RECOVERY - tegra_wdt_recovery_init(); -#endif - tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); - macallan_sensors_init(); - macallan_soctherm_init(); - tegra_register_fuse(); -} - -static void __init tegra_macallan_dt_init(void) -{ - tegra_get_board_info(&board_info); - tegra_get_display_board_info(&display_board_info); - - tegra_macallan_early_init(); - -#ifdef CONFIG_USE_OF - of_platform_populate(NULL, - of_default_bus_match_table, macallan_auxdata_lookup, - &platform_bus); -#else - platform_device_register(&tegra_gpio_device); -#endif - - tegra_macallan_late_init(); -} - -static void __init tegra_macallan_reserve(void) -{ -#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* 1920*1200*4*2 = 18432000 bytes */ - tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M + SZ_2M); -#else - tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_16M + SZ_2M); -#endif -} - -static const char * const macallan_dt_board_compat[] = { - "nvidia,macallan", - NULL -}; - -MACHINE_START(MACALLAN, "macallan") - .atag_offset = 0x100, - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .reserve = tegra_macallan_reserve, - .init_early = tegra11x_init_early, - .init_irq = irqchip_init, - .init_time = clocksource_of_init, - .init_machine = tegra_macallan_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = macallan_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-macallan.h b/arch/arm/mach-tegra/board-macallan.h deleted file mode 100644 index 8f38153125ac..000000000000 --- a/arch/arm/mach-tegra/board-macallan.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * arch/arm/mach-tegra/board-macallan.h - * - * Copyright (c) 2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_BOARD_MACALLAN_H -#define _MACH_TEGRA_BOARD_MACALLAN_H - -#include <mach/irqs.h> -#include "gpio-names.h" -#include <linux/thermal.h> -#include <linux/platform_data/thermal_sensors.h> -#include "tegra11_soctherm.h" - -#define PMC_WAKE_STATUS 0x14 -#define PMC_WAKE2_STATUS 0x168 - -/* External peripheral act as gpio */ -#define PALMAS_TEGRA_GPIO_BASE TEGRA_NR_GPIOS - -/* Audio-related GPIOs */ -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 -#define TEGRA_GPIO_LDO1_EN TEGRA_GPIO_PV3 -#define TEGRA_GPIO_CODEC1_EN TEGRA_GPIO_PP3 -#define TEGRA_GPIO_CODEC2_EN TEGRA_GPIO_PP1 -#define TEGRA_GPIO_CODEC3_EN TEGRA_GPIO_PV0 - -#define TEGRA_GPIO_SPKR_EN -1 -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7 -#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PK3 -#define TEGRA_GPIO_EXT_MIC_EN -1 - -#define TEGRA_SOC_OC_IRQ_BASE TEGRA_NR_IRQS -#define TEGRA_SOC_OC_NUM_IRQ TEGRA_SOC_OC_IRQ_MAX - -/* External peripheral act as interrupt controller */ -#define PALMAS_TEGRA_IRQ_BASE (TEGRA_SOC_OC_IRQ_BASE + TEGRA_SOC_OC_NUM_IRQ) -#define PALMAS_TEGRA_IRQ_END (PALMAS_TEGRA_IRQ_BASE + PALMAS_NUM_IRQ) - -/* I2C related GPIOs */ -#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4 -#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5 -#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5 -#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6 -#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1 -#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2 -#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4 -#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5 -#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6 -#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7 - -/* Camera related GPIOs */ -#define CAM_RSTN TEGRA_GPIO_PBB3 -#define CAM_FLASH_STROBE TEGRA_GPIO_PBB4 -#define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 -#define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 -#define CAM_AF_PWDN TEGRA_GPIO_PBB7 -#define CAM_GPIO1 TEGRA_GPIO_PCC1 -#define CAM_GPIO2 TEGRA_GPIO_PCC2 - -/* Touchscreen definitions */ -#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2 -#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4 - -/* Invensense MPU Definitions */ -#define MPU_GYRO_NAME "mpu6050" -#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PR3 -#define MPU_GYRO_ADDR 0x69 -#define MPU_GYRO_BUS_NUM 0 -#define MPU_GYRO_ORIENTATION { 0, 1, 0, 1, 0, 0, 0, 0, -1 } -#define MPU_COMPASS_NAME "ak8975" -#define MPU_COMPASS_IRQ_GPIO 0 -#define MPU_COMPASS_ADDR 0x0D -#define MPU_COMPASS_BUS_NUM 0 -#define MPU_COMPASS_ORIENTATION { 0, 1, 0, 1, 0, 0, 0, 0, -1 } - -/* Modem related GPIOs */ -#define MODEM_EN TEGRA_GPIO_PP2 -#define MDM_RST TEGRA_GPIO_PP0 -#define MDM_COLDBOOT TEGRA_GPIO_PO5 - -int macallan_regulator_init(void); -int macallan_suspend_init(void); -int macallan_sdhci_init(void); -int macallan_sensors_init(void); -int macallan_emc_init(void); -int macallan_edp_init(void); -int macallan_panel_init(void); -int roth_panel_init(void); -int macallan_kbc_init(void); -int macallan_soctherm_init(void); - - -extern struct tegra_sdhci_platform_data macallan_tegra_sdhci_platform_data0; - -/* UART port which is used by bluetooth*/ -#define BLUETOOTH_UART_DEV_NAME "/dev/ttyTHS2" - -/* Baseband IDs */ -enum tegra_bb_type { - TEGRA_BB_NEMO = 1, -}; - -#define UTMI1_PORT_OWNER_XUSB 0x1 -#define UTMI2_PORT_OWNER_XUSB 0x2 -#define HSIC1_PORT_OWNER_XUSB 0x4 - -#endif diff --git a/arch/arm/mach-tegra/board-pismo-memory.c b/arch/arm/mach-tegra/board-pismo-memory.c deleted file mode 100644 index 6526ad0f0c07..000000000000 --- a/arch/arm/mach-tegra/board-pismo-memory.c +++ /dev/null @@ -1,1620 +0,0 @@ -/* - * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include "board.h" -#include "board-pismo.h" - -#include "tegra-board-id.h" -#include "tegra11_emc.h" -#include "devices.h" - -static struct tegra11_emc_table e1611_h5tc4g63mfr_pba_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c6, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000001, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000002, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000003, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000c, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00060000, /* EMC_DLL_XFORM_DQS4 */ - 0x00060000, /* EMC_DLL_XFORM_DQS5 */ - 0x00060000, /* EMC_DLL_XFORM_DQS6 */ - 0x00060000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00060000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000c, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS1 */ - 0x00060000, /* EMC_DLL_XFORM_DQS2 */ - 0x00060000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000007, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x00000005, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x000000a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x05057404, /* EMC_XM2VTTGENPADCTRL */ - 0x0000001f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT */ - 0x000c000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0405, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a06, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000c2f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c70, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03035504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT */ - 0x0158000c, /* EMC_MRS_WAIT_CNT2 */ - 0x07070707, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000404, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001944, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130b, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ1 */ - 0x00018000, /* EMC_DLL_XFORM_DQ2 */ - 0x00018000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00018000, /* EMC_DLL_XFORM_DQ1 */ - 0x00018000, /* EMC_DLL_XFORM_DQ2 */ - 0x00018000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73200006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 480000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000017, /* EMC_RC */ - 0x00000082, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000010, /* EMC_RAS */ - 0x00000005, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000005, /* EMC_RD_RCD */ - 0x00000005, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x00000004, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000f23, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000003c8, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000b, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000007f, /* EMC_AR2PDEN */ - 0x00000012, /* EMC_RW2PDEN */ - 0x00000089, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000015, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000005, /* EMC_TCLKSTABLE */ - 0x00000006, /* EMC_TCLKSTOP */ - 0x00000f64, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf0140091, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003033d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc084, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077704, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x013f000c, /* EMC_MRS_WAIT_CNT */ - 0x013f000c, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000808, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001f05, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x09000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000f080c, /* MC_EMEM_ARB_DA_COVERS */ - 0x7448170d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x0079e79e, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000f6, /* MC_PTSA_GRANT_DECREMENT */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000f0010, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00120014, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001a0014, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001a, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001a001a, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00b40055, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00b400b4, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x73200006, /* EMC_CFG */ - 0x80000931, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_pdata e1611_h5tc4g63mfr_pba_pdata = { - .description = "e1611_h5tc4g63mfr_pba", - .tables = e1611_h5tc4g63mfr_pba_table, - .num_tables = ARRAY_SIZE(e1611_h5tc4g63mfr_pba_table), -}; - -static struct tegra11_emc_pdata *pismo_get_emc_data(void) -{ - - /* load T40T Table */ - return &e1611_h5tc4g63mfr_pba_pdata; -} - -int __init pismo_emc_init(void) -{ - tegra_emc_device.dev.platform_data = pismo_get_emc_data(); - platform_device_register(&tegra_emc_device); - tegra11_emc_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-pismo-panel.c b/arch/arm/mach-tegra/board-pismo-panel.c deleted file mode 100644 index 3e149e47e859..000000000000 --- a/arch/arm/mach-tegra/board-pismo-panel.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo-panel.c - * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <linux/ioport.h> -#include <linux/fb.h> -#include <linux/nvmap.h> -#include <linux/nvhost.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/of.h> - -#include <mach/irqs.h> -#include <mach/dc.h> - -#include "board.h" -#include "devices.h" -#include "gpio-names.h" -#include "board-panel.h" -#include "common.h" -#include "iomap.h" -#include "tegra11_host1x_devices.h" - -#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH3 -#define DSI_PANEL_BL_PWM_GPIO TEGRA_GPIO_PH1 - -struct platform_device * __init pismo_host1x_init(void) -{ - struct platform_device *pdev = NULL; - -#ifdef CONFIG_TEGRA_GRHOST - if (!of_have_populated_dt()) - pdev = tegra11_register_host1x_devices(); - else - pdev = to_platform_device(bus_find_device_by_name( - &platform_bus_type, NULL, "host1x")); -#endif - return pdev; -} - -/* HDMI Hotplug detection pin */ -#define pismo_hdmi_hpd TEGRA_GPIO_PN7 - -static struct regulator *pismo_hdmi_reg; -static struct regulator *pismo_hdmi_pll; -static struct regulator *pismo_hdmi_vddio; - -static struct resource pismo_disp1_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_GENERAL, - .end = INT_DISPLAY_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY_BASE, - .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by pismo_panel_init() */ - .end = 0, /* Filled in by pismo_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsia_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "ganged_dsib_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "dsi_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "mipi_cal", - .start = TEGRA_MIPI_CAL_BASE, - .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource pismo_disp2_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_B_GENERAL, - .end = INT_DISPLAY_B_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY2_BASE, - .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by pismo_panel_init() */ - .end = 0, /* Filled in by pismo_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "hdmi_regs", - .start = TEGRA_HDMI_BASE, - .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - - -static struct tegra_dc_sd_settings sd_settings; - -static struct tegra_dc_out pismo_disp1_out = { - .type = TEGRA_DC_OUT_DSI, - .sd_settings = &sd_settings, -}; - -static int pismo_hdmi_enable(struct device *dev) -{ - int ret; - if (!pismo_hdmi_reg) { - pismo_hdmi_reg = regulator_get(dev, "avdd_hdmi"); - if (IS_ERR(pismo_hdmi_reg)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); - pismo_hdmi_reg = NULL; - return PTR_ERR(pismo_hdmi_reg); - } - } - ret = regulator_enable(pismo_hdmi_reg); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); - return ret; - } - if (!pismo_hdmi_pll) { - pismo_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll"); - if (IS_ERR(pismo_hdmi_pll)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); - pismo_hdmi_pll = NULL; - regulator_put(pismo_hdmi_reg); - pismo_hdmi_reg = NULL; - return PTR_ERR(pismo_hdmi_pll); - } - } - ret = regulator_enable(pismo_hdmi_pll); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); - return ret; - } - return 0; -} - -static int pismo_hdmi_disable(void) -{ - if (pismo_hdmi_reg) { - regulator_disable(pismo_hdmi_reg); - regulator_put(pismo_hdmi_reg); - pismo_hdmi_reg = NULL; - } - - if (pismo_hdmi_pll) { - regulator_disable(pismo_hdmi_pll); - regulator_put(pismo_hdmi_pll); - pismo_hdmi_pll = NULL; - } - - return 0; -} - -static int pismo_hdmi_postsuspend(void) -{ - if (pismo_hdmi_vddio) { - regulator_disable(pismo_hdmi_vddio); - regulator_put(pismo_hdmi_vddio); - pismo_hdmi_vddio = NULL; - } - return 0; -} - -static int pismo_hdmi_hotplug_init(struct device *dev) -{ - int ret = 0; - if (!pismo_hdmi_vddio) { - pismo_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0"); - if (WARN_ON(IS_ERR(pismo_hdmi_vddio))) { - pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n", - __func__, PTR_ERR(pismo_hdmi_vddio)); - pismo_hdmi_vddio = NULL; - ret = -EINVAL; - } else { - ret = regulator_enable(pismo_hdmi_vddio); - if (ret) - pr_err("Pismo_hdmi regulator enable failed\n"); - } - } - return ret; -} - -static struct tegra_dc_out pismo_disp2_out = { - .type = TEGRA_DC_OUT_HDMI, - .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, - .parent_clk = "pll_d2_out0", - - .ddc_bus = 3, - .hotplug_gpio = pismo_hdmi_hpd, - - .max_pixclock = KHZ2PICOS(148500), - - .align = TEGRA_DC_ALIGN_MSB, - .order = TEGRA_DC_ORDER_RED_BLUE, - - .enable = pismo_hdmi_enable, - .disable = pismo_hdmi_disable, - .postsuspend = pismo_hdmi_postsuspend, - .hotplug_init = pismo_hdmi_hotplug_init, -}; - -static struct tegra_fb_data pismo_disp1_fb_data = { - .win = 0, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data pismo_disp1_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &pismo_disp1_out, - .fb = &pismo_disp1_fb_data, - .emc_clk_rate = 204000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct tegra_fb_data pismo_disp2_fb_data = { - .win = 0, - .xres = 1280, - .yres = 720, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data pismo_disp2_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &pismo_disp2_out, - .fb = &pismo_disp2_fb_data, - .emc_clk_rate = 300000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct platform_device pismo_disp2_device = { - .name = "tegradc", - .id = 1, - .resource = pismo_disp2_resources, - .num_resources = ARRAY_SIZE(pismo_disp2_resources), - .dev = { - .platform_data = &pismo_disp2_pdata, - }, -}; - -static struct platform_device pismo_disp1_device = { - .name = "tegradc", - .id = 0, - .resource = pismo_disp1_resources, - .num_resources = ARRAY_SIZE(pismo_disp1_resources), - .dev = { - .platform_data = &pismo_disp1_pdata, - }, -}; - -static struct nvmap_platform_carveout pismo_carveouts[] = { - [0] = { - .name = "iram", - .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, - .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, - .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, - }, - [1] = { - .name = "generic-0", - .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, - .base = 0, /* Filled in by pismo_panel_init() */ - .size = 0, /* Filled in by pismo_panel_init() */ - }, - [2] = { - .name = "vpr", - .usage_mask = NVMAP_HEAP_CARVEOUT_VPR, - .base = 0, /* Filled in by pismo_panel_init() */ - .size = 0, /* Filled in by pismo_panel_init() */ - }, -}; - -static struct nvmap_platform_data pismo_nvmap_data = { - .carveouts = pismo_carveouts, - .nr_carveouts = ARRAY_SIZE(pismo_carveouts), -}; -static struct platform_device pismo_nvmap_device = { - .name = "tegra-nvmap", - .id = -1, - .dev = { - .platform_data = &pismo_nvmap_data, - }, -}; - -static void pismo_panel_select(void) -{ - struct tegra_panel *panel = NULL; - - panel = &dsi_a_1080p_11_6; - if (panel) { - if (panel->init_sd_settings) - panel->init_sd_settings(&sd_settings); - - if (panel->init_dc_out) { - panel->init_dc_out(&pismo_disp1_out); - pismo_disp1_out.dsi->dsi_instance = DSI_INSTANCE_0; - pismo_disp1_out.dsi->dsi_panel_rst_gpio = - DSI_PANEL_RST_GPIO; - pismo_disp1_out.dsi->dsi_panel_bl_pwm_gpio = - DSI_PANEL_BL_PWM_GPIO; - } - - if (panel->init_fb_data) - panel->init_fb_data(&pismo_disp1_fb_data); - - if (panel->init_cmu_data) - panel->init_cmu_data(&pismo_disp1_pdata); - - if (panel->set_disp_device) - panel->set_disp_device(&pismo_disp1_device); - - tegra_dsi_resources_init(pismo_disp1_out.dsi->dsi_instance, - pismo_disp1_resources, - ARRAY_SIZE(pismo_disp1_resources)); - - if (panel->register_bl_dev) - panel->register_bl_dev(); - - if (panel->register_i2c_bridge) - panel->register_i2c_bridge(); - } - -} -int __init pismo_panel_init(void) -{ - int err = 0; - struct resource __maybe_unused *res; - struct platform_device *phost1x = NULL; - - pismo_panel_select(); - -#ifdef CONFIG_TEGRA_NVMAP - pismo_carveouts[1].base = tegra_carveout_start; - pismo_carveouts[1].size = tegra_carveout_size; - pismo_carveouts[2].base = tegra_vpr_start; - pismo_carveouts[2].size = tegra_vpr_size; - - err = platform_device_register(&pismo_nvmap_device); - if (err) { - pr_err("nvmap device registration failed\n"); - return err; - } -#endif - - phost1x = pismo_host1x_init(); - if (!phost1x) { - pr_err("host1x devices registration failed\n"); - return -EINVAL; - } - - res = platform_get_resource_byname(&pismo_disp1_device, - IORESOURCE_MEM, "fbmem"); - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; - - /* Copy the bootloader fb to the fb. */ - __tegra_move_framebuffer(&pismo_nvmap_device, - tegra_fb_start, tegra_bootloader_fb_start, - min(tegra_fb_size, tegra_bootloader_fb_size)); - - pismo_disp1_device.dev.parent = &phost1x->dev; - err = platform_device_register(&pismo_disp1_device); - if (err) { - pr_err("disp1 device registration failed\n"); - return err; - } - - err = tegra_init_hdmi(&pismo_disp2_device, phost1x); - if (err) - return err; - -#ifdef CONFIG_TEGRA_NVAVP - if (!of_have_populated_dt()) { - nvavp_device.dev.parent = &phost1x->dev; - err = platform_device_register(&nvavp_device); - if (err) { - pr_err("nvavp device registration failed\n"); - return err; - } - } -#endif - return err; -} diff --git a/arch/arm/mach-tegra/board-pismo-power.c b/arch/arm/mach-tegra/board-pismo-power.c deleted file mode 100644 index fcc45b90fbf7..000000000000 --- a/arch/arm/mach-tegra/board-pismo-power.c +++ /dev/null @@ -1,919 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo-power.c - * - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/pda_power.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/io.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/driver.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/as3720.h> -#include <linux/gpio.h> -#include <linux/regulator/userspace-consumer.h> - -#include <asm/mach-types.h> - -#include <mach/irqs.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> - -#include "cpu-tegra.h" -#include "pm.h" -#include "tegra-board-id.h" -#include "board.h" -#include "gpio-names.h" -#include "board-common.h" -#include "board-pismo.h" -#include "tegra_cl_dvfs.h" -#include "devices.h" -#include "tegra11_soctherm.h" -#include "iomap.h" - -#define PMC_CTRL 0x0 -#define PMC_CTRL_INTR_LOW (1 << 17) - -static struct regulator_consumer_supply as3720_ldo0_supply[] = { - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegra_camera"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply as3720_ldo1_supply[] = { - REGULATOR_SUPPLY("vddio_cam", "tegra_camera"), - REGULATOR_SUPPLY("pwrdet_cam", NULL), -}; - -static struct regulator_consumer_supply as3720_ldo2_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), -}; - -static struct regulator_consumer_supply as3720_ldo3_supply[] = { - REGULATOR_SUPPLY("vdd_rtc", NULL), -}; - -static struct regulator_consumer_supply as3720_ldo5_supply[] = { - REGULATOR_SUPPLY("vdd_sensor_2v85", NULL), - REGULATOR_SUPPLY("vdd_als", NULL), - REGULATOR_SUPPLY("vdd", "0-004c"), - REGULATOR_SUPPLY("vdd", "0-0069"), -}; - -static struct regulator_consumer_supply as3720_ldo6_supply[] = { - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"), - REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), -}; - -static struct regulator_consumer_supply as3720_ldo8_supply[] = { - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply as3720_sd0_supply[] = { - REGULATOR_SUPPLY("vdd_cpu", NULL), -}; - -static struct regulator_consumer_supply as3720_sd1_supply[] = { - REGULATOR_SUPPLY("vdd_core", NULL), -}; - -static struct regulator_consumer_supply as3720_sd2_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), - REGULATOR_SUPPLY("vcore_emmc", NULL), - REGULATOR_SUPPLY("avdd", "reg-userspace-consumer.2"), - REGULATOR_SUPPLY("vdd_af_cam1", NULL), -}; - -static struct regulator_consumer_supply as3720_sd3_supply[] = { - REGULATOR_SUPPLY("vdd_emmc", NULL), - REGULATOR_SUPPLY("vddio_sys", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"), - REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), - REGULATOR_SUPPLY("vddio_bb", NULL), - REGULATOR_SUPPLY("pwrdet_bb", NULL), - REGULATOR_SUPPLY("vddio_uart", NULL), - REGULATOR_SUPPLY("pwrdet_uart", NULL), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_osc", NULL), - REGULATOR_SUPPLY("vddio_gmi", NULL), - REGULATOR_SUPPLY("pwrdet_nand", NULL), - REGULATOR_SUPPLY("vddio_audio", NULL), - REGULATOR_SUPPLY("pwrdet_audio", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), - REGULATOR_SUPPLY("pwrdet_mipi", NULL), - REGULATOR_SUPPLY("dvdd", "reg-userspace-consumer.1"), - REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"), - REGULATOR_SUPPLY("dvdd", "reg-userspace-consumer.2"), -}; - -static struct regulator_consumer_supply as3720_sd4_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_plle", NULL), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegra_camera"), - REGULATOR_SUPPLY("vddio_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", NULL), -}; - -static struct regulator_consumer_supply as3720_sd5_supply[] = { - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("vddio_hv", "tegradc.1"), - REGULATOR_SUPPLY("pwrdet_hv", NULL), - REGULATOR_SUPPLY("avdd", "reg-userspace-consumer.1"), - REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"), -}; - -static struct regulator_consumer_supply as3720_sd6_supply[] = { - REGULATOR_SUPPLY("vddio_ddr", NULL), - REGULATOR_SUPPLY("vddio_ddr0", NULL), - REGULATOR_SUPPLY("vddio_ddr1", NULL), -}; - -static struct regulator_init_data as3720_ldo0 = { - .constraints = { - .min_uV = 1200000, - .max_uV = 1200000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = false, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo0_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo0_supply), -}; - -static struct regulator_init_data as3720_ldo1 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo1_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo1_supply), -}; - -static struct regulator_init_data as3720_ldo2 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = false, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo2_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo2_supply), -}; - -static struct regulator_init_data as3720_ldo3 = { - .constraints = { - .min_uV = 1100000, - .max_uV = 1100000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo3_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo3_supply), -}; - -static struct regulator_init_data as3720_ldo5 = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo5_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo5_supply), -}; -static struct regulator_init_data as3720_ldo6 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = false, - .boot_on = 0, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo6_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo6_supply), -}; - -static struct regulator_init_data as3720_ldo8 = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_ldo8_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_ldo8_supply), -}; - -static struct regulator_init_data as3720_sd0 = { - .constraints = { - .min_uV = 1100000, - .max_uV = 1100000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd0_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd0_supply), -}; - -static struct regulator_init_data as3720_sd1 = { - .constraints = { - .min_uV = 900000, - .max_uV = 1400000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 0, - }, - .consumer_supplies = as3720_sd1_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd1_supply), -}; - -static struct regulator_init_data as3720_sd2 = { - .constraints = { - .min_uV = 2850000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd2_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd2_supply), -}; - -static struct regulator_init_data as3720_sd3 = { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd3_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd3_supply), -}; - -static struct regulator_init_data as3720_sd4 = { - .constraints = { - .min_uV = 1050000, - .max_uV = 1050000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd4_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd4_supply), -}; - -static struct regulator_init_data as3720_sd5 = { - .constraints = { - .min_uV = 3300000, - .max_uV = 3300000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd5_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd5_supply), -}; - -static struct regulator_init_data as3720_sd6 = { - .constraints = { - .min_uV = 1350000, - .max_uV = 1350000, - .valid_modes_mask = REGULATOR_MODE_NORMAL - | REGULATOR_MODE_STANDBY, - .valid_ops_mask = REGULATOR_CHANGE_MODE - | REGULATOR_CHANGE_STATUS - | REGULATOR_CHANGE_VOLTAGE, - .always_on = true, - .boot_on = 1, - .apply_uV = 1, - }, - .consumer_supplies = as3720_sd6_supply, - .num_consumer_supplies = ARRAY_SIZE(as3720_sd6_supply), -}; - -static struct as3720_reg_init as3720_core_init_data[] = { - /* disable all regulators */ - AS3720_REG_INIT(AS3720_SD_CONTROL_REG, 0x7f), - AS3720_REG_INIT(AS3720_LDOCONTROL0_REG, 0xef), - AS3720_REG_INIT(AS3720_LDOCONTROL1_REG, 0x01), - /* set to lowest voltage output */ - /* set to OTP settings */ - AS3720_REG_INIT(AS3720_SD0_VOLTAGE_REG, 0x32), - AS3720_REG_INIT(AS3720_SD1_VOLTAGE_REG, 0x32), - AS3720_REG_INIT(AS3720_SD2_VOLTAGE_REG, 0xFF), - AS3720_REG_INIT(AS3720_SD3_VOLTAGE_REG, 0xD0), - AS3720_REG_INIT(AS3720_SD4_VOLTAGE_REG, 0xA4), - AS3720_REG_INIT(AS3720_SD5_VOLTAGE_REG, 0xFE), - AS3720_REG_INIT(AS3720_SD6_VOLTAGE_REG, 0x52), - AS3720_REG_INIT(AS3720_LDO0_VOLTAGE_REG, 0x90), - AS3720_REG_INIT(AS3720_LDO1_VOLTAGE_REG, 0x43), - AS3720_REG_INIT(AS3720_LDO2_VOLTAGE_REG, 0x43), - AS3720_REG_INIT(AS3720_LDO3_VOLTAGE_REG, 0xA8), - AS3720_REG_INIT(AS3720_LDO4_VOLTAGE_REG, 0x00), - AS3720_REG_INIT(AS3720_LDO5_VOLTAGE_REG, 0xff), - AS3720_REG_INIT(AS3720_LDO6_VOLTAGE_REG, 0xff), - AS3720_REG_INIT(AS3720_LDO7_VOLTAGE_REG, 0x90), - AS3720_REG_INIT(AS3720_LDO8_VOLTAGE_REG, 0x7F), - AS3720_REG_INIT(AS3720_LDO9_VOLTAGE_REG, 0x00), - AS3720_REG_INIT(AS3720_LDO10_VOLTAGE_REG, 0x00), - AS3720_REG_INIT(AS3720_LDO11_VOLTAGE_REG, 0x00), - {.reg = AS3720_REG_INIT_TERMINATE}, -}; - -/* config settings are OTP plus initial state - * GPIOsignal_out at 20h not configurable through OTP and is initialized to - * zero. To enable output, the invert bit must be turned on. - * GPIOxcontrol register format - * bit(s) bitname - * --------------------- - * 7 gpiox_invert invert input or output - * 6:3 gpiox_iosf 0: normal - * 2:0 gpiox_mode 0: input, 1: output push/pull, 3: ADC input (tristate) - * - * Examples: - * otp meaning - * ------------ - * 0x3 gpiox_invert=0(no invert), gpiox_iosf=0(normal), gpiox_mode=3(ADC input) - * 0x81 gpiox_invert=1(invert), gpiox_iosf=0(normal), gpiox_mode=1(output) - * - * Note: output state should be defined for gpiox_mode = output. Do not change - * the state of the invert bit for critical devices such as GPIO 7 which enables - * SDRAM. Driver applies invert mask to output state to configure GPIOsignal_out - * register correctly. - * E.g. Invert = 1, (requested) output state = 1 => GPIOsignal_out = 0 - */ - -static struct as3720_gpio_config as3720_gpio_cfgs[] = { - { - /* otp = 0x3 */ - .gpio = AS3720_GPIO0, - .mode = AS3720_GPIO_MODE_ADC_IN, - }, - { - /* otp = 0x3 */ - .gpio = AS3720_GPIO1, - .mode = AS3720_GPIO_MODE_ADC_IN, - }, - { - /* otp = 0x3 */ - .gpio = AS3720_GPIO2, - .mode = AS3720_GPIO_MODE_ADC_IN, - }, - { - /* otp = 0x01 => REGEN_3 = LP0 gate (1.8V, 5 V) */ - .gpio = AS3720_GPIO3, - .invert = AS3720_GPIO_CFG_INVERT, /* don't go into LP0 */ - .mode = AS3720_GPIO_MODE_OUTPUT_VDDH, - .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED, - }, - { - /* otp = 0x81 => on by default - * gates SDMMC3 - */ - .gpio = AS3720_GPIO4, - .invert = AS3720_GPIO_CFG_NO_INVERT, - .mode = AS3720_GPIO_MODE_OUTPUT_VDDH, - .output_state = AS3720_GPIO_CFG_OUTPUT_DISABLED, - }, - { - /* otp = 0x3 EN_MIC_BIAS_L */ - .gpio = AS3720_GPIO5, - .mode = AS3720_GPIO_MODE_ADC_IN, - }, - { - /* otp = 0x3 CAM_LDO1_EN */ - .gpio = AS3720_GPIO6, - .mode = AS3720_GPIO_MODE_ADC_IN, - }, - { - /* otp = 0x81 */ - .gpio = AS3720_GPIO7, - .invert = AS3720_GPIO_CFG_INVERT, - .mode = AS3720_GPIO_MODE_OUTPUT_VDDH, - .output_state = AS3720_GPIO_CFG_OUTPUT_ENABLED, - }, -}; - -static struct as3720_platform_data as3720_pdata = { - .reg_init[AS3720_LDO0] = &as3720_ldo0, - .reg_init[AS3720_LDO1] = &as3720_ldo1, - .reg_init[AS3720_LDO2] = &as3720_ldo2, - .reg_init[AS3720_LDO3] = &as3720_ldo3, - .reg_init[AS3720_LDO5] = &as3720_ldo5, - .reg_init[AS3720_LDO6] = &as3720_ldo6, - .reg_init[AS3720_LDO8] = &as3720_ldo8, - .reg_init[AS3720_SD0] = &as3720_sd0, - .reg_init[AS3720_SD1] = &as3720_sd1, - .reg_init[AS3720_SD2] = &as3720_sd2, - .reg_init[AS3720_SD3] = &as3720_sd3, - .reg_init[AS3720_SD4] = &as3720_sd4, - .reg_init[AS3720_SD5] = &as3720_sd5, - .reg_init[AS3720_SD6] = &as3720_sd6, - - .core_init_data = &as3720_core_init_data[0], - .gpio_base = AS3720_GPIO_BASE, - .rtc_start_year = 2010, - - .num_gpio_cfgs = ARRAY_SIZE(as3720_gpio_cfgs), - .gpio_cfgs = as3720_gpio_cfgs, -}; - -static struct i2c_board_info __initdata as3720_regulators[] = { - { - I2C_BOARD_INFO("as3720", 0x40), - .flags = I2C_CLIENT_WAKE, - .irq = INT_EXTERNAL_PMU, - .platform_data = &as3720_pdata, - }, -}; - -int __init pismo_as3720_regulator_init(void) -{ - printk(KERN_INFO "%s: i2c_register_board_info\n", - __func__); - i2c_register_board_info(4, as3720_regulators, - ARRAY_SIZE(as3720_regulators)); - return 0; -} - -static int ac_online(void) -{ - return 1; -} - -static struct resource pismo_pda_resources[] = { - [0] = { - .name = "ac", - }, -}; - -static struct pda_power_pdata pismo_pda_data = { - .is_ac_online = ac_online, -}; - -static struct platform_device pismo_pda_power_device = { - .name = "pda-power", - .id = -1, - .resource = pismo_pda_resources, - .num_resources = ARRAY_SIZE(pismo_pda_resources), - .dev = { - .platform_data = &pismo_pda_data, - }, -}; - -static struct tegra_suspend_platform_data pismo_suspend_data = { - .cpu_timer = 2000, - .cpu_off_timer = 2000, - .suspend_mode = TEGRA_SUSPEND_NONE, - .core_timer = 0x7e7e, - .core_off_timer = 2000, - .corereq_high = true, - .sysclkreq_high = true, - .cpu_lp2_min_residency = 1000, -}; - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -/* board parameters for cpu dfll */ -static struct tegra_cl_dvfs_cfg_param pismo_cl_dvfs_param = { - .sample_rate = 12500, - - .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, - .cf = 10, - .ci = 0, - .cg = 2, - - .droop_cut_value = 0xF, - .droop_restore_ramp = 0x0, - .scale_out_ramp = 0x0, -}; -#endif - -/* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */ -#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) -static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; -static inline void fill_reg_map(void) -{ - int i; - for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { - pmu_cpu_vdd_map[i].reg_value = i + 0x23; - pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; - } -} - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static struct tegra_cl_dvfs_platform_data pismo_cl_dvfs_data = { - .dfll_clk_name = "dfll_cpu", - .pmu_if = TEGRA_CL_DVFS_PMU_I2C, - .u.pmu_i2c = { - .fs_rate = 400000, - .slave_addr = 0x86, - .reg = 0x00, - }, - .vdd_map = pmu_cpu_vdd_map, - .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, - - .cfg_param = &pismo_cl_dvfs_param, -}; - -static int __init pismo_cl_dvfs_init(void) -{ - fill_reg_map(); - tegra_cl_dvfs_device.dev.platform_data = &pismo_cl_dvfs_data; - platform_device_register(&tegra_cl_dvfs_device); - - return 0; -} -#endif - -static struct regulator_bulk_data pismo_gps_regulator_supply[] = { - [0] = { - .supply = "avdd", - }, - [1] = { - .supply = "dvdd", - }, -}; - -static struct regulator_userspace_consumer_data pismo_gps_regulator_pdata = { - .num_supplies = ARRAY_SIZE(pismo_gps_regulator_supply), - .supplies = pismo_gps_regulator_supply, -}; - -static struct platform_device pismo_gps_regulator_device = { - .name = "reg-userspace-consumer", - .id = 2, - .dev = { - .platform_data = &pismo_gps_regulator_pdata, - }, -}; - -static struct regulator_bulk_data pismo_bt_regulator_supply[] = { - [0] = { - .supply = "avdd", - }, - [1] = { - .supply = "dvdd", - }, -}; - -static struct regulator_userspace_consumer_data pismo_bt_regulator_pdata = { - .num_supplies = ARRAY_SIZE(pismo_bt_regulator_supply), - .supplies = pismo_bt_regulator_supply, -}; - -static struct platform_device pismo_bt_regulator_device = { - .name = "reg-userspace-consumer", - .id = 1, - .dev = { - .platform_data = &pismo_bt_regulator_pdata, - }, -}; - -/* Gated by CAM_LDO1_EN From AMS7230 GPIO6*/ -static struct regulator_consumer_supply fixed_reg_en_1v8_cam_supply[] = { - REGULATOR_SUPPLY("dvdd_cam", NULL), - REGULATOR_SUPPLY("vdd_cam_1v8", NULL), - REGULATOR_SUPPLY("vi2c", "2-0030"), - REGULATOR_SUPPLY("vif", "2-0036"), - REGULATOR_SUPPLY("dovdd", "2-0010"), - REGULATOR_SUPPLY("vdd_i2c", "2-000e"), -}; - -/* Gated by PMU_REGEN3 From AMS7230 GPIO3*/ -static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = { - REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"), -}; - -/* Not gated */ -static struct regulator_consumer_supply fixed_reg_usb1_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"), - REGULATOR_SUPPLY("usb_vbus", "tegra-otg"), -}; - -/* Not Gated */ -static struct regulator_consumer_supply fixed_reg_usb3_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"), -}; - -/* Macro for defining fixed regulator sub device data */ -#define FIXED_SUPPLY(_name) "fixed_reg_"#_name -#define FIXED_REG(_id, _var, _name, _always_on, _boot_on, \ - _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \ - static struct regulator_init_data ri_data_##_var = \ - { \ - .num_consumer_supplies = \ - ARRAY_SIZE(fixed_reg_##_name##_supply), \ - .consumer_supplies = fixed_reg_##_name##_supply, \ - .constraints = { \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - }, \ - }; \ - static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ - { \ - .supply_name = FIXED_SUPPLY(_name), \ - .microvolts = _millivolts * 1000, \ - .gpio = _gpio_nr, \ - .gpio_is_open_drain = _open_drain, \ - .enable_high = _active_high, \ - .enabled_at_boot = _boot_state, \ - .init_data = &ri_data_##_var, \ - }; \ - static struct platform_device fixed_reg_##_var##_dev = { \ - .name = "reg-fixed-voltage", \ - .id = _id, \ - .dev = { \ - .platform_data = &fixed_reg_##_var##_pdata, \ - }, \ - } - -FIXED_REG(1, en_1v8_cam, en_1v8_cam, 0, 0, - AS3720_GPIO_BASE + AS3720_GPIO6, false, true, 0, 1800); - -FIXED_REG(2, vdd_hdmi_5v0, vdd_hdmi_5v0, 0, 0, - TEGRA_GPIO_PK1, false, true, 0, 5000); - -FIXED_REG(3, usb1_vbus, usb1_vbus, 0, 0, - -EINVAL, true, true, 1, 5000); - -FIXED_REG(4, usb3_vbus, usb3_vbus, 0, 0, - -EINVAL, true, true, 1, 5000); - -/* - * Creating the fixed regulator device tables - */ - -#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) - -#define PISMO_COMMON_FIXED_REG \ - ADD_FIXED_REG(usb1_vbus), \ - ADD_FIXED_REG(usb3_vbus), \ - ADD_FIXED_REG(vdd_hdmi_5v0), \ - ADD_FIXED_REG(en_1v8_cam), - -/* Gpio switch regulator platform data for pluto */ -static struct platform_device *fixed_reg_devs_pm347[] = { - PISMO_COMMON_FIXED_REG -}; - - -static int __init pismo_fixed_regulator_init(void) -{ - - if (!machine_is_pismo()) - return 0; - - return platform_add_devices(fixed_reg_devs_pm347, - ARRAY_SIZE(fixed_reg_devs_pm347)); -} - -subsys_initcall_sync(pismo_fixed_regulator_init); - -int __init pismo_regulator_init(void) -{ - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - pismo_cl_dvfs_init(); -#endif - pismo_as3720_regulator_init(); - - platform_device_register(&pismo_pda_power_device); - platform_device_register(&pismo_bt_regulator_device); - platform_device_register(&pismo_gps_regulator_device); - return 0; -} - -int __init pismo_suspend_init(void) -{ - tegra_init_suspend(&pismo_suspend_data); - return 0; -} - -int __init pismo_edp_init(void) -{ -#ifdef CONFIG_TEGRA_EDP_LIMITS - unsigned int regulator_mA; - - regulator_mA = get_maximum_cpu_current_supported(); - if (!regulator_mA) - regulator_mA = 15000; - - pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); - - tegra_init_cpu_edp_limits(regulator_mA); -#endif - return 0; -} - -/* place holder for tpdata for as3720 regulator - * TODO: fill the correct i2c type, bus, reg_addr and data here: -static struct tegra_thermtrip_pmic_data tpdata_as3720 = { - .reset_tegra = , - .pmu_16bit_ops = , - .controller_type = , - .pmu_i2c_addr = , - .i2c_controller_id = , - .poweroff_reg_addr = , - .poweroff_reg_data = , -}; -*/ - -static struct soctherm_platform_data pismo_soctherm_data = { - .therm = { - [THERM_CPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - }, - [THERM_GPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - }, - [THERM_PLL] = { - .zone_enable = true, - }, - }, - .throttle = { - [THROTTLE_HEAVY] = { - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = 1, - }, - }, - }, - }, - /* ENABLE THIS AFTER correctly setting up tpdata_as3720 - * .tshut_pmu_trip_data = &tpdata_as3720, */ -}; - -int __init pismo_soctherm_init(void) -{ - tegra_platform_edp_init(pismo_soctherm_data.therm[THERM_CPU].trips, - &pismo_soctherm_data.therm[THERM_CPU].num_trips, - 6000); /* edp temperature margin */ - tegra_add_cpu_vmax_trips(pismo_soctherm_data.therm[THERM_CPU].trips, - &pismo_soctherm_data.therm[THERM_CPU].num_trips); - tegra_add_core_edp_trips(pismo_soctherm_data.therm[THERM_CPU].trips, - &pismo_soctherm_data.therm[THERM_CPU].num_trips); - - return tegra11_soctherm_init(&pismo_soctherm_data); -} diff --git a/arch/arm/mach-tegra/board-pismo-sdhci.c b/arch/arm/mach-tegra/board-pismo-sdhci.c deleted file mode 100644 index 1a8f35a69465..000000000000 --- a/arch/arm/mach-tegra/board-pismo-sdhci.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo-sdhci.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/wlan_plat.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/regulator/consumer.h> -#include <linux/mmc/host.h> -#include <linux/wl12xx.h> -#include <linux/platform_data/mmc-sdhci-tegra.h> - -#include <asm/mach-types.h> -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> -#include <mach/io_dpd.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-pismo.h" -#include "iomap.h" - -#define PISMO_WLAN_PWR TEGRA_GPIO_PCC5 -#define PISMO_WLAN_RST TEGRA_GPIO_PX7 -#define PISMO_WLAN_WOW TEGRA_GPIO_PU5 -#define PISMO_SD_CD TEGRA_GPIO_PV2 -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; -static int pismo_wifi_status_register(void (*callback)(int , void *), void *); - -static int pismo_wifi_reset(int on); -static int pismo_wifi_power(int on); -static int pismo_wifi_set_carddetect(int val); - -static struct wifi_platform_data pismo_wifi_control = { - .set_power = pismo_wifi_power, - .set_reset = pismo_wifi_reset, - .set_carddetect = pismo_wifi_set_carddetect, -}; - -static struct resource wifi_resource[] = { - [0] = { - .name = "bcm4329_wlan_irq", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - | IORESOURCE_IRQ_SHAREABLE, - }, -}; - -static struct platform_device pismo_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .num_resources = 1, - .resource = wifi_resource, - .dev = { - .platform_data = &pismo_wifi_control, - }, -}; - -static struct resource sdhci_resource0[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -#ifdef CONFIG_MMC_EMBEDDED_SDIO -static struct embedded_sdio_data embedded_sdio_data0 = { - .cccr = { - .sdio_vsn = 2, - .multi_block = 1, - .low_speed = 0, - .wide_bus = 0, - .high_power = 1, - .high_speed = 1, - }, - .cis = { - .vendor = 0x02d0, - .device = 0x4329, - }, -}; -#endif - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = { - .mmc_data = { - .register_status_notify = pismo_wifi_status_register, -#ifdef CONFIG_MMC_EMBEDDED_SDIO - .embedded_sdio = &embedded_sdio_data0, -#endif - .built_in = 0, - .ocr_mask = MMC_OCR_1V8_MASK, - }, -#ifndef CONFIG_MMC_EMBEDDED_SDIO - .pm_flags = MMC_PM_KEEP_POWER, -#endif - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x2, - .trim_delay = 0x2, - .ddr_clk_limit = 41000000, - .uhs_mask = MMC_UHS_MASK_SDR104 | - MMC_UHS_MASK_DDR50, - .disable_clock_gate = true, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { - .cd_gpio = PISMO_SD_CD, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x3, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, - .tap_delay = 0x5, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, - .mmc_data = { - .built_in = 1, - .ocr_mask = MMC_OCR_1V8_MASK, - } -}; - -static struct platform_device tegra_sdhci_device0 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource0, - .num_resources = ARRAY_SIZE(sdhci_resource0), - .dev = { - .platform_data = &tegra_sdhci_platform_data0, - }, -}; - -static struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), - .dev = { - .platform_data = &tegra_sdhci_platform_data2, - }, -}; - -static struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), - .dev = { - .platform_data = &tegra_sdhci_platform_data3, - }, -}; - -static int pismo_wifi_status_register( - void (*callback)(int card_present, void *dev_id), - void *dev_id) -{ - if (wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -static int pismo_wifi_set_carddetect(int val) -{ - pr_debug("%s: %d\n", __func__, val); - if (wifi_status_cb) - wifi_status_cb(val, wifi_status_cb_devid); - else - pr_warning("%s: Nobody to notify\n", __func__); - return 0; -} - -static struct regulator *pismo_vdd_com_3v3; -static struct regulator *pismo_vddio_com_1v8; -#define PISMO_VDD_WIFI_3V3 "avdd" -#define PISMO_VDD_WIFI_1V8 "dvdd" - -static int pismo_wifi_regulator_enable(void) -{ - int ret = 0; - - /* Enable COM's vdd_com_3v3 regulator*/ - if (IS_ERR_OR_NULL(pismo_vdd_com_3v3)) { - pismo_vdd_com_3v3 = regulator_get(&pismo_wifi_device.dev, - PISMO_VDD_WIFI_3V3); - if (IS_ERR(pismo_vdd_com_3v3)) { - pr_err("Couldn't get regulator " - PISMO_VDD_WIFI_3V3 "\n"); - return PTR_ERR(pismo_vdd_com_3v3); - } - - ret = regulator_enable(pismo_vdd_com_3v3); - if (ret < 0) { - pr_err("Couldn't enable regulator " - PISMO_VDD_WIFI_3V3 "\n"); - regulator_put(pismo_vdd_com_3v3); - pismo_vdd_com_3v3 = NULL; - return ret; - } - } - - /* Enable COM's vddio_com_1v8 regulator*/ - if (IS_ERR_OR_NULL(pismo_vddio_com_1v8)) { - pismo_vddio_com_1v8 = regulator_get(&pismo_wifi_device.dev, - PISMO_VDD_WIFI_1V8); - if (IS_ERR(pismo_vddio_com_1v8)) { - pr_err("Couldn't get regulator " - PISMO_VDD_WIFI_1V8 "\n"); - regulator_disable(pismo_vdd_com_3v3); - - regulator_put(pismo_vdd_com_3v3); - pismo_vdd_com_3v3 = NULL; - return PTR_ERR(pismo_vddio_com_1v8); - } - - ret = regulator_enable(pismo_vddio_com_1v8); - if (ret < 0) { - pr_err("Couldn't enable regulator " - PISMO_VDD_WIFI_1V8 "\n"); - regulator_put(pismo_vddio_com_1v8); - pismo_vddio_com_1v8 = NULL; - - regulator_disable(pismo_vdd_com_3v3); - regulator_put(pismo_vdd_com_3v3); - pismo_vdd_com_3v3 = NULL; - return ret; - } - } - - return ret; -} - -static void pismo_wifi_regulator_disable(void) -{ - /* Disable COM's vdd_com_3v3 regulator*/ - if (!IS_ERR_OR_NULL(pismo_vdd_com_3v3)) { - regulator_disable(pismo_vdd_com_3v3); - regulator_put(pismo_vdd_com_3v3); - pismo_vdd_com_3v3 = NULL; - } - - /* Disable COM's vddio_com_1v8 regulator*/ - if (!IS_ERR_OR_NULL(pismo_vddio_com_1v8)) { - regulator_disable(pismo_vddio_com_1v8); - regulator_put(pismo_vddio_com_1v8); - pismo_vddio_com_1v8 = NULL; - } -} - -static int pismo_wifi_power(int on) -{ - struct tegra_io_dpd *sd_dpd; - int ret = 0; - - pr_debug("%s: %d\n", __func__, on); - /* Enable COM's regulators on wi-fi poer on*/ - if (on == 1) { - ret = pismo_wifi_regulator_enable(); - if (ret < 0) { - pr_err("Failed to enable COM regulators\n"); - return ret; - } - } - - /* - * FIXME : we need to revisit IO DPD code - * on how should multiple pins under DPD get controlled - * - * pismo GPIO WLAN enable is part of SDMMC3 pin group - */ - sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); - if (sd_dpd) { - mutex_lock(&sd_dpd->delay_lock); - tegra_io_dpd_disable(sd_dpd); - mutex_unlock(&sd_dpd->delay_lock); - } - gpio_set_value(PISMO_WLAN_PWR, on); - mdelay(100); - gpio_set_value(PISMO_WLAN_RST, on); - mdelay(200); - if (sd_dpd) { - mutex_lock(&sd_dpd->delay_lock); - tegra_io_dpd_enable(sd_dpd); - mutex_unlock(&sd_dpd->delay_lock); - } - - /* Disable COM's regulators on wi-fi poer off*/ - if (on != 1) { - pr_debug("Disabling COM regulators\n"); - pismo_wifi_regulator_disable(); - } - - return ret; -} - -static int pismo_wifi_reset(int on) -{ - pr_debug("%s: do nothing\n", __func__); - return 0; -} - -static int __init pismo_wifi_init(void) -{ - int rc; - - rc = gpio_request(PISMO_WLAN_PWR, "wlan_power"); - if (rc) - pr_err("WLAN_PWR gpio request failed:%d\n", rc); - rc = gpio_request(PISMO_WLAN_RST, "wlan_rst"); - if (rc) - pr_err("WLAN_RST gpio request failed:%d\n", rc); - rc = gpio_request(PISMO_WLAN_WOW, "bcmsdh_sdmmc"); - if (rc) - pr_err("WLAN_WOW gpio request failed:%d\n", rc); - - rc = gpio_direction_output(PISMO_WLAN_PWR, 0); - if (rc) - pr_err("WLAN_PWR gpio direction configuration failed:%d\n", rc); - gpio_direction_output(PISMO_WLAN_RST, 0); - if (rc) - pr_err("WLAN_RST gpio direction configuration failed:%d\n", rc); - rc = gpio_direction_input(PISMO_WLAN_WOW); - if (rc) - pr_err("WLAN_WOW gpio direction configuration failed:%d\n", rc); - - wifi_resource[0].start = wifi_resource[0].end = - gpio_to_irq(PISMO_WLAN_WOW); - - platform_device_register(&pismo_wifi_device); - return 0; -} - -#ifdef CONFIG_TEGRA_PREPOWER_WIFI -static int __init pismo_wifi_prepower(void) -{ - if (!machine_is_pismo()) - return 0; - - pismo_wifi_power(1); - - return 0; -} - -subsys_initcall_sync(pismo_wifi_prepower); -#endif - -int __init pismo_sdhci_init(void) -{ - platform_device_register(&tegra_sdhci_device3); - platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device0); - pismo_wifi_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-pismo-sensors.c b/arch/arm/mach-tegra/board-pismo-sensors.c deleted file mode 100644 index d3e56c95c3e0..000000000000 --- a/arch/arm/mach-tegra/board-pismo-sensors.c +++ /dev/null @@ -1,696 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo-sensors.c - * - * Copyright (c) 2012-2014 NVIDIA CORPORATION, All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * Neither the name of NVIDIA CORPORATION nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/i2c.h> -#include <linux/delay.h> -#include <linux/mpu.h> -#include <linux/regulator/consumer.h> -#include <linux/gpio.h> -#include <linux/therm_est.h> -#include <linux/nct1008.h> -#include <mach/edp.h> - -#include <mach/gpio-tegra.h> -#include <mach/pinmux-t11.h> -#include <mach/pinmux.h> -#include <media/imx091.h> -#include <media/ov9772.h> -#include <media/as364x.h> -#include <media/ad5816.h> -#include <generated/mach-types.h> -#include <linux/power/sbs-battery.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-common.h" -#include "board-pismo.h" -#include "cpu-tegra.h" -#include "devices.h" -#include "tegra-board-id.h" -#include "dvfs.h" - -static struct nvc_gpio_pdata imx091_gpio_pdata[] = { - {IMX091_GPIO_RESET, CAM_RSTN, true, false}, - {IMX091_GPIO_PWDN, CAM1_POWER_DWN_GPIO, true, false}, - {IMX091_GPIO_GP1, CAM_GPIO1, true, false} -}; - -static struct throttle_table tj_throttle_table[] = { - { { 0, 1000 } }, - { { 51000, 1000 } }, - { { 102000, 1000 } }, - { { 204000, 1000 } }, - { { 252000, 1000 } }, - { { 288000, 1000 } }, - { { 372000, 1000 } }, - { { 468000, 1000 } }, - { { 510000, 1000 } }, - { { 612000, 1000 } }, - { { 714000, 1050 } }, - { { 816000, 1050 } }, - { { 918000, 1050 } }, - { {1020000, 1100 } }, - { {1122000, 1100 } }, - { {1224000, 1100 } }, - { {1326000, 1100 } }, - { {1428000, 1100 } }, - { {1530000, 1100 } }, -}; - -static struct balanced_throttle tj_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_throttle_table), - .throt_tab = tj_throttle_table, -}; - -static int __init pismo_throttle_init(void) -{ - if (machine_is_pismo()) - balanced_throttle_register(&tj_throttle, "pismo-nct"); - return 0; -} -module_init(pismo_throttle_init); - -static struct nct1008_platform_data pismo_nct1008_pdata = { - .supported_hwrev = true, - .extended_range = true, - .conv_rate = 0x06, /* 4Hz conversion rate */ - - .sensors = { - [LOC] = { - .shutdown_limit = 120, /* C */ - .num_trips = 0, - .tzp = NULL, - }, - [EXT] = { - .shutdown_limit = 105, /* C */ - .num_trips = 1, - .tzp = NULL, - .trips = { - { - .cdev_type = "suspend_soctherm", - .trip_temp = 50000, - .trip_type = THERMAL_TRIP_ACTIVE, - .upper = 1, - .lower = 1, - .hysteresis = 5000, - .mask = 1, - }, - }, - } - } -}; - -static struct i2c_board_info pismo_i2c4_nct1008_board_info[] = { - { - I2C_BOARD_INFO("nct1008", 0x4C), - .platform_data = &pismo_nct1008_pdata, - .irq = -1, - } -}; - -#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ - { \ - .pingroup = TEGRA_PINGROUP_##_pingroup, \ - .func = TEGRA_MUX_##_mux, \ - .pupd = TEGRA_PUPD_##_pupd, \ - .tristate = TEGRA_TRI_##_tri, \ - .io = TEGRA_PIN_##_io, \ - .lock = TEGRA_PIN_LOCK_##_lock, \ - .od = TEGRA_PIN_OD_DEFAULT, \ - .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ -} - -static int pismo_focuser_power_on(struct ad5816_power_rail *pw) -{ - int err; - - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - err = regulator_enable(pw->vdd_i2c); - if (unlikely(err)) - goto ad5816_vdd_i2c_fail; - - err = regulator_enable(pw->vdd); - if (unlikely(err)) - goto ad5816_vdd_fail; - - return 0; - -ad5816_vdd_fail: - regulator_disable(pw->vdd_i2c); - -ad5816_vdd_i2c_fail: - pr_err("%s FAILED\n", __func__); - - return -ENODEV; -} - -static int pismo_focuser_power_off(struct ad5816_power_rail *pw) -{ - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - regulator_disable(pw->vdd); - regulator_disable(pw->vdd_i2c); - - return 0; -} - -static struct tegra_pingroup_config mclk_disable = - VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config mclk_enable = - VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_disable = - VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_enable = - VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -/* - * As a workaround, pismo_vcmvdd need to be allocated to activate the - * sensor devices. This is due to the focuser device(AD5816) will hook up - * the i2c bus if it is not powered up. -*/ -static struct regulator *pismo_vcmvdd; - -static int pismo_get_vcmvdd(void) -{ - if (!pismo_vcmvdd) { - pismo_vcmvdd = regulator_get(NULL, "vdd_af_cam1"); - if (unlikely(WARN_ON(IS_ERR(pismo_vcmvdd)))) { - pr_err("%s: can't get regulator vcmvdd: %ld\n", - __func__, PTR_ERR(pismo_vcmvdd)); - pismo_vcmvdd = NULL; - return -ENODEV; - } - } - return 0; -} - -static int pismo_imx091_power_on(struct nvc_regulator *vreg) -{ - int err; - - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - if (pismo_get_vcmvdd()) - goto imx091_poweron_fail; - - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(10, 20); - - err = regulator_enable(vreg[IMX091_VREG_AVDD].vreg); - if (err) - goto imx091_avdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_IOVDD].vreg); - if (err) - goto imx091_iovdd_fail; - - usleep_range(1, 2); - gpio_set_value(CAM1_POWER_DWN_GPIO, 1); - - err = regulator_enable(pismo_vcmvdd); - if (unlikely(err)) - goto imx091_vcmvdd_fail; - - tegra_pinmux_config_table(&mclk_enable, 1); - usleep_range(300, 310); - - return 1; - -imx091_vcmvdd_fail: - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - -imx091_iovdd_fail: - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - -imx091_avdd_fail: - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - -imx091_poweron_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int pismo_imx091_power_off(struct nvc_regulator *vreg) -{ - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - usleep_range(1, 2); - tegra_pinmux_config_table(&mclk_disable, 1); - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(1, 2); - - regulator_disable(pismo_vcmvdd); - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - - return 1; -} - -static struct nvc_imager_cap imx091_cap = { - .identifier = "IMX091", - .sensor_nvc_interface = 3, - .pixel_types[0] = 0x100, - .orientation = 0, - .direction = 0, - .initial_clock_rate_khz = 6000, - .clock_profiles[0] = { - .external_clock_khz = 24000, - .clock_multiplier = 10416667, /* value / 1,000,000 */ - }, - .clock_profiles[1] = { - .external_clock_khz = 0, - .clock_multiplier = 0, - }, - .h_sync_edge = 0, - .v_sync_edge = 0, - .mclk_on_vgp0 = 0, - .csi_port = 0, - .data_lanes = 4, - .virtual_channel_id = 0, - .discontinuous_clk_mode = 1, - .cil_threshold_settle = 0x0, - .min_blank_time_width = 16, - .min_blank_time_height = 16, - .preferred_mode_index = 0, - .focuser_guid = NVC_FOCUS_GUID(0), - .torch_guid = NVC_TORCH_GUID(0), - .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2, -}; - -static struct imx091_platform_data imx091_pdata = { - .num = 0, - .sync = 0, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(imx091_gpio_pdata), - .gpio = imx091_gpio_pdata, - .flash_cap = { - .sdo_trigger_enabled = 1, - .adjustable_flash_timing = 1, - }, - .cap = &imx091_cap, - .power_on = pismo_imx091_power_on, - .power_off = pismo_imx091_power_off, -}; - -static struct sbs_platform_data sbs_pdata = { - .poll_retry_count = 100, - .i2c_retry_count = 2, -}; - -static int pismo_ov9772_power_on(struct ov9772_power_rail *pw) -{ - int err; - - if (unlikely(!pw || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - if (pismo_get_vcmvdd()) - goto ov9772_get_vcmvdd_fail; - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - err = regulator_enable(pw->avdd); - if (unlikely(err)) - goto ov9772_avdd_fail; - - err = regulator_enable(pw->dovdd); - if (unlikely(err)) - goto ov9772_dovdd_fail; - - gpio_set_value(CAM_RSTN, 1); - gpio_set_value(CAM2_POWER_DWN_GPIO, 1); - - err = regulator_enable(pismo_vcmvdd); - if (unlikely(err)) - goto ov9772_vcmvdd_fail; - - tegra_pinmux_config_table(&pbb0_enable, 1); - usleep_range(340, 380); - - /* return 1 to skip the in-driver power_on sequence */ - return 1; - -ov9772_vcmvdd_fail: - regulator_disable(pw->dovdd); - -ov9772_dovdd_fail: - regulator_disable(pw->avdd); - -ov9772_avdd_fail: - gpio_set_value(CAM_RSTN, 0); - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - -ov9772_get_vcmvdd_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int pismo_ov9772_power_off(struct ov9772_power_rail *pw) -{ - if (unlikely(!pw || !pismo_vcmvdd || !pw->avdd || !pw->dovdd)) - return -EFAULT; - - usleep_range(21, 25); - tegra_pinmux_config_table(&pbb0_disable, 1); - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - gpio_set_value(CAM_RSTN, 0); - - regulator_disable(pismo_vcmvdd); - regulator_disable(pw->dovdd); - regulator_disable(pw->avdd); - - /* return 1 to skip the in-driver power_off sequence */ - return 1; -} - -static struct nvc_gpio_pdata ov9772_gpio_pdata[] = { - { OV9772_GPIO_TYPE_SHTDN, CAM2_POWER_DWN_GPIO, true, 0, }, - { OV9772_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0, }, -}; - -static struct ov9772_platform_data pismo_ov9772_pdata = { - .num = 1, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(ov9772_gpio_pdata), - .gpio = ov9772_gpio_pdata, - .power_on = pismo_ov9772_power_on, - .power_off = pismo_ov9772_power_off, -}; - -static int pismo_as3648_power_on(struct as364x_power_rail *pw) -{ - int err = pismo_get_vcmvdd(); - - if (err) - return err; - - return regulator_enable(pismo_vcmvdd); -} - -static int pismo_as3648_power_off(struct as364x_power_rail *pw) -{ - if (!pismo_vcmvdd) - return -ENODEV; - - return regulator_disable(pismo_vcmvdd); -} - -static struct as364x_platform_data pismo_as3648_pdata = { - .config = { - .led_mask = 3, - .max_total_current_mA = 1000, - .max_peak_current_mA = 600, - .vin_low_v_run_mV = 3070, - .strobe_type = 1, - }, - .pinstate = { - .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0), - .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0) - }, - .dev_name = "torch", - .type = AS3648, - .gpio_strobe = CAM_FLASH_STROBE, - - .power_on_callback = pismo_as3648_power_on, - .power_off_callback = pismo_as3648_power_off, -}; - -static struct ad5816_platform_data pismo_ad5816_pdata = { - .cfg = 0, - .num = 0, - .sync = 0, - .dev_name = "focuser", - .power_on = pismo_focuser_power_on, - .power_off = pismo_focuser_power_off, -}; - -static struct i2c_board_info pismo_i2c_board_info_e1625[] = { - { - I2C_BOARD_INFO("imx091", 0x36), - .platform_data = &imx091_pdata, - }, - { - I2C_BOARD_INFO("ov9772", 0x10), - .platform_data = &pismo_ov9772_pdata, - }, - { - I2C_BOARD_INFO("as3648", 0x30), - .platform_data = &pismo_as3648_pdata, - }, - { - I2C_BOARD_INFO("ad5816", 0x0E), - .platform_data = &pismo_ad5816_pdata, - }, -}; - -static int pismo_camera_init(void) -{ - tegra_pinmux_config_table(&mclk_disable, 1); - tegra_pinmux_config_table(&pbb0_disable, 1); - - i2c_register_board_info(2, pismo_i2c_board_info_e1625, - ARRAY_SIZE(pismo_i2c_board_info_e1625)); - return 0; -} - -/* MPU board file definition */ -static struct mpu_platform_data mpu9150_gyro_data = { - .int_config = 0x10, - .level_shifter = 0, - /* Located in board_[platformname].h */ - .orientation = MPU_GYRO_ORIENTATION, - .sec_slave_type = SECONDARY_SLAVE_TYPE_COMPASS, - .sec_slave_id = COMPASS_ID_AK8975, - .secondary_i2c_addr = MPU_COMPASS_ADDR, - .secondary_read_reg = 0x06, - .secondary_orientation = MPU_COMPASS_ORIENTATION, - .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22, - 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89}, -}; - -#define TEGRA_CAMERA_GPIO(_gpio, _label, _value) \ - { \ - .gpio = _gpio, \ - .label = _label, \ - .value = _value, \ - } - -static struct i2c_board_info pismo_i2c_board_info_cm3218[] = { - { - I2C_BOARD_INFO("cm3218", 0x48), - }, -}; - -static struct i2c_board_info __initdata inv_mpu9150_i2c2_board_info[] = { - { - I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR), - .platform_data = &mpu9150_gyro_data, - }, -}; - -static void mpuirq_init(void) -{ - int ret = 0; - unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO; - unsigned gyro_bus_num = MPU_GYRO_BUS_NUM; - char *gyro_name = MPU_GYRO_NAME; - - pr_info("*** MPU START *** mpuirq_init...\n"); - - ret = gpio_request(gyro_irq_gpio, gyro_name); - - if (ret < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, ret); - return; - } - - ret = gpio_direction_input(gyro_irq_gpio); - if (ret < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, ret); - gpio_free(gyro_irq_gpio); - return; - } - pr_info("*** MPU END *** mpuirq_init...\n"); - - inv_mpu9150_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO); - i2c_register_board_info(gyro_bus_num, inv_mpu9150_i2c2_board_info, - ARRAY_SIZE(inv_mpu9150_i2c2_board_info)); -} - -static int pismo_nct1008_init(void) -{ - int nct1008_port; - int ret = 0; - - nct1008_port = TEGRA_GPIO_PX6; - - tegra_add_all_vmin_trips(pismo_nct1008_pdata.sensors[EXT].trips, - &pismo_nct1008_pdata.sensors[EXT].num_trips); - - pismo_i2c4_nct1008_board_info[0].irq = - gpio_to_irq(nct1008_port); - pr_info("%s: pismo nct1008 irq %d", __func__, - pismo_i2c4_nct1008_board_info[0].irq); - - ret = gpio_request(nct1008_port, "temp_alert"); - if (ret < 0) - return ret; - - ret = gpio_direction_input(nct1008_port); - if (ret < 0) { - pr_info("%s: calling gpio_free(nct1008_port)", - __func__); - gpio_free(nct1008_port); - } - - /* pismo has thermal sensor on GEN1-I2C i.e. instance 0 */ - i2c_register_board_info(0, pismo_i2c4_nct1008_board_info, - ARRAY_SIZE(pismo_i2c4_nct1008_board_info)); - - return ret; -} - -static struct i2c_board_info __initdata bq20z45_pdata[] = { - { - I2C_BOARD_INFO("sbs-battery", 0x0B), - .platform_data = &sbs_pdata, - }, -}; - -#ifdef CONFIG_TEGRA_SKIN_THROTTLE -static int tegra_skin_match(struct thermal_zone_device *thz, void *data) -{ - return strcmp((char *)data, thz->type) == 0; -} - -static int tegra_skin_get_temp(void *data, long *temp) -{ - struct thermal_zone_device *thz; - - thz = thermal_zone_device_find(data, tegra_skin_match); - - if (!thz || thz->ops->get_temp(thz, temp)) - *temp = 25000; - - return 0; -} - -static struct therm_est_data skin_data = { - .toffset = 9793, - .polling_period = 1100, - .ndevs = 2, - .devs = { - { - .dev_data = "nct_ext", - .get_temp = tegra_skin_get_temp, - .coeffs = { - 2, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 0, - 1, 1, 0, 0, - 0, 0, -1, -7 - }, - }, - { - .dev_data = "nct_int", - .get_temp = tegra_skin_get_temp, - .coeffs = { - -11, -7, -5, -3, - -3, -2, -1, 0, - 0, 0, 1, 1, - 1, 2, 2, 3, - 4, 6, 11, 18 - }, - }, - }, - .trip_temp = 45000, - .tc1 = 10, - .tc2 = 1, - .passive_delay = 15000, -}; - -static struct throttle_table skin_throttle_table[] = { - { { 640000, 1200 } }, - { { 640000, 1200 } }, - { { 760000, 1200 } }, - { { 760000, 1200 } }, - { {1000000, 1200 } }, - { {1000000, 1200 } }, -}; - -static struct balanced_throttle skin_throttle = { - .throt_tab_size = ARRAY_SIZE(skin_throttle_table), - .throt_tab = skin_throttle_table, -}; - -static int __init pismo_skin_init(void) -{ - struct thermal_cooling_device *skin_cdev; - - skin_cdev = balanced_throttle_register(&skin_throttle, "pismo-skin"); - - skin_data.cdev = skin_cdev; - tegra_skin_therm_est_device.dev.platform_data = &skin_data; - platform_device_register(&tegra_skin_therm_est_device); - - return 0; -} -late_initcall(pismo_skin_init); -#endif - -int __init pismo_sensors_init(void) -{ - int err; - - err = pismo_nct1008_init(); - if (err) - return err; - - pismo_camera_init(); - mpuirq_init(); - - i2c_register_board_info(0, pismo_i2c_board_info_cm3218, - ARRAY_SIZE(pismo_i2c_board_info_cm3218)); - - i2c_register_board_info(0, bq20z45_pdata, - ARRAY_SIZE(bq20z45_pdata)); - - return 0; -} diff --git a/arch/arm/mach-tegra/board-pismo.c b/arch/arm/mach-tegra/board-pismo.c deleted file mode 100644 index 8daa8d93949f..000000000000 --- a/arch/arm/mach-tegra/board-pismo.c +++ /dev/null @@ -1,677 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ctype.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/i2c/i2c-hid.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/i2c-tegra.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_data/tegra_usb.h> -#include <linux/spi/spi.h> -#include <linux/spi/rm31080a_ts.h> -#include <linux/memblock.h> -#include <linux/spi/spi-tegra.h> -#include <linux/nfc/pn544.h> -#include <linux/rfkill-gpio.h> -#include <linux/skbuff.h> -#include <linux/ti_wilink_st.h> -#include <linux/regulator/consumer.h> -#include <linux/smb349-charger.h> -#include <linux/max17048_battery.h> -#include <linux/leds.h> -#include <linux/i2c/at24.h> -#include <linux/of_platform.h> -#include <linux/edp.h> -#include <linux/usb/tegra_usb_phy.h> -#include <linux/clk/tegra.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> -#include <linux/irqchip/tegra.h> -#include <linux/tegra_fiq_debugger.h> -#include <linux/platform_data/tegra_usb_modem_power.h> - -#include <mach/irqs.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <mach/io_dpd.h> -#include <mach/i2s.h> -#include <mach/tegra_asoc_pdata.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/gpio-tegra.h> - -#include "board-touch-raydium.h" -#include "board.h" -#include "board-common.h" -#include "clock.h" -#include "board-pismo.h" -#include "devices.h" -#include "gpio-names.h" -#include "pm.h" -#include "common.h" -#include "tegra-board-id.h" -#include "iomap.h" -#include "tegra-of-dev-auxdata.h" - -#ifdef CONFIG_BT_BLUESLEEP -static struct rfkill_gpio_platform_data pismo_bt_rfkill_pdata = { - .name = "bt_rfkill", - .shutdown_gpio = TEGRA_GPIO_PQ7, - .reset_gpio = TEGRA_GPIO_PQ6, - .type = RFKILL_TYPE_BLUETOOTH, -}; - -static struct platform_device pismo_bt_rfkill_device = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &pismo_bt_rfkill_pdata, - }, -}; - -static struct resource pismo_bluesleep_resources[] = { - [0] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [2] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device pismo_bluesleep_device = { - .name = "bluesleep", - .id = -1, - .num_resources = ARRAY_SIZE(pismo_bluesleep_resources), - .resource = pismo_bluesleep_resources, -}; - -static noinline void __init pismo_setup_bt_rfkill(void) -{ - platform_device_register(&pismo_bt_rfkill_device); -} - -static noinline void __init pismo_setup_bluesleep(void) -{ - pismo_bluesleep_resources[2].start = - pismo_bluesleep_resources[2].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&pismo_bluesleep_device); - return; -} -#elif defined CONFIG_BLUEDROID_PM -static struct resource pismo_bluedroid_pm_resources[] = { - [0] = { - .name = "shutdown_gpio", - .start = TEGRA_GPIO_PQ7, - .end = TEGRA_GPIO_PQ7, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, - [2] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [3] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [4] = { - .name = "reset_gpio", - .start = TEGRA_GPIO_PQ6, - .end = TEGRA_GPIO_PQ6, - .flags = IORESOURCE_IO, - }, -}; - -static struct platform_device pismo_bluedroid_pm_device = { - .name = "bluedroid_pm", - .id = 0, - .num_resources = ARRAY_SIZE(pismo_bluedroid_pm_resources), - .resource = pismo_bluedroid_pm_resources, -}; - -static noinline void __init pismo_setup_bluedroid_pm(void) -{ - pismo_bluedroid_pm_resources[1].start = - pismo_bluedroid_pm_resources[1].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&pismo_bluedroid_pm_device); -} -#endif - -static __initdata struct tegra_clk_init_table pismo_clk_init_table[] = { - /* name parent rate enabled */ - { "pll_m", NULL, 0, false}, - { "hda", "pll_p", 108000000, false}, - { "hda2codec_2x", "pll_p", 48000000, false}, - { "pwm", "pll_p", 3187500, false}, - { "blink", "clk_32k", 32768, true}, - { "i2s1", "pll_a_out0", 0, false}, - { "i2s3", "pll_a_out0", 0, false}, - { "i2s4", "pll_a_out0", 0, false}, - { "spdif_out", "pll_a_out0", 0, false}, - { "d_audio", "clk_m", 12000000, false}, - { "dam0", "clk_m", 12000000, false}, - { "dam1", "clk_m", 12000000, false}, - { "dam2", "clk_m", 12000000, false}, - { "audio1", "i2s1_sync", 0, false}, - { "audio3", "i2s3_sync", 0, false}, - /* Setting vi_sensor-clk to true for validation purpose, will imapact - * power, later set to be false.*/ - { "vi_sensor", "pll_p", 150000000, false}, - { "cilab", "pll_p", 150000000, false}, - { "cilcd", "pll_p", 150000000, false}, - { "cile", "pll_p", 150000000, false}, - { "i2c1", "pll_p", 3200000, false}, - { "i2c2", "pll_p", 3200000, false}, - { "i2c3", "pll_p", 3200000, false}, - { "i2c4", "pll_p", 3200000, false}, - { "i2c5", "pll_p", 3200000, false}, - { NULL, NULL, 0, 0}, -}; - -static struct i2c_board_info __initdata rt5640_board_info = { - I2C_BOARD_INFO("rt5640", 0x1c), -}; - -static struct pn544_i2c_platform_data nfc_pdata = { - .irq_gpio = TEGRA_GPIO_PW2, - .ven_gpio = TEGRA_GPIO_PQ3, - .firm_gpio = TEGRA_GPIO_PH0, -}; - -static struct i2c_board_info __initdata nfc_board_info = { - I2C_BOARD_INFO("pn544", 0x28), - .platform_data = &nfc_pdata, -}; - -static struct i2c_hid_platform_data i2c_keyboard_pdata = { - .hid_descriptor_address = 0x0, -}; - -static struct i2c_board_info __initdata i2c_keyboard_board_info = { - I2C_BOARD_INFO("hid", 0x3B), - .platform_data = &i2c_keyboard_pdata, -}; - -static struct i2c_hid_platform_data i2c_touchpad_pdata = { - .hid_descriptor_address = 0x20, -}; - -static struct i2c_board_info __initdata i2c_touchpad_board_info = { - I2C_BOARD_INFO("hid", 0x2C), - .platform_data = &i2c_touchpad_pdata, -}; - -static void pismo_i2c_init(void) -{ - - nfc_board_info.irq = gpio_to_irq(TEGRA_GPIO_PW2); - i2c_register_board_info(0, &nfc_board_info, 1); - - i2c_register_board_info(0, &rt5640_board_info, 1); - - i2c_keyboard_board_info.irq = gpio_to_irq(I2C_KB_IRQ); - i2c_register_board_info(1, &i2c_keyboard_board_info , 1); - - i2c_touchpad_board_info.irq = gpio_to_irq(I2C_TP_IRQ); - i2c_register_board_info(1, &i2c_touchpad_board_info , 1); -} - -static struct platform_device *pismo_uart_devices[] __initdata = { - &tegra_uarta_device, - &tegra_uartb_device, - &tegra_uartc_device, - &tegra_uartd_device, -}; - -static void __init uart_debug_init(void) -{ - int debug_port_id; - - debug_port_id = uart_console_debug_init(3); - if (debug_port_id < 0) - return; - - pismo_uart_devices[debug_port_id] = uart_console_debug_device; -} - -static void __init pismo_uart_init(void) -{ - /* Register low speed only if it is selected */ - if (!is_tegra_debug_uartport_hs()) - uart_debug_init(); - - platform_add_devices(pismo_uart_devices, - ARRAY_SIZE(pismo_uart_devices)); -} - -static struct resource tegra_rtc_resources[] = { - [0] = { - .start = TEGRA_RTC_BASE, - .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_RTC, - .end = INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tegra_rtc_device = { - .name = "tegra_rtc", - .id = -1, - .resource = tegra_rtc_resources, - .num_resources = ARRAY_SIZE(tegra_rtc_resources), -}; - -static struct tegra_asoc_platform_data pismo_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .gpio_codec1 = TEGRA_GPIO_CODEC1_EN, - .gpio_codec2 = TEGRA_GPIO_CODEC2_EN, - .gpio_codec3 = TEGRA_GPIO_CODEC3_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - }, -}; - -static struct platform_device pismo_audio_device = { - .name = "tegra-snd-rt5640", - .id = 0, - .dev = { - .platform_data = &pismo_audio_pdata, - }, -}; - -static struct platform_device tegra_camera = { - .name = "tegra_camera", - .id = -1, -}; - -static struct platform_device *pismo_devices[] __initdata = { - &tegra_pmu_device, - &tegra_rtc_device, - &tegra_udc_device, -#if defined(CONFIG_TEGRA_AVP) - &tegra_avp_device, -#endif - &tegra_camera, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) - &tegra11_se_device, -#endif - &tegra_ahub_device, - &tegra_dam_device0, - &tegra_dam_device1, - &tegra_dam_device2, - &tegra_i2s_device1, - &tegra_i2s_device3, - &tegra_i2s_device4, - &tegra_spdif_device, - &spdif_dit_device, - &bluetooth_dit_device, - &pismo_audio_device, - &tegra_hda_device, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) - &tegra_aes_device, -#endif -}; - -#ifdef CONFIG_USB_SUPPORT -static struct tegra_usb_platform_data tegra_udc_pdata = { - .port_otg = true, - .has_hostpc = true, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_DEVICE, - .u_data.dev = { - .vbus_pmu_irq = 0, - .vbus_gpio = -1, - .charging_supported = true, - .remote_wakeup_supported = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { - .port_otg = true, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x4, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x5, - }, -}; - -static struct tegra_usb_otg_data tegra_otg_pdata = { - .ehci_device = &tegra_ehci1_device, - .ehci_pdata = &tegra_ehci1_utmi_pdata, -}; - -static void pismo_usb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - /* Set USB wake sources for pismo */ - tegra_set_usb_wake_source(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) { - tegra_otg_device.dev.platform_data = &tegra_otg_pdata; - platform_device_register(&tegra_otg_device); - /* Setup the udc platform data */ - tegra_udc_device.dev.platform_data = &tegra_udc_pdata; - } - - if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) { - tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; - platform_device_register(&tegra_ehci3_device); - } -} - -static struct gpio modem_gpios[] = { /* Nemo modem */ - {MODEM_EN, GPIOF_OUT_INIT_HIGH, "MODEM EN"}, - {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"}, -}; - -static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static int baseband_init(void) -{ - int ret; - - ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios)); - if (ret) { - pr_warn("%s:gpio request failed\n", __func__); - return ret; - } - - /* enable pull-down for MDM_COLD_BOOT */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_KB_COL5, - TEGRA_PUPD_PULL_DOWN); - - /* export GPIO for user space access through sysfs */ - gpio_export(MDM_RST, false); - - return 0; -} - -static const struct tegra_modem_operations baseband_operations = { - .init = baseband_init, -}; - -static struct tegra_usb_modem_power_platform_data baseband_pdata = { - .ops = &baseband_operations, - .wake_gpio = -1, - .boot_gpio = MDM_COLDBOOT, - .boot_irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - .autosuspend_delay = 2000, - .short_autosuspend_delay = 50, - .tegra_ehci_device = &tegra_ehci2_device, - .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata, -}; - -static struct platform_device icera_nemo_device = { - .name = "tegra_usb_modem_power", - .id = -1, - .dev = { - .platform_data = &baseband_pdata, - }, -}; - -static void pismo_modem_init(void) -{ - int modem_id = tegra_get_modem_id(); - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - switch (modem_id) { - case TEGRA_BB_NEMO: /* on board i500 HSIC */ - if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) - platform_device_register(&icera_nemo_device); - break; - } -} - -#else -static void pismo_usb_init(void) { } -static void pismo_modem_init(void) { } -#endif - -static void pismo_audio_init(void) -{ - pismo_audio_pdata.codec_name = "rt5640.0-001c"; - pismo_audio_pdata.codec_dai_name = "rt5640-aif1"; -} - -struct rm_spi_ts_platform_data rm31080ts_pismo_data = { - .gpio_reset = 0, - .config = 0, - .platform_id = RM_PLATFORM_D010, - .name_of_clock = "clk_out_2", -}; - -static struct tegra_spi_device_controller_data dev_cdata = { - .rx_clk_tap_delay = 16, - .tx_clk_tap_delay = 16, -}; - -struct spi_board_info rm31080a_pismo_spi_board[1] = { - { - .modalias = "rm_ts_spidev", - .bus_num = 3, - .chip_select = 2, - .max_speed_hz = 12 * 1000 * 1000, - .mode = SPI_MODE_0, - .controller_data = &dev_cdata, - .platform_data = &rm31080ts_pismo_data, - }, -}; - -static void __init tegra_pismo_init(void) -{ - struct board_info board_info; - - tegra_get_display_board_info(&board_info); - tegra_clk_init_from_table(pismo_clk_init_table); - tegra_clk_verify_parents(); - tegra_soc_device_init("pismo"); - pismo_i2c_init(); - pismo_usb_init(); - pismo_uart_init(); - pismo_audio_init(); - platform_add_devices(pismo_devices, ARRAY_SIZE(pismo_devices)); - tegra_io_dpd_init(); - pismo_regulator_init(); - pismo_sdhci_init(); - pismo_suspend_init(); - pismo_emc_init(); - pismo_edp_init(); - pismo_panel_init(); -#ifdef CONFIG_BT_BLUESLEEP - pismo_setup_bluesleep(); - pismo_setup_bt_rfkill(); -#elif defined CONFIG_BLUEDROID_PM - pismo_setup_bluedroid_pm(); -#endif - pismo_modem_init(); -#ifdef CONFIG_TEGRA_WDT_RECOVERY - tegra_wdt_recovery_init(); -#endif - tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); - pismo_sensors_init(); - pismo_soctherm_init(); -} - -#ifdef CONFIG_USE_OF -struct of_dev_auxdata pismo_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", NULL), - T114_SPI_OF_DEV_AUXDATA, - T114_I2C_OF_DEV_AUXDATA, - OF_DEV_AUXDATA("nvidia,tegra114-nvavp", 0x60001000, "nvavp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-pwm", 0x7000a000, "tegra-pwm", NULL), - {} -}; -#endif - -static void __init tegra_pismo_dt_init(void) -{ -#ifdef CONFIG_USE_OF - of_platform_populate(NULL, - of_default_bus_match_table, pismo_auxdata_lookup, - &platform_bus); -#endif - - tegra_pismo_init(); -} - -static void __init tegra_pismo_reserve(void) -{ -#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* 1920*1200*4*2 = 18432000 bytes */ - tegra_reserve(0, SZ_16M + SZ_2M, SZ_16M); -#else - tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M); -#endif -} - -static const char * const pismo_dt_board_compat[] = { - "nvidia,pismo", - NULL -}; - -MACHINE_START(PISMO, "pismo") - .atag_offset = 0x100, - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .reserve = tegra_pismo_reserve, - .init_early = tegra11x_init_early, - .init_irq = irqchip_init, - .init_time = clocksource_of_init, - .init_machine = tegra_pismo_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = pismo_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-pismo.h b/arch/arm/mach-tegra/board-pismo.h deleted file mode 100644 index c3097b9cf43f..000000000000 --- a/arch/arm/mach-tegra/board-pismo.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pismo.h - * - * Copyright (c) 2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_BOARD_PISMO_H -#define _MACH_TEGRA_BOARD_PISMO_H - -#include <mach/irqs.h> -#include "gpio-names.h" - -/* External peripheral act as gpio */ -/* AS3720 GPIO */ -#define AS3720_GPIO_BASE TEGRA_NR_GPIOS - -/* Hall Effect Sensor GPIO */ -#define TEGRA_GPIO_HALL TEGRA_GPIO_PS0 - -/* Audio-related GPIOs */ -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 -#define TEGRA_GPIO_LDO1_EN TEGRA_GPIO_PV3 -#define TEGRA_GPIO_CODEC1_EN TEGRA_GPIO_PP3 -#define TEGRA_GPIO_CODEC2_EN TEGRA_GPIO_PP1 -#define TEGRA_GPIO_CODEC3_EN TEGRA_GPIO_PV0 - -#define TEGRA_GPIO_SPKR_EN -1 -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7 -#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PK3 -#define TEGRA_GPIO_EXT_MIC_EN -1 - -#define TEGRA_GPIO_W_DISABLE TEGRA_GPIO_PDD7 -#define TEGRA_GPIO_MODEM_RSVD1 TEGRA_GPIO_PV0 -#define TEGRA_GPIO_MODEM_RSVD2 TEGRA_GPIO_PH7 - -/* External peripheral act as interrupt controller */ -/* AS3720 IRQs */ -#define AS3270_IRQ_BASE TEGRA_NR_IRQS - -/* I2C related GPIOs */ -#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4 -#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5 -#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5 -#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6 -#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1 -#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2 -#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4 -#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5 -#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6 -#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7 - -/* Camera related GPIOs */ -#define CAM_RSTN TEGRA_GPIO_PBB3 -#define CAM_FLASH_STROBE TEGRA_GPIO_PBB4 -#define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 -#define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 -#define CAM_AF_PWDN TEGRA_GPIO_PBB7 -#define CAM_GPIO1 TEGRA_GPIO_PCC1 -#define CAM_GPIO2 TEGRA_GPIO_PCC2 - -/* Touchscreen definitions */ -#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2 -#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4 - -/* HID over I2C GPIOs */ -#define I2C_KB_IRQ TEGRA_GPIO_PC7 -#define I2C_TP_IRQ TEGRA_GPIO_PH4 - -/* Invensense MPU Definitions */ -#define MPU_GYRO_NAME "mpu9150" -#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PR3 -#define MPU_GYRO_ADDR 0x69 -#define MPU_GYRO_BUS_NUM 0 -#define MPU_GYRO_ORIENTATION { -1, 0, 0, 0, 1, 0, 0, 0, -1 } -#define MPU_ACCEL_NAME "kxtf9" -#define MPU_ACCEL_IRQ_GPIO 0 /* DISABLE ACCELIRQ: TEGRA_GPIO_PJ2 */ -#define MPU_ACCEL_ADDR 0x0F -#define MPU_ACCEL_BUS_NUM 0 -#define MPU_ACCEL_ORIENTATION { 0, 1, 0, -1, 0, 0, 0, 0, 1 } -#define MPU_COMPASS_NAME "ak8975" -#define MPU_COMPASS_IRQ_GPIO 0 -#define MPU_COMPASS_ADDR 0x0D -#define MPU_COMPASS_BUS_NUM 0 -#define MPU_COMPASS_ORIENTATION { 0, 1, 0, -1, 0, 0, 0, 0, 1 } - -/* Modem related GPIOs */ -#define MODEM_EN TEGRA_GPIO_PP2 -#define MDM_RST TEGRA_GPIO_PP0 -#define MDM_COLDBOOT TEGRA_GPIO_PQ5 - -int pismo_regulator_init(void); -int pismo_suspend_init(void); -int pismo_sdhci_init(void); -int pismo_sensors_init(void); -int pismo_emc_init(void); -int pismo_edp_init(void); -int pismo_panel_init(void); -int roth_panel_init(void); -int pismo_kbc_init(void); -int pismo_soctherm_init(void); - -/* Baseband IDs */ -enum tegra_bb_type { - TEGRA_BB_NEMO = 1, -}; - -#define UTMI1_PORT_OWNER_XUSB 0x1 -#define UTMI2_PORT_OWNER_XUSB 0x2 -#define HSIC1_PORT_OWNER_XUSB 0x4 - -#endif diff --git a/arch/arm/mach-tegra/board-pluto-kbc.c b/arch/arm/mach-tegra/board-pluto-kbc.c deleted file mode 100644 index 22e71561aa47..000000000000 --- a/arch/arm/mach-tegra/board-pluto-kbc.c +++ /dev/null @@ -1,136 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-kbc.c - * Keys configuration for Nvidia tegra3 pluto platform. - * - * Copyright (C) 2012 NVIDIA, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/input/tegra_kbc.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> - -#include "board.h" -#include "board-pluto.h" -#include "devices.h" - -#define PLUTO_ROW_COUNT 3 -#define PLUTO_COL_COUNT 3 - -static const u32 kbd_keymap[] = { - KEY(0, 0, KEY_POWER), - KEY(0, 1, KEY_VOLUMEUP), - KEY(0, 2, KEY_VOLUMEDOWN), - - KEY(1, 0, KEY_SEARCH), - KEY(1, 1, KEY_CAMERA), - KEY(1, 2, KEY_CAMERA_FOCUS), - - KEY(2, 0, KEY_HOME), - KEY(2, 1, KEY_BACK), - KEY(2, 2, KEY_MENU), -}; - -static const struct matrix_keymap_data keymap_data = { - .keymap = kbd_keymap, - .keymap_size = ARRAY_SIZE(kbd_keymap), -}; - -static struct tegra_kbc_wake_key pluto_wake_cfg[] = { - [0] = { - .row = 0, - .col = 0, - }, - [1] = { - .row = 0, - .col = 1, - }, - [2] = { - .row = 0, - .col = 2, - }, -}; - -static struct tegra_kbc_platform_data pluto_kbc_platform_data = { - .debounce_cnt = 20 * 32, /* 20 ms debaunce time */ - .repeat_cnt = 1, - .scan_count = 30, - .wakeup = true, - .keymap_data = &keymap_data, - .wake_cnt = 3, - .wake_cfg = &pluto_wake_cfg[0], - .wakeup_key = KEY_POWER, -#ifdef CONFIG_ANDROID - .disable_ev_rep = true, -#endif -}; - -static struct gpio_keys_button pluto_keys[] = { - [0] = { - .code = KEY_MUTE, - .gpio = TEGRA_GPIO_PI5, - .irq = -1, - .type = EV_KEY, - .desc = "RINGER", - .active_low = 0, - .wakeup = 0, - .debounce_interval = 100, - }, -}; - -static struct gpio_keys_platform_data pluto_keys_pdata = { - .buttons = pluto_keys, - .nbuttons = ARRAY_SIZE(pluto_keys), -}; - -static struct platform_device pluto_keys_device = { - .name = "gpio-keys", - .id = 0, - .dev = { - .platform_data = &pluto_keys_pdata, - }, -}; - -int __init pluto_kbc_init(void) -{ - struct tegra_kbc_platform_data *data = &pluto_kbc_platform_data; - int i; - - tegra_kbc_device.dev.platform_data = &pluto_kbc_platform_data; - pr_info("Registering tegra-kbc\n"); - - BUG_ON((KBC_MAX_ROW + KBC_MAX_COL) > KBC_MAX_GPIO); - for (i = 0; i < PLUTO_ROW_COUNT; i++) { - data->pin_cfg[i].num = i; - data->pin_cfg[i].type = PIN_CFG_ROW; - } - for (i = 0; i < PLUTO_COL_COUNT; i++) { - data->pin_cfg[i + KBC_PIN_GPIO_11].num = i; - data->pin_cfg[i + KBC_PIN_GPIO_11].type = PIN_CFG_COL; - } - - platform_device_register(&tegra_kbc_device); - pr_info("Registering successful tegra-kbc\n"); - - platform_device_register(&pluto_keys_device); - pr_info("Registering successful gpio-keys\n"); - - return 0; -} - diff --git a/arch/arm/mach-tegra/board-pluto-memory.c b/arch/arm/mach-tegra/board-pluto-memory.c deleted file mode 100644 index 7c7ef4d8d025..000000000000 --- a/arch/arm/mach-tegra/board-pluto-memory.c +++ /dev/null @@ -1,4406 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-memory.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_data/tegra_emc_pdata.h> -#include <linux/memblock.h> - -#include <asm-generic/sizes.h> - -#include "board.h" -#include "board-pluto.h" -#include "tegra-board-id.h" -#include "tegra11_emc.h" -#include "devices.h" -#include "common.h" - -static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x0000002f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000002, /* EMC_TXSR */ - 0x00000002, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000036, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00048000, /* EMC_DLL_XFORM_DQS4 */ - 0x00048000, /* EMC_DLL_XFORM_DQS5 */ - 0x00048000, /* EMC_DLL_XFORM_DQS6 */ - 0x00048000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000165, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77c30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x0000004c, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000013, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000003, /* EMC_TXSR */ - 0x00000003, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000055, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00048000, /* EMC_DLL_XFORM_DQS4 */ - 0x00048000, /* EMC_DLL_XFORM_DQS5 */ - 0x00048000, /* EMC_DLL_XFORM_DQS6 */ - 0x00048000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000019f, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000002, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000000aa, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00048000, /* EMC_DLL_XFORM_DQS4 */ - 0x00048000, /* EMC_DLL_XFORM_DQS5 */ - 0x00048000, /* EMC_DLL_XFORM_DQS6 */ - 0x00048000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x73030303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x00000008, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000101, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000040, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000000a, /* EMC_TXSR */ - 0x0000000a, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x0000011b, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00048000, /* EMC_DLL_XFORM_DQS4 */ - 0x00048000, /* EMC_DLL_XFORM_DQS5 */ - 0x00048000, /* EMC_DLL_XFORM_DQS6 */ - 0x00048000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000019, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000309, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x72630403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00048000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS1 */ - 0x00048000, /* EMC_DLL_XFORM_DQS2 */ - 0x00048000, /* EMC_DLL_XFORM_DQS3 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0006c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000006, /* EMC_RC */ - 0x0000000d, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000004, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000181, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000000f, /* EMC_TXSR */ - 0x0000000f, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000001a9, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00048000, /* EMC_DLL_XFORM_DQS4 */ - 0x00048000, /* EMC_DLL_XFORM_DQS5 */ - 0x00048000, /* EMC_DLL_XFORM_DQS6 */ - 0x00048000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000025, /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e, /* EMC_MRS_WAIT_CNT */ - 0x000e000e, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000040c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090403, /* MC_EMEM_ARB_DA_COVERS */ - 0x72430504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ1 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ2 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000003, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00048000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00048000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ1 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ2 */ - 0x000c0000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000012, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000c, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000008, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000003, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000001d, /* EMC_TXSR */ - 0x0000001d, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000b, /* EMC_TFAW */ - 0x00000005, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000351, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000004a, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */ - 0x71e40a07, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00058000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00070000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00070000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00058000, /* EMC_DLL_XFORM_DQ1 */ - 0x00058000, /* EMC_DLL_XFORM_DQ2 */ - 0x00058000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00058000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00070000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00070000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00058000, /* EMC_DLL_XFORM_DQ1 */ - 0x00058000, /* EMC_DLL_XFORM_DQ2 */ - 0x00058000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000028, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000005, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000005, /* EMC_RD_RCD */ - 0x00000005, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x0000049d, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000127, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000005, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000002c, /* EMC_TXSR */ - 0x0000002c, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000010, /* EMC_TFAW */ - 0x00000007, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000514, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00020000, /* EMC_DLL_XFORM_DQS4 */ - 0x00020000, /* EMC_DLL_XFORM_DQS5 */ - 0x00020000, /* EMC_DLL_XFORM_DQS6 */ - 0x00020000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000071, /* EMC_ZCAL_WAIT_CNT */ - 0x000e000e, /* EMC_MRS_WAIT_CNT */ - 0x000e000e, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000a4c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000c0709, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c50f0a, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00038000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00038000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ1 */ - 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x00038000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00038000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00038000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ1 */ - 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x00038000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000021, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010083, /* Mode Register 1 */ - 0x00020004, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000011, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x0000000b, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000008, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000005, /* EMC_QRST */ - 0x00000013, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000003, /* EMC_PDEX2RD */ - 0x00000007, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000003a, /* EMC_TXSR */ - 0x0000003a, /* EMC_TXSRDLL */ - 0x00000007, /* EMC_TCKE */ - 0x00000007, /* EMC_TCKESR */ - 0x00000007, /* EMC_TPD */ - 0x00000015, /* EMC_TFAW */ - 0x00000009, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000006a2, /* EMC_TREFBW */ - 0x00000008, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001a886, /* EMC_FBIO_CFG5 */ - 0x00580088, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000093, /* EMC_ZCAL_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06070102, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c7130d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000e, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000011, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410421, /* EMC_XM2DQSPADCTRL3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00018000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00018000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ1 */ - 0x00020000, /* EMC_DLL_XFORM_DQ2 */ - 0x00020000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000e, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000011, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x10410421, /* EMC_XM2DQSPADCTRL3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00018000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00018000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ1 */ - 0x00020000, /* EMC_DLL_XFORM_DQ2 */ - 0x00020000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200006, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x000100c3, /* Mode Register 1 */ - 0x00020006, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000025, /* EMC_RC */ - 0x00000051, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001a, /* EMC_RAS */ - 0x0000000b, /* EMC_RP */ - 0x0000000d, /* EMC_R2W */ - 0x0000000c, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000011, /* EMC_W2P */ - 0x0000000b, /* EMC_RD_RCD */ - 0x0000000b, /* EMC_WR_RCD */ - 0x00000006, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000017, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000004, /* EMC_PDEX2RD */ - 0x0000000b, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000014, /* EMC_RW2PDEN */ - 0x00000058, /* EMC_TXSR */ - 0x00000058, /* EMC_TXSRDLL */ - 0x0000000a, /* EMC_TCKE */ - 0x0000000a, /* EMC_TCKESR */ - 0x0000000a, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x0000000e, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000a28, /* EMC_TREFBW */ - 0x0000000b, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001a886, /* EMC_FBIO_CFG5 */ - 0xf00d0199, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000301, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x000000e1, /* EMC_ZCAL_WAIT_CNT */ - 0x00140014, /* EMC_MRS_WAIT_CNT */ - 0x00140014, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07080103, /* MC_EMEM_ARB_DA_TURNS */ - 0x00160e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x71ca1d14, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000f, /* EMC_QUSE */ - 0x00000009, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000010, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000015, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x00003010, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000010, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x00003010, /* EMC_DLL_XFORM_DQ1 */ - 0x00003010, /* EMC_DLL_XFORM_DQ2 */ - 0x00003010, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000f, /* EMC_QUSE */ - 0x00000009, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000010, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000015, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000010, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000003d, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200000, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010003, /* Mode Register 1 */ - 0x00020018, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 744000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000002c, /* EMC_RC */ - 0x00000061, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001f, /* EMC_RAS */ - 0x0000000d, /* EMC_RP */ - 0x0000000f, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000d, /* EMC_RD_RCD */ - 0x0000000d, /* EMC_WR_RCD */ - 0x00000007, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000d, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000009, /* EMC_QRST */ - 0x0000001a, /* EMC_RDV_MASK */ - 0x00000b1e, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000002c7, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000005, /* EMC_PDEX2WR */ - 0x00000005, /* EMC_PDEX2RD */ - 0x0000000d, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000016, /* EMC_RW2PDEN */ - 0x00000069, /* EMC_TXSR */ - 0x00000069, /* EMC_TXSRDLL */ - 0x0000000c, /* EMC_TCKE */ - 0x0000000c, /* EMC_TCKESR */ - 0x0000000c, /* EMC_TPD */ - 0x00000026, /* EMC_TFAW */ - 0x00000010, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000c21, /* EMC_TREFBW */ - 0x0000010d, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001a886, /* EMC_FBIO_CFG5 */ - 0xf0080199, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f408, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000301, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000010c, /* EMC_ZCAL_WAIT_CNT */ - 0x00150015, /* EMC_MRS_WAIT_CNT */ - 0x00150015, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000172f, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0300000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000016, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000012, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000009, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08090103, /* MC_EMEM_ARB_DA_TURNS */ - 0x00191016, /* MC_EMEM_ARB_DA_COVERS */ - 0x71cc2217, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000012, /* EMC_QUSE */ - 0x0000000b, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000011, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000018, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x00008007, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004009, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000707, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004009, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000800a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQS3 */ - 0x00008007, /* EMC_DLL_XFORM_DQ1 */ - 0x00008007, /* EMC_DLL_XFORM_DQ2 */ - 0x00008007, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000012, /* EMC_QUSE */ - 0x0000000b, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000011, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000018, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x00008007, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004009, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000909, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004009, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000800a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQS3 */ - 0x00008007, /* EMC_DLL_XFORM_DQ1 */ - 0x00008007, /* EMC_DLL_XFORM_DQ2 */ - 0x00008007, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000017d, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0011000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000011, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00740036, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00740074, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200000, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x00010043, /* Mode Register 1 */ - 0x0002001a, /* Mode Register 2 */ - 0x000b0000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_AP40_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000002f, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000000b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000002, /* EMC_TXSR */ - 0x00000002, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000036, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0007c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000165, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77c30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000004c, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000013, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000003, /* EMC_TXSR */ - 0x00000003, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000055, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0007c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000019f, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000002, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000000aa, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0007c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000000f, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x73030303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x00000008, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000101, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000040, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000000a, /* EMC_TXSR */ - 0x0000000a, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x0000011b, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0007c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000019, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000309, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090402, /* MC_EMEM_ARB_DA_COVERS */ - 0x72630403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000006, /* EMC_RC */ - 0x0000000d, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000004, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000001, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000005, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000d, /* EMC_RDV_MASK */ - 0x00000181, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000002, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000000f, /* EMC_TXSR */ - 0x0000000f, /* EMC_TXSRDLL */ - 0x00000003, /* EMC_TCKE */ - 0x00000003, /* EMC_TCKESR */ - 0x00000003, /* EMC_TPD */ - 0x00000008, /* EMC_TFAW */ - 0x00000004, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000001a9, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0007c000, /* EMC_DLL_XFORM_DQS4 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS5 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS6 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000025, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000040c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05040102, /* MC_EMEM_ARB_DA_TURNS */ - 0x00090403, /* MC_EMEM_ARB_DA_COVERS */ - 0x72430504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x0007c000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0007c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000013, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000c, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000008, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000003, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000001d, /* EMC_TXSR */ - 0x0000001d, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000b, /* EMC_TFAW */ - 0x00000005, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000351, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000004a, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */ - 0x71e40a07, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00040000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ1 */ - 0x00040000, /* EMC_DLL_XFORM_DQ2 */ - 0x00040000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00040000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ1 */ - 0x00040000, /* EMC_DLL_XFORM_DQ2 */ - 0x00040000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000028, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000d, /* EMC_RAS */ - 0x00000005, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000005, /* EMC_RD_RCD */ - 0x00000005, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x00000011, /* EMC_RDV_MASK */ - 0x0000049d, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000127, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000005, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000d, /* EMC_RW2PDEN */ - 0x0000002c, /* EMC_TXSR */ - 0x0000002c, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000010, /* EMC_TFAW */ - 0x00000007, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000514, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x00580088, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00020000, /* EMC_DLL_XFORM_DQS4 */ - 0x00020000, /* EMC_DLL_XFORM_DQS5 */ - 0x00020000, /* EMC_DLL_XFORM_DQS6 */ - 0x00020000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000071, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000a4c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000c0709, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c50f0a, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ1 */ - 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x00038000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00024000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00024000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x00038000, /* EMC_DLL_XFORM_DQ1 */ - 0x00038000, /* EMC_DLL_XFORM_DQ2 */ - 0x00038000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000021, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000011, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x0000000a, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000008, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000005, /* EMC_QRST */ - 0x00000013, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000003, /* EMC_PDEX2RD */ - 0x00000007, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000003a, /* EMC_TXSR */ - 0x0000003a, /* EMC_TXSRDLL */ - 0x00000007, /* EMC_TCKE */ - 0x00000007, /* EMC_TCKESR */ - 0x00000007, /* EMC_TPD */ - 0x00000015, /* EMC_TFAW */ - 0x00000009, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x000006a2, /* EMC_TREFBW */ - 0x00000007, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001a886, /* EMC_FBIO_CFG5 */ - 0x00580088, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00020000, /* EMC_DLL_XFORM_DQS4 */ - 0x00020000, /* EMC_DLL_XFORM_DQS5 */ - 0x00020000, /* EMC_DLL_XFORM_DQS6 */ - 0x00020000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0xa1f1f409, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x00000093, /* EMC_ZCAL_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d24, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06060102, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c7130d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000e, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000011, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x14514521, /* EMC_XM2DQSPADCTRL3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ1 */ - 0x00020000, /* EMC_DLL_XFORM_DQ2 */ - 0x00020000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00020000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000e, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000011, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x14514521, /* EMC_XM2DQSPADCTRL3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00008000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00008000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS1 */ - 0x00020000, /* EMC_DLL_XFORM_DQS2 */ - 0x00020000, /* EMC_DLL_XFORM_DQS3 */ - 0x00020000, /* EMC_DLL_XFORM_DQ1 */ - 0x00020000, /* EMC_DLL_XFORM_DQ2 */ - 0x00020000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000029, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200006, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x800100c3, /* Mode Register 1 */ - 0x80020006, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000025, /* EMC_RC */ - 0x00000051, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001a, /* EMC_RAS */ - 0x0000000b, /* EMC_RP */ - 0x0000000c, /* EMC_R2W */ - 0x0000000c, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000011, /* EMC_W2P */ - 0x0000000b, /* EMC_RD_RCD */ - 0x0000000b, /* EMC_WR_RCD */ - 0x00000006, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000017, /* EMC_RDV_MASK */ - 0x00000945, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000251, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000004, /* EMC_PDEX2RD */ - 0x0000000b, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000014, /* EMC_RW2PDEN */ - 0x00000058, /* EMC_TXSR */ - 0x00000058, /* EMC_TXSRDLL */ - 0x0000000a, /* EMC_TCKE */ - 0x0000000a, /* EMC_TCKESR */ - 0x0000000a, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x0000000e, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000a28, /* EMC_TREFBW */ - 0x0000000b, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001a886, /* EMC_FBIO_CFG5 */ - 0xf00d0199, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x000000e1, /* EMC_ZCAL_WAIT_CNT */ - 0x00130013, /* EMC_MRS_WAIT_CNT */ - 0x00130013, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001395, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07070103, /* MC_EMEM_ARB_DA_TURNS */ - 0x00160e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x71ca1d14, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000f, /* EMC_QUSE */ - 0x00000009, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000010, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000015, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x0000c000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000008, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x0000000f, /* EMC_QUSE */ - 0x00000009, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x00000010, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000015, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x18618621, /* EMC_XM2DQSPADCTRL3 */ - 0x00000009, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x0000c000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000c000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x00000008, /* EMC_DLL_XFORM_DQ1 */ - 0x00000009, /* EMC_DLL_XFORM_DQ2 */ - 0x00000008, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000003d, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200000, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010003, /* Mode Register 1 */ - 0x80020018, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000002f, /* EMC_RC */ - 0x00000066, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000021, /* EMC_RAS */ - 0x0000000e, /* EMC_RP */ - 0x0000000f, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000e, /* EMC_RD_RCD */ - 0x0000000e, /* EMC_WR_RCD */ - 0x00000007, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000e, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000009, /* EMC_QRST */ - 0x0000001a, /* EMC_RDV_MASK */ - 0x00000bd0, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000005, /* EMC_PDEX2WR */ - 0x00000005, /* EMC_PDEX2RD */ - 0x0000000e, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000017, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x0000006f, /* EMC_TXSRDLL */ - 0x0000000c, /* EMC_TCKE */ - 0x0000000c, /* EMC_TCKESR */ - 0x0000000c, /* EMC_TPD */ - 0x00000028, /* EMC_TFAW */ - 0x00000011, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000cdf, /* EMC_TREFBW */ - 0x0000000d, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0xf0070199, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000003d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f408, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000011e, /* EMC_ZCAL_WAIT_CNT */ - 0x00150015, /* EMC_MRS_WAIT_CNT */ - 0x00150015, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000018, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000013, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000009, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08090103, /* MC_EMEM_ARB_DA_TURNS */ - 0x001a1118, /* MC_EMEM_ARB_DA_COVERS */ - 0x71ac2419, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000011, /* EMC_QUSE */ - 0x0000000b, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000c, /* EMC_DLL_XFORM_DQS0 */ - 0x00000011, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000018, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000f, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x00000009, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000011, /* EMC_QUSE */ - 0x0000000b, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000c, /* EMC_DLL_XFORM_DQS0 */ - 0x00000011, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000018, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000010, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x0000000f, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x00000009, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000d, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200000, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010043, /* Mode Register 1 */ - 0x8002001a, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_table e1580_h9ccnnn8ktmlbr_ntm_table[] = { - { - 0x40, /* Rev 4.0 */ - 204000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000c, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000008, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000a, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000002, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000e, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000003, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x0000000c, /* EMC_RW2PDEN */ - 0x0000001d, /* EMC_TXSR */ - 0x0000001d, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000b, /* EMC_TFAW */ - 0x00000005, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000351, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0x005800a8, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a01c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x0000004a, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000714, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_W2R */ - 0x05050102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0506, /* MC_EMEM_ARB_DA_COVERS */ - 0x71e40a07, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00040000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ1 */ - 0x00040000, /* EMC_DLL_XFORM_DQ2 */ - 0x00040000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000005, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000a, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00208208, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00040000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00040000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00040000, /* EMC_DLL_XFORM_DQ1 */ - 0x00040000, /* EMC_DLL_XFORM_DQ2 */ - 0x00040000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000017, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf320000e, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x80010083, /* Mode Register 1 */ - 0x80020004, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - }, - { - 0x40, /* Rev 4.0 */ - 504000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001e, /* EMC_RC */ - 0x00000041, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000015, /* EMC_RAS */ - 0x00000009, /* EMC_RP */ - 0x0000000b, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000009, /* EMC_RD_RCD */ - 0x00000009, /* EMC_WR_RCD */ - 0x00000005, /* EMC_RRD */ - 0x00000003, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000003, /* EMC_WDV */ - 0x00000003, /* EMC_WDV_MASK */ - 0x00000008, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000005, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x00000775, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000001dd, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000003, /* EMC_PDEX2RD */ - 0x00000009, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000001, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x00000047, /* EMC_TXSR */ - 0x00000047, /* EMC_TXSRDLL */ - 0x00000008, /* EMC_TCKE */ - 0x00000008, /* EMC_TCKESR */ - 0x00000008, /* EMC_TPD */ - 0x0000001a, /* EMC_TFAW */ - 0x0000000b, /* EMC_TRPAB */ - 0x00000001, /* EMC_TCLKSTABLE */ - 0x00000003, /* EMC_TCLKSTOP */ - 0x00000836, /* EMC_TREFBW */ - 0x00000007, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0001aa86, /* EMC_FBIO_CFG5 */ - 0xf0140099, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x00010220, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0003023d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc004, /* EMC_XM2CLKPADCTRL */ - 0x81f1f008, /* EMC_XM2COMPPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000000, /* EMC_TXDSRVTTGEN */ - 0x02000100, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00064000, /* EMC_ZCAL_INTERVAL */ - 0x000000b6, /* EMC_ZCAL_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT */ - 0x00110011, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001004, /* EMC_DYN_SELF_REF_CONTROL */ - 0x09257359, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x00000017, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x09000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06070103, /* MC_EMEM_ARB_DA_TURNS */ - 0x00120b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x71c81710, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000f, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000b, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000007, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000f, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x007df7df, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10000, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000000, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000102, /* MC_PTSA_GRANT_DECREMENT */ - 0x000e000e, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000013, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00130013, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00190013, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000019, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00190019, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ab0050, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ab00ab, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000032, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0xf3200006, /* EMC_CFG */ - 0x00000000, /* Mode Register 0 */ - 0x800100c3, /* Mode Register 1 */ - 0x80020006, /* Mode Register 2 */ - 0x800b0000, /* Mode Register 4 */ - }, -}; - -static struct tegra11_emc_pdata e1580_no_dram_pdata = { - .description = "e1580_h9ccnnn8ktmlbr_ntm", - .tables = e1580_h9ccnnn8ktmlbr_ntm_table, - .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_table), -}; - -static struct tegra11_emc_pdata e1580_A01P_AP40_pdata = { - .description = "e1580_h9ccnnn8ktmlbr_ntm_AP40", - .tables = e1580_h9ccnnn8ktmlbr_ntm_AP40_table, - .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_AP40_table), -}; - -static struct tegra11_emc_pdata e1580_A01P_AP40_2gb_pdata = { - .description = "e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb", - .tables = e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table, - .num_tables = ARRAY_SIZE(e1580_h9ccnnn8ktmlbr_ntm_AP40_2gb_table), -}; - -static struct tegra11_emc_pdata *pluto_get_emc_data(void) -{ - struct board_info board_info; - unsigned long mem; - - tegra_get_board_info(&board_info); - - /* Load AP40 Table */ - if (board_info.board_id == BOARD_E1580 - && tegra_get_sku_id() == 0x6) { - /* Get the memory size */ - mem = memblock_phys_mem_size(); - if (mem > SZ_1G) - /* Table for 2 GB memory */ - return &e1580_A01P_AP40_2gb_pdata; - else - return &e1580_A01P_AP40_pdata; - } - - /* Default Pluto Table */ - if (board_info.board_id == BOARD_E1580 || - board_info.board_id == BOARD_E1575 || - board_info.board_id == BOARD_E1577) - return &e1580_no_dram_pdata; - - return NULL; -} - -int __init pluto_emc_init(void) -{ - tegra_emc_device.dev.platform_data = pluto_get_emc_data(); - platform_device_register(&tegra_emc_device); - tegra11_emc_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-pluto-panel.c b/arch/arm/mach-tegra/board-pluto-panel.c deleted file mode 100644 index f77aad087902..000000000000 --- a/arch/arm/mach-tegra/board-pluto-panel.c +++ /dev/null @@ -1,449 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-panel.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <linux/ioport.h> -#include <linux/fb.h> -#include <linux/nvmap.h> -#include <linux/nvhost.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/i2c/pca953x.h> -#include <linux/of.h> -#include <mach/irqs.h> -#include <mach/dc.h> - -#include "board.h" -#include "devices.h" -#include "gpio-names.h" -#include "board-pluto.h" -#include "board-panel.h" -#include "common.h" -#include "iomap.h" - -#include "tegra11_host1x_devices.h" - -#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH5 -#define DSI_PANEL_BL_EN_GPIO TEGRA_GPIO_PH2 -#define DSI_PANEL_BL_PWM_GPIO TEGRA_GPIO_PH1 - -struct platform_device * __init pluto_host1x_init(void) -{ - struct platform_device *pdev = NULL; - -#ifdef CONFIG_TEGRA_GRHOST - if (!of_have_populated_dt()) - pdev = tegra11_register_host1x_devices(); - else - pdev = to_platform_device(bus_find_device_by_name( - &platform_bus_type, NULL, "host1x")); -#endif - return pdev; -} - - -/* hdmi pins for hotplug */ -#define pluto_hdmi_hpd TEGRA_GPIO_PN7 - -/* hdmi related regulators */ -static struct regulator *pluto_hdmi_vddio; -static struct regulator *pluto_hdmi_reg; -static struct regulator *pluto_hdmi_pll; - -static struct resource pluto_disp1_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_GENERAL, - .end = INT_DISPLAY_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY_BASE, - .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by pluto_panel_init() */ - .end = 0, /* Filled in by pluto_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "dsi_regs", - .start = 0, /* Filled in the panel file by init_resources() */ - .end = 0, /* Filled in the panel file by init_resources() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "mipi_cal", - .start = TEGRA_MIPI_CAL_BASE, - .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource pluto_disp2_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_B_GENERAL, - .end = INT_DISPLAY_B_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY2_BASE, - .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by pluto_panel_init() */ - .end = 0, /* Filled in by pluto_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "hdmi_regs", - .start = TEGRA_HDMI_BASE, - .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct tegra_dc_sd_settings sd_settings; - -static struct tegra_dc_out pluto_disp1_out = { - .type = TEGRA_DC_OUT_DSI, - .sd_settings = &sd_settings, -}; - -static int pluto_hdmi_enable(struct device *dev) -{ - int ret; - if (!pluto_hdmi_reg) { - pluto_hdmi_reg = regulator_get(dev, "avdd_hdmi"); - if (IS_ERR(pluto_hdmi_reg)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); - pluto_hdmi_reg = NULL; - return PTR_ERR(pluto_hdmi_reg); - } - } - ret = regulator_enable(pluto_hdmi_reg); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); - return ret; - } - if (!pluto_hdmi_pll) { - pluto_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll"); - if (IS_ERR(pluto_hdmi_pll)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); - pluto_hdmi_pll = NULL; - regulator_put(pluto_hdmi_reg); - pluto_hdmi_reg = NULL; - return PTR_ERR(pluto_hdmi_pll); - } - } - ret = regulator_enable(pluto_hdmi_pll); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); - return ret; - } - return 0; -} - -static int pluto_hdmi_disable(void) -{ - if (pluto_hdmi_reg) { - regulator_disable(pluto_hdmi_reg); - regulator_put(pluto_hdmi_reg); - pluto_hdmi_reg = NULL; - } - - if (pluto_hdmi_pll) { - regulator_disable(pluto_hdmi_pll); - regulator_put(pluto_hdmi_pll); - pluto_hdmi_pll = NULL; - } - - return 0; -} - -static int pluto_hdmi_postsuspend(void) -{ - if (pluto_hdmi_vddio) { - regulator_disable(pluto_hdmi_vddio); - regulator_put(pluto_hdmi_vddio); - pluto_hdmi_vddio = NULL; - } - return 0; -} - -static int pluto_hdmi_hotplug_init(struct device *dev) -{ - int ret = 0; - if (!pluto_hdmi_vddio) { - pluto_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0"); - if (IS_ERR(pluto_hdmi_vddio)) { - ret = PTR_ERR(pluto_hdmi_vddio); - pr_err("hdmi: couldn't get regulator vdd_hdmi_5v0\n"); - pluto_hdmi_vddio = NULL; - return ret; - } - } - ret = regulator_enable(pluto_hdmi_vddio); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator vdd_hdmi_5v0\n"); - regulator_put(pluto_hdmi_vddio); - pluto_hdmi_vddio = NULL; - return ret; - } - return ret; -} - -static struct tegra_dc_out pluto_disp2_out = { - .type = TEGRA_DC_OUT_HDMI, - .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, - .parent_clk = "pll_d2_out0", - - .ddc_bus = 3, - .hotplug_gpio = pluto_hdmi_hpd, - - .max_pixclock = KHZ2PICOS(297000), - - .enable = pluto_hdmi_enable, - .disable = pluto_hdmi_disable, - .postsuspend = pluto_hdmi_postsuspend, - .hotplug_init = pluto_hdmi_hotplug_init, -}; - -static struct tegra_fb_data pluto_disp1_fb_data = { - .win = 0, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data pluto_disp1_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &pluto_disp1_out, - .fb = &pluto_disp1_fb_data, - .emc_clk_rate = 204000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct tegra_fb_data pluto_disp2_fb_data = { - .win = 0, - .xres = 1024, - .yres = 600, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data pluto_disp2_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &pluto_disp2_out, - .fb = &pluto_disp2_fb_data, - .emc_clk_rate = 300000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct platform_device pluto_disp2_device = { - .name = "tegradc", - .id = 1, - .resource = pluto_disp2_resources, - .num_resources = ARRAY_SIZE(pluto_disp2_resources), - .dev = { - .platform_data = &pluto_disp2_pdata, - }, -}; - -static struct platform_device pluto_disp1_device = { - .name = "tegradc", - .id = 0, - .resource = pluto_disp1_resources, - .num_resources = ARRAY_SIZE(pluto_disp1_resources), - .dev = { - .platform_data = &pluto_disp1_pdata, - }, -}; - -static struct nvmap_platform_carveout pluto_carveouts[] = { - [0] = { - .name = "iram", - .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, - .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, - .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, - }, - [1] = { - .name = "generic-0", - .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, - .base = 0, /* Filled in by pluto_panel_init() */ - .size = 0, /* Filled in by pluto_panel_init() */ - }, - [2] = { - .name = "vpr", - .usage_mask = NVMAP_HEAP_CARVEOUT_VPR, - .base = 0, /* Filled in by pluto_panel_init() */ - .size = 0, /* Filled in by pluto_panel_init() */ - }, -}; - -static struct nvmap_platform_data pluto_nvmap_data = { - .carveouts = pluto_carveouts, - .nr_carveouts = ARRAY_SIZE(pluto_carveouts), -}; - -static struct platform_device pluto_nvmap_device = { - .name = "tegra-nvmap", - .id = -1, - .dev = { - .platform_data = &pluto_nvmap_data, - }, -}; - -static void pluto_panel_select(void) -{ - struct tegra_panel *panel; - struct board_info board; - u8 dsi_instance = 0; - - tegra_get_display_board_info(&board); - - switch (board.board_id) { - case BOARD_E1605: - panel = &dsi_j_720p_4_7; - dsi_instance = DSI_INSTANCE_1; - break; - case BOARD_E1577: - panel = &dsi_s_1080p_5; - break; - case BOARD_E1582: - default: - if (tegra_get_board_panel_id()) { - panel = &dsi_s_1080p_5; - dsi_instance = DSI_INSTANCE_1; - } else { - panel = &dsi_l_720p_5; - dsi_instance = DSI_INSTANCE_0; - } - break; - } - - if (panel->init_sd_settings) - panel->init_sd_settings(&sd_settings); - - if (panel->init_dc_out) { - panel->init_dc_out(&pluto_disp1_out); - pluto_disp1_out.dsi->dsi_instance = dsi_instance; - pluto_disp1_out.dsi->dsi_panel_rst_gpio = DSI_PANEL_RST_GPIO; - pluto_disp1_out.dsi->dsi_panel_bl_en_gpio = - DSI_PANEL_BL_EN_GPIO; - pluto_disp1_out.dsi->dsi_panel_bl_pwm_gpio = - DSI_PANEL_BL_PWM_GPIO; - /* update the init cmd if dependent on reset GPIO */ - tegra_dsi_update_init_cmd_gpio_rst(&pluto_disp1_out); - } - - if (panel->init_fb_data) - panel->init_fb_data(&pluto_disp1_fb_data); - - if (panel->init_cmu_data) - panel->init_cmu_data(&pluto_disp1_pdata); - - if (panel->set_disp_device) - panel->set_disp_device(&pluto_disp1_device); - - tegra_dsi_resources_init(dsi_instance, pluto_disp1_resources, - ARRAY_SIZE(pluto_disp1_resources)); - - if (panel->register_bl_dev) - panel->register_bl_dev(); - -} -int __init pluto_panel_init(void) -{ - int err = 0; - struct resource __maybe_unused *res; - struct platform_device *phost1x = NULL; - - pluto_panel_select(); - -#ifdef CONFIG_TEGRA_NVMAP - pluto_carveouts[1].base = tegra_carveout_start; - pluto_carveouts[1].size = tegra_carveout_size; - pluto_carveouts[2].base = tegra_vpr_start; - pluto_carveouts[2].size = tegra_vpr_size; -#ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT - pluto_carveouts[1].cma_dev = &tegra_generic_cma_dev; - pluto_carveouts[1].resize = false; - pluto_carveouts[2].cma_dev = &tegra_vpr_cma_dev; - pluto_carveouts[2].resize = true; - pluto_carveouts[2].cma_chunk_size = SZ_32M; -#endif - - err = platform_device_register(&pluto_nvmap_device); - if (err) { - pr_err("nvmap device registration failed\n"); - return err; - } -#endif - phost1x = pluto_host1x_init(); - if (!phost1x) { - pr_err("host1x devices registration failed\n"); - return -EINVAL; - } - - res = platform_get_resource_byname(&pluto_disp1_device, - IORESOURCE_MEM, "fbmem"); - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; - - /* Copy the bootloader fb to the fb. */ - __tegra_move_framebuffer(&pluto_nvmap_device, - tegra_fb_start, tegra_bootloader_fb_start, - min(tegra_fb_size, tegra_bootloader_fb_size)); - - pluto_disp1_device.dev.parent = &phost1x->dev; - err = platform_device_register(&pluto_disp1_device); - if (err) { - pr_err("disp1 device registration failed\n"); - return err; - } - - err = tegra_init_hdmi(&pluto_disp2_device, phost1x); - if (err) - return err; - -#ifdef CONFIG_TEGRA_NVAVP - if (!of_have_populated_dt()) { - nvavp_device.dev.parent = &phost1x->dev; - err = platform_device_register(&nvavp_device); - if (err) { - pr_err("nvavp device registration failed\n"); - return err; - } - } -#endif - return err; -} diff --git a/arch/arm/mach-tegra/board-pluto-power.c b/arch/arm/mach-tegra/board-pluto-power.c deleted file mode 100644 index 39722415e1dc..000000000000 --- a/arch/arm/mach-tegra/board-pluto-power.c +++ /dev/null @@ -1,946 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-power.c - * - * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/pda_power.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/io.h> -#include <linux/gpio.h> - -#include <mach/edp.h> -#include <mach/irqs.h> -#include <mach/io_dpd.h> -#include <linux/tegra-soc.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/palmas.h> -#include <linux/regulator/machine.h> -#include <linux/irq.h> -#include <linux/pid_thermal_gov.h> -#include <linux/tegra-pmc.h> - -#include <asm/mach-types.h> - -#include "cpu-tegra.h" -#include "pm.h" -#include "board.h" -#include "board-common.h" -#include "board-pluto.h" -#include "board-pmu-defines.h" -#include "iomap.h" -#include "tegra_cl_dvfs.h" -#include "devices.h" -#include "tegra11_soctherm.h" - -#define PMC_CTRL 0x0 -#define PMC_CTRL_INTR_LOW (1 << 17) -#define PLUTO_4K_REWORKED 0x2 - -/************************ Pluto based regulator ****************/ -static struct regulator_consumer_supply palmas_smps123_supply[] = { - REGULATOR_SUPPLY("vdd_cpu", NULL), -}; - -static struct regulator_consumer_supply palmas_smps45_supply[] = { - REGULATOR_SUPPLY("vdd_core", NULL), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.0"), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.2"), - REGULATOR_SUPPLY("vdd_core", "sdhci-tegra.3"), -}; - -static struct regulator_consumer_supply palmas_smps6_supply[] = { - REGULATOR_SUPPLY("vdd_core_bb", NULL), -}; - -static struct regulator_consumer_supply palmas_smps7_supply[] = { - REGULATOR_SUPPLY("vddio_ddr", NULL), - REGULATOR_SUPPLY("vddio_lpddr3", NULL), - REGULATOR_SUPPLY("vcore2_lpddr3", NULL), - REGULATOR_SUPPLY("vcore_audio_1v2", NULL), -}; - -static struct regulator_consumer_supply palmas_smps8_supply[] = { - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_osc", NULL), - REGULATOR_SUPPLY("vddio_sys", NULL), - REGULATOR_SUPPLY("vddio_bb", NULL), - REGULATOR_SUPPLY("pwrdet_bb", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"), - REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("vdd_emmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), - REGULATOR_SUPPLY("vddio_audio", NULL), - REGULATOR_SUPPLY("pwrdet_audio", NULL), - REGULATOR_SUPPLY("vddio_uart", NULL), - REGULATOR_SUPPLY("pwrdet_uart", NULL), - REGULATOR_SUPPLY("vddio_gmi", NULL), - REGULATOR_SUPPLY("pwrdet_nand", NULL), - REGULATOR_SUPPLY("vddio_cam", "vi"), - REGULATOR_SUPPLY("pwrdet_cam", NULL), - REGULATOR_SUPPLY("dvdd", "0-0077"), - REGULATOR_SUPPLY("vlogic", "0-0069"), - REGULATOR_SUPPLY("vid", "0-000d"), - REGULATOR_SUPPLY("vddio", "0-0078"), - REGULATOR_SUPPLY("vdd_dtv", NULL), - REGULATOR_SUPPLY("vdd_bb", NULL), - REGULATOR_SUPPLY("vcore1_lpddr", NULL), - REGULATOR_SUPPLY("vcore_lpddr", NULL), - REGULATOR_SUPPLY("vddio_lpddr", NULL), - REGULATOR_SUPPLY("vdd_rf", NULL), - REGULATOR_SUPPLY("vdd_modem2", NULL), - REGULATOR_SUPPLY("vdd_dbg", NULL), - REGULATOR_SUPPLY("vdd_sim_1v8", NULL), - REGULATOR_SUPPLY("vdd_sim1a_1v8", NULL), - REGULATOR_SUPPLY("vdd_sim1b_1v8", NULL), - REGULATOR_SUPPLY("dvdd_audio", NULL), - REGULATOR_SUPPLY("avdd_audio", NULL), - REGULATOR_SUPPLY("vdd_com_1v8", NULL), - REGULATOR_SUPPLY("dvdd", "spi3.2"), - REGULATOR_SUPPLY("avdd_pll_bb", NULL), -}; - -static struct regulator_consumer_supply palmas_smps9_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"), - REGULATOR_SUPPLY("vdd_sim_mmc", NULL), - REGULATOR_SUPPLY("vdd_sim1a_mmc", NULL), - REGULATOR_SUPPLY("vdd_sim1b_mmc", NULL), -}; - -static struct regulator_consumer_supply palmas_smps10_out1_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"), - REGULATOR_SUPPLY("usb_vbus", "tegra-otg"), - REGULATOR_SUPPLY("avddio_usb", "tegra-xhci"), - REGULATOR_SUPPLY("usb_vbus0", "tegra-xhci"), - REGULATOR_SUPPLY("vdd_lcd", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo1_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo1_4K_supply[] = { - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo2_supply[] = { - REGULATOR_SUPPLY("avdd_lcd", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo3_supply[] = { - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_dsi_csi", "vi"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-ehci.2"), - REGULATOR_SUPPLY("vddio_hsic", "tegra-xhci"), - REGULATOR_SUPPLY("pwrdet_mipi", NULL), - REGULATOR_SUPPLY("vddio_hsic_bb", NULL), - REGULATOR_SUPPLY("vddio_hsic_modem2", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo4_supply[] = { - REGULATOR_SUPPLY("vdd_spare", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo4_4K_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), - REGULATOR_SUPPLY("vdd_spare", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo5_supply[] = { - REGULATOR_SUPPLY("avdd_cam1", NULL), - REGULATOR_SUPPLY("vana", "2-0010"), -}; - -static struct regulator_consumer_supply palmas_ldo6_supply[] = { - REGULATOR_SUPPLY("vdd_temp", NULL), - REGULATOR_SUPPLY("vdd_mb", NULL), - REGULATOR_SUPPLY("vin", "1-004d"), - REGULATOR_SUPPLY("avdd", "0-0077"), - REGULATOR_SUPPLY("vdd_irled", NULL), - REGULATOR_SUPPLY("vdd_sensor_3v0", NULL), - REGULATOR_SUPPLY("vdd_3v0_pm", NULL), - REGULATOR_SUPPLY("vaux_3v3", NULL), - REGULATOR_SUPPLY("vdd", "0-0044"), - REGULATOR_SUPPLY("vdd", "0-004c"), - REGULATOR_SUPPLY("avdd", "spi3.2"), - REGULATOR_SUPPLY("vdd", "0-0069"), - REGULATOR_SUPPLY("vdd", "0-000d"), - REGULATOR_SUPPLY("vdd", "0-0078"), - REGULATOR_SUPPLY("vcc", "1-0071"), -}; - -static struct regulator_consumer_supply palmas_ldo7_supply[] = { - REGULATOR_SUPPLY("vdd_af_cam1", NULL), - REGULATOR_SUPPLY("imx132_reg1", NULL), - REGULATOR_SUPPLY("imx091_vcm_vdd", NULL), - REGULATOR_SUPPLY("vdd", "2-000e"), -}; -static struct regulator_consumer_supply palmas_ldo8_supply[] = { - REGULATOR_SUPPLY("vdd_rtc", NULL), -}; -static struct regulator_consumer_supply palmas_ldo9_supply[] = { - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"), - REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), -}; -static struct regulator_consumer_supply palmas_ldoln_supply[] = { - REGULATOR_SUPPLY("avdd_cam2", NULL), - REGULATOR_SUPPLY("vana", "2-0036"), - REGULATOR_SUPPLY("vana_imx132", "2-0036"), -}; - -static struct regulator_consumer_supply palmas_ldousb_supply[] = { - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("hvdd_usb", "tegra-xhci"), - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), - REGULATOR_SUPPLY("vddio_hv", "tegradc.1"), - REGULATOR_SUPPLY("pwrdet_hv", NULL), - REGULATOR_SUPPLY("vdd_dtv_3v3", NULL), - -}; - -static struct regulator_consumer_supply palmas_regen1_supply[] = { - REGULATOR_SUPPLY("mic_ventral", NULL), -}; - -static struct regulator_consumer_supply palmas_regen2_supply[] = { - REGULATOR_SUPPLY("vdd_mic", NULL), -}; - -PALMAS_REGS_PDATA(smps123, 900, 1350, NULL, 0, 0, 0, NORMAL, - 0, PALMAS_EXT_CONTROL_ENABLE1, 0, 2500, 0); -PALMAS_REGS_PDATA(smps45, 900, 1400, NULL, 0, 0, 0, NORMAL, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 2500, 0); -PALMAS_REGS_PDATA(smps6, 850, 850, NULL, 0, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps7, 1200, 1200, NULL, 0, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps8, 1800, 1800, NULL, 1, 1, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps9, 2800, 2800, NULL, 1, 0, 1, NORMAL, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(smps10_out1, 5000, 5000, NULL, 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo1, 1050, 1050, palmas_rails(smps7), 0, 0, 1, 0, - 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0, 0); -PALMAS_REGS_PDATA(ldo2, 2800, 3000, NULL, 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo3, 1200, 1200, palmas_rails(smps8), 0, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo4, 1200, 1200, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo5, 2700, 2700, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo6, 3000, 3000, NULL, 1, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo7, 2800, 2800, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo8, 900, 900, NULL, 1, 1, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldo9, 1800, 3300, palmas_rails(smps9), 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldoln, 2700, 2700, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(ldousb, 3300, 3300, NULL, 0, 0, 1, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(regen1, 4300, 4300, NULL, 0, 0, 0, 0, - 0, 0, 0, 0, 0); -PALMAS_REGS_PDATA(regen2, 4300, 4300, palmas_rails(smps8), 0, 0, 0, 0, - 0, 0, 0, 0, 0); - -#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname -static struct regulator_init_data *pluto_reg_data[PALMAS_NUM_REGS] = { - NULL, - PALMAS_REG_PDATA(smps123), - NULL, - PALMAS_REG_PDATA(smps45), - NULL, - PALMAS_REG_PDATA(smps6), - PALMAS_REG_PDATA(smps7), - PALMAS_REG_PDATA(smps8), - PALMAS_REG_PDATA(smps9), - NULL, - PALMAS_REG_PDATA(smps10_out1), - PALMAS_REG_PDATA(ldo1), - PALMAS_REG_PDATA(ldo2), - PALMAS_REG_PDATA(ldo3), - PALMAS_REG_PDATA(ldo4), - PALMAS_REG_PDATA(ldo5), - PALMAS_REG_PDATA(ldo6), - PALMAS_REG_PDATA(ldo7), - PALMAS_REG_PDATA(ldo8), - PALMAS_REG_PDATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_PDATA(ldoln), - PALMAS_REG_PDATA(ldousb), - PALMAS_REG_PDATA(regen1), - PALMAS_REG_PDATA(regen2), - NULL, - NULL, - NULL, -}; - -#define PALMAS_REG_INIT_DATA(_sname) ®_init_data_##_sname -static struct palmas_reg_init *pluto_reg_init[PALMAS_NUM_REGS] = { - NULL, - PALMAS_REG_INIT_DATA(smps123), - NULL, - PALMAS_REG_INIT_DATA(smps45), - NULL, - PALMAS_REG_INIT_DATA(smps6), - PALMAS_REG_INIT_DATA(smps7), - PALMAS_REG_INIT_DATA(smps8), - PALMAS_REG_INIT_DATA(smps9), - NULL, - PALMAS_REG_INIT_DATA(smps10_out1), - PALMAS_REG_INIT_DATA(ldo1), - PALMAS_REG_INIT_DATA(ldo2), - PALMAS_REG_INIT_DATA(ldo3), - PALMAS_REG_INIT_DATA(ldo4), - PALMAS_REG_INIT_DATA(ldo5), - PALMAS_REG_INIT_DATA(ldo6), - PALMAS_REG_INIT_DATA(ldo7), - PALMAS_REG_INIT_DATA(ldo8), - PALMAS_REG_INIT_DATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_INIT_DATA(ldoln), - PALMAS_REG_INIT_DATA(ldousb), - PALMAS_REG_INIT_DATA(regen1), - PALMAS_REG_INIT_DATA(regen2), - NULL, - NULL, - NULL, -}; - -static int ac_online(void) -{ - return 1; -} - -static struct resource pluto_pda_resources[] = { - [0] = { - .name = "ac", - }, -}; - -static struct pda_power_pdata pluto_pda_data = { - .is_ac_online = ac_online, -}; - -static struct platform_device pluto_pda_power_device = { - .name = "pda-power", - .id = -1, - .resource = pluto_pda_resources, - .num_resources = ARRAY_SIZE(pluto_pda_resources), - .dev = { - .platform_data = &pluto_pda_data, - }, -}; - -/* Always ON /Battery regulator */ -static struct regulator_consumer_supply fixed_reg_en_battery_supply[] = { - REGULATOR_SUPPLY("vdd_sys_cam", NULL), - REGULATOR_SUPPLY("vdd_sys_bl", NULL), - REGULATOR_SUPPLY("vdd_sys_com", NULL), - REGULATOR_SUPPLY("vdd_sys_bt", NULL), - REGULATOR_SUPPLY("vdd_sys_audio", NULL), - REGULATOR_SUPPLY("vdd_vbrtr", NULL), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_cam_supply[] = { - REGULATOR_SUPPLY("vddio_cam_mb", NULL), - REGULATOR_SUPPLY("imx132_reg2", NULL), - REGULATOR_SUPPLY("imx091_i2c_vdd", NULL), - REGULATOR_SUPPLY("vdd_1v8_cam12", NULL), - REGULATOR_SUPPLY("vif", "2-0010"), - REGULATOR_SUPPLY("vif", "2-0036"), - REGULATOR_SUPPLY("vdd_i2c", "2-000e"), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_1v2_cam_supply[] = { - REGULATOR_SUPPLY("vdd_1v2_cam", NULL), - REGULATOR_SUPPLY("vdig", "2-0010"), - REGULATOR_SUPPLY("vdig", "2-0036"), -}; - -static struct regulator_consumer_supply fixed_reg_en_avdd_usb3_1v05_supply[] = { - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-xhci"), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_mmc_sdmmc3_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_1v8_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_1v8_s", NULL), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_lcd_mmc_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_mmc_s_f", NULL), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_1v8_mic_supply[] = { - REGULATOR_SUPPLY("vdd_1v8_mic", NULL), -}; - -static struct regulator_consumer_supply fixed_reg_en_vdd_hdmi_5v0_supply[] = { - REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"), -}; - -static struct regulator_consumer_supply fixed_reg_en_vpp_fuse_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), - REGULATOR_SUPPLY("v_efuse", NULL), -}; - -/* Macro for defining fixed regulator sub device data */ -#define FIXED_SUPPLY(_name) "fixed_reg_en"#_name -#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ - _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts, \ - _sdelay) \ - static struct regulator_init_data ri_data_##_var = \ - { \ - .supply_regulator = _in_supply, \ - .num_consumer_supplies = \ - ARRAY_SIZE(fixed_reg_en_##_name##_supply), \ - .consumer_supplies = fixed_reg_en_##_name##_supply, \ - .constraints = { \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - }, \ - }; \ - static struct fixed_voltage_config fixed_reg_en_##_var##_pdata = \ - { \ - .supply_name = FIXED_SUPPLY(_name), \ - .microvolts = _millivolts * 1000, \ - .gpio = _gpio_nr, \ - .gpio_is_open_drain = _open_drain, \ - .enable_high = _active_high, \ - .enabled_at_boot = _boot_state, \ - .init_data = &ri_data_##_var, \ - .startup_delay = _sdelay \ - }; \ - static struct platform_device fixed_reg_en_##_var##_dev = { \ - .name = "reg-fixed-voltage", \ - .id = _id, \ - .dev = { \ - .platform_data = &fixed_reg_en_##_var##_pdata, \ - }, \ - } - -FIXED_REG(0, battery, battery, - NULL, 0, 0, - -1, false, true, 0, 3300, 0); - -FIXED_REG(1, vdd_1v8_cam, vdd_1v8_cam, - palmas_rails(smps8), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO1, false, true, 0, 1800, - 0); - -FIXED_REG(2, vdd_1v2_cam, vdd_1v2_cam, - palmas_rails(smps7), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO2, false, true, 0, 1200, - 0); - -FIXED_REG(3, avdd_usb3_1v05, avdd_usb3_1v05, - palmas_rails(smps8), 0, 0, - TEGRA_GPIO_PK5, false, true, 0, 1050, 0); - -FIXED_REG(4, vdd_mmc_sdmmc3, vdd_mmc_sdmmc3, - palmas_rails(smps9), 0, 0, - TEGRA_GPIO_PK1, false, true, 0, 3300, 0); - -FIXED_REG(5, vdd_lcd_1v8, vdd_lcd_1v8, - palmas_rails(smps8), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO4, false, true, 0, 1800, - 0); - -FIXED_REG(6, vdd_lcd_mmc, vdd_lcd_mmc, - palmas_rails(smps9), 0, 0, - TEGRA_GPIO_PI4, false, true, 0, 1800, 0); - -FIXED_REG(7, vdd_1v8_mic, vdd_1v8_mic, - palmas_rails(smps8), 0, 0, - -1, false, true, 0, 1800, 0); - -FIXED_REG(8, vdd_hdmi_5v0, vdd_hdmi_5v0, - NULL, 0, 0, - TEGRA_GPIO_PK6, true, true, 0, 5000, 5000); - -FIXED_REG(9, vpp_fuse, vpp_fuse, - palmas_rails(smps8), 0, 0, - TEGRA_GPIO_PX4, false, true, 0, 1800, 0); - -/* - * Creating the fixed regulator device tables - */ -#define ADD_FIXED_REG(_name) (&fixed_reg_en_##_name##_dev) - -#define E1580_COMMON_FIXED_REG \ - ADD_FIXED_REG(battery), \ - ADD_FIXED_REG(vdd_1v8_cam), \ - ADD_FIXED_REG(vdd_1v2_cam), \ - ADD_FIXED_REG(avdd_usb3_1v05), \ - ADD_FIXED_REG(vdd_mmc_sdmmc3), \ - ADD_FIXED_REG(vdd_lcd_1v8), \ - ADD_FIXED_REG(vdd_lcd_mmc), \ - ADD_FIXED_REG(vdd_1v8_mic), \ - ADD_FIXED_REG(vdd_hdmi_5v0), - -#define E1580_T114_FIXED_REG \ - ADD_FIXED_REG(vpp_fuse), - -/* Gpio switch regulator platform data for Pluto E1580 */ -static struct platform_device *pfixed_reg_devs[] = { - E1580_COMMON_FIXED_REG - E1580_T114_FIXED_REG -}; - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -/* board parameters for cpu dfll */ -static struct tegra_cl_dvfs_cfg_param pluto_cl_dvfs_param = { - .sample_rate = 11500, - - .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, - .cf = 10, - .ci = 0, - .cg = 2, - - .droop_cut_value = 0xF, - .droop_restore_ramp = 0x0, - .scale_out_ramp = 0x0, -}; -#endif - -/* palmas: fixed 10mV steps from 600mV to 1400mV, with offset 0x10 */ -#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) -static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; -static inline void fill_reg_map(void) -{ - int i; - for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { - pmu_cpu_vdd_map[i].reg_value = i + 0x10; - pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; - } -} - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static struct tegra_cl_dvfs_platform_data pluto_cl_dvfs_data = { - .dfll_clk_name = "dfll_cpu", - .pmu_if = TEGRA_CL_DVFS_PMU_I2C, - .u.pmu_i2c = { - .fs_rate = 400000, - .slave_addr = 0xb0, - .reg = 0x23, - }, - .vdd_map = pmu_cpu_vdd_map, - .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, - .pmu_undershoot_gb = 100, - - .cfg_param = &pluto_cl_dvfs_param, -}; - -static int __init pluto_cl_dvfs_init(void) -{ - fill_reg_map(); - if (tegra_revision < TEGRA_REVISION_A02) - pluto_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET; - tegra_cl_dvfs_device.dev.platform_data = &pluto_cl_dvfs_data; - platform_device_register(&tegra_cl_dvfs_device); - - return 0; -} -#endif - -static struct palmas_dvfs_init_data palmas_dvfs_idata[] = { - { - .en_pwm = false, - }, { - .en_pwm = true, - .ext_ctrl = PALMAS_EXT_CONTROL_ENABLE2, - .reg_id = PALMAS_REG_SMPS6, - .step_20mV = true, - .base_voltage_uV = 500000, - .max_voltage_uV = 1100000, - }, -}; - -static struct palmas_pmic_platform_data pmic_platform = { - .dvfs_init_data = palmas_dvfs_idata, - .dvfs_init_data_size = ARRAY_SIZE(palmas_dvfs_idata), -}; - -static struct palmas_clk32k_init_data palmas_clk32k_idata[] = { - { - .clk32k_id = PALMAS_CLOCK32KG, - .enable = true, - }, { - .clk32k_id = PALMAS_CLOCK32KG_AUDIO, - .enable = true, - }, -}; - -static struct palmas_pinctrl_config palmas_pincfg[] = { - PALMAS_PINMUX("powergood", "powergood", NULL, NULL), - PALMAS_PINMUX("vac", "vac", NULL, NULL), - PALMAS_PINMUX("gpio0", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio1", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio2", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio3", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio4", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio5", "clk32kgaudio", NULL, NULL), - PALMAS_PINMUX("gpio6", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio7", "gpio", NULL, NULL), -}; - -static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = { - .pincfg = palmas_pincfg, - .num_pinctrl = ARRAY_SIZE(palmas_pincfg), - .dvfs1_enable = false, - .dvfs2_enable = true, -}; - -static struct palmas_platform_data palmas_pdata = { - .gpio_base = PALMAS_TEGRA_GPIO_BASE, - .irq_base = PALMAS_TEGRA_IRQ_BASE, - .pmic_pdata = &pmic_platform, - .clk32k_init_data = palmas_clk32k_idata, - .clk32k_init_data_size = ARRAY_SIZE(palmas_clk32k_idata), - .irq_flags = IRQ_TYPE_LEVEL_HIGH, - .pinctrl_pdata = &palmas_pinctrl_pdata, -}; - -static struct i2c_board_info palma_device[] = { - { - I2C_BOARD_INFO("tps65913", 0x58), - .irq = INT_EXTERNAL_PMU, - .platform_data = &palmas_pdata, - }, -}; - -int __init pluto_regulator_init(void) -{ - void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - u32 pmc_ctrl; - int i; - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - pluto_cl_dvfs_init(); -#endif - - /* TPS65913: Normal state of INT request line is LOW. - * configure the power management controller to trigger PMU - * interrupts when HIGH. - */ - pmc_ctrl = readl(pmc + PMC_CTRL); - writel(pmc_ctrl & ~PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); - - /* Enable full constraints */ - regulator_has_full_constraints(); - - /* Tracking configuration */ - reg_init_data_ldo8.config_flags = - PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE | - PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE; - - if (get_power_config() & PLUTO_4K_REWORKED) { - /* Account for the change of avdd_hdmi_pll from ldo1 to ldo4 */ - reg_idata_ldo1.consumer_supplies = palmas_ldo1_4K_supply; - reg_idata_ldo1.num_consumer_supplies = - ARRAY_SIZE(palmas_ldo1_4K_supply); - reg_idata_ldo4.consumer_supplies = palmas_ldo4_4K_supply; - reg_idata_ldo4.num_consumer_supplies = - ARRAY_SIZE(palmas_ldo4_4K_supply); - reg_init_data_ldo4.roof_floor = PALMAS_EXT_CONTROL_NSLEEP; - reg_idata_ldo4.constraints.always_on = 1; - reg_idata_ldo4.constraints.boot_on = 1; - } - - for (i = 0; i < PALMAS_NUM_REGS ; i++) { - pmic_platform.reg_data[i] = pluto_reg_data[i]; - pmic_platform.reg_init[i] = pluto_reg_init[i]; - } - - platform_device_register(&pluto_pda_power_device); - i2c_register_board_info(4, palma_device, - ARRAY_SIZE(palma_device)); - return 0; -} - -static int __init pluto_fixed_regulator_init(void) -{ - if (!of_machine_is_compatible("nvidia,pluto")) - return 0; - - return platform_add_devices(pfixed_reg_devs, - ARRAY_SIZE(pfixed_reg_devs)); -} -subsys_initcall_sync(pluto_fixed_regulator_init); - -static struct tegra_io_dpd hv_io = { - .name = "HV", - .io_dpd_reg_index = 1, - .io_dpd_bit = 6, -}; - -static void pluto_board_suspend(int state, enum suspend_stage stage) -{ - /* put HV IOs into DPD mode to save additional power */ - if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_SUSPEND_BEFORE_CPU) { - gpio_direction_input(TEGRA_GPIO_PK6); - tegra_io_dpd_enable(&hv_io); - } -} - -static void pluto_board_resume(int state, enum resume_stage stage) -{ - /* bring HV IOs back from DPD mode, GPIO configuration - * will be restored by gpio driver - */ - if (state == TEGRA_SUSPEND_LP1 && stage == TEGRA_RESUME_AFTER_CPU) - tegra_io_dpd_disable(&hv_io); -} - -static struct tegra_suspend_platform_data pluto_suspend_data = { - .cpu_timer = 300, - .cpu_off_timer = 300, - .suspend_mode = TEGRA_SUSPEND_LP0, - .core_timer = 0x157e, - .core_off_timer = 2000, - .corereq_high = true, - .sysclkreq_high = true, - .cpu_lp2_min_residency = 1000, - .min_residency_crail = 20000, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .lp1_lowvolt_support = true, - .i2c_base_addr = TEGRA_I2C5_BASE, - .pmuslave_addr = 0xB0, - .core_reg_addr = 0x2B, - .lp1_core_volt_low_cold = 0x33, - .lp1_core_volt_low = 0x2e, - .lp1_core_volt_high = 0x42, -#endif - .board_suspend = pluto_board_suspend, - .board_resume = pluto_board_resume, -}; - -int __init pluto_suspend_init(void) -{ - tegra_init_suspend(&pluto_suspend_data); - return 0; -} - -int __init pluto_edp_init(void) -{ - unsigned int regulator_mA; - - regulator_mA = get_maximum_cpu_current_supported(); - if (!regulator_mA) - regulator_mA = 9000; - - pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); - tegra_init_cpu_edp_limits(regulator_mA); - - regulator_mA = get_maximum_core_current_supported(); - if (!regulator_mA) - regulator_mA = 4000; - - pr_info("%s: core regulator %d mA\n", __func__, regulator_mA); - tegra_init_core_edp_limits(regulator_mA); - - return 0; -} - -static struct pid_thermal_gov_params soctherm_pid_params = { - .max_err_temp = 9000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 20, - .down_compensation = 20, -}; - -static struct thermal_zone_params soctherm_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &soctherm_pid_params, -}; - -static struct tegra_thermtrip_pmic_data tpdata_palmas = { - .reset_tegra = 1, - .pmu_16bit_ops = 0, - .controller_type = 0, - .pmu_i2c_addr = 0x58, - .i2c_controller_id = 4, - .poweroff_reg_addr = 0xa0, - .poweroff_reg_data = 0x0, -}; - -static struct soctherm_platform_data pluto_soctherm_data = { - .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE, - .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ, - .therm = { - [THERM_CPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &soctherm_tzp, - }, - [THERM_GPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 3, - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - .tzp = &soctherm_tzp, - }, - [THERM_PLL] = { - .zone_enable = true, - }, - }, - .throttle = { - [THROTTLE_HEAVY] = { - .priority = 100, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 80, - }, - [THROTTLE_DEV_GPU] = { - .depth = 80, - .enable = true, - }, - }, - }, - [THROTTLE_OC4] = { - .throt_mode = BRIEF, - .polarity = 1, - .intr = true, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 50, - }, - [THROTTLE_DEV_GPU] = { - .enable = true, - .depth = 50, - }, - }, - }, - }, - .tshut_pmu_trip_data = &tpdata_palmas, -}; - -int __init pluto_soctherm_init(void) -{ - tegra_platform_edp_init(pluto_soctherm_data.therm[THERM_CPU].trips, - &pluto_soctherm_data.therm[THERM_CPU].num_trips, - 6000); /* edp temperature margin */ - tegra_add_cpu_vmax_trips(pluto_soctherm_data.therm[THERM_CPU].trips, - &pluto_soctherm_data.therm[THERM_CPU].num_trips); - tegra_add_core_edp_trips(pluto_soctherm_data.therm[THERM_CPU].trips, - &pluto_soctherm_data.therm[THERM_CPU].num_trips); - - return tegra11_soctherm_init(&pluto_soctherm_data); -} diff --git a/arch/arm/mach-tegra/board-pluto-sdhci.c b/arch/arm/mach-tegra/board-pluto-sdhci.c deleted file mode 100644 index fb42b5866447..000000000000 --- a/arch/arm/mach-tegra/board-pluto-sdhci.c +++ /dev/null @@ -1,350 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-sdhci.c - * - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/wlan_plat.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/mmc/host.h> -#include <linux/wl12xx.h> -#include <linux/platform_data/mmc-sdhci-tegra.h> - -#include "tegra-board-id.h" -#include <asm/mach-types.h> -#include <mach/irqs.h> -#include <mach/gpio-tegra.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-pluto.h" -#include "dvfs.h" -#include "iomap.h" - -#define PLUTO_WLAN_PWR TEGRA_GPIO_PCC5 -#define PLUTO_WLAN_WOW TEGRA_GPIO_PU5 -#define PLUTO_SD_CD TEGRA_GPIO_PV2 -#define WLAN_PWR_STR "wlan_power" -#define WLAN_WOW_STR "bcmsdh_sdmmc" -#if defined(CONFIG_BCMDHD_EDP_SUPPORT) -/* Wifi power levels */ -#define ON 1080 /* 1080 mW */ -#define OFF 0 -static unsigned int wifi_states[] = {ON, OFF}; -#endif - -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; -static int pluto_wifi_status_register(void (*callback)(int , void *), void *); - -static int pluto_wifi_reset(int on); -static int pluto_wifi_power(int on); -static int pluto_wifi_set_carddetect(int val); - -static struct wifi_platform_data pluto_wifi_control = { - .set_power = pluto_wifi_power, - .set_reset = pluto_wifi_reset, - .set_carddetect = pluto_wifi_set_carddetect, -}; - -static struct resource wifi_resource[] = { - [0] = { - .name = "bcm4329_wlan_irq", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - | IORESOURCE_IRQ_SHAREABLE, - }, -}; - -static struct platform_device pluto_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .num_resources = 1, - .resource = wifi_resource, - .dev = { - .platform_data = &pluto_wifi_control, - }, -}; - -#ifdef CONFIG_MMC_EMBEDDED_SDIO -static struct embedded_sdio_data embedded_sdio_data0 = { - .cccr = { - .sdio_vsn = 2, - .multi_block = 1, - .low_speed = 0, - .wide_bus = 0, - .high_power = 1, - .high_speed = 1, - }, - .cis = { - .vendor = 0x02d0, - .device = 0x4329, - }, -}; -#endif - -struct tegra_sdhci_platform_data pluto_tegra_sdhci_platform_data0 = { - .mmc_data = { - .register_status_notify = pluto_wifi_status_register, -#ifdef CONFIG_MMC_EMBEDDED_SDIO - .embedded_sdio = &embedded_sdio_data0, -#endif - .built_in = 0, - .ocr_mask = MMC_OCR_1V8_MASK, - }, -#ifndef CONFIG_MMC_EMBEDDED_SDIO - .pm_flags = MMC_PM_KEEP_POWER, -#endif - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x2, - .trim_delay = 0x2, - .ddr_clk_limit = 41000000, - .max_clk_limit = 82000000, - .uhs_mask = MMC_UHS_MASK_DDR50, - .disable_clock_gate = true, -}; - -static struct resource sdhci_resource0[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { - .cd_gpio = PLUTO_SD_CD, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x3, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, - .max_clk_limit = 156000000, - .uhs_mask = MMC_UHS_MASK_DDR50, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, - .tap_delay = 0x5, - .trim_delay = 0xA, - .ddr_trim_delay = -1, - .ddr_clk_limit = 41000000, - .max_clk_limit = 156000000, - .mmc_data = { - .built_in = 1, - .ocr_mask = MMC_OCR_1V8_MASK, - } -}; - -static struct platform_device tegra_sdhci_device0 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource0, - .num_resources = ARRAY_SIZE(sdhci_resource0), - .dev = { - .platform_data = &pluto_tegra_sdhci_platform_data0, - }, -}; - -static struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), - .dev = { - .platform_data = &tegra_sdhci_platform_data2, - }, -}; - -static struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), - .dev = { - .platform_data = &tegra_sdhci_platform_data3, - }, -}; - -static int pluto_wifi_status_register( - void (*callback)(int card_present, void *dev_id), - void *dev_id) -{ - if (wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -static int pluto_wifi_set_carddetect(int val) -{ - pr_debug("%s: %d\n", __func__, val); - if (wifi_status_cb) - wifi_status_cb(val, wifi_status_cb_devid); - else - pr_warning("%s: Nobody to notify\n", __func__); - return 0; -} - -static int pluto_wifi_power(int on) -{ - pr_debug("%s: %d\n", __func__, on); - - gpio_set_value(PLUTO_WLAN_PWR, on); - mdelay(100); - - return 0; -} - -static int pluto_wifi_reset(int on) -{ - pr_debug("%s: do nothing\n", __func__); - return 0; -} - -static int __init pluto_wifi_init(void) -{ - int rc = 0; - - /* init wlan_pwr gpio */ - rc = gpio_request(PLUTO_WLAN_PWR, WLAN_PWR_STR); - /* Due to pre powering, sometimes gpio req returns EBUSY */ - if ((rc < 0) && (rc != -EBUSY)) { - pr_err("Wifi init: gpio req failed:%d\n", rc); - return rc; - } - - /* Due to pre powering, sometimes gpio req returns EBUSY */ - rc = gpio_direction_output(PLUTO_WLAN_PWR, 0); - if ((rc < 0) && (rc != -EBUSY)) { - gpio_free(PLUTO_WLAN_PWR); - return rc; - } - /* init wlan_wow gpio */ - rc = gpio_request(PLUTO_WLAN_WOW, WLAN_WOW_STR); - if (rc < 0) { - pr_err("wifi init: gpio req failed:%d\n", rc); - gpio_free(PLUTO_WLAN_PWR); - return rc; - } - - rc = gpio_direction_input(PLUTO_WLAN_WOW); - if (rc < 0) { - gpio_free(PLUTO_WLAN_WOW); - gpio_free(PLUTO_WLAN_PWR); - return rc; - } - - wifi_resource[0].start = wifi_resource[0].end = - gpio_to_irq(PLUTO_WLAN_WOW); - - platform_device_register(&pluto_wifi_device); - return rc; -} - -#ifdef CONFIG_TEGRA_PREPOWER_WIFI -static int __init pluto_wifi_prepower(void) -{ - if (!machine_is_tegra_pluto()) - return 0; - - pluto_wifi_power(1); - - return 0; -} - -subsys_initcall_sync(pluto_wifi_prepower); -#endif - -int __init pluto_sdhci_init(void) -{ - int nominal_core_mv; - int min_vcore_override_mv; - int boot_vcore_mv; - - nominal_core_mv = - tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); - if (nominal_core_mv > 0) { - pluto_tegra_sdhci_platform_data0.nominal_vcore_mv = - nominal_core_mv; - tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv; - tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv; - } - min_vcore_override_mv = - tegra_dvfs_rail_get_override_floor(tegra_core_rail); - if (min_vcore_override_mv) { - pluto_tegra_sdhci_platform_data0.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data2.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data3.min_vcore_override_mv = - min_vcore_override_mv; - } - boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail); - if (boot_vcore_mv) { - pluto_tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv; - } - - if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200) - && (!(tegra_sdhci_platform_data3.uhs_mask & - MMC_UHS_MASK_DDR50))) - tegra_sdhci_platform_data3.trim_delay = 0; - platform_device_register(&tegra_sdhci_device3); - platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device0); - pluto_wifi_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-pluto-sensors.c b/arch/arm/mach-tegra/board-pluto-sensors.c deleted file mode 100644 index caf66f541986..000000000000 --- a/arch/arm/mach-tegra/board-pluto-sensors.c +++ /dev/null @@ -1,1031 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto-sensors.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ -#include <linux/i2c.h> -#include <linux/delay.h> -#include <linux/regulator/consumer.h> -#include <linux/gpio.h> -#include <linux/mpu.h> -#include <linux/max77665-charger.h> -#include <linux/mfd/max77665.h> -#include <linux/input/max77665-haptic.h> -#include <linux/power/max17042_battery.h> -#include <linux/power/power_supply_extcon.h> -#include <linux/nct1008.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <linux/pid_thermal_gov.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> -#include <mach/pinmux-t11.h> -#include <mach/pinmux.h> -#include <media/max77665-flash.h> -#ifndef CONFIG_OF -#include <media/imx091.h> -#include <media/imx132.h> -#include <media/ad5816.h> -#endif -#include <asm/mach-types.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-common.h" -#include "board-pluto.h" -#include "cpu-tegra.h" -#include "devices.h" -#include "tegra-board-id.h" -#include "dvfs.h" -#include "pm.h" -#include "battery-ini-model-data.h" - -#ifndef CONFIG_OF -static struct nvc_gpio_pdata imx091_gpio_pdata[] = { - {IMX091_GPIO_RESET, CAM_RSTN, true, false}, - {IMX091_GPIO_PWDN, CAM1_POWER_DWN_GPIO, true, false}, - {IMX091_GPIO_GP1, CAM_GPIO1, true, false} -}; -#endif - -static struct board_info board_info; - -static struct max17042_platform_data max17042_pdata = { - .config_data = &pluto_yoku_2000mA_max17042_battery, - .init_data = NULL, - .num_init_data = 0, - .enable_por_init = 1, /* Use POR init from Maxim appnote */ - .enable_current_sense = 1, - .r_sns = 0, - .is_battery_present = false, /* False as default */ -}; - -static struct i2c_board_info max17042_device[] = { - { - I2C_BOARD_INFO("max17042", 0x36), - .platform_data = &max17042_pdata, - }, -}; - -static struct nvc_torch_lumi_level_v1 pluto_max77665_lumi_tbl[] = { - {0, 100000}, - {1, 201690}, - {2, 298080}, - {3, 387700}, - {4, 479050}, - {5, 562000}, - {6, 652560}, - {7, 732150}, - {8, 816050}, - {9, 896710}, - {10, 976890}, - {11, 1070160}, - {12, 1151000}, - {13, 1227790}, - {14, 1287690}, - {15, 1375060}, -}; - -static struct max77665_f_platform_data pluto_max77665_flash_pdata = { - .config = { - .led_mask = 3, - /* set to true only when using the torch strobe input - * to trigger the flash. - */ - .flash_on_torch = false, - /* use ONE-SHOOT flash mode - flash triggered at the - * raising edge of strobe or strobe signal. - */ - .flash_mode = 1, - /* .flash_on_torch = true, */ - .max_total_current_mA = 1000, - .max_peak_current_mA = 600, - .max_flash_threshold_mV = 3400, - .max_flash_hysteresis_mV = 200, - .max_flash_lbdly_f_uS = 256, - .max_flash_lbdly_r_uS = 256, - .led_config[0] = { - .flash_torch_ratio = 18100, - .granularity = 1000, - .flash_levels = ARRAY_SIZE(pluto_max77665_lumi_tbl), - .lumi_levels = pluto_max77665_lumi_tbl, - }, - .led_config[1] = { - .flash_torch_ratio = 18100, - .granularity = 1000, - .flash_levels = ARRAY_SIZE(pluto_max77665_lumi_tbl), - .lumi_levels = pluto_max77665_lumi_tbl, - }, - }, - .pinstate = { - .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0), - .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0), - }, - .dev_name = "torch", - .gpio_strobe = CAM_FLASH_STROBE, -}; - -static struct max77665_haptic_platform_data max77665_haptic_pdata = { - .pwm_channel_id = 2, - .pwm_period = 50, - .type = MAX77665_HAPTIC_LRA, - .mode = MAX77665_INTERNAL_MODE, - .internal_mode_pattern = 0, - .pattern_cycle = 10, - .pattern_signal_period = 0xD0, - .pwm_divisor = MAX77665_PWM_DIVISOR_128, - .feedback_duty_cycle = 12, - .invert = MAX77665_INVERT_OFF, - .cont_mode = MAX77665_CONT_MODE, - .motor_startup_val = 0, - .scf_val = 2, -}; - -static struct max77665_charger_cable maxim_cable[] = { - { - .name = "USB", - }, - { - .name = "USB-Host", - }, - { - .name = "TA", - }, - { - .name = "Fast-charger", - }, - { - .name = "Slow-charger", - }, - { - .name = "Charge-downstream", - }, -}; - -static struct regulator_consumer_supply max77665_charger_supply[] = { - REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"), -}; - -static struct max77665_charger_plat_data max77665_charger = { - .fast_chg_cc = 1500, /* fast charger current*/ - .term_volt = 3700, /* charger termination voltage */ - .curr_lim = 1500, /* input current limit */ - .num_cables = MAX_CABLES, - .cables = maxim_cable, - .extcon_name = "tegra-udc", - .is_battery_present = false, /* false as default */ - .consumer_supplies = max77665_charger_supply, - .num_consumer_supplies = ARRAY_SIZE(max77665_charger_supply), -}; - -static struct max77665_muic_platform_data max77665_muic = { - .ext_conn_name = "MAX77665_MUIC_ID", -}; - -struct max77665_system_interrupt max77665_sys_int = { - .enable_thermal_interrupt = true, - .enable_low_sys_interrupt = true, -}; - -static struct max77665_platform_data pluto_max77665_pdata = { - .irq_base = MAX77665_TEGRA_IRQ_BASE, - .irq_flag = IRQF_ONESHOT | IRQF_TRIGGER_FALLING, - .system_interrupt = &max77665_sys_int, - .muic_platform_data = { - .pdata = &max77665_muic, - .size = sizeof(max77665_muic), - }, - .charger_platform_data = { - .pdata = &max77665_charger, - .size = sizeof(max77665_charger), - }, - .flash_platform_data = { - .pdata = &pluto_max77665_flash_pdata, - .size = sizeof(pluto_max77665_flash_pdata), - }, - .haptic_platform_data = { - .pdata = &max77665_haptic_pdata, - .size = sizeof(max77665_haptic_pdata), - }, -}; - -static struct i2c_board_info pluto_i2c_board_info_max77665[] = { - { - I2C_BOARD_INFO("max77665", 0x66), - .platform_data = &pluto_max77665_pdata, - .irq = (TEGRA_SOC_OC_IRQ_BASE + TEGRA_SOC_OC_IRQ_4), - }, -}; - -static struct power_supply_extcon_plat_data psy_extcon_pdata = { - .extcon_name = "tegra-udc", -}; - -static struct platform_device psy_extcon_device = { - .name = "power-supply-extcon", - .id = -1, - .dev = { - .platform_data = &psy_extcon_pdata, - }, -}; - - -/* isl29029 support is provided by isl29028*/ -static struct i2c_board_info pluto_i2c1_isl_board_info[] = { - { - I2C_BOARD_INFO("isl29028", 0x44), - } -}; - -static struct throttle_table tj_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle tj_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_throttle_table), - .throt_tab = tj_throttle_table, -}; - -static int __init pluto_throttle_init(void) -{ - if (machine_is_tegra_pluto()) - balanced_throttle_register(&tj_throttle, "tegra-balanced"); - return 0; -} -module_init(pluto_throttle_init); - -static struct nct1008_platform_data pluto_nct1008_pdata = { - .supported_hwrev = true, - .extended_range = true, - .conv_rate = 0x06, /* 4Hz conversion rate */ - - .sensors = { - [LOC] = { - .shutdown_limit = 120, /* C */ - .num_trips = 0, - .tzp = NULL, - }, - [EXT] = { - .shutdown_limit = 105, /* C */ - .num_trips = 1, - .tzp = NULL, - .trips = { - { - .cdev_type = "suspend_soctherm", - .trip_temp = 50000, - .trip_type = THERMAL_TRIP_ACTIVE, - .upper = 1, - .lower = 1, - .hysteresis = 5000, - .mask = 1, - }, - }, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .suspend_limit_hi = 25000, - .suspend_limit_lo = 20000, -#endif - } - }, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .suspend_with_wakeup = tegra_is_lp1_suspend_mode, -#endif -}; - -static struct i2c_board_info pluto_i2c4_nct1008_board_info[] = { - { - I2C_BOARD_INFO("nct1008", 0x4C), - .platform_data = &pluto_nct1008_pdata, - .irq = -1, - } -}; - -#ifndef CONFIG_OF -#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ - { \ - .pingroup = TEGRA_PINGROUP_##_pingroup, \ - .func = TEGRA_MUX_##_mux, \ - .pupd = TEGRA_PUPD_##_pupd, \ - .tristate = TEGRA_TRI_##_tri, \ - .io = TEGRA_PIN_##_io, \ - .lock = TEGRA_PIN_LOCK_##_lock, \ - .od = TEGRA_PIN_OD_DEFAULT, \ - .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ -} - -static int pluto_focuser_power_on(struct ad5816_power_rail *pw) -{ - int err; - - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - err = regulator_enable(pw->vdd_i2c); - if (unlikely(err)) - goto ad5816_vdd_i2c_fail; - - err = regulator_enable(pw->vdd); - if (unlikely(err)) - goto ad5816_vdd_fail; - - return 0; - -ad5816_vdd_fail: - regulator_disable(pw->vdd_i2c); - -ad5816_vdd_i2c_fail: - pr_err("%s FAILED\n", __func__); - - return -ENODEV; -} - -static int pluto_focuser_power_off(struct ad5816_power_rail *pw) -{ - if (unlikely(WARN_ON(!pw || !pw->vdd || !pw->vdd_i2c))) - return -EFAULT; - - regulator_disable(pw->vdd); - regulator_disable(pw->vdd_i2c); - - return 0; -} - -static struct tegra_pingroup_config mclk_disable = - VI_PINMUX(CAM_MCLK, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config mclk_enable = - VI_PINMUX(CAM_MCLK, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_disable = - VI_PINMUX(GPIO_PBB0, VI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -static struct tegra_pingroup_config pbb0_enable = - VI_PINMUX(GPIO_PBB0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT); - -/* - * more regulators need to be allocated to activate the sensor devices. - * pluto_vcmvdd: this is a workaround due to the focuser device(AD5816) will - * hook up the i2c bus if it is not powered up. - * pluto_i2cvdd: by default, the power supply on the i2c bus is OFF. So it - * should be turned on every time any sensor device is activated. -*/ -static struct regulator *pluto_vcmvdd; -static struct regulator *pluto_i2cvdd; - -static int pluto_get_extra_regulators(void) -{ - if (!pluto_vcmvdd) { - pluto_vcmvdd = regulator_get(NULL, "vdd_af_cam1"); - if (WARN_ON(IS_ERR(pluto_vcmvdd))) { - pr_err("%s: can't get regulator vdd_af_cam1: %ld\n", - __func__, PTR_ERR(pluto_vcmvdd)); - pluto_vcmvdd = NULL; - return -ENODEV; - } - } - - if (!pluto_i2cvdd) { - pluto_i2cvdd = regulator_get(NULL, "vddio_cam_mb"); - if (unlikely(WARN_ON(IS_ERR(pluto_i2cvdd)))) { - pr_err("%s: can't get regulator vddio_cam_mb: %ld\n", - __func__, PTR_ERR(pluto_i2cvdd)); - pluto_i2cvdd = NULL; - return -ENODEV; - } - } - - return 0; -} - -static int pluto_imx091_power_on(struct nvc_regulator *vreg) -{ - int err; - - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - if (pluto_get_extra_regulators()) - goto imx091_poweron_fail; - - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(10, 20); - - err = regulator_enable(vreg[IMX091_VREG_AVDD].vreg); - if (unlikely(err)) - goto imx091_avdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_DVDD].vreg); - if (unlikely(err)) - goto imx091_dvdd_fail; - - err = regulator_enable(vreg[IMX091_VREG_IOVDD].vreg); - if (unlikely(err)) - goto imx091_iovdd_fail; - - usleep_range(1, 2); - gpio_set_value(CAM1_POWER_DWN_GPIO, 1); - - tegra_pinmux_config_table(&mclk_enable, 1); - err = regulator_enable(pluto_i2cvdd); - if (unlikely(err)) - goto imx091_i2c_fail; - - err = regulator_enable(pluto_vcmvdd); - if (unlikely(err)) - goto imx091_vcm_fail; - usleep_range(300, 310); - - return 1; - -imx091_vcm_fail: - regulator_disable(pluto_i2cvdd); - -imx091_i2c_fail: - tegra_pinmux_config_table(&mclk_disable, 1); - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - -imx091_iovdd_fail: - regulator_disable(vreg[IMX091_VREG_DVDD].vreg); - -imx091_dvdd_fail: - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - -imx091_avdd_fail: -imx091_poweron_fail: - pr_err("%s FAILED\n", __func__); - return -ENODEV; -} - -static int pluto_imx091_power_off(struct nvc_regulator *vreg) -{ - if (unlikely(WARN_ON(!vreg))) - return -EFAULT; - - usleep_range(1, 2); - tegra_pinmux_config_table(&mclk_disable, 1); - gpio_set_value(CAM1_POWER_DWN_GPIO, 0); - usleep_range(1, 2); - - regulator_disable(vreg[IMX091_VREG_IOVDD].vreg); - regulator_disable(vreg[IMX091_VREG_DVDD].vreg); - regulator_disable(vreg[IMX091_VREG_AVDD].vreg); - if (pluto_i2cvdd) - regulator_disable(pluto_i2cvdd); - if (pluto_vcmvdd) - regulator_disable(pluto_vcmvdd); - - return 0; -} - -static struct nvc_imager_cap imx091_cap = { - .identifier = "IMX091", - .sensor_nvc_interface = 3, - .pixel_types[0] = 0x100, - .orientation = 0, - .direction = 0, - .initial_clock_rate_khz = 6000, - .clock_profiles[0] = { - .external_clock_khz = 24000, - .clock_multiplier = 850000, /* value / 1,000,000 */ - }, - .clock_profiles[1] = { - .external_clock_khz = 0, - .clock_multiplier = 0, - }, - .h_sync_edge = 0, - .v_sync_edge = 0, - .mclk_on_vgp0 = 0, - .csi_port = 0, - .data_lanes = 4, - .virtual_channel_id = 0, - .discontinuous_clk_mode = 1, - .cil_threshold_settle = 0x0, - .min_blank_time_width = 16, - .min_blank_time_height = 16, - .preferred_mode_index = 0, - .focuser_guid = NVC_FOCUS_GUID(0), - .torch_guid = NVC_TORCH_GUID(0), - .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2, -}; - -static struct imx091_platform_data imx091_pdata = { - .num = 0, - .sync = 0, - .dev_name = "camera", - .gpio_count = ARRAY_SIZE(imx091_gpio_pdata), - .gpio = imx091_gpio_pdata, - .flash_cap = { - .sdo_trigger_enabled = 1, - .adjustable_flash_timing = 1, - }, - .cap = &imx091_cap, - .power_on = pluto_imx091_power_on, - .power_off = pluto_imx091_power_off, -}; - -static int pluto_imx132_power_on(struct imx132_power_rail *pw) -{ - int err; - - if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd))) - return -EFAULT; - - if (pluto_get_extra_regulators()) - goto pluto_imx132_poweron_fail; - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - - tegra_pinmux_config_table(&pbb0_enable, 1); - - err = regulator_enable(pluto_i2cvdd); - if (unlikely(err)) - goto imx132_i2c_fail; - - err = regulator_enable(pluto_vcmvdd); - if (unlikely(err)) - goto imx132_vcm_fail; - - err = regulator_enable(pw->avdd); - if (unlikely(err)) - goto imx132_avdd_fail; - - err = regulator_enable(pw->dvdd); - if (unlikely(err)) - goto imx132_dvdd_fail; - - err = regulator_enable(pw->iovdd); - if (unlikely(err)) - goto imx132_iovdd_fail; - - usleep_range(1, 2); - - gpio_set_value(CAM2_POWER_DWN_GPIO, 1); - - return 0; - -imx132_iovdd_fail: - regulator_disable(pw->dvdd); - -imx132_dvdd_fail: - regulator_disable(pw->avdd); - -imx132_avdd_fail: - regulator_disable(pluto_vcmvdd); - -imx132_vcm_fail: - regulator_disable(pluto_i2cvdd); - -imx132_i2c_fail: - tegra_pinmux_config_table(&pbb0_disable, 1); - -pluto_imx132_poweron_fail: - pr_err("%s failed.\n", __func__); - return -ENODEV; -} - -static int pluto_imx132_power_off(struct imx132_power_rail *pw) -{ - if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd || - !pluto_i2cvdd || !pluto_vcmvdd))) - return -EFAULT; - - gpio_set_value(CAM2_POWER_DWN_GPIO, 0); - - usleep_range(1, 2); - - regulator_disable(pw->iovdd); - regulator_disable(pw->dvdd); - regulator_disable(pw->avdd); - - tegra_pinmux_config_table(&pbb0_disable, 1); - - regulator_disable(pluto_vcmvdd); - regulator_disable(pluto_i2cvdd); - - return 0; -} - -struct imx132_platform_data imx132_pdata = { - .power_on = pluto_imx132_power_on, - .power_off = pluto_imx132_power_off, -}; - -static struct ad5816_platform_data pluto_ad5816_pdata = { - .cfg = 0, - .num = 0, - .sync = 0, - .dev_name = "focuser", - .power_on = pluto_focuser_power_on, - .power_off = pluto_focuser_power_off, -}; - -static struct i2c_board_info pluto_i2c_board_info_e1625[] = { - { - I2C_BOARD_INFO("imx091", 0x10), - .platform_data = &imx091_pdata, - }, - { - I2C_BOARD_INFO("imx132", 0x36), - .platform_data = &imx132_pdata, - }, - { - I2C_BOARD_INFO("ad5816", 0x0E), - .platform_data = &pluto_ad5816_pdata, - }, -}; - -static int pluto_camera_init(void) -{ - pr_debug("%s: ++\n", __func__); - - tegra_pinmux_config_table(&mclk_disable, 1); - tegra_pinmux_config_table(&pbb0_disable, 1); - i2c_register_board_info(2, pluto_i2c_board_info_e1625, - ARRAY_SIZE(pluto_i2c_board_info_e1625)); - - return 0; -} -#endif - -/* MPU board file definition */ -static struct mpu_platform_data mpu_gyro_data = { - .int_config = 0x00, - .level_shifter = 0, - .orientation = MPU_GYRO_ORIENTATION, - .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE, - .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22, - 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89}, -}; - -static struct mpu_platform_data mpu_compass_data = { - .orientation = MPU_COMPASS_ORIENTATION, - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct mpu_platform_data bmp180_pdata = { - .config = NVI_CONFIG_BOOT_MPU, -}; - -static struct i2c_board_info __initdata inv_mpu_i2c0_board_info[] = { - { - I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR), - .platform_data = &mpu_gyro_data, - }, - { - /* The actual BMP180 address is 0x77 but because this conflicts - * with another device, this address is hacked so Linux will - * call the driver. The conflict is technically okay since the - * BMP180 is behind the MPU. Also, the BMP180 driver uses a - * hard-coded address of 0x77 since it can't be changed anyway. - */ - I2C_BOARD_INFO("bmp180", 0x78), - .platform_data = &bmp180_pdata, - }, - { - I2C_BOARD_INFO(MPU_COMPASS_NAME, MPU_COMPASS_ADDR), - .platform_data = &mpu_compass_data, - }, -}; - -static void mpuirq_init(void) -{ - int ret = 0; - int i = 0; - - pr_info("*** MPU START *** mpuirq_init...\n"); - - /* MPU-IRQ assignment */ - ret = gpio_request(MPU_GYRO_IRQ_GPIO, MPU_GYRO_NAME); - if (ret < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, ret); - return; - } - - ret = gpio_direction_input(MPU_GYRO_IRQ_GPIO); - if (ret < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, ret); - gpio_free(MPU_GYRO_IRQ_GPIO); - return; - } - pr_info("*** MPU END *** mpuirq_init...\n"); - - inv_mpu_i2c0_board_info[i++].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO); -#if MPU_COMPASS_IRQ_GPIO - inv_mpu_i2c0_board_info[i++].irq = gpio_to_irq(MPU_COMPASS_IRQ_GPIO); -#endif - i2c_register_board_info(MPU_GYRO_BUS_NUM, inv_mpu_i2c0_board_info, - ARRAY_SIZE(inv_mpu_i2c0_board_info)); -} - -static int pluto_nct1008_init(void) -{ - int nct1008_port; - int ret = 0; - - if (board_info.board_id == BOARD_E1580 || - board_info.board_id == BOARD_E1575 || - board_info.board_id == BOARD_E1577) { - nct1008_port = TEGRA_GPIO_PX6; - } else { - nct1008_port = TEGRA_GPIO_PX6; - pr_err("Warning: nct alert port assumed TEGRA_GPIO_PX6 for unknown pluto board id E%d\n", - board_info.board_id); - } - - tegra_add_all_vmin_trips(pluto_nct1008_pdata.sensors[EXT].trips, - &pluto_nct1008_pdata.sensors[EXT].num_trips); - - pluto_i2c4_nct1008_board_info[0].irq = - gpio_to_irq(nct1008_port); - pr_info("%s: pluto nct1008 irq %d", - __func__, pluto_i2c4_nct1008_board_info[0].irq); - - ret = gpio_request(nct1008_port, "temp_alert"); - if (ret < 0) - return ret; - - ret = gpio_direction_input(nct1008_port); - if (ret < 0) { - pr_info("%s: calling gpio_free(nct1008_port)", __func__); - gpio_free(nct1008_port); - } - - /* pluto has thermal sensor on GEN1-I2C i.e. instance 0 */ - i2c_register_board_info(0, pluto_i2c4_nct1008_board_info, - ARRAY_SIZE(pluto_i2c4_nct1008_board_info)); - - return ret; -} - -#ifdef CONFIG_TEGRA_SKIN_THROTTLE -static struct thermal_trip_info skin_trips[] = { - { - .cdev_type = "skin-balanced", - .trip_temp = 43000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 57000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, -}; - -static struct therm_est_subdevice skin_devs[] = { - { - .dev_data = "Tdiode", - .coeffs = { - 2, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 0, - 1, 1, 0, 0, - 0, 0, -1, -7 - }, - }, - { - .dev_data = "Tboard", - .coeffs = { - -11, -7, -5, -3, - -3, -2, -1, 0, - 0, 0, 1, 1, - 1, 2, 2, 3, - 4, 6, 11, 18 - }, - }, -}; - -static struct pid_thermal_gov_params skin_pid_params = { - .max_err_temp = 4000, - .max_err_gain = 1000, - - .gain_p = 1000, - .gain_d = 0, - - .up_compensation = 15, - .down_compensation = 15, -}; - -static struct thermal_zone_params skin_tzp = { - .governor_name = "pid_thermal_gov", - .governor_params = &skin_pid_params, -}; - -static struct therm_est_data skin_data = { - .num_trips = ARRAY_SIZE(skin_trips), - .trips = skin_trips, - .toffset = 9793, - .polling_period = 1100, - .passive_delay = 15000, - .tc1 = 10, - .tc2 = 1, - .ndevs = ARRAY_SIZE(skin_devs), - .devs = skin_devs, - .tzp = &skin_tzp, -}; - -static struct throttle_table skin_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle skin_throttle = { - .throt_tab_size = ARRAY_SIZE(skin_throttle_table), - .throt_tab = skin_throttle_table, -}; - -static int __init pluto_skin_init(void) -{ - if (machine_is_tegra_pluto()) { - balanced_throttle_register(&skin_throttle, "skin-balanced"); - tegra_skin_therm_est_device.dev.platform_data = &skin_data; - platform_device_register(&tegra_skin_therm_est_device); - } - - return 0; -} -late_initcall(pluto_skin_init); -#endif - -void __init max77665_init(void) -{ - int err; - - /* For battery presence into charger driver */ - if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) - max77665_charger.is_battery_present = true; - - err = i2c_register_board_info(4, pluto_i2c_board_info_max77665, - ARRAY_SIZE(pluto_i2c_board_info_max77665)); - if (err) - pr_err("%s: max77665 device register failed.\n", __func__); - - platform_device_register(&psy_extcon_device); - - return; -} - -int __init pluto_sensors_init(void) -{ - int err; - - tegra_get_board_info(&board_info); - - pr_debug("%s: ++\n", __func__); - -#ifndef CONFIG_OF - pluto_camera_init(); -#endif - err = pluto_nct1008_init(); - if (err) - return err; - - err = i2c_register_board_info(0, pluto_i2c1_isl_board_info, - ARRAY_SIZE(pluto_i2c1_isl_board_info)); - if (err) - pr_err("%s: isl board register failed.\n", __func__); - - mpuirq_init(); - max77665_init(); - - if (get_power_supply_type() == POWER_SUPPLY_TYPE_BATTERY) - max17042_pdata.is_battery_present = true; - - err = i2c_register_board_info(0, max17042_device, - ARRAY_SIZE(max17042_device)); - if (err) - pr_err("%s: max17042 device register failed.\n", __func__); - - - return 0; -} diff --git a/arch/arm/mach-tegra/board-pluto.c b/arch/arm/mach-tegra/board-pluto.c deleted file mode 100644 index 92ebc053da8f..000000000000 --- a/arch/arm/mach-tegra/board-pluto.c +++ /dev/null @@ -1,1297 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ctype.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/i2c-tegra.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_data/tegra_usb.h> -#include <linux/spi/spi.h> -#include <linux/spi/rm31080a_ts.h> -#include <linux/platform_data/serial-tegra.h> -#include <linux/memblock.h> -#include <linux/spi/spi-tegra.h> -#include <linux/nfc/pn544.h> -#include <linux/nfc/bcm2079x.h> -#include <linux/rfkill-gpio.h> -#include <linux/skbuff.h> -#include <linux/ti_wilink_st.h> -#include <linux/regulator/consumer.h> -#include <linux/smb349-charger.h> -#include <linux/max17048_battery.h> -#include <linux/leds.h> -#include <linux/i2c/at24.h> -#include <linux/mfd/max8831.h> -#include <linux/of_platform.h> -#include <linux/a2220.h> -#include <linux/mfd/tlv320aic3262-registers.h> -#include <linux/mfd/tlv320aic3xxx-core.h> -#include <linux/usb/tegra_usb_phy.h> -#include <linux/clk/tegra.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> -#include <linux/tegra_fiq_debugger.h> -#include <linux/platform_data/tegra_usb_modem_power.h> - -#include <mach/irqs.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <mach/io_dpd.h> -#include <mach/i2s.h> -#include <mach/isomgr.h> -#include <mach/tegra_asoc_pdata.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/gpio-tegra.h> -#include <mach/tegra-bb-power.h> -#include <mach/tegra_wakeup_monitor.h> -#include <mach/xusb.h> -#include <media/tegra_dtv.h> - -#include "board.h" -#include "board-common.h" -#include "board-touch.h" -#include "board-touch-raydium.h" -#include "clock.h" -#include "board-pluto.h" -#include "baseband-xmm-power.h" -#include "tegra-board-id.h" -#include "devices.h" -#include "gpio-names.h" -#include "pm.h" -#include "common.h" -#include "iomap.h" -#include "tegra-of-dev-auxdata.h" - - -#ifdef CONFIG_BT_BLUESLEEP -static struct rfkill_gpio_platform_data pluto_bt_rfkill_pdata = { - .name = "bt_rfkill", - .shutdown_gpio = TEGRA_GPIO_PQ7, - .reset_gpio = TEGRA_GPIO_PQ6, - .type = RFKILL_TYPE_BLUETOOTH, -}; - -static struct platform_device pluto_bt_rfkill_device = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &pluto_bt_rfkill_pdata, - }, -}; - -static noinline void __init pluto_setup_bt_rfkill(void) -{ - platform_device_register(&pluto_bt_rfkill_device); -} - -static struct resource pluto_bluesleep_resources[] = { - [0] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [2] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device pluto_bluesleep_device = { - .name = "bluesleep", - .id = -1, - .num_resources = ARRAY_SIZE(pluto_bluesleep_resources), - .resource = pluto_bluesleep_resources, -}; - -static noinline void __init pluto_setup_bluesleep(void) -{ - pluto_bluesleep_resources[2].start = - pluto_bluesleep_resources[2].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&pluto_bluesleep_device); - return; -} -#elif defined CONFIG_BLUEDROID_PM -static struct resource pluto_bluedroid_pm_resources[] = { - [0] = { - .name = "shutdown_gpio", - .start = TEGRA_GPIO_PQ7, - .end = TEGRA_GPIO_PQ7, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, - [2] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [3] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [4] = { - .name = "reset_gpio", - .start = TEGRA_GPIO_PQ6, - .end = TEGRA_GPIO_PQ6, - .flags = IORESOURCE_IO, - }, -}; - -static struct platform_device pluto_bluedroid_pm_device = { - .name = "bluedroid_pm", - .id = 0, - .num_resources = ARRAY_SIZE(pluto_bluedroid_pm_resources), - .resource = pluto_bluedroid_pm_resources, -}; - -static noinline void __init pluto_setup_bluedroid_pm(void) -{ - pluto_bluedroid_pm_resources[1].start = - pluto_bluedroid_pm_resources[1].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&pluto_bluedroid_pm_device); -} -#endif - -static __initdata struct tegra_clk_init_table pluto_clk_init_table[] = { - /* name parent rate enabled */ - { "pll_m", NULL, 0, false}, - { "hda", "pll_p", 108000000, false}, - { "hda2codec_2x", "pll_p", 48000000, false}, - { "pwm", "pll_p", 3187500, false}, - { "i2s1", "pll_a_out0", 0, false}, - { "i2s2", "pll_a_out0", 0, false}, - { "i2s3", "pll_a_out0", 0, false}, - { "i2s4", "pll_a_out0", 0, false}, - { "spdif_out", "pll_a_out0", 0, false}, - { "d_audio", "clk_m", 12000000, false}, - { "dam0", "clk_m", 12000000, false}, - { "dam1", "clk_m", 12000000, false}, - { "dam2", "clk_m", 12000000, false}, - { "audio0", "i2s0_sync", 0, false}, - { "audio1", "i2s1_sync", 0, false}, - { "audio2", "i2s2_sync", 0, false}, - { "audio3", "i2s3_sync", 0, false}, - { "audio4", "i2s4_sync", 0, false}, - { "vi_sensor", "pll_p", 150000000, false}, - { "cilab", "pll_p", 150000000, false}, - { "cilcd", "pll_p", 150000000, false}, - { "cile", "pll_p", 150000000, false}, - { "i2c1", "pll_p", 3200000, false}, - { "i2c2", "pll_p", 3200000, false}, - { "i2c3", "pll_p", 3200000, false}, - { "i2c4", "pll_p", 3200000, false}, - { "i2c5", "pll_p", 3200000, false}, - { "sbc1", "pll_p", 25000000, false}, - { "sbc2", "pll_p", 25000000, false}, - { "sbc3", "pll_p", 25000000, false}, - { "sbc4", "pll_p", 25000000, false}, - { "sbc5", "pll_p", 25000000, false}, - { "sbc6", "pll_p", 25000000, false}, - { "extern3", "clk_m", 12000000, false}, - { "dsia", "pll_d2_out0", 0, false}, - { "uarta", "pll_p", 408000000, false}, - { "uartb", "pll_p", 408000000, false}, - { "uartc", "pll_p", 408000000, false}, - { "uartd", "pll_p", 408000000, false}, - { NULL, NULL, 0, 0}, -}; - -static struct bcm2079x_platform_data nfc_pdata = { - .irq_gpio = TEGRA_GPIO_PW2, - .en_gpio = TEGRA_GPIO_PU4, - .wake_gpio = TEGRA_GPIO_PX7, - }; - -static struct i2c_board_info __initdata pluto_i2c_bus3_board_info[] = { - { - I2C_BOARD_INFO("bcm2079x-i2c", 0x77), - .platform_data = &nfc_pdata, - }, -}; - -static struct aic3262_gpio_setup aic3262_gpio[] = { - /* GPIO 1*/ - { - .used = 1, - .in = 0, - .value = AIC3262_GPIO1_FUNC_INT1_OUTPUT , - }, - /* GPIO 2*/ - { - .used = 1, - .in = 0, - .value = AIC3262_GPIO2_FUNC_ADC_MOD_CLK_OUTPUT, - }, - /* GPI1 */ - { - .used = 1, - .in = 1, - }, - /* GPI2 */ - { - .used = 1, - .in = 1, - .in_reg = AIC3262_DMIC_INPUT_CNTL, - .in_reg_bitmask = AIC3262_DMIC_CONFIGURE_MASK, - .in_reg_shift = AIC3262_DMIC_CONFIGURE_SHIFT, - .value = AIC3262_DMIC_GPI2_LEFT_GPI2_RIGHT, - }, - /* GPO1 */ - { - .used = 1, - .in = 0, - .value = AIC3262_GPO1_FUNC_MSO_OUTPUT_FOR_SPI, - }, -}; -static struct aic3xxx_pdata aic3262_codec_pdata = { - .gpio_irq = 0, - .gpio = aic3262_gpio, - .naudint_irq = 0, - .irq_base = AIC3262_CODEC_IRQ_BASE, -}; - -static struct i2c_board_info __initdata cs42l73_board_info = { - I2C_BOARD_INFO("cs42l73", 0x4a), -}; - -static struct i2c_board_info __initdata pluto_codec_a2220_info = { - I2C_BOARD_INFO("audience_a2220", 0x3E), -}; - -static struct i2c_board_info __initdata pluto_codec_aic326x_info = { - I2C_BOARD_INFO("tlv320aic3262", 0x18), - .platform_data = &aic3262_codec_pdata, -}; - -static void pluto_i2c_init(void) -{ - pluto_i2c_bus3_board_info[0].irq = gpio_to_irq(TEGRA_GPIO_PW2); - i2c_register_board_info(0, pluto_i2c_bus3_board_info, 1); - i2c_register_board_info(0, &pluto_codec_aic326x_info, 1); - i2c_register_board_info(0, &pluto_codec_a2220_info, 1); - i2c_register_board_info(0, &cs42l73_board_info, 1); -} - -static struct tegra_serial_platform_data pluto_uartd_pdata = { - .dma_req_selector = 19, - .modem_interrupt = false, -}; - -static void __init pluto_uart_init(void) -{ - int debug_port_id; - - /* Register low speed only if it is selected */ - if (!is_tegra_debug_uartport_hs()) { - debug_port_id = uart_console_debug_init(3); - if (debug_port_id < 0) - return; - - platform_device_register(uart_console_debug_device); - - } else { - tegra_uartd_device.dev.platform_data = &pluto_uartd_pdata; - platform_device_register(&tegra_uartd_device); - } - -} - -static struct resource tegra_rtc_resources[] = { - [0] = { - .start = TEGRA_RTC_BASE, - .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_RTC, - .end = INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tegra_rtc_device = { - .name = "tegra_rtc", - .id = -1, - .resource = tegra_rtc_resources, - .num_resources = ARRAY_SIZE(tegra_rtc_resources), -}; - -#if defined(CONFIG_TEGRA_WAKEUP_MONITOR) -static struct tegra_wakeup_monitor_platform_data - pluto_tegra_wakeup_monitor_pdata = { - .wifi_wakeup_source = 6, - .rtc_wakeup_source = 18, -}; - -static struct platform_device pluto_tegra_wakeup_monitor_device = { - .name = "tegra_wakeup_monitor", - .id = -1, - .dev = { - .platform_data = &pluto_tegra_wakeup_monitor_pdata, - }, -}; -#endif - -static struct tegra_asoc_platform_data pluto_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 0, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .channels = 2, - }, - .i2s_param[BASEBAND] = { - .audio_port_id = 2, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .rate = 16000, - .channels = 2, - .bit_clk = 1024000, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - .sample_size = 16, - .channels = 1, - .bit_clk = 512000, - }, - .i2s_param[VOICE_CODEC] = { - .audio_port_id = 0, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .rate = 16000, - .channels = 2, - }, -}; - -static struct tegra_asoc_platform_data pluto_aic3262_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 0, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .rate = 48000, - .channels = 2, - }, - .i2s_param[BASEBAND] = { - .audio_port_id = 2, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .rate = 16000, - .channels = 2, - .bit_clk = 1024000, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - .sample_size = 16, - .channels = 1, - .bit_clk = 512000, - }, - .i2s_param[VOICE_CODEC] = { - .audio_port_id = 0, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - .sample_size = 16, - .rate = 16000, - .channels = 2, - }, -}; - -static struct platform_device pluto_audio_device = { - .name = "tegra-snd-cs42l73", - .id = 2, - .dev = { - .platform_data = &pluto_audio_pdata, - }, -}; - -static struct platform_device pluto_audio_aic326x_device = { - .name = "tegra-snd-aic326x", - .id = 2, - .dev = { - .platform_data = &pluto_aic3262_pdata, - }, -}; - -static struct tegra_spi_device_controller_data dev_bdata = { - .rx_clk_tap_delay = 0, - .tx_clk_tap_delay = 0, -}; -static struct spi_board_info aic326x_spi_board_info[] = { - { - .modalias = "tlv320aic3xxx", - .bus_num = 3, - .chip_select = 0, - .max_speed_hz = 4*1000*1000, - .mode = SPI_MODE_1, - .controller_data = &dev_bdata, - .platform_data = &aic3262_codec_pdata, - }, -}; - -#ifdef CONFIG_MHI_NETDEV -struct platform_device mhi_netdevice0 = { - .name = "mhi_net_device", - .id = 0, -}; -#endif /* CONFIG_MHI_NETDEV */ - -static struct platform_device *pluto_devices[] __initdata = { - &tegra_pmu_device, - &tegra_rtc_device, - &tegra_udc_device, -#if defined(CONFIG_TEGRA_WATCHDOG) - &tegra_wdt0_device, -#endif -#if defined(CONFIG_TEGRA_AVP) - &tegra_avp_device, -#endif -#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) - &tegra11_se_device, -#endif - &tegra_ahub_device, - &tegra_dam_device0, - &tegra_dam_device1, - &tegra_dam_device2, - &tegra_i2s_device0, - &tegra_i2s_device1, - &tegra_i2s_device2, - &tegra_i2s_device3, - &tegra_i2s_device4, - &tegra_spdif_device, - &spdif_dit_device, - &pluto_audio_aic326x_device, - &bluetooth_dit_device, - &baseband_dit_device, -#if defined(CONFIG_TEGRA_WAKEUP_MONITOR) - &pluto_tegra_wakeup_monitor_device, -#endif - &pluto_audio_device, - &tegra_hda_device, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) - &tegra_aes_device, -#endif -#ifdef CONFIG_MHI_NETDEV - &mhi_netdevice0, /* MHI netdevice */ -#endif /* CONFIG_MHI_NETDEV */ -}; - -#ifdef CONFIG_USB_SUPPORT - -static void pluto_usb_hsic_postsupend(void) -{ - pr_debug("%s\n", __func__); -#ifdef CONFIG_TEGRA_BB_XMM_POWER - baseband_xmm_set_power_status(BBXMM_PS_L2); -#endif -} - -static void pluto_usb_hsic_preresume(void) -{ - pr_debug("%s\n", __func__); -#ifdef CONFIG_TEGRA_BB_XMM_POWER - baseband_xmm_set_power_status(BBXMM_PS_L2TOL0); -#endif -} - -static void pluto_usb_hsic_post_resume(void) -{ - pr_debug("%s\n", __func__); -#ifdef CONFIG_TEGRA_BB_XMM_POWER - baseband_xmm_set_power_status(BBXMM_PS_L0); -#endif -} - -static void pluto_usb_hsic_phy_power(void) -{ - pr_debug("%s\n", __func__); -#ifdef CONFIG_TEGRA_BB_XMM_POWER - baseband_xmm_set_power_status(BBXMM_PS_L0); -#endif -} - -static void pluto_usb_hsic_post_phy_off(void) -{ - pr_debug("%s\n", __func__); -#ifdef CONFIG_TEGRA_BB_XMM_POWER - baseband_xmm_set_power_status(BBXMM_PS_L2); -#endif -} - -static struct tegra_usb_phy_platform_ops oem2_plat_ops = { - .post_suspend = pluto_usb_hsic_postsupend, - .pre_resume = pluto_usb_hsic_preresume, - .port_power = pluto_usb_hsic_phy_power, - .post_resume = pluto_usb_hsic_post_resume, - .post_phy_off = pluto_usb_hsic_post_phy_off, -}; - -static struct tegra_usb_platform_data tegra_ehci3_hsic_smsc_hub_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static struct tegra_usb_platform_data tegra_udc_pdata = { - .port_otg = true, - .has_hostpc = true, - .id_det_type = TEGRA_USB_PMU_ID, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_DEVICE, - .u_data.dev = { - .vbus_pmu_irq = 0, - .vbus_gpio = -1, - .charging_supported = true, - .remote_wakeup_supported = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { - .port_otg = true, - .has_hostpc = true, - .id_det_type = TEGRA_USB_PMU_ID, - .id_extcon_dev_name = "MAX77665_MUIC_ID", - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_lsfslew = 0, - .xcvr_lsrslew = 3, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x7, - }, -}; - -static struct tegra_usb_otg_data tegra_otg_pdata = { - .ehci_device = &tegra_ehci1_device, - .ehci_pdata = &tegra_ehci1_utmi_pdata, -}; - -static struct regulator *baseband_reg; -static struct gpio modem_gpios[] = { /* i500 modem */ - {MDM_RST, GPIOF_OUT_INIT_LOW, "MODEM RESET"}, -}; - -static struct gpio modem2_gpios[] = { - {MDM2_PWR_ON, GPIOF_OUT_INIT_LOW, "MODEM2 PWR ON"}, - {MDM2_RST, GPIOF_OUT_INIT_LOW, "MODEM2 RESET"}, -}; - -static struct tegra_usb_platform_data tegra_ehci2_hsic_baseband_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci3_hsic_baseband2_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static struct tegra_usb_platform_data tegra_hsic_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_HSIC, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = false, - .remote_wakeup_supported = true, - .power_off_on_suspend = true, - }, -}; - -static struct platform_device * -tegra_usb_hsic_host_register(struct platform_device *ehci_dev) -{ - struct platform_device *pdev; - int val; - - pdev = platform_device_alloc(ehci_dev->name, ehci_dev->id); - if (!pdev) - return NULL; - - val = platform_device_add_resources(pdev, ehci_dev->resource, - ehci_dev->num_resources); - if (val) - goto error; - - pdev->dev.dma_mask = ehci_dev->dev.dma_mask; - pdev->dev.coherent_dma_mask = ehci_dev->dev.coherent_dma_mask; - - val = platform_device_add_data(pdev, &tegra_hsic_pdata, - sizeof(struct tegra_usb_platform_data)); - if (val) - goto error; - - val = platform_device_add(pdev); - if (val) - goto error; - - return pdev; - -error: - pr_err("%s: failed to add the host contoller device\n", __func__); - platform_device_put(pdev); - return NULL; -} - -static void tegra_usb_hsic_host_unregister(struct platform_device **platdev) -{ - struct platform_device *pdev = *platdev; - - if (pdev && &pdev->dev) { - platform_device_unregister(pdev); - *platdev = NULL; - } else - pr_err("%s: no platform device\n", __func__); -} - -static struct tegra_usb_phy_platform_ops oem1_hsic_pops; - -static union tegra_bb_gpio_id bb_gpio_oem1 = { - .oem1 = { - .reset = BB_OEM1_GPIO_RST, - .pwron = BB_OEM1_GPIO_ON, - .awr = BB_OEM1_GPIO_AWR, - .cwr = BB_OEM1_GPIO_CWR, - .spare = BB_OEM1_GPIO_SPARE, - .wdi = BB_OEM1_GPIO_WDI, - }, -}; - -static struct tegra_bb_pdata bb_pdata_oem1 = { - .id = &bb_gpio_oem1, - .device = &tegra_ehci3_device, - .ehci_register = tegra_usb_hsic_host_register, - .ehci_unregister = tegra_usb_hsic_host_unregister, - .bb_id = TEGRA_BB_OEM1, -}; - -static struct platform_device tegra_bb_oem1 = { - .name = "tegra_baseband_power", - .id = -1, - .dev = { - .platform_data = &bb_pdata_oem1, - }, -}; - -static int baseband_init(void) -{ - int ret; - - ret = gpio_request_array(modem_gpios, ARRAY_SIZE(modem_gpios)); - if (ret) { - pr_warn("%s:gpio request failed\n", __func__); - return ret; - } - - baseband_reg = regulator_get(NULL, "vdd_core_bb"); - if (IS_ERR(baseband_reg)) - pr_warn("%s: baseband regulator get failed\n", __func__); - else { - if (regulator_enable(baseband_reg) != 0) - pr_warn("baseband regulator enable failed\n"); - } - - /* enable pull-up for MDM1 UART RX */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_GPIO_PU1, - TEGRA_PUPD_PULL_UP); - - /* enable pull-down for MDM1_COLD_BOOT */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_ULPI_DATA4, - TEGRA_PUPD_PULL_DOWN); - - /* export GPIO for user space access through sysfs */ - gpio_export(MDM_RST, false); - - return 0; -} - -static const struct tegra_modem_operations baseband_operations = { - .init = baseband_init, -}; - -static struct tegra_usb_modem_power_platform_data baseband_pdata = { - .ops = &baseband_operations, - .wake_gpio = -1, - .boot_gpio = MDM_COLDBOOT, - .boot_irq_flags = IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING | - IRQF_ONESHOT, - .autosuspend_delay = 2000, - .short_autosuspend_delay = 50, - .tegra_ehci_device = &tegra_ehci2_device, - .tegra_ehci_pdata = &tegra_ehci2_hsic_baseband_pdata, -}; - -static struct platform_device icera_baseband_device = { - .name = "tegra_usb_modem_power", - .id = -1, - .dev = { - .platform_data = &baseband_pdata, - }, -}; - -static void baseband2_start(void) -{ - pr_info("%s\n", __func__); - gpio_set_value(MDM2_PWR_ON, 1); -} - -static void baseband2_reset(void) -{ - /* Initiate power cycle on baseband sub system */ - pr_info("%s\n", __func__); - gpio_set_value(MDM2_RST, 0); - mdelay(200); - gpio_set_value(MDM2_RST, 1); -} - -static int baseband2_init(void) -{ - int ret; - - tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPIO_X1_AUD, TEGRA_TRI_NORMAL); - - ret = gpio_request_array(modem2_gpios, ARRAY_SIZE(modem2_gpios)); - if (ret) - return ret; - - /* enable pull-down for MDM2_COLD_BOOT */ - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_KB_ROW4, - TEGRA_PUPD_PULL_DOWN); - - /* export GPIO for user space access through sysfs */ - gpio_export(MDM2_RST, false); - - return 0; -} - -static const struct tegra_modem_operations baseband2_operations = { - .init = baseband2_init, - .start = baseband2_start, - .reset = baseband2_reset, -}; - -static struct tegra_usb_modem_power_platform_data baseband2_pdata = { - .ops = &baseband2_operations, - .wake_gpio = -1, - .boot_gpio = MDM2_COLDBOOT, - .boot_irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - .autosuspend_delay = 2000, - .short_autosuspend_delay = 50, - .tegra_ehci_device = &tegra_ehci3_device, - .tegra_ehci_pdata = &tegra_ehci3_hsic_baseband2_pdata, -}; - -static struct platform_device icera_baseband2_device = { - .name = "tegra_usb_modem_power", - .id = -1, - .dev = { - .platform_data = &baseband2_pdata, - }, -}; - -static struct baseband_power_platform_data tegra_baseband_xmm_power_data = { - .baseband_type = BASEBAND_XMM, - .modem = { - .xmm = { - .bb_rst = XMM_GPIO_BB_RST, - .bb_on = XMM_GPIO_BB_ON, - .ipc_bb_wake = XMM_GPIO_IPC_BB_WAKE, - .ipc_ap_wake = XMM_GPIO_IPC_AP_WAKE, - .ipc_hsic_active = XMM_GPIO_IPC_HSIC_ACTIVE, - .ipc_hsic_sus_req = XMM_GPIO_IPC_HSIC_SUS_REQ, - }, - }, -}; - -static struct platform_device tegra_baseband_xmm_power_device = { - .name = "baseband_xmm_power", - .id = -1, - .dev = { - .platform_data = &tegra_baseband_xmm_power_data, - }, -}; - -static struct platform_device tegra_baseband_xmm_power2_device = { - .name = "baseband_xmm_power2", - .id = -1, - .dev = { - .platform_data = &tegra_baseband_xmm_power_data, - }, -}; - -static void pluto_usb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) { - tegra_otg_pdata.is_xhci = false; - tegra_udc_pdata.u_data.dev.is_xhci = false; - } else { - tegra_otg_pdata.is_xhci = true; - tegra_udc_pdata.u_data.dev.is_xhci = true; - } - tegra_otg_device.dev.platform_data = &tegra_otg_pdata; - platform_device_register(&tegra_otg_device); - - /* Setup the udc platform data */ - tegra_udc_device.dev.platform_data = &tegra_udc_pdata; -} - -static void pluto_modem_init(void) -{ - int modem_id = tegra_get_modem_id(); - struct board_info board_info; - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - tegra_get_board_info(&board_info); - pr_info("%s: modem_id = %d\n", __func__, modem_id); - - switch (modem_id) { - case TEGRA_BB_I500: /* on board i500 HSIC */ - if (!(usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)) - platform_device_register(&icera_baseband_device); - break; - case TEGRA_BB_I500SWD: /* i500 SWD HSIC */ - if (!(usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)) - platform_device_register(&icera_baseband2_device); - break; - case TEGRA_BB_OEM1: /* OEM1 HSIC */ - if ((board_info.board_id == BOARD_E1575) || - ((board_info.board_id == BOARD_E1580) && - (board_info.fab >= BOARD_FAB_A03))) { - tegra_pinmux_set_tristate(TEGRA_PINGROUP_GPIO_X1_AUD, - TEGRA_TRI_NORMAL); - bb_gpio_oem1.oem1.pwron = BB_OEM1_GPIO_ON_V; - } - if (!(usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)) { - tegra_hsic_pdata.ops = &oem1_hsic_pops; - tegra_ehci3_device.dev.platform_data - = &tegra_hsic_pdata; - platform_device_register(&tegra_bb_oem1); - } - break; - case TEGRA_BB_OEM2: /* XMM6260/XMM6360 HSIC */ - /* fix wrong wiring in Pluto A02 */ - if ((board_info.board_id == BOARD_E1580) && - (board_info.fab == BOARD_FAB_A02)) { - pr_info( -"%s: Pluto A02: replace MDM2_PWR_ON with MDM2_PWR_ON_FOR_PLUTO_A02\n", - __func__); - if (tegra_baseband_xmm_power_data.modem.xmm.bb_on - != MDM2_PWR_ON) - pr_err( -"%s: expected MDM2_PWR_ON default gpio for XMM bb_on\n", - __func__); - tegra_baseband_xmm_power_data.modem.xmm.bb_on - = MDM2_PWR_ON_FOR_PLUTO_A02; - } - /* baseband-power.ko will register ehci3 device */ - tegra_hsic_pdata.ops = &oem2_plat_ops; - tegra_hsic_pdata.u_data.host.remote_wakeup_supported = false; - tegra_hsic_pdata.u_data.host.power_off_on_suspend = false; - tegra_ehci3_device.dev.platform_data = - &tegra_hsic_pdata; - tegra_baseband_xmm_power_data.hsic_register = - &tegra_usb_hsic_host_register; - tegra_baseband_xmm_power_data.hsic_unregister = - &tegra_usb_hsic_host_unregister; - tegra_baseband_xmm_power_data.ehci_device = - &tegra_ehci3_device; - platform_device_register(&tegra_baseband_xmm_power_device); - platform_device_register(&tegra_baseband_xmm_power2_device); - /* override audio settings - use 8kHz */ - pluto_audio_pdata.i2s_param[BASEBAND].audio_port_id - = pluto_aic3262_pdata.i2s_param[BASEBAND].audio_port_id - = 2; - pluto_audio_pdata.i2s_param[BASEBAND].is_i2s_master - = pluto_aic3262_pdata.i2s_param[BASEBAND].is_i2s_master - = 1; - pluto_audio_pdata.i2s_param[BASEBAND].i2s_mode - = pluto_aic3262_pdata.i2s_param[BASEBAND].i2s_mode - = TEGRA_DAIFMT_I2S; - pluto_audio_pdata.i2s_param[BASEBAND].sample_size - = pluto_aic3262_pdata.i2s_param[BASEBAND].sample_size - = 16; - pluto_audio_pdata.i2s_param[BASEBAND].rate - = pluto_aic3262_pdata.i2s_param[BASEBAND].rate - = 8000; - pluto_audio_pdata.i2s_param[BASEBAND].channels - = pluto_aic3262_pdata.i2s_param[BASEBAND].channels - = 2; - break; - case TEGRA_BB_HSIC_HUB: /* HSIC hub */ - if (!(usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)) { - tegra_ehci3_device.dev.platform_data = - &tegra_ehci3_hsic_smsc_hub_pdata; - platform_device_register(&tegra_ehci3_device); - } - break; - default: - return; - } -} - -static struct tegra_xusb_platform_data xusb_pdata = { - .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0, -}; - -static void pluto_xusb_init(void) -{ - int usb_port_owner_info = tegra_get_usb_port_owner_info(); - - if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) - xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0 | - TEGRA_XUSB_SS_P0); -} -#else -static void pluto_usb_init(void) { } -static void pluto_modem_init(void) { } -static void pluto_xusb_init(void) { } -#endif - -static void pluto_audio_init(void) -{ - struct board_info board_info; - - tegra_get_board_info(&board_info); - - spi_register_board_info(aic326x_spi_board_info, - ARRAY_SIZE(aic326x_spi_board_info)); -} - -static __initdata struct tegra_clk_init_table touch_clk_init_table[] = { - /* name parent rate enabled */ - { "extern2", "pll_p", 41000000, false}, - { "clk_out_2", "extern2", 40800000, false}, - { NULL, NULL, 0, 0}, -}; - -struct rm_spi_ts_platform_data rm31080ts_pluto_data = { - .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI, - .config = 0, - .platform_id = RM_PLATFORM_P005, - .name_of_clock = "clk_out_2", - .name_of_clock_con = "extern2", -}; - -static struct tegra_spi_device_controller_data dev_cdata = { - .rx_clk_tap_delay = 0, - .tx_clk_tap_delay = 0, -}; - -struct spi_board_info rm31080a_pluto_spi_board[1] = { - { - .modalias = "rm_ts_spidev", - .bus_num = 3, - .chip_select = 2, - .max_speed_hz = 12 * 1000 * 1000, - .mode = SPI_MODE_0, - .controller_data = &dev_cdata, - .platform_data = &rm31080ts_pluto_data, - }, -}; - -static struct synaptics_gpio_data synaptics_gpio_pluto_data = { - .attn_gpio = SYNAPTICS_ATTN_GPIO, - .attn_polarity = RMI_ATTN_ACTIVE_LOW, - .reset_gpio = SYNAPTICS_RESET_GPIO, -}; - -static struct rmi_device_platform_data synaptics_pluto_platformdata = { - .sensor_name = "TM9999", - .attn_gpio = SYNAPTICS_ATTN_GPIO, - .attn_polarity = RMI_ATTN_ACTIVE_LOW, - .gpio_data = &synaptics_gpio_pluto_data, - .gpio_config = synaptics_touchpad_gpio_setup, - .spi_data = { - .block_delay_us = 100, - .read_delay_us = 100, - .write_delay_us = 20, - }, - .power_management = { - .nosleep = RMI_F01_NOSLEEP_OFF, - }, - .f19_button_map = &synaptics_button_map, - .f54_direct_touch_report_size = 944, -}; - -static struct spi_board_info synaptics_9999_spi_board_pluto[] = { - { - .modalias = "rmi_spi", - .bus_num = 3, - .chip_select = 2, - .max_speed_hz = 8*1000*1000, - .mode = SPI_MODE_3, - .platform_data = &synaptics_pluto_platformdata, - }, -}; - -static int __init pluto_touch_init(void) -{ - tegra_clk_init_from_table(touch_clk_init_table); - if (tegra_get_touch_vendor_id() == RAYDIUM_TOUCH) { - pr_info("%s: initializing raydium\n", __func__); - rm31080a_pluto_spi_board[0].irq = - gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI); - touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI, - TOUCH_GPIO_RST_RAYDIUM_SPI, - &rm31080ts_pluto_data, - &rm31080a_pluto_spi_board[0], - ARRAY_SIZE(rm31080a_pluto_spi_board)); - } else { - pr_info("%s: initializing synaptics\n", __func__); - touch_init_synaptics(synaptics_9999_spi_board_pluto, - ARRAY_SIZE(synaptics_9999_spi_board_pluto)); - } - return 0; -} - -#ifdef CONFIG_USE_OF -struct of_dev_auxdata pluto_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra114-apbdma", 0x6000a000, "tegra-apbdma", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000600, "sdhci-tegra.3", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000400, "sdhci-tegra.2", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-sdhci", 0x78000000, "sdhci-tegra.0", - &pluto_tegra_sdhci_platform_data0), - OF_DEV_AUXDATA("nvidia,tegra114-camera", 0x0, "tegra_camera", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", - NULL), - T114_I2C_OF_DEV_AUXDATA, - T114_SPI_OF_DEV_AUXDATA, - OF_DEV_AUXDATA("nvidia,tegra114-kbc", 0x7000e200, "tegra-kbc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-xhci", 0x70090000, "tegra-xhci", - &xusb_pdata), - OF_DEV_AUXDATA("nvidia,tegra114-nvavp", 0x60001000, "nvavp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-pwm", 0x7000a000, "tegra-pwm", NULL), - {} -}; -#endif - -static struct tegra_dtv_platform_data pluto_dtv_pdata = { - .dma_req_selector = 11, -}; - -static void __init pluto_dtv_init(void) -{ - tegra_dtv_device.dev.platform_data = &pluto_dtv_pdata; - platform_device_register(&tegra_dtv_device); -} - -static void __init tegra_pluto_early_init(void) -{ - tegra_clk_init_from_table(pluto_clk_init_table); - tegra_clk_verify_parents(); - tegra_soc_device_init("tegra_pluto"); -} - -static void __init tegra_pluto_late_init(void) -{ - pluto_i2c_init(); - pluto_usb_init(); - pluto_xusb_init(); - pluto_uart_init(); - pluto_audio_init(); - platform_add_devices(pluto_devices, ARRAY_SIZE(pluto_devices)); - tegra_io_dpd_init(); - pluto_sdhci_init(); - pluto_regulator_init(); - pluto_dtv_init(); - pluto_suspend_init(); - pluto_touch_init(); - pluto_emc_init(); - pluto_edp_init(); - isomgr_init(); - pluto_panel_init(); - pluto_kbc_init(); -#ifdef CONFIG_BT_BLUESLEEP - pluto_setup_bluesleep(); - pluto_setup_bt_rfkill(); -#elif defined CONFIG_BLUEDROID_PM - pluto_setup_bluedroid_pm(); -#endif - pluto_modem_init(); -#ifdef CONFIG_TEGRA_WDT_RECOVERY - tegra_wdt_recovery_init(); -#endif - pluto_sensors_init(); - tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); - pluto_soctherm_init(); - tegra_register_fuse(); -} - - -static void __init tegra_pluto_dt_init(void) -{ - tegra_pluto_early_init(); - - of_platform_populate(NULL, - of_default_bus_match_table, pluto_auxdata_lookup, - &platform_bus); - - tegra_pluto_late_init(); -} - -static void __init tegra_pluto_reserve(void) -{ -#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* for PANEL_5_SHARP_1080p: 1920*1080*4*2 = 16588800 bytes */ - tegra_reserve(0, SZ_16M, SZ_4M); -#else - tegra_reserve(SZ_128M, SZ_16M, SZ_4M); -#endif -} - -static const char * const pluto_dt_board_compat[] = { - "nvidia,pluto", - NULL -}; - -MACHINE_START(TEGRA_PLUTO, "tegra_pluto") - .atag_offset = 0x100, - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .reserve = tegra_pluto_reserve, - .init_early = tegra11x_init_early, - .init_irq = irqchip_init, - .init_time = clocksource_of_init, - .init_machine = tegra_pluto_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = pluto_dt_board_compat, - .init_late = tegra_init_late -MACHINE_END diff --git a/arch/arm/mach-tegra/board-pluto.h b/arch/arm/mach-tegra/board-pluto.h deleted file mode 100644 index 8ff87b372b62..000000000000 --- a/arch/arm/mach-tegra/board-pluto.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * arch/arm/mach-tegra/board-pluto.h - * - * Copyright (c) 2012, NVIDIA Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_BOARD_PLUTO_H -#define _MACH_TEGRA_BOARD_PLUTO_H - -#include <mach/gpio-tegra.h> -#include <mach/irqs.h> -#include <linux/mfd/palmas.h> -#include <linux/mfd/max77665.h> -#include "gpio-names.h" -#include <linux/thermal.h> -#include <linux/platform_data/thermal_sensors.h> -#include "tegra11_soctherm.h" - -/* External peripheral act as gpio */ -/* PALMAS GPIO */ -#define PALMAS_TEGRA_GPIO_BASE TEGRA_NR_GPIOS - -/* Audio-related GPIOs */ -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 -#define TEGRA_GPIO_LDO1_EN TEGRA_GPIO_PV3 -#define TEGRA_GPIO_SPKR_EN TEGRA_GPIO_PN4 -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7 -#define TEGRA_GPIO_INT_MIC_EN -1 -#define TEGRA_GPIO_EXT_MIC_EN -1 - -#define TEGRA_SOC_OC_IRQ_BASE TEGRA_NR_IRQS -#define TEGRA_SOC_OC_NUM_IRQ TEGRA_SOC_OC_IRQ_MAX - -/* External peripheral act as interrupt controller */ -/* PLUTO IRQs */ -#define PALMAS_TEGRA_IRQ_BASE (TEGRA_SOC_OC_IRQ_BASE + TEGRA_SOC_OC_NUM_IRQ) -#define MAX77665_TEGRA_IRQ_BASE (PALMAS_TEGRA_IRQ_BASE + PALMAS_NUM_IRQ) - -/* AIC326X IRQs */ -/* Assuming TPS is the PMIC on Ent */ -#define AIC3262_CODEC_IRQ_BASE (MAX77665_TEGRA_IRQ_BASE + MAX77665_NUM_IRQ) -#define AIC3262_CODEC_IRQ_END (AIC3262_CODEC_IRQ_BASE + 6) - -/* I2C related GPIOs */ -#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4 -#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5 -#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5 -#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6 -#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1 -#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2 -#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4 -#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5 -#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6 -#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7 - -/* Camera related GPIOs */ -#define CAM_RSTN TEGRA_GPIO_PBB3 -#define CAM_FLASH_STROBE TEGRA_GPIO_PBB4 -#define CAM1_POWER_DWN_GPIO TEGRA_GPIO_PBB5 -#define CAM2_POWER_DWN_GPIO TEGRA_GPIO_PBB6 -#define CAM_AF_PWDN TEGRA_GPIO_PBB7 -#define CAM_GPIO1 TEGRA_GPIO_PCC1 -#define CAM_GPIO2 TEGRA_GPIO_PCC2 - -/* Touchscreen definitions */ -#define SYNAPTICS_ATTN_GPIO TEGRA_GPIO_PK2 -#define SYNAPTICS_RESET_GPIO TEGRA_GPIO_PK4 - -#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2 -#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4 - -/* Invensense MPU Definitions */ -#define MPU_GYRO_NAME "mpu6050" -#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PO7 -#define MPU_GYRO_ADDR 0x69 -#define MPU_GYRO_BUS_NUM 0 -#define MPU_GYRO_ORIENTATION { -1, 0, 0, 0, -1, 0, 0, 0, 1 } -#define MPU_COMPASS_NAME "ak8975" -#define MPU_COMPASS_IRQ_GPIO 0 -#define MPU_COMPASS_ADDR 0x0D -#define MPU_COMPASS_BUS_NUM 0 -#define MPU_COMPASS_ORIENTATION { -1, 0, 0, 0, -1, 0, 0, 0, 1 } - -/* Modem1 related GPIOs */ -#define MDM_RST TEGRA_GPIO_PR3 -#define MDM_COLDBOOT TEGRA_GPIO_PO5 - -/* Modem2 related GPIOs */ -#define MDM2_PWR_ON TEGRA_GPIO_PX1 -#define MDM2_RST TEGRA_GPIO_PR5 -#define MDM2_COLDBOOT TEGRA_GPIO_PR4 -#define MDM2_REQ1 TEGRA_GPIO_PV0 -#define MDM2_ACK1 TEGRA_GPIO_PO2 -#define MDM2_REQ2 TEGRA_GPIO_PV1 -#define MDM2_ACK2 TEGRA_GPIO_PO3 - -/* Modem2 related GPIOs (for Pluto Rev A02 only) */ -#define MDM2_PWR_ON_FOR_PLUTO_A02 TEGRA_GPIO_PR6 - /* If Pluto A03 or later, use PX1 */ - -/* OEM1 Modem related GPIOs */ - -#define BB_OEM1_GPIO_RST TEGRA_GPIO_PR5 -#define BB_OEM1_GPIO_ON TEGRA_GPIO_PR6 -#define BB_OEM1_GPIO_ON_V TEGRA_GPIO_PX1 -#define BB_OEM1_GPIO_AWR TEGRA_GPIO_PG2 -#define BB_OEM1_GPIO_CWR TEGRA_GPIO_PV1 -#define BB_OEM1_GPIO_SPARE TEGRA_GPIO_PO2 -#define BB_OEM1_GPIO_WDI TEGRA_GPIO_PV0 - -/* OEM2 Modem related GPIOs */ - -#define XMM_GPIO_BB_ON MDM2_PWR_ON /* AP -> BB */ - /* E1193 Rev B7: pin 55 = MDM_PWRON_AP2BB */ -#define XMM_GPIO_BB_RST MDM2_RST /* AP -> BB */ - /* E1193 Rev B7: pin 53 = RESET_AP2BB* */ -#define XMM_GPIO_IPC_HSIC_ACTIVE MDM2_ACK2 /* AP -> BB */ - /* E1193 Rev B7: pin 46 = HS2_AP2BB */ -#define XMM_GPIO_IPC_HSIC_SUS_REQ MDM2_REQ2 /* BB -> AP */ - /* E1193 Rev B7: pin 41 = HS2_BB2AP */ -#define XMM_GPIO_IPC_BB_WAKE MDM2_ACK1 /* AP -> BB */ - /* E1193 Rev B7: pin 45 = HS1_AP2BB */ -#define XMM_GPIO_IPC_AP_WAKE MDM2_REQ1 /* BB -> AP */ - /* E1193 Rev B7: pin 43 = HS1_BB2AP */ - -int pluto_regulator_init(void); -int pluto_suspend_init(void); -int pluto_sdhci_init(void); -int pluto_sensors_init(void); -int pluto_emc_init(void); -int pluto_edp_init(void); -int pluto_panel_init(void); -int pluto_kbc_init(void); -int pluto_baseband_init(void); -int pluto_soctherm_init(void); - -extern struct tegra_sdhci_platform_data pluto_tegra_sdhci_platform_data0; - -/* Baseband IDs */ -enum tegra_bb_type { - TEGRA_BB_I500 = 1, - TEGRA_BB_I500SWD, - TEGRA_BB_OEM1, - TEGRA_BB_OEM2, - TEGRA_BB_OEM3, - TEGRA_BB_HSIC_HUB, -}; - -#define UTMI1_PORT_OWNER_XUSB 0x1 -#define HSIC1_PORT_OWNER_XUSB 0x4 -#define HSIC2_PORT_OWNER_XUSB 0x8 - -#endif diff --git a/arch/arm/mach-tegra/board-roth-fan.c b/arch/arm/mach-tegra/board-roth-fan.c deleted file mode 100644 index 6d8fe46f4211..000000000000 --- a/arch/arm/mach-tegra/board-roth-fan.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-fan.c - * - * Copyright (c) 2012-2013 NVIDIA CORPORATION, All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/platform_data/pwm_fan.h> -#include <linux/platform_device.h> - -#include <mach/gpio-tegra.h> - -#include "gpio-names.h" -#include "devices.h" -#include "board.h" -#include "board-common.h" -#include "board-roth.h" -#include "tegra-board-id.h" - -static struct pwm_fan_platform_data fan_data_yltc_8k = { - .active_steps = MAX_ACTIVE_STATES, - .active_rpm = { - 0, 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000, 11000}, - .active_pwm = {0, 158*1024, 227*1024 , 230*1024, 235*1024, 240*1024, - 245*1024, 250*1024, 252*1024, 255*1024}, - .active_rru = {1024*50, 1024, 1024, 256, 256, 256, 256, 256, 256, 256}, - .active_rrd = {1024*50, 1024, 1024, 256, 256, 256, 256, 128, 128, 128}, - /*Lookup table to get the actual state cap*/ - .state_cap_lookup = {1, 1, 1, 1, 1, 1, 1, 2, 2, 2}, - .pwm_period = 256, - .pwm_id = 0, - .step_time = 100, /*msecs*/ - .state_cap = 1, - .precision_multiplier = 1024, - .tach_gpio = -1, -}; - -static struct pwm_fan_platform_data fan_data_delta_6k = { - .active_steps = MAX_ACTIVE_STATES, - .active_rpm = { - 0, 1000, 2000, 3000, 4000, 5000, 6000, 7000, 10000, 11000}, - .active_pwm = {0, 80*1024, 110*1024 , 150*1024, 235*1024, 240*1024, - 245*1024, 250*1024, 252*1024, 255*1024}, - .active_rru = {1024*40, 1024*2, 1024, 256, - 256, 256, 256, 256, 256, 256}, - .active_rrd = {1024*40, 1024*2, 1024, 256, 256, - 256, 256, 128, 128, 128}, - .state_cap_lookup = {2, 2, 2, 2, 2, 2, 2, 3, 3, 3}, - .pwm_period = 256, - .pwm_id = 0, - .step_time = 100, /*msecs*/ - .state_cap = 2, - .precision_multiplier = 1024, - .tach_gpio = TEGRA_GPIO_PU2, -}; - -static struct platform_device pwm_fan_therm_cooling_device_yltc_8k = { - .name = "pwm-fan", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &fan_data_yltc_8k, - }, -}; - -static struct platform_device pwm_fan_therm_cooling_device_delta_6k = { - .name = "pwm-fan", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &fan_data_delta_6k, - }, -}; - -int __init roth_fan_init(void) -{ - int err; - struct board_info board_info; - - tegra_get_board_info(&board_info); - - err = gpio_request(TEGRA_GPIO_PU3, "pwm-fan"); - if (err < 0) { - pr_err("FAN:gpio request failed\n"); - return err; - } - gpio_free(TEGRA_GPIO_PU3); - - if (board_info.board_id == BOARD_P2560) { - platform_device_register( - &pwm_fan_therm_cooling_device_delta_6k); - pr_info("FAN:registering for P2560\n"); - } else { - platform_device_register(&pwm_fan_therm_cooling_device_yltc_8k); - pr_info("FAN:registering for P2454\n"); - } - return 0; -} diff --git a/arch/arm/mach-tegra/board-roth-kbc.c b/arch/arm/mach-tegra/board-roth-kbc.c deleted file mode 100644 index a563b66d047b..000000000000 --- a/arch/arm/mach-tegra/board-roth-kbc.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-kbc.c - * Keys configuration for Nvidia tegra3 roth platform. - * - * Copyright (C) 2012 NVIDIA, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/input.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/gpio_keys.h> -#include <linux/mfd/palmas.h> - -#include "tegra-board-id.h" -#include "board.h" -#include "board-roth.h" -#include "devices.h" -#include "iomap.h" -#include "wakeups-t11x.h" - -#define GPIO_KEY(_id, _gpio, _iswake) \ - { \ - .code = _id, \ - .gpio = TEGRA_GPIO_##_gpio, \ - .active_low = 1, \ - .desc = #_id, \ - .type = EV_KEY, \ - .wakeup = _iswake, \ - .debounce_interval = 10, \ - } - -#define GPIO_IKEY(_id, _irq, _iswake, _deb) \ - { \ - .code = _id, \ - .gpio = -1, \ - .irq = _irq, \ - .desc = #_id, \ - .type = EV_KEY, \ - .wakeup = _iswake, \ - .debounce_interval = _deb, \ - } - -static struct gpio_keys_button roth_gpio_keys[] = { - [0] = GPIO_KEY(KEY_POWER, PQ0, 1), - [1] = GPIO_KEY(KEY_BACK, PR2, 0), - [2] = GPIO_KEY(KEY_HOME, PR1, 0), - [3] = { - .code = KEY_WAKEUP, - .gpio = TEGRA_GPIO_PI5, - .irq = -1, - .type = EV_KEY, - .desc = "Controller", - .active_low = 0, - .wakeup = 1, - .debounce_interval = 10, - }, - [4] = { - .code = SW_LID, - .gpio = TEGRA_GPIO_HALL, - .irq = -1, - .type = EV_SW, - .desc = "Hall Effect Sensor", - .active_low = 1, - .wakeup = 1, - .debounce_interval = 100, - }, -}; - -static int roth_wakeup_key(void) -{ - int wakeup_key; - u64 status = readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS) - | (u64)readl(IO_ADDRESS(TEGRA_PMC_BASE) - + PMC_WAKE2_STATUS) << 32; - - if (status & (1ULL << TEGRA_WAKE_GPIO_PQ0)) - wakeup_key = KEY_POWER; - else if (status & (1ULL << TEGRA_WAKE_GPIO_PI5)) - wakeup_key = KEY_WAKEUP; - else if (status & (1ULL << TEGRA_WAKE_GPIO_PS0)) - wakeup_key = SW_LID; - else - wakeup_key = -1; - - return wakeup_key; -} - -static struct gpio_keys_platform_data roth_gpio_keys_pdata = { - .buttons = roth_gpio_keys, - .nbuttons = ARRAY_SIZE(roth_gpio_keys), - .wakeup_key = roth_wakeup_key, -}; - -static struct platform_device roth_gpio_keys_device = { - .name = "gpio-keys", - .id = 0, - .dev = { - .platform_data = &roth_gpio_keys_pdata, - }, -}; - -int __init roth_kbc_init(void) -{ - platform_device_register(&roth_gpio_keys_device); - return 0; -} - diff --git a/arch/arm/mach-tegra/board-roth-leds.c b/arch/arm/mach-tegra/board-roth-leds.c deleted file mode 100644 index 68d2b180038b..000000000000 --- a/arch/arm/mach-tegra/board-roth-leds.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-leds.c - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/gpio.h> -#include <linux/platform_device.h> -#include <linux/leds.h> -#include <linux/leds_pwm.h> -#include <linux/pwm.h> -#include <mach/gpio-tegra.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> - -#include "gpio-names.h" -#include "devices.h" -#include "board.h" -#include "board-common.h" -#include "board-roth.h" -#include "tegra-board-id.h" - -#define LED_ENABLE_GPIO TEGRA_GPIO_PU1 - -#ifdef CONFIG_LEDS_PWM - -static struct led_pwm roth_led_info[] = { - { - .name = "roth-led", - .default_trigger = "none", - .pwm_id = 2, - .active_low = 0, - .max_brightness = 255, - .pwm_period_ns = 10000000, - }, -}; - -static struct led_pwm_platform_data roth_leds_pdata = { - .leds = roth_led_info, - .num_leds = ARRAY_SIZE(roth_led_info), -}; - -static struct platform_device roth_leds_pwm_device = { - .name = "leds_pwm", - .id = -1, - .dev = { - .platform_data = &roth_leds_pdata, - }, -}; - - -#else -static struct gpio_led roth_led_info[] = { - { - .name = "roth-led", - .default_trigger = "none", - .gpio = TEGRA_GPIO_PQ3, - .active_low = 0, - .retain_state_suspended = 0, - .default_state = LEDS_GPIO_DEFSTATE_OFF, - }, -}; - -static struct gpio_led_platform_data roth_leds_pdata = { - .leds = roth_led_info, - .num_leds = ARRAY_SIZE(roth_led_info), -}; - -static struct platform_device roth_leds_gpio_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &roth_leds_pdata, - }, -}; -#endif - -/*static struct platform_device *roth_led_device[] = { - &tegra_pwfm2_device, -};*/ - -int __init roth_led_init(void) -{ -#ifdef CONFIG_LEDS_PWM - platform_device_register(&roth_leds_pwm_device); -#else - platform_device_register(&roth_leds_gpio_device); -#endif - gpio_request(LED_ENABLE_GPIO, "LED Trisate Buffer OE"); - gpio_direction_output(LED_ENABLE_GPIO, 1); - gpio_export(LED_ENABLE_GPIO, false); - return 0; -} diff --git a/arch/arm/mach-tegra/board-roth-memory.c b/arch/arm/mach-tegra/board-roth-memory.c deleted file mode 100644 index 5256c4623461..000000000000 --- a/arch/arm/mach-tegra/board-roth-memory.c +++ /dev/null @@ -1,2597 +0,0 @@ -/* - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA - * 02111-1307, USA - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/platform_data/tegra_emc_pdata.h> - -#include "board.h" -#include "board-roth.h" - -#include "tegra11_emc.h" -#include "devices.h" - -static struct tegra11_emc_table h5tc4g63afr_pba_table[] = { - { - 0x41, /* Rev 4.0.3 */ - 12750, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000003e, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000003, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000060, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000005, /* EMC_TXSR */ - 0x00000005, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000064, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00078000, /* EMC_DLL_XFORM_DQS4 */ - 0x00078000, /* EMC_DLL_XFORM_DQS5 */ - 0x00078000, /* EMC_DLL_XFORM_DQS6 */ - 0x00078000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000007, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40040001, /* MC_EMEM_ARB_CFG */ - 0x8000003f, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x77e30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000000e, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7324000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 57820, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 20400, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000026, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000000, /* EMC_RC */ - 0x00000005, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000000, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x0000009a, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000007, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000006, /* EMC_TXSR */ - 0x00000006, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x000000a0, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00078000, /* EMC_DLL_XFORM_DQS4 */ - 0x00078000, /* EMC_DLL_XFORM_DQS5 */ - 0x00078000, /* EMC_DLL_XFORM_DQS6 */ - 0x00078000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x0000000b, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x40020001, /* MC_EMEM_ARB_CFG */ - 0x80000046, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x76230303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000014, /* MC_PTSA_GRANT_DECREMENT */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7324000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 35610, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 40800, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000012, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000001, /* EMC_RC */ - 0x0000000a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000001, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000134, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000008, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000000c, /* EMC_TXSR */ - 0x0000000c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000013f, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00078000, /* EMC_DLL_XFORM_DQS4 */ - 0x00078000, /* EMC_DLL_XFORM_DQS5 */ - 0x00078000, /* EMC_DLL_XFORM_DQS6 */ - 0x00078000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000015, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0xa0000001, /* MC_EMEM_ARB_CFG */ - 0x8000005b, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74a30303, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000002a, /* MC_PTSA_GRANT_DECREMENT */ - 0x00b000b0, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00b000c4, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00d700eb, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x000000eb, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00eb00eb, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00ff00eb, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000ff, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7324000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 20850, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 68000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x4000000a, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000003, /* EMC_RC */ - 0x00000011, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000002, /* EMC_RAS */ - 0x00000000, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000000, /* EMC_RD_RCD */ - 0x00000000, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000202, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000000f, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000013, /* EMC_TXSR */ - 0x00000013, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000004, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000213, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00078000, /* EMC_DLL_XFORM_DQS4 */ - 0x00078000, /* EMC_DLL_XFORM_DQS5 */ - 0x00078000, /* EMC_DLL_XFORM_DQS6 */ - 0x00078000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000022, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x00000001, /* MC_EMEM_ARB_CFG */ - 0x80000076, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ - 0x74230403, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000046, /* MC_PTSA_GRANT_DECREMENT */ - 0x00690069, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00690075, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0081008d, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000008d, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x008d008d, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00bc008d, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x000000bc, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00bc00bc, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7324000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 10720, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 102000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000006, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000004, /* EMC_RC */ - 0x0000001a, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000003, /* EMC_RAS */ - 0x00000001, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000001, /* EMC_RD_RCD */ - 0x00000001, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000303, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000018, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x0000001c, /* EMC_TXSR */ - 0x0000001c, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000005, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x0000031c, /* EMC_TREFBW */ - 0x00000005, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00078000, /* EMC_DLL_XFORM_DQS4 */ - 0x00078000, /* EMC_DLL_XFORM_DQS5 */ - 0x00078000, /* EMC_DLL_XFORM_DQS6 */ - 0x00078000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000033, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00000000, /* EMC_ZCAL_INTERVAL */ - 0x00000042, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x08000001, /* MC_EMEM_ARB_CFG */ - 0x80000098, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ - 0x73c30504, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00078000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS1 */ - 0x00078000, /* EMC_DLL_XFORM_DQS2 */ - 0x00078000, /* EMC_DLL_XFORM_DQS3 */ - 0x00078000, /* EMC_DLL_XFORM_DQ1 */ - 0x00078000, /* EMC_DLL_XFORM_DQ2 */ - 0x00078000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000068, /* MC_PTSA_GRANT_DECREMENT */ - 0x00460046, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0046004e, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0056005e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000005e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x005e005e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x007d005e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000007d, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x007d007d, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7324000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 6890, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 204000, /* SDRAM frequency */ - 900, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000009, /* EMC_RC */ - 0x00000035, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000006, /* EMC_RAS */ - 0x00000002, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x0000000a, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x0000000b, /* EMC_W2P */ - 0x00000002, /* EMC_RD_RCD */ - 0x00000002, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000607, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x00000002, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000032, /* EMC_AR2PDEN */ - 0x0000000f, /* EMC_RW2PDEN */ - 0x00000038, /* EMC_TXSR */ - 0x00000038, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000009, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000638, /* EMC_TREFBW */ - 0x00000006, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000aa88, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00064000, /* EMC_DLL_XFORM_DQS4 */ - 0x00064000, /* EMC_DLL_XFORM_DQS5 */ - 0x00064000, /* EMC_DLL_XFORM_DQS6 */ - 0x00064000, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000a11c, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000066, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT */ - 0x000f000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x01000003, /* MC_EMEM_ARB_CFG */ - 0x800000fe, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030102, /* MC_EMEM_ARB_DA_TURNS */ - 0x000a0404, /* MC_EMEM_ARB_DA_COVERS */ - 0x73840a05, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000004, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00064000, /* EMC_DLL_XFORM_DQS0 */ - 0x00000009, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS1 */ - 0x00064000, /* EMC_DLL_XFORM_DQS2 */ - 0x00064000, /* EMC_DLL_XFORM_DQS3 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ1 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ2 */ - 0x0007c000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d0, /* MC_PTSA_GRANT_DECREMENT */ - 0x00230023, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00230027, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x002b002f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000002f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x002f002f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x003e002f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000003e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x003e003e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff00c8, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x7320000e, /* EMC_CFG */ - 0x80001221, /* Mode Register 0 */ - 0x80100003, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 3420, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 312000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000000d, /* EMC_RC */ - 0x00000050, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000009, /* EMC_RAS */ - 0x00000003, /* EMC_RP */ - 0x00000004, /* EMC_R2W */ - 0x00000008, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x00000009, /* EMC_W2P */ - 0x00000003, /* EMC_RD_RCD */ - 0x00000003, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x0000000f, /* EMC_RDV_MASK */ - 0x00000941, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x00000250, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000004d, /* EMC_AR2PDEN */ - 0x0000000e, /* EMC_RW2PDEN */ - 0x00000055, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x0000000d, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000982, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0x002c00a0, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x0000009c, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0171000f, /* EMC_MRS_WAIT_CNT */ - 0x0171000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000138d, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0b000004, /* MC_EMEM_ARB_CFG */ - 0x8000016a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */ - 0x76e50f08, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000b, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000d, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00048000, /* EMC_DLL_XFORM_DQ1 */ - 0x00048000, /* EMC_DLL_XFORM_DQ2 */ - 0x00048000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000140, /* MC_PTSA_GRANT_DECREMENT */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00170019, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x001c001e, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000001e, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x001e001e, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0029001e, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000029, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00290029, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00ff0082, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x5300000e, /* EMC_CFG */ - 0x80000321, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200000, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 2680, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 408000, /* SDRAM frequency */ - 1000, /* min voltage */ - "pll_p", /* clock source id */ - 0x40000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000012, /* EMC_RC */ - 0x00000069, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000c, /* EMC_RAS */ - 0x00000004, /* EMC_RP */ - 0x00000005, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000004, /* EMC_RD_RCD */ - 0x00000004, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000006, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000004, /* EMC_QRST */ - 0x00000010, /* EMC_RDV_MASK */ - 0x00000c2e, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000008, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000066, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000006f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000011, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000c6f, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x000000cc, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0158000f, /* EMC_MRS_WAIT_CNT */ - 0x0158000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x02000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06040202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000e0709, /* MC_EMEM_ARB_DA_COVERS */ - 0x7547130a, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000006, /* EMC_QUSE */ - 0x00000005, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000e, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00030000, /* EMC_DLL_XFORM_DQ1 */ - 0x00030000, /* EMC_DLL_XFORM_DQ2 */ - 0x00030000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000d1, /* MC_PTSA_GRANT_DECREMENT */ - 0x00110011, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00110013, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00150017, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000017, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00170017, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001f0017, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001f, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001f001f, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00d30064, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00d300d3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000006, /* EMC_CFG */ - 0x80000731, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 450000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x00000002, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000014, /* EMC_RC */ - 0x00000073, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000000e, /* EMC_RAS */ - 0x00000005, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000c, /* EMC_W2P */ - 0x00000005, /* EMC_RD_RCD */ - 0x00000005, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000004, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000007, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000005, /* EMC_QRST */ - 0x00000011, /* EMC_RDV_MASK */ - 0x00000d76, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000001, /* EMC_PDEX2WR */ - 0x00000009, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000071, /* EMC_AR2PDEN */ - 0x00000011, /* EMC_RW2PDEN */ - 0x0000007a, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000012, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000004, /* EMC_TCLKSTABLE */ - 0x00000005, /* EMC_TCLKSTOP */ - 0x00000db6, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0x002c0080, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00030000, /* EMC_DLL_XFORM_DQS4 */ - 0x00030000, /* EMC_DLL_XFORM_DQS5 */ - 0x00030000, /* EMC_DLL_XFORM_DQS6 */ - 0x00030000, /* EMC_DLL_XFORM_DQS7 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0001013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x03037504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x000000e1, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x014d000f, /* EMC_MRS_WAIT_CNT */ - 0x014d000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0c000006, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x000f080b, /* MC_EMEM_ARB_DA_COVERS */ - 0x74c7150c, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ1 */ - 0x00034000, /* EMC_DLL_XFORM_DQ2 */ - 0x00034000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000004, /* EMC_FBIO_CFG6 */ - 0x00000007, /* EMC_QUSE */ - 0x00000006, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x00030000, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x0000000f, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS1 */ - 0x00030000, /* EMC_DLL_XFORM_DQS2 */ - 0x00030000, /* EMC_DLL_XFORM_DQS3 */ - 0x00034000, /* EMC_DLL_XFORM_DQ1 */ - 0x00034000, /* EMC_DLL_XFORM_DQ2 */ - 0x00034000, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000000e6, /* MC_PTSA_GRANT_DECREMENT */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00100011, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00130015, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000015, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00150015, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x001c0015, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000001c, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x001c001c, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00c0005a, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00c000c0, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000006, /* EMC_CFG */ - 0x80000741, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1750, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 528000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000018, /* EMC_RC */ - 0x00000088, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000010, /* EMC_RAS */ - 0x00000006, /* EMC_RP */ - 0x00000006, /* EMC_R2W */ - 0x00000009, /* EMC_W2R */ - 0x00000002, /* EMC_R2P */ - 0x0000000d, /* EMC_W2P */ - 0x00000006, /* EMC_RD_RCD */ - 0x00000006, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x00000009, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000006, /* EMC_QRST */ - 0x00000012, /* EMC_RDV_MASK */ - 0x00000fd6, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000b, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x00000084, /* EMC_AR2PDEN */ - 0x00000012, /* EMC_RW2PDEN */ - 0x0000008f, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000004, /* EMC_TCKE */ - 0x00000004, /* EMC_TCKESR */ - 0x00000004, /* EMC_TPD */ - 0x00000016, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000005, /* EMC_TCLKSTABLE */ - 0x00000006, /* EMC_TCLKSTOP */ - 0x00001017, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0120091, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000108, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x013a000f, /* EMC_MRS_WAIT_CNT */ - 0x013a000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80002062, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0f000007, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ - 0x06050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */ - 0x7428180d, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000008, /* EMC_QUSE */ - 0x00000007, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000010, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000010e, /* MC_PTSA_GRANT_DECREMENT */ - 0x000d000d, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000d000f, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x00100012, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x00000012, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x00120012, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x00180012, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000018, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00180018, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x00a3004d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00a300a3, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000004, /* EMC_CFG */ - 0x80000941, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200008, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 624000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_c", /* clock source id */ - 0x24000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000001c, /* EMC_RC */ - 0x000000a1, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000014, /* EMC_RAS */ - 0x00000007, /* EMC_RP */ - 0x00000007, /* EMC_R2W */ - 0x0000000b, /* EMC_W2R */ - 0x00000003, /* EMC_R2P */ - 0x00000010, /* EMC_W2P */ - 0x00000007, /* EMC_RD_RCD */ - 0x00000007, /* EMC_WR_RCD */ - 0x00000002, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000005, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000a, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000007, /* EMC_QRST */ - 0x00000014, /* EMC_RDV_MASK */ - 0x000012c3, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000004b0, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000002, /* EMC_PDEX2WR */ - 0x0000000d, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x0000009c, /* EMC_AR2PDEN */ - 0x00000015, /* EMC_RW2PDEN */ - 0x000000a9, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000019, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000006, /* EMC_TCLKSTABLE */ - 0x00000007, /* EMC_TCLKSTOP */ - 0x00001304, /* EMC_TREFBW */ - 0x00000009, /* EMC_QUSE_EXTRA */ - 0x00000020, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x0000ba88, /* EMC_FBIO_CFG5 */ - 0xf00d0191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x00000138, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x0122000f, /* EMC_MRS_WAIT_CNT */ - 0x0122000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80002617, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x06000009, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_RC */ - 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */ - 0x07050202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00130b0f, /* MC_EMEM_ARB_DA_COVERS */ - 0x736a1d10, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000001, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000001, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x00000009, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000004, /* EMC_EINPUT_DURATION */ - 0x0000000a, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000c, /* EMC_QSAFE */ - 0x00020000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000012, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000001, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000808, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000001, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ2 */ - 0x0000000b, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00020000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x0000013f, /* MC_PTSA_GRANT_DECREMENT */ - 0x000b000b, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000e000f, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000f, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000f000f, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0014000f, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000014, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00140014, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x008a0041, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x008a008a, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000000, /* EMC_CFG */ - 0x80000b61, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200010, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1440, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 792000, /* SDRAM frequency */ - 1100, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x00000024, /* EMC_RC */ - 0x000000cc, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x00000019, /* EMC_RAS */ - 0x0000000a, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x0000000d, /* EMC_W2R */ - 0x00000004, /* EMC_R2P */ - 0x00000013, /* EMC_W2P */ - 0x0000000a, /* EMC_RD_RCD */ - 0x0000000a, /* EMC_WR_RCD */ - 0x00000003, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000006, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000b, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x00000008, /* EMC_QRST */ - 0x00000016, /* EMC_RDV_MASK */ - 0x000017e1, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000003, /* EMC_PDEX2WR */ - 0x00000011, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000c6, /* EMC_AR2PDEN */ - 0x00000018, /* EMC_RW2PDEN */ - 0x000000d6, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000005, /* EMC_TCKE */ - 0x00000005, /* EMC_TCKESR */ - 0x00000005, /* EMC_TPD */ - 0x00000020, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000007, /* EMC_TCLKSTABLE */ - 0x00000008, /* EMC_TCLKSTOP */ - 0x00001822, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x80000000, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0070191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x00000007, /* EMC_DLL_XFORM_DQS4 */ - 0x00000007, /* EMC_DLL_XFORM_DQS5 */ - 0x00000007, /* EMC_DLL_XFORM_DQS6 */ - 0x00000007, /* EMC_DLL_XFORM_DQS7 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x0000018c, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000100, /* EMC_ZCAL_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT */ - 0x00f8000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x80003012, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0e00000b, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ - 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ - 0x08060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */ - 0x734c2414, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000007, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00008000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS1 */ - 0x00000007, /* EMC_DLL_XFORM_DQS2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000a, /* EMC_QUSE */ - 0x00000008, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000007, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00008000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000014, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00004000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00004000, /* EMC_DLL_XFORM_ADDR2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS1 */ - 0x00000007, /* EMC_DLL_XFORM_DQS2 */ - 0x00000007, /* EMC_DLL_XFORM_DQS3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00008000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000196, /* MC_PTSA_GRANT_DECREMENT */ - 0x00090009, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x000b000c, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000c, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000c000c, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x0010000c, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x00000010, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x00100010, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x006d0033, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x006d006d, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000000, /* EMC_CFG */ - 0x80000d71, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200418, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, - { - 0x41, /* Rev 4.0.3 */ - 900000, /* SDRAM frequency */ - 1200, /* min voltage */ - "pll_m", /* clock source id */ - 0x80000000, /* CLK_SOURCE_EMC */ - 99, /* number of burst_regs */ - 30, /* number of trim_regs (each channel) */ - 11, /* number of up_down_regs */ - { - 0x0000002a, /* EMC_RC */ - 0x000000e8, /* EMC_RFC */ - 0x00000000, /* EMC_RFC_SLR */ - 0x0000001d, /* EMC_RAS */ - 0x0000000b, /* EMC_RP */ - 0x00000008, /* EMC_R2W */ - 0x0000000f, /* EMC_W2R */ - 0x00000005, /* EMC_R2P */ - 0x00000016, /* EMC_W2P */ - 0x0000000b, /* EMC_RD_RCD */ - 0x0000000b, /* EMC_WR_RCD */ - 0x00000004, /* EMC_RRD */ - 0x00000001, /* EMC_REXT */ - 0x00000000, /* EMC_WEXT */ - 0x00000007, /* EMC_WDV */ - 0x0000000f, /* EMC_WDV_MASK */ - 0x0000000d, /* EMC_IBDLY */ - 0x00010000, /* EMC_PUTERM_EXTRA */ - 0x00000000, /* EMC_CDB_CNTL_2 */ - 0x0000000a, /* EMC_QRST */ - 0x00000018, /* EMC_RDV_MASK */ - 0x00001b2c, /* EMC_REFRESH */ - 0x00000000, /* EMC_BURST_REFRESH_NUM */ - 0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */ - 0x00000004, /* EMC_PDEX2WR */ - 0x00000014, /* EMC_PDEX2RD */ - 0x00000001, /* EMC_PCHG2PDEN */ - 0x00000000, /* EMC_ACT2PDEN */ - 0x000000e0, /* EMC_AR2PDEN */ - 0x0000001b, /* EMC_RW2PDEN */ - 0x000000f3, /* EMC_TXSR */ - 0x00000200, /* EMC_TXSRDLL */ - 0x00000006, /* EMC_TCKE */ - 0x00000006, /* EMC_TCKESR */ - 0x00000006, /* EMC_TPD */ - 0x00000024, /* EMC_TFAW */ - 0x00000000, /* EMC_TRPAB */ - 0x00000008, /* EMC_TCLKSTABLE */ - 0x00000009, /* EMC_TCLKSTOP */ - 0x00001b6c, /* EMC_TREFBW */ - 0x00000000, /* EMC_QUSE_EXTRA */ - 0x80000000, /* EMC_ODT_WRITE */ - 0x00000000, /* EMC_ODT_READ */ - 0x00005088, /* EMC_FBIO_CFG5 */ - 0xf0040191, /* EMC_CFG_DIG_DLL */ - 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ - 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE4 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE5 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE6 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE7 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ - 0x001112a0, /* EMC_XM2CMDPADCTRL */ - 0x00000000, /* EMC_XM2CMDPADCTRL4 */ - 0x0000013d, /* EMC_XM2DQSPADCTRL2 */ - 0x00000000, /* EMC_XM2DQPADCTRL2 */ - 0x77ffc085, /* EMC_XM2CLKPADCTRL */ - 0x81f1f108, /* EMC_XM2COMPPADCTRL */ - 0x07077504, /* EMC_XM2VTTGENPADCTRL */ - 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */ - 0x0000003f, /* EMC_DSR_VTTGEN_DRV */ - 0x000001c2, /* EMC_TXDSRVTTGEN */ - 0x02000000, /* EMC_FBIO_SPARE */ - 0x00000802, /* EMC_CTT_TERM_CTRL */ - 0x00020000, /* EMC_ZCAL_INTERVAL */ - 0x00000120, /* EMC_ZCAL_WAIT_CNT */ - 0x00d6000f, /* EMC_MRS_WAIT_CNT */ - 0x00d6000f, /* EMC_MRS_WAIT_CNT2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */ - 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */ - 0x00000000, /* EMC_CTT */ - 0x00000000, /* EMC_CTT_DURATION */ - 0x8000367c, /* EMC_DYN_SELF_REF_CONTROL */ - 0x1f7df7df, /* EMC_CA_TRAINING_TIMING_CNTL1 */ - 0x0000001f, /* EMC_CA_TRAINING_TIMING_CNTL2 */ - 0x0800000d, /* MC_EMEM_ARB_CFG */ - 0x80000190, /* MC_EMEM_ARB_OUTSTANDING_REQ */ - 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ - 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ - 0x00000015, /* MC_EMEM_ARB_TIMING_RC */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ - 0x00000011, /* MC_EMEM_ARB_TIMING_FAW */ - 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ - 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ - 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */ - 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ - 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ - 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */ - 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ - 0x09060202, /* MC_EMEM_ARB_DA_TURNS */ - 0x001a1015, /* MC_EMEM_ARB_DA_COVERS */ - 0x734e2916, /* MC_EMEM_ARB_MISC0 */ - 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000c, /* EMC_QUSE */ - 0x0000000a, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000009, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00018000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ0 */ - 0xa0f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x00000000, /* EMC_CDB_CNTL_1 */ - 0x00000006, /* EMC_FBIO_CFG6 */ - 0x0000000c, /* EMC_QUSE */ - 0x0000000a, /* EMC_EINPUT */ - 0x00000006, /* EMC_EINPUT_DURATION */ - 0x00000009, /* EMC_DLL_XFORM_DQS0 */ - 0x0000000d, /* EMC_QSAFE */ - 0x00018000, /* EMC_DLL_XFORM_QUSE0 */ - 0x00000016, /* EMC_RDV */ - 0x00249249, /* EMC_XM2DQSPADCTRL4 */ - 0x20820800, /* EMC_XM2DQSPADCTRL3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ0 */ - 0xa8f10f0f, /* EMC_AUTO_CAL_CONFIG */ - 0x00000000, /* EMC_DLL_XFORM_ADDR0 */ - 0x00000a0a, /* EMC_XM2CLKPADCTRL2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR1 */ - 0x00000000, /* EMC_DLL_XFORM_ADDR2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ - 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ1 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ2 */ - 0x0000400a, /* EMC_DLL_XFORM_DQ3 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ - 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE1 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE2 */ - 0x00018000, /* EMC_DLL_XFORM_QUSE3 */ - }, - { - 0x000001cd, /* MC_PTSA_GRANT_DECREMENT */ - 0x00080008, /* MC_LATENCY_ALLOWANCE_G2_0 */ - 0x00080008, /* MC_LATENCY_ALLOWANCE_G2_1 */ - 0x0009000a, /* MC_LATENCY_ALLOWANCE_NV_0 */ - 0x0000000a, /* MC_LATENCY_ALLOWANCE_NV2_0 */ - 0x000a000a, /* MC_LATENCY_ALLOWANCE_NV_2 */ - 0x000e000a, /* MC_LATENCY_ALLOWANCE_NV_1 */ - 0x0000000e, /* MC_LATENCY_ALLOWANCE_NV2_1 */ - 0x000e000e, /* MC_LATENCY_ALLOWANCE_NV3 */ - 0x0060002d, /* MC_LATENCY_ALLOWANCE_EPP_0 */ - 0x00600060, /* MC_LATENCY_ALLOWANCE_EPP_1 */ - }, - 0x0000004a, /* EMC_ZCAL_WAIT_CNT after clock change */ - 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ - 0x53000000, /* EMC_CFG */ - 0x80000f15, /* Mode Register 0 */ - 0x80100002, /* Mode Register 1 */ - 0x80200420, /* Mode Register 2 */ - 0x00000000, /* Mode Register 4 */ - 1200, /* expected dvfs latency (ns) */ - }, -}; - -static struct tegra11_emc_pdata h5tc4g63afr_pba_pdata = { - .description = "h5tc4g63afr_pba", - .tables = h5tc4g63afr_pba_table, - .num_tables = ARRAY_SIZE(h5tc4g63afr_pba_table), -}; - -static struct tegra11_emc_pdata *roth_get_emc_data(void) -{ - return &h5tc4g63afr_pba_pdata; -} - -int __init roth_emc_init(void) -{ - tegra_emc_device.dev.platform_data = roth_get_emc_data(); - platform_device_register(&tegra_emc_device); - tegra11_emc_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-roth-panel.c b/arch/arm/mach-tegra/board-roth-panel.c deleted file mode 100644 index e158ffc825da..000000000000 --- a/arch/arm/mach-tegra/board-roth-panel.c +++ /dev/null @@ -1,971 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-panel.c - * - * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ -#include <linux/ioport.h> -#include <linux/fb.h> -#include <linux/nvmap.h> -#include <linux/nvhost.h> -#include <linux/init.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/tegra_pwm_bl.h> -#include <linux/regulator/consumer.h> -#include <linux/pwm_backlight.h> -#include <linux/of.h> - -#include <mach/irqs.h> -#include <mach/dc.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <asm/mach-types.h> - -#include "board.h" -#include "board-panel.h" -#include "devices.h" -#include "gpio-names.h" -#include "iomap.h" -#include "tegra11_host1x_devices.h" - -struct platform_device * __init roth_host1x_init(void) -{ - struct platform_device *pdev = NULL; - -#ifdef CONFIG_TEGRA_GRHOST - if (!of_have_populated_dt()) - pdev = tegra11_register_host1x_devices(); - else - pdev = to_platform_device(bus_find_device_by_name( - &platform_bus_type, NULL, "host1x")); -#endif - return pdev; -} - -#define IS_EXTERNAL_PWM 1 - -#define DSI_PANEL_RESET 1 - -#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH3 -#define DSI_PANEL_BL_PWM TEGRA_GPIO_PH1 - -#define DSI_PANEL_CE 0 - -#define DC_CTRL_MODE TEGRA_DC_OUT_CONTINUOUS_MODE - -/* HDMI Hotplug detection pin */ -#define roth_hdmi_hpd TEGRA_GPIO_PN7 - -static bool reg_requested; -static bool gpio_requested; - -static struct regulator *vdd_lcd_s_1v8; -static struct regulator *vdd_lcd_bl; -static struct regulator *vdd_lcd_bl_en; -static struct regulator *avdd_lcd_3v0_2v8; - -static struct regulator *roth_hdmi_reg; -static struct regulator *roth_hdmi_pll; -static struct regulator *roth_hdmi_vddio; - -#ifdef CONFIG_TEGRA_DC_CMU -static struct tegra_dc_cmu roth_cmu = { - /* lut1 maps sRGB to linear space. */ - { - 0, 1, 2, 4, 5, 6, 7, 9, - 10, 11, 12, 14, 15, 16, 18, 20, - 21, 23, 25, 27, 29, 31, 33, 35, - 37, 40, 42, 45, 48, 50, 53, 56, - 59, 62, 66, 69, 72, 76, 79, 83, - 87, 91, 95, 99, 103, 107, 112, 116, - 121, 126, 131, 136, 141, 146, 151, 156, - 162, 168, 173, 179, 185, 191, 197, 204, - 210, 216, 223, 230, 237, 244, 251, 258, - 265, 273, 280, 288, 296, 304, 312, 320, - 329, 337, 346, 354, 363, 372, 381, 390, - 400, 409, 419, 428, 438, 448, 458, 469, - 479, 490, 500, 511, 522, 533, 544, 555, - 567, 578, 590, 602, 614, 626, 639, 651, - 664, 676, 689, 702, 715, 728, 742, 755, - 769, 783, 797, 811, 825, 840, 854, 869, - 884, 899, 914, 929, 945, 960, 976, 992, - 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125, - 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267, - 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420, - 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582, - 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755, - 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939, - 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133, - 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339, - 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555, - 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783, - 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022, - 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272, - 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535, - 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809, - 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095, - }, - /* csc */ - { - 0x100, 0x0, 0x0, - 0x0, 0x100, 0x0, - 0x0, 0x0, 0x100, - }, - /* lut2 maps linear space to sRGB*/ - { - 0, 0, 1, 2, 3, 3, 4, 5, - 6, 6, 7, 8, 8, 9, 10, 10, - 11, 12, 12, 13, 13, 14, 14, 15, - 16, 16, 17, 17, 18, 18, 19, 19, - 19, 20, 20, 21, 21, 22, 22, 22, - 23, 23, 24, 24, 24, 25, 25, 25, - 26, 26, 27, 27, 27, 28, 28, 28, - 28, 29, 29, 29, 30, 30, 30, 31, - 31, 31, 31, 32, 32, 32, 33, 33, - 33, 33, 34, 34, 34, 35, 35, 35, - 35, 36, 36, 36, 36, 37, 37, 37, - 38, 38, 38, 38, 39, 39, 39, 39, - 40, 40, 40, 40, 40, 41, 41, 41, - 41, 42, 42, 42, 42, 43, 43, 43, - 43, 43, 44, 44, 44, 44, 45, 45, - 45, 45, 45, 46, 46, 46, 46, 46, - 47, 47, 47, 47, 47, 48, 48, 48, - 48, 48, 49, 49, 49, 49, 49, 49, - 50, 50, 50, 50, 50, 50, 51, 51, - 51, 51, 51, 51, 52, 52, 52, 52, - 52, 52, 53, 53, 53, 53, 53, 53, - 54, 54, 54, 54, 54, 54, 54, 55, - 55, 55, 55, 55, 55, 55, 55, 56, - 56, 56, 56, 56, 56, 56, 57, 57, - 57, 57, 57, 57, 57, 57, 58, 58, - 58, 58, 58, 58, 58, 58, 58, 59, - 59, 59, 59, 59, 59, 59, 59, 59, - 60, 60, 60, 60, 60, 60, 60, 60, - 60, 61, 61, 61, 61, 61, 61, 61, - 61, 61, 61, 62, 62, 62, 62, 62, - 62, 62, 62, 62, 62, 63, 63, 63, - 63, 63, 63, 63, 63, 63, 63, 63, - 64, 64, 64, 64, 64, 64, 64, 64, - 64, 64, 64, 65, 65, 65, 65, 65, - 65, 65, 65, 65, 65, 65, 66, 66, - 66, 66, 66, 66, 66, 66, 66, 66, - 66, 66, 67, 67, 67, 67, 67, 67, - 67, 67, 67, 67, 67, 67, 68, 68, - 68, 68, 68, 68, 68, 68, 68, 68, - 68, 68, 69, 69, 69, 69, 69, 69, - 69, 69, 69, 69, 69, 69, 70, 70, - 70, 70, 70, 70, 70, 70, 70, 70, - 70, 70, 70, 71, 71, 71, 71, 71, - 71, 71, 71, 71, 71, 71, 71, 71, - 72, 72, 72, 72, 72, 72, 72, 72, - 72, 72, 72, 72, 72, 73, 73, 73, - 73, 73, 73, 73, 73, 73, 73, 73, - 73, 73, 73, 74, 74, 74, 74, 74, - 74, 74, 74, 74, 74, 74, 74, 74, - 75, 75, 75, 75, 75, 75, 75, 75, - 75, 75, 75, 75, 75, 75, 76, 76, - 76, 76, 76, 76, 76, 76, 76, 76, - 76, 76, 76, 76, 77, 77, 77, 77, - 77, 77, 77, 77, 77, 77, 77, 77, - 77, 77, 78, 78, 78, 78, 78, 78, - 78, 78, 78, 78, 78, 78, 78, 78, - 79, 79, 79, 79, 79, 79, 79, 79, - 79, 79, 79, 79, 79, 79, 80, 80, - 80, 80, 80, 80, 80, 80, 80, 80, - 80, 80, 80, 80, 81, 81, 81, 81, - 81, 81, 81, 81, 81, 81, 81, 81, - 81, 81, 82, 82, 82, 82, 82, 82, - 82, 82, 82, 82, 82, 82, 82, 82, - 83, 83, 83, 83, 83, 83, 83, 83, - 84, 84, 85, 85, 86, 86, 87, 88, - 88, 89, 89, 90, 90, 91, 92, 92, - 93, 93, 94, 94, 95, 95, 96, 96, - 97, 97, 98, 98, 99, 99, 100, 100, - 101, 101, 102, 102, 103, 103, 104, 104, - 105, 105, 106, 106, 107, 107, 107, 108, - 108, 109, 109, 110, 110, 111, 111, 111, - 112, 112, 113, 113, 114, 114, 114, 115, - 115, 116, 116, 117, 117, 117, 118, 118, - 119, 119, 119, 120, 120, 121, 121, 121, - 122, 122, 123, 123, 123, 124, 124, 125, - 125, 126, 126, 126, 127, 127, 128, 128, - 128, 129, 129, 129, 130, 130, 131, 131, - 131, 132, 132, 133, 133, 133, 134, 134, - 135, 135, 135, 136, 136, 137, 137, 137, - 138, 138, 138, 139, 139, 140, 140, 140, - 141, 141, 142, 142, 142, 143, 143, 143, - 144, 144, 145, 145, 145, 146, 146, 146, - 147, 147, 147, 148, 148, 149, 149, 149, - 150, 150, 150, 151, 151, 151, 152, 152, - 153, 153, 153, 154, 154, 154, 155, 155, - 156, 156, 156, 157, 157, 157, 158, 158, - 159, 159, 159, 160, 160, 160, 161, 161, - 162, 162, 162, 163, 163, 164, 164, 164, - 165, 165, 166, 166, 166, 167, 167, 168, - 168, 168, 169, 169, 170, 170, 170, 171, - 171, 172, 172, 172, 173, 173, 173, 174, - 174, 175, 175, 175, 176, 176, 176, 177, - 177, 177, 178, 178, 178, 179, 179, 179, - 180, 180, 180, 180, 181, 181, 181, 182, - 182, 182, 182, 183, 183, 183, 184, 184, - 184, 184, 185, 185, 185, 185, 186, 186, - 186, 186, 187, 187, 187, 187, 188, 188, - 188, 188, 189, 189, 189, 190, 190, 190, - 190, 191, 191, 191, 191, 192, 192, 192, - 193, 193, 193, 193, 194, 194, 194, 195, - 195, 195, 195, 196, 196, 196, 197, 197, - 197, 198, 198, 198, 198, 199, 199, 199, - 200, 200, 200, 201, 201, 201, 202, 202, - 202, 203, 203, 204, 204, 204, 205, 205, - 205, 206, 206, 206, 207, 207, 208, 208, - 208, 209, 209, 209, 210, 210, 211, 211, - 211, 212, 212, 213, 213, 213, 214, 214, - 215, 215, 215, 216, 216, 217, 217, 217, - 218, 218, 218, 219, 219, 220, 220, 220, - 221, 221, 221, 222, 222, 222, 223, 223, - 223, 224, 224, 224, 225, 225, 225, 225, - 226, 226, 226, 226, 227, 227, 227, 227, - 228, 228, 228, 228, 229, 229, 229, 229, - 229, 230, 230, 230, 230, 231, 231, 231, - 231, 232, 232, 232, 233, 233, 233, 233, - 234, 234, 234, 235, 235, 235, 236, 236, - 236, 237, 237, 238, 238, 239, 239, 239, - 240, 240, 241, 241, 242, 242, 243, 244, - 244, 245, 245, 246, 247, 247, 248, 249, - 250, 250, 251, 252, 253, 254, 254, 255, - }, -}; -#endif - -static struct resource roth_disp1_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_GENERAL, - .end = INT_DISPLAY_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY_BASE, - .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by roth_panel_init() */ - .end = 0, /* Filled in by roth_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "dsi_regs", - .start = TEGRA_DSI_BASE, - .end = TEGRA_DSI_BASE + TEGRA_DSI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "mipi_cal", - .start = TEGRA_MIPI_CAL_BASE, - .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource roth_disp2_resources[] = { - { - .name = "irq", - .start = INT_DISPLAY_B_GENERAL, - .end = INT_DISPLAY_B_GENERAL, - .flags = IORESOURCE_IRQ, - }, - { - .name = "regs", - .start = TEGRA_DISPLAY2_BASE, - .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - { - .name = "fbmem", - .start = 0, /* Filled in by roth_panel_init() */ - .end = 0, /* Filled in by roth_panel_init() */ - .flags = IORESOURCE_MEM, - }, - { - .name = "hdmi_regs", - .start = TEGRA_HDMI_BASE, - .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static u8 panel_dsi_config[] = {0xe0, 0x43, 0x0, 0x80, 0x0, 0x0}; -static u8 panel_disp_ctrl1[] = {0xb5, 0x34, 0x20, 0x40, 0x0, 0x20}; -static u8 panel_disp_ctrl2[] = {0xb6, 0x04, 0x74, 0x0f, 0x16, 0x13}; -static u8 panel_internal_clk[] = {0xc0, 0x01, 0x08}; -static u8 panel_pwr_ctrl3[] = { - 0xc3, 0x0, 0x09, 0x10, 0x02, 0x0, 0x66, 0x00, 0x13, 0x0}; -static u8 panel_pwr_ctrl4[] = {0xc4, 0x23, 0x24, 0x12, 0x12, 0x60}; -static u8 panel_positive_gamma_red[] = { - 0xd0, 0x21, 0x25, 0x67, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03}; -static u8 panel_negetive_gamma_red[] = { - 0xd1, 0x31, 0x25, 0x66, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03}; -static u8 panel_positive_gamma_green[] = { - 0xd2, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03}; -static u8 panel_negetive_gamma_green[] = { - 0xd3, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03}; -static u8 panel_positive_gamma_blue[] = { - 0xd4, 0x41, 0x26, 0x56, 0x36, 0x0a, 0x06, 0x61, 0x23, 0x03}; -static u8 panel_negetive_gamma_blue[] = { - 0xd5, 0x51, 0x26, 0x55, 0x36, 0x05, 0x06, 0x61, 0x23, 0x03}; - -#if DSI_PANEL_CE -static u8 panel_ce2[] = {0x71, 0x0, 0x0, 0x01, 0x01}; -static u8 panel_ce3[] = {0x72, 0x01, 0x0e}; -static u8 panel_ce4[] = {0x73, 0x34, 0x52, 0x0}; -static u8 panel_ce5[] = {0x74, 0x05, 0x0, 0x06}; -static u8 panel_ce6[] = {0x75, 0x03, 0x0, 0x07}; -static u8 panel_ce7[] = {0x76, 0x07, 0x0, 0x06}; -static u8 panel_ce8[] = {0x77, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f}; -static u8 panel_ce9[] = {0x78, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; -static u8 panel_ce10[] = { - 0x79, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40}; -static u8 panel_ce11[] = {0x7a, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; -static u8 panel_ce12[] = {0x7b, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; -static u8 panel_ce13[] = {0x7c, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; -#endif - -static struct tegra_dsi_cmd dsi_init_cmd[] = { - DSI_DLY_MS(20), - DSI_GPIO_SET(DSI_PANEL_RST_GPIO, 1), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_dsi_config), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl1), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_disp_ctrl2), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_internal_clk), - - /* panel power control 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x0), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl3), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_pwr_ctrl4), - - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_red), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_red), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_green), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_green), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_positive_gamma_blue), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_negetive_gamma_blue), - - DSI_CMD_SHORT(DSI_DCS_WRITE_1_PARAM, DSI_DCS_SET_ADDR_MODE, 0x0B), - - /* panel OTP 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x0), - -#if DSI_PANEL_CE - /* panel CE 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0x70, 0x0), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce2), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce3), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce4), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce5), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce6), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce7), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce8), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce9), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce10), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce11), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce12), - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_ce13), -#endif - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x02), - DSI_DLY_MS(20), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x06), - DSI_DLY_MS(20), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x4e), - DSI_DLY_MS(100), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_EXIT_SLEEP_MODE, 0x0), - DSI_DLY_MS(140), - - /* panel OTP 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xf9, 0x80), - DSI_DLY_MS(20), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_ON, 0x0), -}; - -static u8 panel_suspend_pwr_ctrl4[] = {0xc4, 0x0, 0x0, 0x0, 0x0, 0x0}; - -static struct tegra_dsi_cmd dsi_suspend_cmd[] = { - DSI_DLY_MS(40), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_SET_DISPLAY_OFF, 0x0), - DSI_DLY_MS(20), - - DSI_CMD_SHORT(DSI_DCS_WRITE_0_PARAM, DSI_DCS_ENTER_SLEEP_MODE, 0x0), - - /* panel power control 2 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc2, 0x0), - - /* panel power control 4 */ - DSI_CMD_LONG(DSI_GENERIC_LONG_WRITE, panel_suspend_pwr_ctrl4), - - /* panel power control 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x2), - DSI_DLY_MS(20), - - /* panel power control 1 */ - DSI_CMD_SHORT(DSI_GENERIC_SHORT_WRITE_2_PARAMS, 0xc1, 0x3), - DSI_DLY_MS(20), -}; - -static struct tegra_dsi_out roth_dsi = { - .n_data_lanes = 4, - .controller_vs = DSI_VS_1, - .pixel_format = TEGRA_DSI_PIXEL_FORMAT_24BIT_P, - .refresh_rate = 60, - .virtual_channel = TEGRA_DSI_VIRTUAL_CHANNEL_0, - - .dsi_instance = DSI_INSTANCE_0, - - .panel_reset = DSI_PANEL_RESET, - .power_saving_suspend = true, - .video_data_type = TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE, - .video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS, - .video_burst_mode = TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END, - .dsi_init_cmd = dsi_init_cmd, - .n_init_cmd = ARRAY_SIZE(dsi_init_cmd), - .dsi_suspend_cmd = dsi_suspend_cmd, - .n_suspend_cmd = ARRAY_SIZE(dsi_suspend_cmd), -}; - -static int roth_dsi_regulator_get(struct device *dev) -{ - int err = 0; - - if (reg_requested) - return 0; - - avdd_lcd_3v0_2v8 = regulator_get(dev, "avdd_lcd"); - if (IS_ERR(avdd_lcd_3v0_2v8)) { - pr_err("avdd_lcd regulator get failed\n"); - err = PTR_ERR(avdd_lcd_3v0_2v8); - avdd_lcd_3v0_2v8 = NULL; - goto fail; - } - vdd_lcd_s_1v8 = regulator_get(dev, "dvdd_lcd"); - if (IS_ERR(vdd_lcd_s_1v8)) { - pr_err("vdd_lcd_1v8_s regulator get failed\n"); - err = PTR_ERR(vdd_lcd_s_1v8); - vdd_lcd_s_1v8 = NULL; - goto fail; - } - - if (machine_is_dalmore()) { - vdd_lcd_bl = regulator_get(dev, "vdd_lcd_bl"); - if (IS_ERR(vdd_lcd_bl)) { - pr_err("vdd_lcd_bl regulator get failed\n"); - err = PTR_ERR(vdd_lcd_bl); - vdd_lcd_bl = NULL; - goto fail; - } - } - - vdd_lcd_bl_en = regulator_get(dev, "vdd_lcd_bl_en"); - if (IS_ERR(vdd_lcd_bl_en)) { - pr_err("vdd_lcd_bl_en regulator get failed\n"); - err = PTR_ERR(vdd_lcd_bl_en); - vdd_lcd_bl_en = NULL; - goto fail; - } - reg_requested = true; - return 0; -fail: - return err; -} - -static int roth_dsi_gpio_get(void) -{ - int err = 0; - - if (gpio_requested) - return 0; - - err = gpio_request(DSI_PANEL_RST_GPIO, "panel rst"); - if (err < 0) { - pr_err("panel reset gpio request failed\n"); - goto fail; - } - - gpio_requested = true; - return 0; -fail: - return err; -} - -static struct tegra_dc_out roth_disp1_out; - -static int roth_dsi_panel_enable(struct device *dev) -{ - int err = 0; - - err = roth_dsi_regulator_get(dev); - if (err < 0) { - pr_err("dsi regulator get failed\n"); - goto fail; - } - err = roth_dsi_gpio_get(); - if (err < 0) { - pr_err("dsi gpio request failed\n"); - goto fail; - } - - /* Skip panel programming if in initialized mode */ - if (!(roth_disp1_out.flags & TEGRA_DC_OUT_INITIALIZED_MODE)) { - roth_dsi.dsi_init_cmd = dsi_init_cmd; - gpio_set_value(DSI_PANEL_RST_GPIO, 0); - } else { - roth_dsi.dsi_init_cmd = dsi_init_cmd + 2; - } - - if (vdd_lcd_s_1v8) { - err = regulator_enable(vdd_lcd_s_1v8); - if (err < 0) { - pr_err("vdd_lcd_1v8_s regulator enable failed\n"); - goto fail; - } - } - usleep_range(3000, 5000); - - if (avdd_lcd_3v0_2v8) { - err = regulator_enable(avdd_lcd_3v0_2v8); - if (err < 0) { - pr_err("avdd_lcd_3v0_2v8 regulator enable failed\n"); - goto fail; - } - regulator_set_voltage(avdd_lcd_3v0_2v8, 2800000, 2800000); - } - usleep_range(3000, 5000); - - if (vdd_lcd_bl) { - err = regulator_enable(vdd_lcd_bl); - if (err < 0) { - pr_err("vdd_lcd_bl regulator enable failed\n"); - goto fail; - } - } - - if (vdd_lcd_bl_en) { - err = regulator_enable(vdd_lcd_bl_en); - if (err < 0) { - pr_err("vdd_lcd_bl_en regulator enable failed\n"); - goto fail; - } - } - - return 0; -fail: - return err; -} - -static int roth_dsi_panel_disable(void) -{ - if (vdd_lcd_bl) - regulator_disable(vdd_lcd_bl); - - if (vdd_lcd_bl_en) - regulator_disable(vdd_lcd_bl_en); - - gpio_set_value(DSI_PANEL_RST_GPIO, 0); - mdelay(20); - - if (vdd_lcd_s_1v8) - regulator_disable(vdd_lcd_s_1v8); - - if (avdd_lcd_3v0_2v8) - regulator_disable(avdd_lcd_3v0_2v8); - - return 0; -} - -static int roth_dsi_panel_postsuspend(void) -{ - /* TODO */ - return 0; -} - -static struct tegra_dc_mode roth_dsi_modes[] = { - { - .pclk = 66700000, - .h_ref_to_sync = 4, - .v_ref_to_sync = 1, - .h_sync_width = 4, - .v_sync_width = 4, - .h_back_porch = 112, - .v_back_porch = 12, - .h_active = 720, - .v_active = 1280, - .h_front_porch = 12, - .v_front_porch = 8, - }, -}; - -static struct tegra_dc_sd_settings sd_settings; - -static struct tegra_dc_out roth_disp1_out = { - .type = TEGRA_DC_OUT_DSI, - .dsi = &roth_dsi, - - .flags = DC_CTRL_MODE, - .sd_settings = &sd_settings, - - .modes = roth_dsi_modes, - .n_modes = ARRAY_SIZE(roth_dsi_modes), - - .enable = roth_dsi_panel_enable, - .disable = roth_dsi_panel_disable, - .postsuspend = roth_dsi_panel_postsuspend, - .width = 62, - .height = 110, -}; - -static int roth_hdmi_enable(struct device *dev) -{ - int ret; - if (!roth_hdmi_reg) { - roth_hdmi_reg = regulator_get(dev, "avdd_hdmi"); - if (IS_ERR(roth_hdmi_reg)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); - roth_hdmi_reg = NULL; - return PTR_ERR(roth_hdmi_reg); - } - } - ret = regulator_enable(roth_hdmi_reg); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); - return ret; - } - if (!roth_hdmi_pll) { - roth_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll"); - if (IS_ERR(roth_hdmi_pll)) { - pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); - roth_hdmi_pll = NULL; - regulator_put(roth_hdmi_reg); - roth_hdmi_reg = NULL; - return PTR_ERR(roth_hdmi_pll); - } - } - ret = regulator_enable(roth_hdmi_pll); - if (ret < 0) { - pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); - return ret; - } - return 0; -} - -static int roth_hdmi_disable(void) -{ - if (roth_hdmi_reg) { - regulator_disable(roth_hdmi_reg); - regulator_put(roth_hdmi_reg); - roth_hdmi_reg = NULL; - } - - if (roth_hdmi_pll) { - regulator_disable(roth_hdmi_pll); - regulator_put(roth_hdmi_pll); - roth_hdmi_pll = NULL; - } - - return 0; -} - -static int roth_hdmi_postsuspend(void) -{ - if (roth_hdmi_vddio) { - regulator_disable(roth_hdmi_vddio); - regulator_put(roth_hdmi_vddio); - roth_hdmi_vddio = NULL; - } - return 0; -} - -static int roth_hdmi_hotplug_init(struct device *dev) -{ - int e = 0; - - if (!roth_hdmi_vddio) { - roth_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0"); - if (WARN_ON(IS_ERR(roth_hdmi_vddio))) { - e = PTR_ERR(roth_hdmi_vddio); - pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %d\n", - __func__, e); - roth_hdmi_vddio = NULL; - } else - e = regulator_enable(roth_hdmi_vddio); - } - return e; -} - -static void roth_hdmi_hotplug_report(bool state) -{ - if (state) { - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA, - TEGRA_PUPD_PULL_DOWN); - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL, - TEGRA_PUPD_PULL_DOWN); - } else { - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SDA, - TEGRA_PUPD_NORMAL); - tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_DDC_SCL, - TEGRA_PUPD_NORMAL); - } -} - -static struct tegra_dc_out roth_disp2_out = { - .type = TEGRA_DC_OUT_HDMI, - .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, - .parent_clk = "pll_d2_out0", - - .ddc_bus = 3, - .hotplug_gpio = roth_hdmi_hpd, - - .max_pixclock = KHZ2PICOS(297000), - - .align = TEGRA_DC_ALIGN_MSB, - .order = TEGRA_DC_ORDER_RED_BLUE, - - .enable = roth_hdmi_enable, - .disable = roth_hdmi_disable, - .postsuspend = roth_hdmi_postsuspend, - .hotplug_init = roth_hdmi_hotplug_init, - .hotplug_report = roth_hdmi_hotplug_report, -}; - -static struct tegra_fb_data roth_disp1_fb_data = { - .win = 0, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, - .xres = 720, - .yres = 1280, -}; - -static struct tegra_dc_platform_data roth_disp1_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &roth_disp1_out, - .fb = &roth_disp1_fb_data, - .emc_clk_rate = 204000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, - .cmu = &roth_cmu, -#endif -}; - -static struct tegra_fb_data roth_disp2_fb_data = { - .win = 0, - .xres = 1024, - .yres = 600, - .bits_per_pixel = 32, - .flags = TEGRA_FB_FLIP_ON_PROBE, -}; - -static struct tegra_dc_platform_data roth_disp2_pdata = { - .flags = TEGRA_DC_FLAG_ENABLED, - .default_out = &roth_disp2_out, - .fb = &roth_disp2_fb_data, - .emc_clk_rate = 300000000, -#ifdef CONFIG_TEGRA_DC_CMU - .cmu_enable = 1, -#endif -}; - -static struct platform_device roth_disp2_device = { - .name = "tegradc", - .id = 1, - .resource = roth_disp2_resources, - .num_resources = ARRAY_SIZE(roth_disp2_resources), - .dev = { - .platform_data = &roth_disp2_pdata, - }, -}; - -static struct platform_device roth_disp1_device = { - .name = "tegradc", - .id = 0, - .resource = roth_disp1_resources, - .num_resources = ARRAY_SIZE(roth_disp1_resources), - .dev = { - .platform_data = &roth_disp1_pdata, - }, -}; - -static struct nvmap_platform_carveout roth_carveouts[] = { - [0] = { - .name = "iram", - .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM, - .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, - .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, - }, - [1] = { - .name = "generic-0", - .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, - .base = 0, /* Filled in by roth_panel_init() */ - .size = 0, /* Filled in by roth_panel_init() */ - }, - [2] = { - .name = "vpr", - .usage_mask = NVMAP_HEAP_CARVEOUT_VPR, - .base = 0, /* Filled in by roth_panel_init() */ - .size = 0, /* Filled in by roth_panel_init() */ - }, -}; - -static struct nvmap_platform_data roth_nvmap_data = { - .carveouts = roth_carveouts, - .nr_carveouts = ARRAY_SIZE(roth_carveouts), -}; - -static struct platform_device roth_nvmap_device = { - .name = "tegra-nvmap", - .id = -1, - .dev = { - .platform_data = &roth_nvmap_data, - }, -}; - -static int roth_disp1_bl_notify(struct device *unused, int brightness) -{ - int cur_sd_brightness = atomic_read(&sd_brightness); - - /* SD brightness is a percentage */ - brightness = (brightness * cur_sd_brightness) / 255; - - /* Apply any backlight response curve */ - if (brightness > 255) - pr_info("Error: Brightness > 255!\n"); - - return brightness; -} - -static int roth_disp1_check_fb(struct device *dev, struct fb_info *info) -{ - return info->device == &roth_disp1_device.dev; -} - -static struct platform_pwm_backlight_data roth_disp1_bl_data = { - .pwm_id = 1, - .max_brightness = 255, - .dft_brightness = 77, - .pwm_period_ns = 40000, - .pwm_gpio = DSI_PANEL_BL_PWM, - .notify = roth_disp1_bl_notify, - /* Only toggle backlight on fb blank notifications for disp1 */ - .check_fb = roth_disp1_check_fb, -}; - -static struct platform_device __maybe_unused - roth_disp1_bl_device = { - .name = "pwm-backlight", - .id = -1, - .dev = { - .platform_data = &roth_disp1_bl_data, - }, -}; - -static struct platform_device __maybe_unused - *roth_bl_device[] __initdata = { - &roth_disp1_bl_device, -}; - -int __init roth_panel_init(int board_id) -{ - int err = 0; - struct resource __maybe_unused *res; - struct platform_device *phost1x = NULL; - -#ifdef CONFIG_TEGRA_NVMAP - roth_carveouts[1].base = tegra_carveout_start; - roth_carveouts[1].size = tegra_carveout_size; - roth_carveouts[2].base = tegra_vpr_start; - roth_carveouts[2].size = tegra_vpr_size; - - err = platform_device_register(&roth_nvmap_device); - if (err) { - pr_err("nvmap device registration failed\n"); - return err; - } -#endif - - phost1x = roth_host1x_init(); - if (!phost1x) { - pr_err("host1x devices registration failed\n"); - return -EINVAL; - } - - res = platform_get_resource_byname(&roth_disp1_device, - IORESOURCE_MEM, "fbmem"); - res->start = tegra_fb_start; - res->end = tegra_fb_start + tegra_fb_size - 1; - - /* Copy the bootloader fb to the fb. */ - __tegra_move_framebuffer(&roth_nvmap_device, - tegra_fb_start, tegra_bootloader_fb_start, - min(tegra_fb_size, tegra_bootloader_fb_size)); - - /* - * only roth supports initialized mode. - */ - if (!board_id) - roth_disp1_out.flags |= TEGRA_DC_OUT_INITIALIZED_MODE; - - roth_disp1_device.dev.parent = &phost1x->dev; - err = platform_device_register(&roth_disp1_device); - if (err) { - pr_err("disp1 device registration failed\n"); - return err; - } - - err = tegra_init_hdmi(&roth_disp2_device, phost1x); - if (err) - return err; - -#if IS_EXTERNAL_PWM - err = platform_add_devices(roth_bl_device, - ARRAY_SIZE(roth_bl_device)); - if (err) { - pr_err("disp1 bl device registration failed"); - return err; - } -#endif - -#ifdef CONFIG_TEGRA_NVAVP - if (!of_have_populated_dt()) { - nvavp_device.dev.parent = &phost1x->dev; - err = platform_device_register(&nvavp_device); - if (err) { - pr_err("nvavp device registration failed\n"); - return err; - } - } -#endif - return err; -} diff --git a/arch/arm/mach-tegra/board-roth-power.c b/arch/arm/mach-tegra/board-roth-power.c deleted file mode 100644 index 195c55f91692..000000000000 --- a/arch/arm/mach-tegra/board-roth-power.c +++ /dev/null @@ -1,882 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-power.c - * - * Copyright (c) 2012-2014 NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/i2c.h> -#include <linux/pda_power.h> -#include <linux/platform_device.h> -#include <linux/resource.h> -#include <linux/io.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/driver.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/palmas.h> -#include <linux/power/power_supply_extcon.h> -#include <linux/regulator/tps51632-regulator.h> -#include <linux/power/bq2419x-charger.h> -#include <linux/max17048_battery.h> -#include <linux/gpio.h> -#include <linux/regulator/userspace-consumer.h> -#include <linux/tegra-soc.h> -#include <linux/tegra-pmc.h> - -#include <asm/mach-types.h> - -#include <mach/irqs.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> - -#include "cpu-tegra.h" -#include "pm.h" -#include "tegra-board-id.h" -#include "board-pmu-defines.h" -#include "board.h" -#include "gpio-names.h" -#include "board-roth.h" -#include "tegra_cl_dvfs.h" -#include "devices.h" -#include "tegra11_soctherm.h" -#include "iomap.h" -#include "battery-ini-model-data.h" - -#define PMC_CTRL 0x0 -#define PMC_CTRL_INTR_LOW (1 << 17) - -/* TPS51632 DC-DC converter */ -static struct regulator_consumer_supply tps51632_dcdc_supply[] = { - REGULATOR_SUPPLY("vdd_cpu", NULL), -}; - -static struct regulator_init_data tps51632_init_data = { - .constraints = { \ - .min_uV = 500000, \ - .max_uV = 1520000, \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = 1, \ - .boot_on = 1, \ - .apply_uV = 0, \ - }, \ - .num_consumer_supplies = ARRAY_SIZE(tps51632_dcdc_supply), \ - .consumer_supplies = tps51632_dcdc_supply, \ -}; - -static struct tps51632_regulator_platform_data tps51632_pdata = { - .reg_init_data = &tps51632_init_data, - .enable_pwm_dvfs = false, - .max_voltage_uV = 1520000, - .base_voltage_uV = 500000, -/* .slew_rate_uv_per_us = 6000, */ -}; - -static struct i2c_board_info __initdata tps51632_boardinfo[] = { - { - I2C_BOARD_INFO("tps51632", 0x43), - .platform_data = &tps51632_pdata, - }, -}; - -/* BQ2419X VBUS regulator */ -static struct regulator_consumer_supply bq2419x_vbus_supply[] = { - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.0"), - REGULATOR_SUPPLY("usb_vbus", "tegra-otg"), -}; - -static struct regulator_consumer_supply bq2419x_batt_supply[] = { - REGULATOR_SUPPLY("usb_bat_chg", "tegra-udc.0"), -}; - -static struct bq2419x_vbus_platform_data bq2419x_vbus_pdata = { - .gpio_otg_iusb = TEGRA_GPIO_PI4, - .num_consumer_supplies = ARRAY_SIZE(bq2419x_vbus_supply), - .consumer_supplies = bq2419x_vbus_supply, -}; - -struct bq2419x_charger_platform_data bq2419x_charger_pdata = { - .max_charge_current_mA = 3000, - .termination_current_limit_mA = 100, - .consumer_supplies = bq2419x_batt_supply, - .num_consumer_supplies = ARRAY_SIZE(bq2419x_batt_supply), - .wdt_timeout = 40, - .rtc_alarm_time = 3600, - .chg_restart_time = 1800, -}; - -struct bq2419x_platform_data bq2419x_pdata = { - .vbus_pdata = &bq2419x_vbus_pdata, - .bcharger_pdata = &bq2419x_charger_pdata, -}; - -static struct i2c_board_info __initdata bq2419x_boardinfo[] = { - { - I2C_BOARD_INFO("bq2419x", 0x6b), - .platform_data = &bq2419x_pdata, - }, -}; - -static struct max17048_platform_data max17048_pdata; - -static struct i2c_board_info __initdata max17048_boardinfo[] = { - { - I2C_BOARD_INFO("max17048", 0x36), - .platform_data = &max17048_pdata, - }, -}; - -static struct power_supply_extcon_plat_data psy_extcon_pdata = { - .extcon_name = "tegra-udc", -}; - -static struct platform_device psy_extcon_device = { - .name = "power-supply-extcon", - .id = -1, - .dev = { - .platform_data = &psy_extcon_pdata, - }, -}; - -/************************ Palmas based regulator ****************/ -static struct regulator_consumer_supply palmas_smps12_supply[] = { - REGULATOR_SUPPLY("vddio_ddr0", NULL), - REGULATOR_SUPPLY("vddio_ddr1", NULL), -}; - -static struct regulator_consumer_supply palmas_smps3_supply[] = { - REGULATOR_SUPPLY("avdd_osc", NULL), - REGULATOR_SUPPLY("vddio_sys", NULL), - REGULATOR_SUPPLY("vddio_gmi", NULL), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.1"), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.0"), - REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), - REGULATOR_SUPPLY("vccq", "sdhci-tegra.3"), - REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), - REGULATOR_SUPPLY("vddio_audio", NULL), - REGULATOR_SUPPLY("pwrdet_audio", NULL), - REGULATOR_SUPPLY("avdd_audio_1v8", NULL), - REGULATOR_SUPPLY("vdd_audio_1v8", NULL), - REGULATOR_SUPPLY("vddio_uart", NULL), - REGULATOR_SUPPLY("pwrdet_uart", NULL), - REGULATOR_SUPPLY("pwrdet_nand", NULL), - REGULATOR_SUPPLY("pwrdet_bb", NULL), - REGULATOR_SUPPLY("pwrdet_cam", NULL), - REGULATOR_SUPPLY("dbvdd", NULL), - REGULATOR_SUPPLY("vlogic", "0-0068"), -}; - -static struct regulator_consumer_supply palmas_smps45_supply[] = { - REGULATOR_SUPPLY("vdd_core", NULL), -}; - -#define palmas_smps457_supply palmas_smps45_supply - -static struct regulator_consumer_supply palmas_smps8_supply[] = { - REGULATOR_SUPPLY("avdd_plla_p_c", NULL), - REGULATOR_SUPPLY("avdd_pllx", NULL), - REGULATOR_SUPPLY("avdd_pllm", NULL), - REGULATOR_SUPPLY("avdd_pllu", NULL), - REGULATOR_SUPPLY("avdd_plle", NULL), - REGULATOR_SUPPLY("vdd_ddr_hs", NULL), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.0"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "tegradc.1"), - REGULATOR_SUPPLY("avdd_csi_dsi_pll", "vi"), - REGULATOR_SUPPLY("avdd_usb_pll", "tegra-ehci.2"), - REGULATOR_SUPPLY("avddio_usb", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply palmas_smps9_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.3"), -}; - -static struct regulator_consumer_supply palmas_smps10_out2_supply[] = { - REGULATOR_SUPPLY("vdd_vbrtr", NULL), - REGULATOR_SUPPLY("vdd_5v0", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo2_supply[] = { - REGULATOR_SUPPLY("avdd_lcd", NULL), - REGULATOR_SUPPLY("vci_2v8", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo3_supply[] = { - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.0"), - REGULATOR_SUPPLY("avdd_dsi_csi", "tegradc.1"), - REGULATOR_SUPPLY("avdd_dsi_csi", "vi"), - REGULATOR_SUPPLY("pwrdet_mipi", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo4_supply[] = { - REGULATOR_SUPPLY("vpp_fuse", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo5_supply[] = { - REGULATOR_SUPPLY("avdd_hdmi_pll", "tegradc.1"), -}; - -static struct regulator_consumer_supply palmas_ldo6_supply[] = { - REGULATOR_SUPPLY("vdd_sensor_2v85", NULL), - REGULATOR_SUPPLY("vdd", "0-004c"), - REGULATOR_SUPPLY("vdd", "1-004c"), - REGULATOR_SUPPLY("vdd", "1-004d"), - REGULATOR_SUPPLY("vdd", "0-0068"), -}; - -static struct regulator_consumer_supply palmas_ldo8_supply[] = { - REGULATOR_SUPPLY("vdd_rtc", NULL), -}; - -static struct regulator_consumer_supply palmas_ldo9_supply[] = { - REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.2"), - REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), -}; - -static struct regulator_consumer_supply palmas_ldousb_supply[] = { - REGULATOR_SUPPLY("avdd_usb", "tegra-udc.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.0"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.1"), - REGULATOR_SUPPLY("avdd_usb", "tegra-ehci.2"), - REGULATOR_SUPPLY("avdd_hdmi", "tegradc.1"), - REGULATOR_SUPPLY("vddio_hv", "tegradc.1"), - REGULATOR_SUPPLY("pwrdet_hv", NULL), -}; - -static struct regulator_consumer_supply palmas_regen1_supply[] = { - REGULATOR_SUPPLY("vdd_3v3_sys", NULL), - REGULATOR_SUPPLY("vdd", "4-004c"), - REGULATOR_SUPPLY("vdd", "0-004d"), - REGULATOR_SUPPLY("usb_vbus", "tegra-ehci.2"), -}; - -static struct regulator_consumer_supply palmas_regen2_supply[] = { - REGULATOR_SUPPLY("vdd_5v0_sys", NULL), -}; - -PALMAS_PDATA_INIT(smps12, 1200, 1500, NULL, 0, 0, 0, NORMAL); -PALMAS_PDATA_INIT(smps3, 1800, 1800, NULL, 0, 0, 0, NORMAL); -PALMAS_PDATA_INIT(smps45, 900, 1400, NULL, 1, 1, 0, NORMAL); -PALMAS_PDATA_INIT(smps457, 900, 1400, NULL, 1, 1, 0, NORMAL); -PALMAS_PDATA_INIT(smps8, 1050, 1050, NULL, 1, 1, 1, NORMAL); -PALMAS_PDATA_INIT(smps9, 2800, 2800, NULL, 0, 0, 0, NORMAL); -PALMAS_PDATA_INIT(smps10_out2, 5000, 5000, NULL, 0, 0, 0, 0); -PALMAS_PDATA_INIT(ldo2, 2800, 2800, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(ldo3, 1200, 1200, NULL, 1, 1, 1, 0); -PALMAS_PDATA_INIT(ldo4, 1800, 1800, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(ldo5, 1200, 1200, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(ldo6, 2850, 2850, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(ldo8, 900, 900, NULL, 1, 1, 1, 0); -PALMAS_PDATA_INIT(ldo9, 1800, 3300, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(ldousb, 3300, 3300, NULL, 0, 0, 1, 0); -PALMAS_PDATA_INIT(regen1, 3300, 3300, NULL, 0, 0, 0, 0); -PALMAS_PDATA_INIT(regen2, 5000, 5000, NULL, 0, 0, 0, 0); - -#define PALMAS_REG_PDATA(_sname) ®_idata_##_sname -static struct regulator_init_data *roth_reg_data[PALMAS_NUM_REGS] = { - PALMAS_REG_PDATA(smps12), - NULL, - PALMAS_REG_PDATA(smps3), - PALMAS_REG_PDATA(smps45), - PALMAS_REG_PDATA(smps457), - NULL, - NULL, - PALMAS_REG_PDATA(smps8), - PALMAS_REG_PDATA(smps9), - PALMAS_REG_PDATA(smps10_out2), - NULL, - NULL, /* LDO1 */ - PALMAS_REG_PDATA(ldo2), - PALMAS_REG_PDATA(ldo3), - PALMAS_REG_PDATA(ldo4), - PALMAS_REG_PDATA(ldo5), - PALMAS_REG_PDATA(ldo6), - NULL, - PALMAS_REG_PDATA(ldo8), - PALMAS_REG_PDATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_PDATA(ldousb), - PALMAS_REG_PDATA(regen1), - PALMAS_REG_PDATA(regen2), - NULL, - NULL, - NULL, -}; - -#define PALMAS_REG_INIT(_name, _warm_reset, _roof_floor, _mode_sleep, \ - _vsel) \ - static struct palmas_reg_init reg_init_data_##_name = { \ - .warm_reset = _warm_reset, \ - .roof_floor = _roof_floor, \ - .mode_sleep = _mode_sleep, \ - .vsel = _vsel, \ - } - -PALMAS_REG_INIT(smps12, 0, 0, 0, 0); -PALMAS_REG_INIT(smps123, 0, 0, 0, 0); -PALMAS_REG_INIT(smps3, 0, 0, 0, 0); -PALMAS_REG_INIT(smps45, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0); -PALMAS_REG_INIT(smps457, 0, PALMAS_EXT_CONTROL_NSLEEP, 0, 0); -PALMAS_REG_INIT(smps6, 0, 0, 0, 0); -PALMAS_REG_INIT(smps7, 0, 0, 0, 0); -PALMAS_REG_INIT(smps8, 0, 0, 0, 0); -PALMAS_REG_INIT(smps9, 0, 0, 0, 0); -PALMAS_REG_INIT(smps10_out2, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo1, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo2, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo3, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo4, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo5, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo6, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo7, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo8, 0, 0, 0, 0); -PALMAS_REG_INIT(ldo9, 0, 0, 0, 0); -PALMAS_REG_INIT(ldoln, 0, 0, 0, 0); -PALMAS_REG_INIT(ldousb, 0, 0, 0, 0); -PALMAS_REG_INIT(regen1, 0, 0, 0, 0); -PALMAS_REG_INIT(regen2, 0, 0, 0, 0); -PALMAS_REG_INIT(regen3, 0, 0, 0, 0); -PALMAS_REG_INIT(sysen1, 0, 0, 0, 0); -PALMAS_REG_INIT(sysen2, 0, 0, 0, 0); - -#define PALMAS_REG_INIT_DATA(_sname) ®_init_data_##_sname -static struct palmas_reg_init *roth_reg_init[PALMAS_NUM_REGS] = { - PALMAS_REG_INIT_DATA(smps12), - PALMAS_REG_INIT_DATA(smps123), - PALMAS_REG_INIT_DATA(smps3), - PALMAS_REG_INIT_DATA(smps45), - PALMAS_REG_INIT_DATA(smps457), - PALMAS_REG_INIT_DATA(smps6), - PALMAS_REG_INIT_DATA(smps7), - PALMAS_REG_INIT_DATA(smps8), - PALMAS_REG_INIT_DATA(smps9), - PALMAS_REG_INIT_DATA(smps10_out2), - NULL, - PALMAS_REG_INIT_DATA(ldo1), - PALMAS_REG_INIT_DATA(ldo2), - PALMAS_REG_INIT_DATA(ldo3), - PALMAS_REG_INIT_DATA(ldo4), - PALMAS_REG_INIT_DATA(ldo5), - PALMAS_REG_INIT_DATA(ldo6), - PALMAS_REG_INIT_DATA(ldo7), - PALMAS_REG_INIT_DATA(ldo8), - PALMAS_REG_INIT_DATA(ldo9), - NULL, - NULL, - NULL, - NULL, - NULL, - PALMAS_REG_INIT_DATA(ldoln), - PALMAS_REG_INIT_DATA(ldousb), - PALMAS_REG_INIT_DATA(regen1), - PALMAS_REG_INIT_DATA(regen2), - PALMAS_REG_INIT_DATA(regen3), - PALMAS_REG_INIT_DATA(sysen1), - PALMAS_REG_INIT_DATA(sysen2), -}; - -static struct palmas_pmic_platform_data pmic_platform = { -}; - -static struct palmas_pinctrl_config palmas_pincfg[] = { - PALMAS_PINMUX("powergood", "powergood", NULL, NULL), - PALMAS_PINMUX("vac", "vac", NULL, NULL), - PALMAS_PINMUX("gpio0", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio1", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio2", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio3", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio4", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio5", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio6", "gpio", NULL, NULL), - PALMAS_PINMUX("gpio7", "gpio", NULL, NULL), -}; - -static struct palmas_pinctrl_platform_data palmas_pinctrl_pdata = { - .pincfg = palmas_pincfg, - .num_pinctrl = ARRAY_SIZE(palmas_pincfg), - .dvfs1_enable = true, - .dvfs2_enable = false, -}; - -static struct palmas_platform_data palmas_pdata = { - .gpio_base = PALMAS_TEGRA_GPIO_BASE, - .irq_base = PALMAS_TEGRA_IRQ_BASE, - .pmic_pdata = &pmic_platform, - .pinctrl_pdata = &palmas_pinctrl_pdata, -}; - -static struct i2c_board_info palma_device[] = { - { - I2C_BOARD_INFO("tps65913", 0x58), - .irq = INT_EXTERNAL_PMU, - .platform_data = &palmas_pdata, - }, -}; - -static struct regulator_consumer_supply fixed_reg_vdd_hdmi_5v0_supply[] = { - REGULATOR_SUPPLY("vdd_hdmi_5v0", "tegradc.1"), -}; - -static struct regulator_consumer_supply fixed_reg_fan_5v0_supply[] = { - REGULATOR_SUPPLY("fan_5v0", NULL), -}; - -/* LCD_BL_EN GMI_AD10 */ -static struct regulator_consumer_supply fixed_reg_lcd_bl_en_supply[] = { - REGULATOR_SUPPLY("vdd_lcd_bl_en", NULL), -}; - -/* VDD_3V3_COM controled by Wifi */ -static struct regulator_consumer_supply fixed_reg_com_3v3_supply[] = { - REGULATOR_SUPPLY("avdd", "bcm4329_wlan.1"), - REGULATOR_SUPPLY("avdd", "bluedroid_pm.0"), - REGULATOR_SUPPLY("vdd_wl_pa", "reg-userspace-consumer.2"), -}; - -/* VDD_1v8_COM controled by Wifi */ -static struct regulator_consumer_supply fixed_reg_com_1v8_supply[] = { - REGULATOR_SUPPLY("dvdd", "bcm4329_wlan.1"), - REGULATOR_SUPPLY("dvdd", "bluedroid_pm.0"), - REGULATOR_SUPPLY("vddio", "reg-userspace-consumer.2"), -}; - -/* vdd_3v3_sd PH0 */ -static struct regulator_consumer_supply fixed_reg_sd_3v3_supply[] = { - REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.2"), -}; - -/* EN_3V3_TS From TEGRA_GPIO_PH5 */ -static struct regulator_consumer_supply fixed_reg_avdd_ts_supply[] = { - REGULATOR_SUPPLY("avdd", "spi3.2"), -}; - -/* EN_1V8_TS From TEGRA_GPIO_PK3 */ -static struct regulator_consumer_supply fixed_reg_dvdd_ts_supply[] = { - REGULATOR_SUPPLY("dvdd", "spi3.2"), -}; - -/* EN_1V8_TS From TEGRA_GPIO_PU4 */ -static struct regulator_consumer_supply fixed_reg_dvdd_lcd_supply[] = { - REGULATOR_SUPPLY("dvdd_lcd", NULL), -}; -/* Macro for defining fixed regulator sub device data */ -#define FIXED_SUPPLY(_name) "fixed_reg_"#_name -#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ - _gpio_nr, _open_drain, _active_high, _boot_state, _millivolts) \ - static struct regulator_init_data ri_data_##_var = \ - { \ - .supply_regulator = _in_supply, \ - .num_consumer_supplies = \ - ARRAY_SIZE(fixed_reg_##_name##_supply), \ - .consumer_supplies = fixed_reg_##_name##_supply, \ - .constraints = { \ - .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ - REGULATOR_MODE_STANDBY), \ - .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ - REGULATOR_CHANGE_STATUS | \ - REGULATOR_CHANGE_VOLTAGE), \ - .always_on = _always_on, \ - .boot_on = _boot_on, \ - }, \ - }; \ - static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ - { \ - .supply_name = FIXED_SUPPLY(_name), \ - .microvolts = _millivolts * 1000, \ - .gpio = _gpio_nr, \ - .gpio_is_open_drain = _open_drain, \ - .enable_high = _active_high, \ - .enabled_at_boot = _boot_state, \ - .init_data = &ri_data_##_var, \ - }; \ - static struct platform_device fixed_reg_##_var##_dev = { \ - .name = "reg-fixed-voltage", \ - .id = _id, \ - .dev = { \ - .platform_data = &fixed_reg_##_var##_pdata, \ - }, \ - } - -FIXED_REG(0, fan_5v0, fan_5v0, - palmas_rails(smps10_out2), 0, 0, - PALMAS_TEGRA_GPIO_BASE + PALMAS_GPIO6, false, true, 0, 5000); - -FIXED_REG(1, vdd_hdmi_5v0, vdd_hdmi_5v0, - palmas_rails(smps10_out2), 0, 0, - TEGRA_GPIO_PK1, false, true, 0, 5000); - -FIXED_REG(2, lcd_bl_en, lcd_bl_en, - NULL, 0, 0, - TEGRA_GPIO_PH2, false, true, 1, 5000); - -FIXED_REG(3, avdd_ts, avdd_ts, - palmas_rails(regen1), 0, 0, - TEGRA_GPIO_PH5, false, true, 0, 3300); - -FIXED_REG(4, dvdd_ts, dvdd_ts, - palmas_rails(smps3), 0, 0, - TEGRA_GPIO_PK3, false, true, 0, 1800); - -FIXED_REG(5, com_3v3, com_3v3, - palmas_rails(regen1), 0, 0, - TEGRA_GPIO_PX7, false, true, 0, 3300); - -FIXED_REG(6, sd_3v3, sd_3v3, - palmas_rails(regen1), 0, 0, - TEGRA_GPIO_PH0, false, true, 0, 3300); - -FIXED_REG(7, com_1v8, com_1v8, - palmas_rails(smps3), 0, 0, - TEGRA_GPIO_PX1, false, true, 0, 1800); - -FIXED_REG(8, dvdd_lcd, dvdd_lcd, - palmas_rails(smps3), 0, 0, - TEGRA_GPIO_PU4, false, true, 1, 1800); - -/* - * Creating the fixed regulator device tables - */ - -#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) - -#define ROTH_COMMON_FIXED_REG \ - ADD_FIXED_REG(usb1_vbus), \ - ADD_FIXED_REG(usb3_vbus), \ - ADD_FIXED_REG(vdd_hdmi_5v0), - -#define E1612_FIXED_REG \ - ADD_FIXED_REG(avdd_usb_hdmi), \ - ADD_FIXED_REG(en_1v8_cam), \ - ADD_FIXED_REG(vpp_fuse), \ - -#define ROTH_FIXED_REG \ - ADD_FIXED_REG(en_1v8_cam_roth), - -/* Gpio switch regulator platform data for Roth */ -static struct platform_device *fixed_reg_devs_roth[] = { - ADD_FIXED_REG(fan_5v0), - ADD_FIXED_REG(vdd_hdmi_5v0), - ADD_FIXED_REG(lcd_bl_en), - ADD_FIXED_REG(avdd_ts), - ADD_FIXED_REG(dvdd_ts), - ADD_FIXED_REG(com_3v3), - ADD_FIXED_REG(sd_3v3), - ADD_FIXED_REG(com_1v8), - ADD_FIXED_REG(dvdd_lcd), -}; - -int __init roth_palmas_regulator_init(void) -{ - void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); - u32 pmc_ctrl; - int i; - - /* TPS65913: Normal state of INT request line is LOW. - * configure the power management controller to trigger PMU - * interrupts when HIGH. - */ - pmc_ctrl = readl(pmc + PMC_CTRL); - writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); - - /* Tracking configuration */ - reg_init_data_ldo8.config_flags = - PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE | - PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE; - - for (i = 0; i < PALMAS_NUM_REGS ; i++) { - pmic_platform.reg_data[i] = roth_reg_data[i]; - pmic_platform.reg_init[i] = roth_reg_init[i]; - } - - i2c_register_board_info(4, palma_device, - ARRAY_SIZE(palma_device)); - return 0; -} - -static int ac_online(void) -{ - return 1; -} - -static struct resource roth_pda_resources[] = { - [0] = { - .name = "ac", - }, -}; - -static struct pda_power_pdata roth_pda_data = { - .is_ac_online = ac_online, -}; - -static struct platform_device roth_pda_power_device = { - .name = "pda-power", - .id = -1, - .resource = roth_pda_resources, - .num_resources = ARRAY_SIZE(roth_pda_resources), - .dev = { - .platform_data = &roth_pda_data, - }, -}; - -static struct tegra_suspend_platform_data roth_suspend_data = { - .cpu_timer = 500, - .cpu_off_timer = 300, - .suspend_mode = TEGRA_SUSPEND_LP0, - .core_timer = 0x157e, - .core_off_timer = 2000, - .corereq_high = true, - .sysclkreq_high = true, - .cpu_lp2_min_residency = 1000, - .min_residency_crail = 20000, -#ifdef CONFIG_TEGRA_LP1_LOW_COREVOLTAGE - .lp1_lowvolt_support = false, - .i2c_base_addr = 0, - .pmuslave_addr = 0, - .core_reg_addr = 0, - .lp1_core_volt_low_cold = 0, - .lp1_core_volt_low = 0, - .lp1_core_volt_high = 0, -#endif -}; -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -/* board parameters for cpu dfll */ -static struct tegra_cl_dvfs_cfg_param roth_cl_dvfs_param = { - .sample_rate = 12500, - - .force_mode = TEGRA_CL_DVFS_FORCE_FIXED, - .cf = 10, - .ci = 0, - .cg = 2, - - .droop_cut_value = 0xF, - .droop_restore_ramp = 0x0, - .scale_out_ramp = 0x0, -}; -#endif - -/* TPS51632: fixed 10mV steps from 600mV to 1400mV, with offset 0x23 */ -#define PMU_CPU_VDD_MAP_SIZE ((1400000 - 600000) / 10000 + 1) -static struct voltage_reg_map pmu_cpu_vdd_map[PMU_CPU_VDD_MAP_SIZE]; -static inline void fill_reg_map(void) -{ - int i; - for (i = 0; i < PMU_CPU_VDD_MAP_SIZE; i++) { - pmu_cpu_vdd_map[i].reg_value = i + 0x23; - pmu_cpu_vdd_map[i].reg_uV = 600000 + 10000 * i; - } -} - -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS -static struct tegra_cl_dvfs_platform_data roth_cl_dvfs_data = { - .dfll_clk_name = "dfll_cpu", - .pmu_if = TEGRA_CL_DVFS_PMU_I2C, - .u.pmu_i2c = { - .fs_rate = 400000, - .slave_addr = 0x86, - .reg = 0x00, - }, - .vdd_map = pmu_cpu_vdd_map, - .vdd_map_size = PMU_CPU_VDD_MAP_SIZE, - - .cfg_param = &roth_cl_dvfs_param, -}; - -static int __init roth_cl_dvfs_init(void) -{ - fill_reg_map(); - if (tegra_revision < TEGRA_REVISION_A02) - roth_cl_dvfs_data.flags = TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET; - tegra_cl_dvfs_device.dev.platform_data = &roth_cl_dvfs_data; - platform_device_register(&tegra_cl_dvfs_device); - - return 0; -} -#endif - -static int __init roth_fixed_regulator_init(void) -{ - if (!machine_is_roth()) - return 0; - - return platform_add_devices(fixed_reg_devs_roth, - ARRAY_SIZE(fixed_reg_devs_roth)); -} -subsys_initcall_sync(roth_fixed_regulator_init); - -int __init roth_regulator_init(void) -{ - struct board_info board_info; -#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS - roth_cl_dvfs_init(); -#endif - tegra_get_board_info(&board_info); - - if (board_info.board_id == BOARD_P2560) - max17048_pdata.model_data = &max17048_mdata_p2560; - else - max17048_pdata.model_data = &max17048_mdata_p2454; - - roth_palmas_regulator_init(); - - bq2419x_boardinfo[0].irq = gpio_to_irq(TEGRA_GPIO_PJ0); - i2c_register_board_info(4, tps51632_boardinfo, 1); - i2c_register_board_info(0, max17048_boardinfo, 1); - i2c_register_board_info(0, bq2419x_boardinfo, 1); - platform_device_register(&psy_extcon_device); - platform_device_register(&roth_pda_power_device); - return 0; -} - -int __init roth_suspend_init(void) -{ - tegra_init_suspend(&roth_suspend_data); - return 0; -} - -int __init roth_edp_init(void) -{ - unsigned int regulator_mA; - - regulator_mA = get_maximum_cpu_current_supported(); - if (!regulator_mA) - regulator_mA = 15000; - - pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); - tegra_init_cpu_edp_limits(regulator_mA); - - regulator_mA = get_maximum_core_current_supported(); - if (!regulator_mA) - regulator_mA = 4000; - - pr_info("%s: core regulator %d mA\n", __func__, regulator_mA); - tegra_init_core_edp_limits(regulator_mA); - - return 0; -} - -static struct tegra_thermtrip_pmic_data tpdata_palmas = { - .reset_tegra = 1, - .pmu_16bit_ops = 0, - .controller_type = 0, - .pmu_i2c_addr = 0x58, - .i2c_controller_id = 4, - .poweroff_reg_addr = 0xa0, - .poweroff_reg_data = 0x0, -}; - -static struct soctherm_platform_data roth_soctherm_data = { - .therm = { - [THERM_CPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 0, /* Disables the trips config below */ - /* - * Following .trips config retained for compatibility - * with dalmore/pluto and later enablement when needed - */ - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - }, - [THERM_GPU] = { - .zone_enable = true, - .passive_delay = 1000, - .hotspot_offset = 6000, - .num_trips = 0, /* Disables the trips config below */ - /* - * Following .trips config retained for compatibility - * with dalmore/pluto and later enablement when needed - */ - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 90000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-heavy", - .trip_temp = 100000, - .trip_type = THERMAL_TRIP_HOT, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 102000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - }, - }, - }, - [THERM_PLL] = { - .zone_enable = true, - }, - }, - .throttle = { - [THROTTLE_HEAVY] = { - .priority = 100, - .devs = { - [THROTTLE_DEV_CPU] = { - .enable = true, - .depth = 80, - }, - [THROTTLE_DEV_GPU] = { - .enable = true, - .depth = 80, - }, - }, - }, - }, - .tshut_pmu_trip_data = &tpdata_palmas, -}; - -int __init roth_soctherm_init(void) -{ - return tegra11_soctherm_init(&roth_soctherm_data); -} diff --git a/arch/arm/mach-tegra/board-roth-sdhci.c b/arch/arm/mach-tegra/board-roth-sdhci.c deleted file mode 100644 index a61e450d7b0c..000000000000 --- a/arch/arm/mach-tegra/board-roth-sdhci.c +++ /dev/null @@ -1,460 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-sdhci.c - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012-2013 NVIDIA Corporation. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/resource.h> -#include <linux/platform_device.h> -#include <linux/wlan_plat.h> -#include <linux/delay.h> -#include <linux/gpio.h> -#include <linux/clk.h> -#include <linux/err.h> -#include <linux/regulator/consumer.h> -#include <linux/mmc/host.h> -#include <linux/wl12xx.h> -#include <linux/platform_data/mmc-sdhci-tegra.h> - -#include <asm/mach-types.h> -#include <mach/irqs.h> -#include<mach/gpio-tegra.h> -#include <mach/io_dpd.h> - -#include "dvfs.h" -#include "gpio-names.h" -#include "board.h" -#include "board-roth.h" -#include "iomap.h" - -#define ROTH_WLAN_PWR TEGRA_GPIO_PCC5 -#define ROTH_WLAN_RST TEGRA_GPIO_INVALID -#define ROTH_WLAN_WOW TEGRA_GPIO_PU5 -#define ROTH_SD_CD TEGRA_GPIO_PV2 -#define WLAN_PWR_STR "wlan_power" -#define WLAN_WOW_STR "bcmsdh_sdmmc" - -static void (*wifi_status_cb)(int card_present, void *dev_id); -static void *wifi_status_cb_devid; -static int roth_wifi_status_register(void (*callback)(int , void *), void *); - -static int roth_wifi_reset(int on); -static int roth_wifi_power(int on); -static int roth_wifi_set_carddetect(int val); - -static struct wifi_platform_data roth_wifi_control = { - .set_power = roth_wifi_power, - .set_reset = roth_wifi_reset, - .set_carddetect = roth_wifi_set_carddetect, -}; - -static struct resource wifi_resource[] = { - [0] = { - .name = "bcm4329_wlan_irq", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL - | IORESOURCE_IRQ_SHAREABLE, - }, -}; - -static struct platform_device roth_wifi_device = { - .name = "bcm4329_wlan", - .id = 1, - .num_resources = 1, - .resource = wifi_resource, - .dev = { - .platform_data = &roth_wifi_control, - }, -}; - -static struct resource sdhci_resource0[] = { - [0] = { - .start = INT_SDMMC1, - .end = INT_SDMMC1, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC1_BASE, - .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource2[] = { - [0] = { - .start = INT_SDMMC3, - .end = INT_SDMMC3, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC3_BASE, - .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource sdhci_resource3[] = { - [0] = { - .start = INT_SDMMC4, - .end = INT_SDMMC4, - .flags = IORESOURCE_IRQ, - }, - [1] = { - .start = TEGRA_SDMMC4_BASE, - .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1, - .flags = IORESOURCE_MEM, - }, -}; - -#ifdef CONFIG_MMC_EMBEDDED_SDIO -static struct embedded_sdio_data embedded_sdio_data0 = { - .cccr = { - .sdio_vsn = 2, - .multi_block = 1, - .low_speed = 0, - .wide_bus = 0, - .high_power = 1, - .high_speed = 1, - }, - .cis = { - .vendor = 0x02d0, - .device = 0x4324, - }, -}; -#endif - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = { - .mmc_data = { - .register_status_notify = roth_wifi_status_register, -#ifdef CONFIG_MMC_EMBEDDED_SDIO - .embedded_sdio = &embedded_sdio_data0, -#endif - .built_in = 0, - .ocr_mask = MMC_OCR_1V8_MASK, - }, -#ifndef CONFIG_MMC_EMBEDDED_SDIO - .pm_flags = MMC_PM_KEEP_POWER, -#endif - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x2, - .trim_delay = 0x2, - .ddr_clk_limit = 41000000, - .uhs_mask = MMC_UHS_MASK_DDR50, - .disable_clock_gate = true, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = { - .cd_gpio = ROTH_SD_CD, - .wp_gpio = -1, - .power_gpio = -1, - .tap_delay = 0x3, - .trim_delay = 0x3, - .ddr_clk_limit = 41000000, - .uhs_mask = MMC_UHS_MASK_DDR50, - .power_off_rail = true, -}; - -static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = { - .cd_gpio = -1, - .wp_gpio = -1, - .power_gpio = -1, - .is_8bit = 1, - .tap_delay = 0x5, - .trim_delay = 0xA, - .ddr_trim_delay = -1, - .ddr_clk_limit = 41000000, - .max_clk_limit = 156000000, - .mmc_data = { - .built_in = 1, - } -}; - -static struct platform_device tegra_sdhci_device0 = { - .name = "sdhci-tegra", - .id = 0, - .resource = sdhci_resource0, - .num_resources = ARRAY_SIZE(sdhci_resource0), - .dev = { - .platform_data = &tegra_sdhci_platform_data0, - }, -}; - -static struct platform_device tegra_sdhci_device2 = { - .name = "sdhci-tegra", - .id = 2, - .resource = sdhci_resource2, - .num_resources = ARRAY_SIZE(sdhci_resource2), - .dev = { - .platform_data = &tegra_sdhci_platform_data2, - }, -}; - -static struct platform_device tegra_sdhci_device3 = { - .name = "sdhci-tegra", - .id = 3, - .resource = sdhci_resource3, - .num_resources = ARRAY_SIZE(sdhci_resource3), - .dev = { - .platform_data = &tegra_sdhci_platform_data3, - }, -}; - -static int roth_wifi_status_register( - void (*callback)(int card_present, void *dev_id), - void *dev_id) -{ - if (wifi_status_cb) - return -EAGAIN; - wifi_status_cb = callback; - wifi_status_cb_devid = dev_id; - return 0; -} - -static int roth_wifi_set_carddetect(int val) -{ - pr_debug("%s: %d\n", __func__, val); - if (wifi_status_cb) - wifi_status_cb(val, wifi_status_cb_devid); - else - pr_warning("%s: Nobody to notify\n", __func__); - return 0; -} - -static struct regulator *roth_vdd_com_3v3; -static struct regulator *roth_vddio_com_1v8; -#define ROTH_VDD_WIFI_3V3 "avdd" -#define ROTH_VDD_WIFI_1V8 "dvdd" - - -static int roth_wifi_regulator_enable(void) -{ - int ret = 0; - - /* Enable COM's vdd_com_3v3 regulator*/ - if (IS_ERR_OR_NULL(roth_vdd_com_3v3)) { - roth_vdd_com_3v3 = regulator_get(&roth_wifi_device.dev, - ROTH_VDD_WIFI_3V3); - if (IS_ERR(roth_vdd_com_3v3)) { - pr_err("Couldn't get regulator " - ROTH_VDD_WIFI_3V3 "\n"); - return PTR_ERR(roth_vdd_com_3v3); - } - - ret = regulator_enable(roth_vdd_com_3v3); - if (ret < 0) { - pr_err("Couldn't enable regulator " - ROTH_VDD_WIFI_3V3 "\n"); - regulator_put(roth_vdd_com_3v3); - roth_vdd_com_3v3 = NULL; - return ret; - } - } - - /* Enable COM's vddio_com_1v8 regulator*/ - if (IS_ERR_OR_NULL(roth_vddio_com_1v8)) { - roth_vddio_com_1v8 = regulator_get(&roth_wifi_device.dev, - ROTH_VDD_WIFI_1V8); - if (IS_ERR(roth_vddio_com_1v8)) { - pr_err("Couldn't get regulator " - ROTH_VDD_WIFI_1V8 "\n"); - regulator_disable(roth_vdd_com_3v3); - - regulator_put(roth_vdd_com_3v3); - roth_vdd_com_3v3 = NULL; - return PTR_ERR(roth_vddio_com_1v8); - } - - ret = regulator_enable(roth_vddio_com_1v8); - if (ret < 0) { - pr_err("Couldn't enable regulator " - ROTH_VDD_WIFI_1V8 "\n"); - regulator_put(roth_vddio_com_1v8); - roth_vddio_com_1v8 = NULL; - - regulator_disable(roth_vdd_com_3v3); - regulator_put(roth_vdd_com_3v3); - roth_vdd_com_3v3 = NULL; - return ret; - } - } - - return ret; -} - -static void roth_wifi_regulator_disable(void) -{ - /* Disable COM's vdd_com_3v3 regulator*/ - if (!IS_ERR_OR_NULL(roth_vdd_com_3v3)) { - regulator_disable(roth_vdd_com_3v3); - regulator_put(roth_vdd_com_3v3); - roth_vdd_com_3v3 = NULL; - } - - /* Disable COM's vddio_com_1v8 regulator*/ - if (!IS_ERR_OR_NULL(roth_vddio_com_1v8)) { - regulator_disable(roth_vddio_com_1v8); - regulator_put(roth_vddio_com_1v8); - roth_vddio_com_1v8 = NULL; - } -} - -static int roth_wifi_power(int on) -{ - struct tegra_io_dpd *sd_dpd; - int ret = 0; - - pr_debug("%s: %d\n", __func__, on); - /* Enable COM's regulators on wi-fi poer on*/ - if (on == 1) { - ret = roth_wifi_regulator_enable(); - if (ret < 0) { - pr_err("Failed to enable COM regulators\n"); - return ret; - } - } - - /* - * FIXME : we need to revisit IO DPD code - * on how should multiple pins under DPD get controlled - * - * roth GPIO WLAN enable is part of SDMMC3 pin group - */ - sd_dpd = tegra_io_dpd_get(&tegra_sdhci_device2.dev); - if (sd_dpd) { - mutex_lock(&sd_dpd->delay_lock); - tegra_io_dpd_disable(sd_dpd); - mutex_unlock(&sd_dpd->delay_lock); - } - gpio_set_value(ROTH_WLAN_PWR, on); - mdelay(100); - - if (sd_dpd) { - mutex_lock(&sd_dpd->delay_lock); - tegra_io_dpd_enable(sd_dpd); - mutex_unlock(&sd_dpd->delay_lock); - } - - /* Disable COM's regulators on wi-fi poer off*/ - if (on != 1) { - pr_debug("Disabling COM regulators\n"); - roth_wifi_regulator_disable(); - } - - return ret; -} - -static int roth_wifi_reset(int on) -{ - pr_debug("%s: do nothing\n", __func__); - return 0; -} - -static int __init roth_wifi_init(void) -{ - int rc = 0; - - /* init wlan_pwr gpio */ - rc = gpio_request(ROTH_WLAN_PWR, WLAN_PWR_STR); - /* Due to pre-init, during first time boot, - * gpio request returns -EBUSY - */ - if ((rc < 0) && (rc != -EBUSY)) { - pr_err("gpio req failed:%d\n", rc); - return rc; - } - - rc = gpio_direction_output(ROTH_WLAN_PWR, 0); - if ((rc < 0) && (rc != -EBUSY)) { - gpio_free(ROTH_WLAN_PWR); - return rc; - } - - /* init wlan_wow gpio */ - rc = gpio_request(ROTH_WLAN_WOW, WLAN_WOW_STR); - if (rc) { - pr_err("gpio req failed:%d\n", rc); - gpio_free(ROTH_WLAN_PWR); - return rc; - } - - rc = gpio_direction_input(ROTH_WLAN_WOW); - if (rc) { - gpio_free(ROTH_WLAN_WOW); - gpio_free(ROTH_WLAN_PWR); - return rc; - } - - wifi_resource[0].start = wifi_resource[0].end = - gpio_to_irq(ROTH_WLAN_WOW); - - platform_device_register(&roth_wifi_device); - return rc; -} - -#ifdef CONFIG_TEGRA_PREPOWER_WIFI -static int __init roth_wifi_prepower(void) -{ - if (!machine_is_roth()) - return 0; - - roth_wifi_power(1); - - return 0; -} - -subsys_initcall_sync(roth_wifi_prepower); -#endif - -int __init roth_sdhci_init(void) -{ - int nominal_core_mv; - int min_vcore_override_mv; - int boot_vcore_mv; - - nominal_core_mv = - tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail); - if (nominal_core_mv > 0) { - tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv; - tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv; - tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv; - } - min_vcore_override_mv = - tegra_dvfs_rail_get_override_floor(tegra_core_rail); - if (min_vcore_override_mv) { - tegra_sdhci_platform_data0.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data2.min_vcore_override_mv = - min_vcore_override_mv; - tegra_sdhci_platform_data3.min_vcore_override_mv = - min_vcore_override_mv; - } - boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail); - if (boot_vcore_mv) { - tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv; - tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv; - } - - if ((tegra_sdhci_platform_data3.uhs_mask & MMC_MASK_HS200) - && (!(tegra_sdhci_platform_data3.uhs_mask & - MMC_UHS_MASK_DDR50))) - tegra_sdhci_platform_data3.trim_delay = 0; - - platform_device_register(&tegra_sdhci_device3); - platform_device_register(&tegra_sdhci_device2); - platform_device_register(&tegra_sdhci_device0); - roth_wifi_init(); - return 0; -} diff --git a/arch/arm/mach-tegra/board-roth-sensors.c b/arch/arm/mach-tegra/board-roth-sensors.c deleted file mode 100644 index c7e8ac1585fc..000000000000 --- a/arch/arm/mach-tegra/board-roth-sensors.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth-sensors.c - * - * Copyright (c) 2012-2014 NVIDIA CORPORATION, All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * Neither the name of NVIDIA CORPORATION nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <linux/i2c.h> -#include <linux/delay.h> -#include <linux/mpu.h> -#include <linux/gpio.h> -#include <linux/therm_est.h> -#include <linux/nct1008.h> -#include <mach/edp.h> -#include <mach/gpio-tegra.h> -#include <mach/pinmux-t11.h> -#include <mach/pinmux.h> -#include <generated/mach-types.h> - -#include "gpio-names.h" -#include "board.h" -#include "board-common.h" -#include "board-roth.h" -#include "cpu-tegra.h" -#include "devices.h" -#include "tegra-board-id.h" -#include "dvfs.h" - -static struct throttle_table tj_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle tj_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_throttle_table), - .throt_tab = tj_throttle_table, -}; - -static struct throttle_table tj_hard_throttle_table[] = { - { { 204000, 420000, 360000, 208000, 204000 } }, -}; - -static struct balanced_throttle tj_hard_throttle = { - .throt_tab_size = ARRAY_SIZE(tj_hard_throttle_table), - .throt_tab = tj_hard_throttle_table, -}; - -static int __init roth_throttle_init(void) -{ - if (machine_is_roth()) { - balanced_throttle_register(&tj_throttle, "tegra-balanced"); - balanced_throttle_register(&tj_hard_throttle, "tegra-hard"); - } - - return 0; -} -module_init(roth_throttle_init); - -static struct nct1008_platform_data roth_nct1008_pdata = { - .supported_hwrev = true, - .extended_range = true, - .conv_rate = 0x08, - .loc_name = "soc", - - .sensors = { - [LOC] = { - .shutdown_limit = 120, /* C */ - .num_trips = 0, - .tzp = NULL, - }, - [EXT] = { - .shutdown_limit = 91, /* C */ - .num_trips = 2, - .tzp = NULL, - - .passive_delay = 2000, - - /* Thermal Throttling */ - .trips = { - { - .cdev_type = "tegra-balanced", - .trip_temp = 80000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - .mask = 1, - }, - { - .cdev_type = "tegra-hard", - /*shutdown_limit - 2C*/ - .trip_temp = 86000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = 1, - .lower = 1, - .hysteresis = 6000, - .mask = 1, - }, - { - .cdev_type = "suspend_soctherm", - .trip_temp = 50000, - .trip_type = THERMAL_TRIP_ACTIVE, - .upper = 1, - .lower = 1, - .hysteresis = 5000, - .mask = 1, - } - }, - } - } -}; - -static struct i2c_board_info roth_i2c4_nct1008_board_info[] = { - { - I2C_BOARD_INFO("nct1008", 0x4C), - .platform_data = &roth_nct1008_pdata, - .irq = -1, - } -}; - -#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ - { \ - .pingroup = TEGRA_PINGROUP_##_pingroup, \ - .func = TEGRA_MUX_##_mux, \ - .pupd = TEGRA_PUPD_##_pupd, \ - .tristate = TEGRA_TRI_##_tri, \ - .io = TEGRA_PIN_##_io, \ - .lock = TEGRA_PIN_LOCK_##_lock, \ - .od = TEGRA_PIN_OD_DEFAULT, \ - .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ - } - -/* MPU board file definition */ -static struct mpu_platform_data mpu6050_gyro_data = { - .int_config = 0x10, - .level_shifter = 0, - /* Located in board_[platformname].h */ - .orientation = MPU_GYRO_ORIENTATION, - .sec_slave_type = SECONDARY_SLAVE_TYPE_NONE, - .key = {0x4E, 0xCC, 0x7E, 0xEB, 0xF6, 0x1E, 0x35, 0x22, - 0x00, 0x34, 0x0D, 0x65, 0x32, 0xE9, 0x94, 0x89}, -}; - -static struct i2c_board_info __initdata inv_mpu6050_i2c2_board_info[] = { - { - I2C_BOARD_INFO(MPU_GYRO_NAME, MPU_GYRO_ADDR), - .platform_data = &mpu6050_gyro_data, - }, -}; - -static void mpuirq_init(void) -{ - int ret = 0; - unsigned gyro_irq_gpio = MPU_GYRO_IRQ_GPIO; - unsigned gyro_bus_num = MPU_GYRO_BUS_NUM; - char *gyro_name = MPU_GYRO_NAME; - - pr_info("*** MPU START *** mpuirq_init...\n"); - - ret = gpio_request(gyro_irq_gpio, gyro_name); - - if (ret < 0) { - pr_err("%s: gpio_request failed %d\n", __func__, ret); - return; - } - - ret = gpio_direction_input(gyro_irq_gpio); - if (ret < 0) { - pr_err("%s: gpio_direction_input failed %d\n", __func__, ret); - gpio_free(gyro_irq_gpio); - return; - } - pr_info("*** MPU END *** mpuirq_init...\n"); - - inv_mpu6050_i2c2_board_info[0].irq = gpio_to_irq(MPU_GYRO_IRQ_GPIO); - i2c_register_board_info(gyro_bus_num, inv_mpu6050_i2c2_board_info, - ARRAY_SIZE(inv_mpu6050_i2c2_board_info)); -} - -static int roth_nct1008_init(void) -{ - int nct1008_port = TEGRA_GPIO_PX6; - int ret = 0; - - tegra_platform_edp_init(roth_nct1008_pdata.sensors[EXT].trips, - &roth_nct1008_pdata.sensors[EXT].num_trips, - 0); /* edp temperature margin */ - tegra_add_all_vmin_trips(roth_nct1008_pdata.sensors[EXT].trips, - &roth_nct1008_pdata.sensors[EXT].num_trips); - tegra_add_cpu_vmax_trips(roth_nct1008_pdata.sensors[EXT].trips, - &roth_nct1008_pdata.sensors[EXT].num_trips); - tegra_add_core_edp_trips(roth_nct1008_pdata.sensors[EXT].trips, - &roth_nct1008_pdata.sensors[EXT].num_trips); - - roth_i2c4_nct1008_board_info[0].irq = gpio_to_irq(nct1008_port); - pr_info("%s: roth nct1008 irq %d", __func__, \ - roth_i2c4_nct1008_board_info[0].irq); - - ret = gpio_request(nct1008_port, "temp_alert"); - if (ret < 0) - return ret; - - ret = gpio_direction_input(nct1008_port); - if (ret < 0) { - pr_info("%s: calling gpio_free(nct1008_port)", __func__); - gpio_free(nct1008_port); - } - - /* roth has thermal sensor on GEN1-I2C i.e. instance 0 */ - i2c_register_board_info(0, roth_i2c4_nct1008_board_info, - ARRAY_SIZE(roth_i2c4_nct1008_board_info)); - - return ret; -} - -#ifdef CONFIG_TEGRA_SKIN_THROTTLE -static struct thermal_trip_info skin_trips[] = { - { - .cdev_type = "skin-balanced", - .trip_temp = 45000, - .trip_type = THERMAL_TRIP_PASSIVE, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, - { - .cdev_type = "tegra-shutdown", - .trip_temp = 57000, - .trip_type = THERMAL_TRIP_CRITICAL, - .upper = THERMAL_NO_LIMIT, - .lower = THERMAL_NO_LIMIT, - .hysteresis = 0, - }, -}; - -static struct therm_est_subdevice skin_devs[] = { - { - .dev_data = "Tdiode", - .coeffs = { - 2, 1, 1, 1, - 1, 1, 1, 1, - 1, 1, 1, 0, - 1, 1, 0, 0, - 0, 0, -1, -7 - }, - }, - { - .dev_data = "Tboard", - .coeffs = { - -11, -7, -5, -3, - -3, -2, -1, 0, - 0, 0, 1, 1, - 1, 2, 2, 3, - 4, 6, 11, 18 - }, - }, -}; - -static struct therm_est_data skin_data = { - .num_trips = ARRAY_SIZE(skin_trips), - .trips = skin_trips, - .toffset = 9793, - .polling_period = 1100, - .passive_delay = 15000, - .tc1 = 10, - .tc2 = 1, - .ndevs = ARRAY_SIZE(skin_devs), - .devs = skin_devs, -}; - -static struct throttle_table skin_throttle_table[] = { - /* CPU_THROT_LOW cannot be used by other than CPU */ - /* CPU, C2BUS, C3BUS, SCLK, EMC */ - { { 1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1606500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1581000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1555500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1530000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1504500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1479000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1453500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1428000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1402500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1377000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1351500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1326000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1300500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1275000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1249500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1224000, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1198500, NO_CAP, NO_CAP, NO_CAP, NO_CAP } }, - { { 1173000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1147500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1122000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1096500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1071000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1045500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 1020000, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 994500, 636000, NO_CAP, NO_CAP, NO_CAP } }, - { { 969000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 943500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 918000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 892500, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 867000, 600000, NO_CAP, NO_CAP, NO_CAP } }, - { { 841500, 564000, NO_CAP, NO_CAP, NO_CAP } }, - { { 816000, 564000, NO_CAP, NO_CAP, 792000 } }, - { { 790500, 564000, NO_CAP, 372000, 792000 } }, - { { 765000, 564000, 468000, 372000, 792000 } }, - { { 739500, 528000, 468000, 372000, 792000 } }, - { { 714000, 528000, 468000, 336000, 792000 } }, - { { 688500, 528000, 420000, 336000, 792000 } }, - { { 663000, 492000, 420000, 336000, 792000 } }, - { { 637500, 492000, 420000, 336000, 408000 } }, - { { 612000, 492000, 420000, 300000, 408000 } }, - { { 586500, 492000, 360000, 336000, 408000 } }, - { { 561000, 420000, 420000, 300000, 408000 } }, - { { 535500, 420000, 360000, 228000, 408000 } }, - { { 510000, 420000, 288000, 228000, 408000 } }, - { { 484500, 324000, 288000, 228000, 408000 } }, - { { 459000, 324000, 288000, 228000, 408000 } }, - { { 433500, 324000, 288000, 228000, 408000 } }, - { { 408000, 324000, 288000, 228000, 408000 } }, -}; - -static struct balanced_throttle skin_throttle = { - .throt_tab_size = ARRAY_SIZE(skin_throttle_table), - .throt_tab = skin_throttle_table, -}; - -static int __init roth_skin_init(void) -{ - if (machine_is_roth()) { - balanced_throttle_register(&skin_throttle, "skin-balanced"); - tegra_skin_therm_est_device.dev.platform_data = &skin_data; - platform_device_register(&tegra_skin_therm_est_device); - } - - return 0; -} -late_initcall(roth_skin_init); -#endif - -static int roth_fan_est_match(struct thermal_zone_device *thz, void *data) -{ - return (strcmp((char *)data, thz->type) == 0); -} - -static int roth_fan_est_get_temp(void *data, long *temp) -{ - struct thermal_zone_device *thz; - - thz = thermal_zone_device_find(data, roth_fan_est_match); - - if (!thz || thz->ops->get_temp(thz, temp)) - *temp = 25000; - - return 0; -} - -/*Fan thermal estimator init data for P2454*/ -static struct therm_fan_est_data fan_est_data_p2454 = { - .toffset = 0, - .polling_period = 1100, - .ndevs = 2, - .devs = { - { - .dev_data = "Tdiode_soc", - .get_temp = roth_fan_est_get_temp, - .coeffs = { - 100, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 - }, - }, - { - .dev_data = "Tboard_soc", - .get_temp = roth_fan_est_get_temp, - .coeffs = { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 - }, - }, - }, - .cdev_type = "pwm-fan", - .active_trip_temps = {0, 70000, 82000, 120000, 130000, - 140000, 150000, 160000, 170000, 180000}, - .active_hysteresis = {0, 10000, 7000, 0, 0, 0, 0, 0, 0, 0}, -}; - -static struct platform_device roth_fan_therm_est_device_p2454 = { - .name = "therm-fan-est", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &fan_est_data_p2454, - }, -}; - -/*Fan thermal estimator data for P2560*/ -static struct therm_fan_est_data fan_est_data_p2560 = { - .toffset = 0, - .polling_period = 1100, - .ndevs = 2, - .devs = { - { - .dev_data = "nct_ext_soc", - .get_temp = roth_fan_est_get_temp, - .coeffs = { - 100, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 - }, - }, - { - .dev_data = "nct_int_soc", - .get_temp = roth_fan_est_get_temp, - .coeffs = { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 - }, - }, - }, - .cdev_type = "pwm-fan", - .active_trip_temps = {0, 47000, 55000, 67000, 103000, - 140000, 150000, 160000, 170000, 180000}, - .active_hysteresis = {0, 12000, 7000, 10000, 0, 0, 0, 0, 0, 0}, -}; - -static struct platform_device roth_fan_therm_est_device_p2560 = { - .name = "therm-fan-est", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &fan_est_data_p2560, - }, -}; - -static int __init roth_fan_est_init(void) -{ - struct board_info board_info; - - tegra_get_board_info(&board_info); - if (board_info.board_id == BOARD_P2560) - platform_device_register(&roth_fan_therm_est_device_p2560); - else - platform_device_register(&roth_fan_therm_est_device_p2454); - - return 0; -} - -int __init roth_sensors_init(void) -{ - int err; - - err = roth_nct1008_init(); - if (err) - return err; - - mpuirq_init(); - - roth_fan_est_init(); - - return 0; -} diff --git a/arch/arm/mach-tegra/board-roth.c b/arch/arm/mach-tegra/board-roth.c deleted file mode 100644 index 6ed937c1a48d..000000000000 --- a/arch/arm/mach-tegra/board-roth.c +++ /dev/null @@ -1,660 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth.c - * - * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/slab.h> -#include <linux/ctype.h> -#include <linux/platform_device.h> -#include <linux/clk.h> -#include <linux/serial_8250.h> -#include <linux/i2c.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> -#include <linux/i2c-tegra.h> -#include <linux/gpio.h> -#include <linux/input.h> -#include <linux/platform_data/tegra_usb.h> -#include <linux/spi/spi.h> -#include <linux/spi/rm31080a_ts.h> -#include <linux/spi/spi-tegra.h> -#include <linux/memblock.h> -#include <linux/rfkill-gpio.h> -#include <linux/skbuff.h> -#include <linux/ti_wilink_st.h> -#include <linux/regulator/consumer.h> -#include <linux/max17048_battery.h> -#include <linux/leds.h> -#include <linux/leds_pwm.h> -#include <linux/i2c/at24.h> -#include <linux/issp.h> -#include <linux/of_platform.h> -#include <linux/usb/tegra_usb_phy.h> -#include <linux/clk/tegra.h> -#include <linux/clocksource.h> -#include <linux/irqchip.h> -#include <linux/tegra_fiq_debugger.h> - -#include <asm/system_info.h> - -#include <mach/irqs.h> -#include <mach/pinmux.h> -#include <mach/pinmux-t11.h> -#include <mach/io_dpd.h> -#include <mach/i2s.h> -#include <mach/isomgr.h> -#include <mach/tegra_asoc_pdata.h> -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <mach/gpio-tegra.h> -#include <mach/edp.h> - -#include "board.h" -#include "board-common.h" -#include "clock.h" -#include "board-roth.h" -#include "devices.h" -#include "gpio-names.h" -#include "iomap.h" -#include "pm.h" -#include "common.h" -#include "tegra-board-id.h" -#include "board-touch-raydium.h" -#include "tegra-of-dev-auxdata.h" - -#ifdef CONFIG_BT_BLUESLEEP -static struct rfkill_gpio_platform_data roth_bt_rfkill_pdata = { - .name = "bt_rfkill", - .shutdown_gpio = TEGRA_GPIO_PQ7, - .type = RFKILL_TYPE_BLUETOOTH, -}; - -static struct platform_device roth_bt_rfkill_device = { - .name = "rfkill_gpio", - .id = -1, - .dev = { - .platform_data = &roth_bt_rfkill_pdata, - }, -}; - -static struct resource roth_bluesleep_resources[] = { - [0] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [2] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, -}; - -static struct platform_device roth_bluesleep_device = { - .name = "bluesleep", - .id = -1, - .num_resources = ARRAY_SIZE(roth_bluesleep_resources), - .resource = roth_bluesleep_resources, -}; - -static noinline void __init roth_setup_bt_rfkill(void) -{ - roth_bt_rfkill_pdata.reset_gpio = TEGRA_GPIO_PQ6; - platform_device_register(&roth_bt_rfkill_device); -} - -static noinline void __init roth_setup_bluesleep(void) -{ - roth_bluesleep_resources[2].start = - roth_bluesleep_resources[2].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&roth_bluesleep_device); - return; -} -#elif defined CONFIG_BLUEDROID_PM -static struct resource roth_bluedroid_pm_resources[] = { - [0] = { - .name = "shutdown_gpio", - .start = TEGRA_GPIO_PQ7, - .end = TEGRA_GPIO_PQ7, - .flags = IORESOURCE_IO, - }, - [1] = { - .name = "host_wake", - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - }, - [2] = { - .name = "gpio_ext_wake", - .start = TEGRA_GPIO_PEE1, - .end = TEGRA_GPIO_PEE1, - .flags = IORESOURCE_IO, - }, - [3] = { - .name = "gpio_host_wake", - .start = TEGRA_GPIO_PU6, - .end = TEGRA_GPIO_PU6, - .flags = IORESOURCE_IO, - }, -}; - -static struct platform_device roth_bluedroid_pm_device = { - .name = "bluedroid_pm", - .id = 0, - .num_resources = ARRAY_SIZE(roth_bluedroid_pm_resources), - .resource = roth_bluedroid_pm_resources, -}; - -static noinline void __init roth_setup_bluedroid_pm(void) -{ - roth_bluedroid_pm_resources[1].start = - roth_bluedroid_pm_resources[1].end = - gpio_to_irq(TEGRA_GPIO_PU6); - platform_device_register(&roth_bluedroid_pm_device); -} -#endif -static __initdata struct tegra_clk_init_table roth_clk_init_table[] = { - /* name parent rate enabled */ - { "pll_m", NULL, 0, false}, - { "hda", "pll_p", 108000000, false}, - { "hda2codec_2x", "pll_p", 48000000, false}, - { "pwm", "pll_p", 6000000, false}, - { "blink", "clk_32k", 32768, true}, - { "i2s1", "pll_a_out0", 0, false}, - { "i2s3", "pll_a_out0", 0, false}, - { "i2s4", "pll_a_out0", 0, false}, - { "spdif_out", "pll_a_out0", 0, false}, - { "d_audio", "clk_m", 12000000, false}, - { "dam0", "clk_m", 12000000, false}, - { "dam1", "clk_m", 12000000, false}, - { "dam2", "clk_m", 12000000, false}, - { "audio1", "i2s1_sync", 0, false}, - { "audio3", "i2s3_sync", 0, false}, - /* Setting vi_sensor-clk to true for validation purpose, will imapact - * power, later set to be false.*/ - { "vi_sensor", "pll_p", 150000000, false}, - { "cilab", "pll_p", 150000000, false}, - { "cilcd", "pll_p", 150000000, false}, - { "cile", "pll_p", 150000000, false}, - { "i2c1", "pll_p", 3200000, false}, - { "i2c2", "pll_p", 3200000, false}, - { "i2c3", "pll_p", 3200000, false}, - { "i2c4", "pll_p", 3200000, false}, - { "i2c5", "pll_p", 3200000, false}, - { NULL, NULL, 0, 0}, -}; - -#if defined(CONFIG_ARCH_TEGRA_11x_SOC) -static struct i2c_board_info __initdata rt5640_board_info = { - I2C_BOARD_INFO("rt5640", 0x1c), -}; - -static struct i2c_board_info __initdata roth_codec_tfa9887R_info = { - I2C_BOARD_INFO("tfa9887R", 0x37), -}; - -static struct i2c_board_info __initdata roth_codec_tfa9887L_info = { - I2C_BOARD_INFO("tfa9887L", 0x34), -}; -#endif - -static void roth_i2c_init(void) -{ - i2c_register_board_info(0, &rt5640_board_info, 1); - i2c_register_board_info(0, &roth_codec_tfa9887R_info, 1); - i2c_register_board_info(0, &roth_codec_tfa9887L_info, 1); -} - -static struct platform_device *roth_uart_devices[] __initdata = { - &tegra_uarta_device, - &tegra_uartb_device, - &tegra_uartc_device, - &tegra_uartd_device, -}; - -static void __init uart_debug_init(void) -{ - int debug_port_id; - - debug_port_id = uart_console_debug_init(3); - if (debug_port_id < 0) - return; - - roth_uart_devices[debug_port_id] = uart_console_debug_device; -} - -static void __init roth_uart_init(void) -{ - /* Register low speed only if it is selected */ - if (!is_tegra_debug_uartport_hs()) - uart_debug_init(); - - platform_add_devices(roth_uart_devices, - ARRAY_SIZE(roth_uart_devices)); -} - -static struct resource tegra_rtc_resources[] = { - [0] = { - .start = TEGRA_RTC_BASE, - .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = INT_RTC, - .end = INT_RTC, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device tegra_rtc_device = { - .name = "tegra_rtc", - .id = -1, - .resource = tegra_rtc_resources, - .num_resources = ARRAY_SIZE(tegra_rtc_resources), -}; - -static struct tegra_asoc_platform_data roth_audio_pdata = { - .gpio_spkr_en = TEGRA_GPIO_SPKR_EN, - .gpio_hp_det = TEGRA_GPIO_HP_DET, - .gpio_hp_mute = -1, - .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN, - .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN, - .gpio_ldo1_en = TEGRA_GPIO_LDO1_EN, - .gpio_codec1 = TEGRA_GPIO_CODEC1_EN, - .gpio_codec2 = TEGRA_GPIO_CODEC2_EN, - .gpio_codec3 = TEGRA_GPIO_CODEC3_EN, - .i2s_param[HIFI_CODEC] = { - .audio_port_id = 1, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_I2S, - }, - .i2s_param[BT_SCO] = { - .audio_port_id = 3, - .is_i2s_master = 1, - .i2s_mode = TEGRA_DAIFMT_DSP_A, - }, -}; - -static struct platform_device roth_audio_device = { - .name = "tegra-snd-rt5640", - .id = 0, - .dev = { - .platform_data = &roth_audio_pdata, - }, -}; - -static struct platform_device tegra_camera = { - .name = "tegra_camera", - .id = -1, -}; - - -static struct issp_platform_data roth_issp_pdata_p2454 = { - .reset_gpio = TEGRA_GPIO_PH4, - .data_gpio = TEGRA_GPIO_PH6, - .clk_gpio = TEGRA_GPIO_PH7, - .fw_name = "p2454-uc.fw", - .si_id = {0x00, 0xA2, 0x52, 0x21}, /* CY7C64345 */ - .block_size = 128, - .blocks = 128, - .security_size = 64, - .version_addr = 0x0286, - .force_update = 1, -}; - -static struct platform_device roth_issp_device_p2454 = { - .name = "issp", - .dev = { - .platform_data = &roth_issp_pdata_p2454, - }, -}; - -static struct issp_platform_data roth_issp_pdata_p2560 = { - .reset_gpio = TEGRA_GPIO_PH4, - .data_gpio = TEGRA_GPIO_PH6, - .clk_gpio = TEGRA_GPIO_PH7, - .fw_name = "p2560-uc.fw", - .si_id = {0x00, 0xA2, 0x52, 0x21}, /* CY7C64345 */ - .block_size = 128, - .blocks = 128, - .security_size = 64, - .version_addr = 0x0286, - .force_update = 0, -}; - -static struct platform_device roth_issp_device_p2560 = { - .name = "issp", - .dev = { - .platform_data = &roth_issp_pdata_p2560, - }, -}; - -static void __init roth_issp_init(void) -{ - if (system_rev == P2454) - platform_device_register(&roth_issp_device_p2454); - else - platform_device_register(&roth_issp_device_p2560); -} - -static struct platform_device *roth_devices[] __initdata = { - &tegra_pmu_device, - &tegra_rtc_device, - &tegra_udc_device, -#if defined(CONFIG_TEGRA_AVP) - &tegra_avp_device, -#endif - &tegra_camera, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) - &tegra11_se_device, -#endif - &tegra_ahub_device, - &tegra_dam_device0, - &tegra_dam_device1, - &tegra_dam_device2, - &tegra_i2s_device1, - &tegra_i2s_device3, - &tegra_i2s_device4, - &tegra_spdif_device, - &spdif_dit_device, - &bluetooth_dit_device, - &roth_audio_device, - &tegra_hda_device, -#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) - &tegra_aes_device, -#endif -}; - -#ifdef CONFIG_USB_SUPPORT -static struct tegra_usb_platform_data tegra_udc_pdata = { - .port_otg = true, - .has_hostpc = true, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_DEVICE, - .u_data.dev = { - .vbus_pmu_irq = 0, - .vbus_gpio = -1, - .charging_supported = true, - .remote_wakeup_supported = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { - .port_otg = true, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = true, - .remote_wakeup_supported = true, - .power_off_on_suspend = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 15, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x4, - }, -}; - -static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { - .port_otg = false, - .has_hostpc = true, - .unaligned_dma_buf_supported = false, - .phy_intf = TEGRA_USB_PHY_INTF_UTMI, - .op_mode = TEGRA_USB_OPMODE_HOST, - .u_data.host = { - .vbus_gpio = -1, - .hot_plug = true, - .remote_wakeup_supported = true, - .power_off_on_suspend = false, - }, - .u_cfg.utmi = { - .hssync_start_delay = 0, - .elastic_limit = 16, - .idle_wait_delay = 17, - .term_range_adj = 6, - .xcvr_setup = 8, - .xcvr_lsfslew = 2, - .xcvr_lsrslew = 2, - .xcvr_setup_offset = 0, - .xcvr_use_fuses = 1, - .vbus_oc_map = 0x5, - }, -}; - -static struct tegra_usb_otg_data tegra_otg_pdata = { - .ehci_device = &tegra_ehci1_device, - .ehci_pdata = &tegra_ehci1_utmi_pdata, -}; - -static void roth_usb_init(void) -{ - tegra_otg_device.dev.platform_data = &tegra_otg_pdata; - platform_device_register(&tegra_otg_device); - - /* Setup the udc platform data */ - tegra_udc_device.dev.platform_data = &tegra_udc_pdata; - - tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; - platform_device_register(&tegra_ehci3_device); -} - -#else -static void roth_usb_init(void) { } -#endif - -static void roth_audio_init(void) -{ - roth_audio_pdata.codec_name = "rt5640.0-001c"; - roth_audio_pdata.codec_dai_name = "rt5640-aif1"; -} - -static __initdata struct tegra_clk_init_table touch_clk_init_table[] = { - /* name parent rate enabled */ - { "extern2", "pll_p", 41000000, false}, - { "clk_out_2", "extern2", 40800000, false}, - { NULL, NULL, 0, 0}, -}; - -struct rm_spi_ts_platform_data rm31080ts_roth_data = { - .gpio_reset = TOUCH_GPIO_RST_RAYDIUM_SPI, - .config = 0, - .platform_id = RM_PLATFORM_R005, - .name_of_clock = "clk_out_2", - .name_of_clock_con = "extern2", -}; - -static struct tegra_spi_device_controller_data dev_cdata = { - .rx_clk_tap_delay = 16, - .tx_clk_tap_delay = 16, -}; - -struct spi_board_info rm31080a_roth_spi_board[1] = { - { - .modalias = "rm_ts_spidev", - .bus_num = 3, - .chip_select = 2, - .max_speed_hz = 12 * 1000 * 1000, - .mode = SPI_MODE_0, - .controller_data = &dev_cdata, - .platform_data = &rm31080ts_roth_data, - }, -}; - -static int __init roth_touch_init(void) -{ - struct board_info board_info; - int touch_panel_id = tegra_get_touch_panel_id(); - - tegra_get_board_info(&board_info); - if (touch_panel_id == PANEL_TPK || - touch_panel_id == PANEL_WINTEK) { - int err; - err = gpio_request(TOUCH_GPIO_CLK, "touch-gpio-clk"); - if (err < 0) - pr_err("%s: gpio_request failed %d\n", - __func__, err); - else { - err = gpio_direction_output(TOUCH_GPIO_CLK, 0); - if (err < 0) - pr_err("%s: set output failed %d\n", - __func__, err); - gpio_free(TOUCH_GPIO_CLK); - } - tegra_pinmux_set_pullupdown(TOUCH_GPIO_CLK_PG, - TEGRA_PUPD_NORMAL); - tegra_pinmux_set_tristate(TOUCH_GPIO_CLK_PG, - TEGRA_TRI_TRISTATE); - rm31080ts_roth_data.name_of_clock = NULL; - rm31080ts_roth_data.name_of_clock_con = NULL; - } else - tegra_clk_init_from_table(touch_clk_init_table); - rm31080a_roth_spi_board[0].irq = - gpio_to_irq(TOUCH_GPIO_IRQ_RAYDIUM_SPI); - touch_init_raydium(TOUCH_GPIO_IRQ_RAYDIUM_SPI, - TOUCH_GPIO_RST_RAYDIUM_SPI, - &rm31080ts_roth_data, - &rm31080a_roth_spi_board[0], - ARRAY_SIZE(rm31080a_roth_spi_board)); - return 0; -} - -static void __init tegra_roth_init(void) -{ - tegra_clk_init_from_table(roth_clk_init_table); - tegra_clk_verify_parents(); - tegra_soc_device_init("roth"); - roth_i2c_init(); - roth_usb_init(); - roth_uart_init(); - roth_led_init(); - roth_audio_init(); - platform_add_devices(roth_devices, ARRAY_SIZE(roth_devices)); - tegra_io_dpd_init(); - roth_regulator_init(); - roth_sdhci_init(); - roth_suspend_init(); - roth_emc_init(); - roth_edp_init(); - isomgr_init(); - roth_touch_init(); - /* roth will pass a null board id to panel_init */ - roth_panel_init(0); - roth_kbc_init(); -#ifdef CONFIG_BT_BLUESLEEP - roth_setup_bluesleep(); - roth_setup_bt_rfkill(); -#elif defined CONFIG_BLUEDROID_PM - roth_setup_bluedroid_pm(); -#endif -#ifdef CONFIG_TEGRA_WDT_RECOVERY - tegra_wdt_recovery_init(); -#endif - tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); - roth_sensors_init(); - roth_soctherm_init(); - roth_fan_init(); - tegra_register_fuse(); - roth_issp_init(); -} - -#ifdef CONFIG_USE_OF -struct of_dev_auxdata roth_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra114-host1x", TEGRA_HOST1X_BASE, "host1x", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr3d", TEGRA_GR3D_BASE, "gr3d", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-gr2d", TEGRA_GR2D_BASE, "gr2d", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-msenc", TEGRA_MSENC_BASE, "msenc", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-vi", TEGRA_VI_BASE, "vi", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-isp", TEGRA_ISP_BASE, "isp", NULL), - OF_DEV_AUXDATA("nvidia,tegra114-tsec", TEGRA_TSEC_BASE, "tsec", NULL), - T114_SPI_OF_DEV_AUXDATA, - T114_I2C_OF_DEV_AUXDATA, - OF_DEV_AUXDATA("nvidia,tegra114-nvavp", 0x60001000, "nvavp", - NULL), - OF_DEV_AUXDATA("nvidia,tegra114-pwm", 0x7000a000, "tegra-pwm", NULL), - - {} -}; -#endif - -static void __init tegra_roth_dt_init(void) -{ -#ifdef CONFIG_USE_OF - of_platform_populate(NULL, - of_default_bus_match_table, roth_auxdata_lookup, - &platform_bus); -#endif - - tegra_roth_init(); -} - -static void __init tegra_roth_reserve(void) -{ -#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) - /* 1920*1200*4*2 = 18432000 bytes */ - tegra_reserve(0, SZ_16M + SZ_2M, SZ_4M); -#else - tegra_reserve(SZ_128M, SZ_16M + SZ_2M, SZ_4M); -#endif -} - -static const char * const roth_dt_board_compat[] = { - "nvidia,roth", - NULL -}; - -MACHINE_START(ROTH, "roth") - .atag_offset = 0x100, - .smp = smp_ops(tegra_smp_ops), - .map_io = tegra_map_common_io, - .reserve = tegra_roth_reserve, - .init_early = tegra11x_init_early, - .init_irq = irqchip_init, - .init_time = clocksource_of_init, - .init_machine = tegra_roth_dt_init, - .restart = tegra_assert_system_reset, - .dt_compat = roth_dt_board_compat, -MACHINE_END diff --git a/arch/arm/mach-tegra/board-roth.h b/arch/arm/mach-tegra/board-roth.h deleted file mode 100644 index 265c1e93cd4b..000000000000 --- a/arch/arm/mach-tegra/board-roth.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * arch/arm/mach-tegra/board-roth.h - * - * Copyright (c) 2012 - 2013, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - */ - -#ifndef _MACH_TEGRA_BOARD_ROTH_H -#define _MACH_TEGRA_BOARD_ROTH_H - -#include <mach/irqs.h> -#include <linux/mfd/max77663-core.h> -#include "gpio-names.h" - -#define PMC_WAKE_STATUS 0x14 -#define PMC_WAKE2_STATUS 0x168 - -/* External peripheral act as gpio */ -/* MAX77663 GPIO */ -#define MAX77663_GPIO_BASE TEGRA_NR_GPIOS -#define PALMAS_TEGRA_GPIO_BASE TEGRA_NR_GPIOS -#define MAX77663_GPIO_END (MAX77663_GPIO_BASE + MAX77663_GPIO_NR) - -/* Hall Effect Sensor GPIO */ -#define TEGRA_GPIO_HALL TEGRA_GPIO_PS0 - -/* Audio-related GPIOs */ -#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PW3 -#define TEGRA_GPIO_LDO1_EN TEGRA_GPIO_PV3 -#define TEGRA_GPIO_CODEC1_EN TEGRA_GPIO_PP3 -#define TEGRA_GPIO_CODEC2_EN TEGRA_GPIO_PP1 -#define TEGRA_GPIO_CODEC3_EN TEGRA_GPIO_PV0 - -#define TEGRA_GPIO_SPKR_EN -1 -#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7 -#define TEGRA_GPIO_INT_MIC_EN -1 -#define TEGRA_GPIO_EXT_MIC_EN -1 - -#define TEGRA_GPIO_W_DISABLE TEGRA_GPIO_PDD7 -#define TEGRA_GPIO_MODEM_RSVD1 TEGRA_GPIO_PV0 -#define TEGRA_GPIO_MODEM_RSVD2 TEGRA_GPIO_PH7 - -/* External peripheral act as interrupt controller */ -/* MAX77663 IRQs */ -#define PALMAS_TEGRA_IRQ_BASE TEGRA_NR_IRQS -#define MAX77663_IRQ_BASE TEGRA_NR_IRQS -#define MAX77663_IRQ_END (MAX77663_IRQ_BASE + MAX77663_IRQ_NR) -#define MAX77663_IRQ_ACOK_RISING MAX77663_IRQ_ONOFF_ACOK_RISING - -/* I2C related GPIOs */ -#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4 -#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5 -#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5 -#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6 -#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1 -#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2 -#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4 -#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5 -#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6 -#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7 - -/* Touchscreen definitions */ -#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2 -#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4 - -#define TOUCH_GPIO_CLK TEGRA_GPIO_PW5 -#define TOUCH_GPIO_CLK_PG TEGRA_PINGROUP_CLK2_OUT - -enum panel_id { - PANEL_RESERVED = 0, - PANEL_WINTEK, - PANEL_TPK, - PANEL_TOUCH_TURNS, -}; - -/* Invensense MPU Definitions */ -#define MPU_GYRO_NAME "mpu6050" -#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PR3 -#define MPU_GYRO_ADDR 0x68 -#define MPU_GYRO_BUS_NUM 0 -#define MPU_GYRO_ORIENTATION { 0, 1, 0, 0, 0, 1, 1, 0, 0 } -#define MPU_COMPASS_NAME "ak8975" -#define MPU_COMPASS_IRQ_GPIO 0 -#define MPU_COMPASS_ADDR 0x0D -#define MPU_COMPASS_BUS_NUM 0 -#define MPU_COMPASS_ORIENTATION MTMAT_TOP_CCW_270 - -enum { - P2454 = 1, - P2560, -}; - -int roth_regulator_init(void); -int roth_suspend_init(void); -int roth_sdhci_init(void); -int roth_sensors_init(void); -int roth_emc_init(void); -int roth_edp_init(void); -int roth_panel_init(int board_id); -int roth_kbc_init(void); -int roth_soctherm_init(void); -int roth_fan_init(void); -int roth_led_init(void); - -#endif |