diff options
| author | Richard Zhu <Richard.Zhu@freescale.com> | 2015-12-16 14:38:44 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@nxp.com> | 2016-01-14 11:02:45 -0600 |
| commit | fe86dc3b7e7cec7cb4f3ff52757b0d486beee408 (patch) | |
| tree | d44e8f515140996c8a8629dd494c7a401b656e0b | |
| parent | ead3722761f33b390a8a8815e72ddd2d69495ac3 (diff) | |
MLK-12026 arm: imx: correct the lvds1_sel parent clk
The IMX6QDL_CLK_SATA_REF_100M and IMX6QDL_CLK_PCIE_REF_125M
should be the source of the LVDS#_SEL.
And the parent clock of IMX6QDL_CLK_LVDS1_SEL should be
IMX6QDL_CLK_SATA_REF_100M.
Otherwise, imx6dl would be hang, when imx6dl pcie try to
access the dbi register when the IMX6QDL_CLK_SATA_REF_100M
is not enabled.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 79c6cd72a2fb..c7545d3583b4 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -85,7 +85,7 @@ static const char *cko_sels[] = { "cko1", "cko2", }; static const char *lvds_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", - "pcie_ref", "sata_ref", + "pcie_ref_125m", "sata_ref_100m", }; static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; @@ -869,7 +869,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) /* All existing boards with PCIe use LVDS1 */ if (IS_ENABLED(CONFIG_PCI_IMX6)) - imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF]); + imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); /* set eim_slow to 135Mhz */ imx_clk_set_rate(clk[IMX6QDL_CLK_EIM_SLOW], 135000000); |