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authorCatalin Marinas <catalin.marinas@arm.com>2014-04-25 16:39:49 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2014-05-03 22:20:35 +0100
commit7a8d1ec16dfbb7785e82ccc97b0076cc34911701 (patch)
treee7294b4ad8ac2cdc3ff855dbd1372def91bb5ef1 /Documentation/devicetree
parent6ecba8eb51b7d23fda66388a5420be7d8688b186 (diff)
arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent
Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Loc Ho <lho@apm.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/ata/apm-xgene.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/ata/apm-xgene.txt b/Documentation/devicetree/bindings/ata/apm-xgene.txt
index 7bcfbf59810e..a668f0e7d001 100644
--- a/Documentation/devicetree/bindings/ata/apm-xgene.txt
+++ b/Documentation/devicetree/bindings/ata/apm-xgene.txt
@@ -24,6 +24,7 @@ Required properties:
* "sata-phy" for the SATA 6.0Gbps PHY
Optional properties:
+- dma-coherent : Present if dma operations are coherent
- status : Shall be "ok" if enabled or "disabled" if disabled.
Default is "ok".
@@ -55,6 +56,7 @@ Example:
<0x0 0x1f22e000 0x0 0x1000>,
<0x0 0x1f227000 0x0 0x1000>;
interrupts = <0x0 0x87 0x4>;
+ dma-coherent;
status = "ok";
clocks = <&sataclk 0>;
phys = <&phy2 0>;
@@ -69,6 +71,7 @@ Example:
<0x0 0x1f23e000 0x0 0x1000>,
<0x0 0x1f237000 0x0 0x1000>;
interrupts = <0x0 0x88 0x4>;
+ dma-coherent;
status = "ok";
clocks = <&sataclk 0>;
phys = <&phy3 0>;